diff options
| author | fyang <fyang@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-05-05 15:59:12 +0000 |
|---|---|---|
| committer | fyang <fyang@138bc75d-0d04-0410-961f-82ee72b054a4> | 2015-05-05 15:59:12 +0000 |
| commit | 802e63ed5ee2dbb6163584f60f5511b8463c628d (patch) | |
| tree | eb9fdab26faa689ae87875740075ad4b2bea3c75 | |
| parent | 71cbf10d66accf91ff85d38cc07c3e57b73a2513 (diff) | |
Backported from mainline
2015-01-19 Jiong Wang <jiong.wang@arm.com>
Andrew Pinski <apinski@cavium.com>
PR target/64304
* config/aarch64/aarch64.md (define_insn "*ashl<mode>3_insn"): Deleted.
(ashl<mode>3): Don't expand if operands[2] is not constant.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@222814 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/pr64304.c | 18 |
4 files changed, 37 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5648860fd0d..b57291553a0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,13 @@ +2015-05-05 Shanyao Chen <chenshanyao@huawei.com> + + Backported from mainline + 2015-01-19 Jiong Wang <jiong.wang@arm.com> + Andrew Pinski <apinski@cavium.com> + + PR target/64304 + * config/aarch64/aarch64.md (define_insn "*ashl<mode>3_insn"): Deleted. + (ashl<mode>3): Don't expand if operands[2] is not constant. + 2015-05-05 Peter Bergner <bergner@vnet.ibm.com> Backport from mainline. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c879024ebf6..f5c0761d4f1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2612,6 +2612,8 @@ DONE; } } + else + FAIL; } ) @@ -2681,16 +2683,6 @@ (set_attr "mode" "SI")] ) -(define_insn "*ashl<mode>3_insn" - [(set (match_operand:SHORT 0 "register_operand" "=r") - (ashift:SHORT (match_operand:SHORT 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_si" "rUss")))] - "" - "lsl\\t%<w>0, %<w>1, %<w>2" - [(set_attr "v8type" "shift") - (set_attr "mode" "<MODE>")] -) - (define_insn "*<optab><mode>3_insn" [(set (match_operand:SHORT 0 "register_operand" "=r") (ASHIFT:SHORT (match_operand:SHORT 1 "register_operand" "r") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 2f354153452..dde3fb3e441 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2015-05-05 Shanyao chen <chenshanyao@huawei.com> + + Backported from mainline + 2015-01-19 Jiong Wang <jiong.wang@arm.com> + + * gcc.target/aarch64/pr64304.c: New testcase. + 2015-05-05 Peter Bergner <bergner@vnet.ibm.com> Backport from mainline. diff --git a/gcc/testsuite/gcc.target/aarch64/pr64304.c b/gcc/testsuite/gcc.target/aarch64/pr64304.c new file mode 100644 index 00000000000..721b6b95805 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr64304.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --save-temps" } */ + +unsigned char byte = 0; + +void +set_bit (unsigned int bit, unsigned char value) +{ + unsigned char mask = (unsigned char) (1 << (bit & 7)); + + if (! value) + byte &= (unsigned char)~mask; + else + byte |= mask; + /* { dg-final { scan-assembler "and\tw\[0-9\]+, w\[0-9\]+, 7" } } */ +} + +/* { dg-final { cleanup-saved-temps } } */ |