diff options
| author | bernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-05-18 12:45:03 +0000 |
|---|---|---|
| committer | bernds <bernds@138bc75d-0d04-0410-961f-82ee72b054a4> | 2001-05-18 12:45:03 +0000 |
| commit | 13e9316ae80ba96efa29b70232a5d869a761855f (patch) | |
| tree | 3e5fa177131163ceee004ed65c592792ec1f31d8 | |
| parent | 63aab77d5460fe517fd655cd7c05e0c84a829ab3 (diff) | |
Revert an incorrect change
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@42262 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 12 |
2 files changed, 13 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cf694258dc7..a2ee872c903 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2001-05-18 Bernd Schmidt <bernds@redhat.com> + + Revert + 2001-02-09 Nick Clifton <nickc@redhat.com> + * config/arm/arm.md: Change output constraint on post inc + load/store multiple patterns to be a read/write constraint. + 2001-05-18 Mark Mitchell <mark@codesourcery.com> * function.c (expand_function_start): Avoid creating BLKmode diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f69e0fee170..17c40b0b9dd 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -5239,7 +5239,7 @@ (define_insn "*ldmsi_postinc4" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) (set (match_operand:SI 3 "arm_hard_register_operand" "") @@ -5258,7 +5258,7 @@ (define_insn "*ldmsi_postinc3" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) (set (match_operand:SI 3 "arm_hard_register_operand" "") @@ -5275,7 +5275,7 @@ (define_insn "*ldmsi_postinc2" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) (set (match_operand:SI 3 "arm_hard_register_operand" "") @@ -5361,7 +5361,7 @@ (define_insn "*stmsi_postinc4" [(match_parallel 0 "store_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 16))) (set (mem:SI (match_dup 2)) @@ -5380,7 +5380,7 @@ (define_insn "*stmsi_postinc3" [(match_parallel 0 "store_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 12))) (set (mem:SI (match_dup 2)) @@ -5397,7 +5397,7 @@ (define_insn "*stmsi_postinc2" [(match_parallel 0 "store_multiple_operation" - [(set (match_operand:SI 1 "s_register_operand" "+r") + [(set (match_operand:SI 1 "s_register_operand" "=r") (plus:SI (match_operand:SI 2 "s_register_operand" "1") (const_int 8))) (set (mem:SI (match_dup 2)) |