Change vector width to 256 bits.

Restructure parts dependent on vector width.


git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/st/cli-be-vect@159119 138bc75d-0d04-0410-961f-82ee72b054a4

11 files changed, 637 insertions, 231 deletions

diff --git a/gcc/config/cil32/cil-builtins.c b/gcc/config/cil32/cil-builtins.c
index 0b5a5d29cb3..2cc832a41b3 100644
--- a/gcc/config/cil32/cil-builtins.c
+++ b/gcc/config/cil32/cil-builtins.c
@@ -1,6 +1,6 @@
 /*
 
-   Copyright (C) 2006-2009 Free Software Foundation, Inc.
+   Copyright (C) 2006-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -40,6 +40,47 @@ Erven Rohou             <erven.rohou@inria.fr>
 #include "cil-builtins.h"
 #include "cil-refs.h"
 
+
+/* When changing UNITS_PER_SIMD_WORD, need to change the following
+   accordingly. */
+#if 0
+/* This is for 64-bit vectors */
+#define VQI_type_node intQI8_type_node
+#define VHI_type_node intHI4_type_node
+#define VSI_type_node intSI2_type_node
+#define VDI_type_node intDI2_type_node  /* FIXME */
+
+#define VSF_type_node float2_type_node
+#define VDF_type_node double2_type_node  /* FIXME */
+
+#define VQI_ptr_type_node V8QI_ptr_type_node
+#define VHI_ptr_type_node V4HI_ptr_type_node
+#define VSI_ptr_type_node V2SI_ptr_type_node
+#define VDI_ptr_type_node V2DI_ptr_type_node  /* FIXME */
+
+#define VSF_ptr_type_node V2SF_ptr_type_node
+#define VDF_ptr_type_node V2DF_ptr_type_node  /* FIXME */
+
+#else
+/* This is for 256-bit vectors */
+#define VQI_type_node intQI32_type_node
+#define VHI_type_node intHI16_type_node
+#define VSI_type_node intSI8_type_node
+#define VDI_type_node intDI4_type_node
+
+#define VSF_type_node float8_type_node
+#define VDF_type_node double4_type_node
+
+#define VQI_ptr_type_node V32QI_ptr_type_node
+#define VHI_ptr_type_node V16HI_ptr_type_node
+#define VSI_ptr_type_node V8SI_ptr_type_node
+#define VDI_ptr_type_node V4DI_ptr_type_node
+
+#define VSF_ptr_type_node V8SF_ptr_type_node
+#define VDF_ptr_type_node V4DF_ptr_type_node
+
+#endif
+
 tree cil32_builtins[CIL32_MAX_BUILT_IN] = {NULL_TREE};
 
 tree cil32_va_list_type = NULL_TREE;
@@ -95,27 +136,51 @@ cil_init_builtins (void)
   /* Vector types */
   tree float2_type_node = build_vector_type (float_type_node, 2);
   tree float4_type_node = build_vector_type (float_type_node, 4);
+  tree float8_type_node = build_vector_type (float_type_node, 8);
+
   tree double2_type_node = build_vector_type (double_type_node, 2);
-  tree intDI2_type_node = build_vector_type (intDI_type_node, 2);
-  tree intQI4_type_node = build_vector_type (intQI_type_node, 4);
+  tree double4_type_node = build_vector_type (double_type_node, 4);
+
   tree intHI2_type_node = build_vector_type (intHI_type_node, 2);
-  tree intQI8_type_node = build_vector_type (intQI_type_node, 8);
   tree intHI4_type_node = build_vector_type (intHI_type_node, 4);
-  tree intSI2_type_node = build_vector_type (intSI_type_node, 2);
-  tree intSI4_type_node = build_vector_type (intSI_type_node, 4);
   tree intHI8_type_node = build_vector_type (intHI_type_node, 8);
+  tree intHI16_type_node = build_vector_type (intHI_type_node, 16);
+
+  tree intQI4_type_node = build_vector_type (intQI_type_node, 4);
+  tree intQI8_type_node = build_vector_type (intQI_type_node, 8);
   tree intQI16_type_node = build_vector_type (intQI_type_node, 16);
+  tree intQI32_type_node = build_vector_type (intQI_type_node, 32);
+
+  tree intSI2_type_node = build_vector_type (intSI_type_node, 2);
+  tree intSI4_type_node = build_vector_type (intSI_type_node, 4);
+  tree intSI8_type_node = build_vector_type (intSI_type_node, 8);
 
+  tree intDI2_type_node = build_vector_type (intDI_type_node, 2);
+  tree intDI4_type_node = build_vector_type (intDI_type_node, 4);
+
+  /* Pointers to vectors */
   tree V2DF_ptr_type_node = build_pointer_type (double2_type_node);
+  tree V4DF_ptr_type_node = build_pointer_type (double4_type_node);
+
   tree V2SF_ptr_type_node = build_pointer_type (float2_type_node);
   tree V4SF_ptr_type_node = build_pointer_type (float4_type_node);
+  tree V8SF_ptr_type_node = build_pointer_type (float8_type_node);
+
   tree V2DI_ptr_type_node = build_pointer_type (intDI2_type_node);
+  tree V4DI_ptr_type_node = build_pointer_type (intDI4_type_node);
+
   tree V2SI_ptr_type_node = build_pointer_type (intSI2_type_node);
   tree V4SI_ptr_type_node = build_pointer_type (intSI4_type_node);
+  tree V8SI_ptr_type_node = build_pointer_type (intSI8_type_node);
+
   tree V4HI_ptr_type_node = build_pointer_type (intHI4_type_node);
   tree V8HI_ptr_type_node = build_pointer_type (intHI8_type_node);
+  tree V16HI_ptr_type_node = build_pointer_type (intHI16_type_node);
+
+  tree V4QI_ptr_type_node = build_pointer_type (intQI4_type_node);
   tree V8QI_ptr_type_node = build_pointer_type (intQI8_type_node);
   tree V16QI_ptr_type_node = build_pointer_type (intQI16_type_node);
+  tree V32QI_ptr_type_node = build_pointer_type (intQI32_type_node);
 
   /* Complex types */
   tree complex_char_type_node = build_complex_type (char_type_node);
diff --git a/gcc/config/cil32/cil-builtins.def b/gcc/config/cil32/cil-builtins.def
index b91b4890e75..39b2e4d4760 100644
--- a/gcc/config/cil32/cil-builtins.def
+++ b/gcc/config/cil32/cil-builtins.def
@@ -992,16 +992,21 @@ DEF_CILBUILTIN(GCC_V2SI_TO_DI, "[gcc4net]gcc4net.V2SI::V2SI_to_di", ATTR_NULL, \
 	       1, intSI2_type_node)
 
 /* Split vectorization.  */
+DEF_CILBUILTIN(GCC_GET_STRIDE_VDF, "[genvec_support]genvec_support.VDF::stride", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               unsigned_type_node, \
+               0)
+
 DEF_CILBUILTIN(GCC_GET_STRIDE_VSF, "[genvec_support]genvec_support.VSF::stride", \
                ATTR_CONST_NOTHROW_LIST, \
                unsigned_type_node,     \
                0)
-#if 0
+
 DEF_CILBUILTIN(GCC_GET_STRIDE_VDI, "[genvec_support]genvec_support.VDI::stride", \
                ATTR_CONST_NOTHROW_LIST,          \
                unsigned_type_node, \
                0)
-#endif
+
 DEF_CILBUILTIN(GCC_GET_STRIDE_VSI, "[genvec_support]genvec_support.VSI::stride", \
                ATTR_CONST_NOTHROW_LIST, \
                unsigned_type_node,     \
@@ -1018,91 +1023,77 @@ DEF_CILBUILTIN(GCC_GET_STRIDE_VQI, "[genvec_support]genvec_support.VQI::stride",
                0)
 
 /* uniform */
-#if 0
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VDF, "[genvec_support]genvec_support.VDF::VDF_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               double2_type_node, \
+               VDF_type_node, \
                1, \
                double_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VSF, "[genvec_support]genvec_support.VSF::VSF_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               float4_type_node, \
-               1, \
-               float_type_node)
-#endif
-DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VSF, "[genvec_support]genvec_support.VSF::VSF_uniform_vec", \
-               ATTR_CONST_NOTHROW_LIST,        \
-               float2_type_node, \
+               VSF_type_node, \
                1, \
                float_type_node)
-#if 0
+
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VDI, "[genvec_support]genvec_support.VDI::VDI_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intDI2_type_node, \
+               VDI_type_node, \
                1, \
                intDI_type_node)
-#endif
+
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VSI, "[genvec_support]genvec_support.VSI::VSI_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intSI2_type_node, \
+               VSI_type_node, \
                1, \
                intSI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VHI, "[genvec_support]genvec_support.VHI::VHI_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intHI4_type_node, \
+               VHI_type_node, \
                1, \
                intHI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_UNIFORM_VEC_VQI, "[genvec_support]genvec_support.VQI::VQI_uniform_vec", \
                ATTR_CONST_NOTHROW_LIST,         \
-               intQI8_type_node, \
+               VQI_type_node, \
                1, \
                intQI_type_node)
 
 
 /* affine */
-#if 0
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VDF, "[genvec_support]genvec_support.VDF::VDF_affine_vec", \
                ATTR_CONST_NOTHROW_LIST, \
-               double2_type_node, \
+               VDF_type_node, \
                2, \
                double_type_node, double_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VSF, "[genvec_support]genvec_support.VSF::VSF_affine_vec", \
                ATTR_CONST_NOTHROW_LIST, \
-               float4_type_node, \
+               VSF_type_node, \
                2, \
                float_type_node, float_type_node)
-#endif
-DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VSF, "[genvec_support]genvec_support.VSF::VSF_affine_vec", \
-               ATTR_CONST_NOTHROW_LIST, \
-               float2_type_node, \
-               2, \
-               float_type_node, float_type_node)
-#if 0
+
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VDI, "[genvec_support]genvec_support.VDI::VDI_affine_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intDI2_type_node, \
+               VDI_type_node, \
                2, \
                intDI_type_node, integer_type_node)
-#endif
+
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VSI, "[genvec_support]genvec_support.VSI::VSI_affine_vec", \
                ATTR_CONST_NOTHROW_LIST, \
-               intSI2_type_node, \
+               VSI_type_node, \
                2, \
                intSI_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VHI, "[genvec_support]genvec_support.VHI::VHI_affine_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intHI4_type_node, \
+               VHI_type_node, \
                2, \
                intHI_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_AFFINE_VEC_VQI, "[genvec_support]genvec_support.VQI::VQI_affine_vec", \
                ATTR_CONST_NOTHROW_LIST,         \
-               intQI8_type_node, \
+               VQI_type_node, \
                2, \
                intQI_type_node, integer_type_node)
 
@@ -1114,11 +1105,21 @@ DEF_CILBUILTIN(GCC_GET_STEP, "[genvec_support]genvec_support.VQI::get_vec_size",
                0)
 
 /* align */
+DEF_CILBUILTIN(GCC_GET_ALIGN_VDF, "[genvec_support]genvec_support.VDF::VDF_align", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               unsigned_type_node, \
+               0)
+
 DEF_CILBUILTIN(GCC_GET_ALIGN_VSF, "[genvec_support]genvec_support.VSF::VSF_align", \
                ATTR_CONST_NOTHROW_LIST,          \
                unsigned_type_node, \
                0)
 
+DEF_CILBUILTIN(GCC_GET_ALIGN_VDI, "[genvec_support]genvec_support.VDI::VDI_align", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               unsigned_type_node, \
+               0)
+
 DEF_CILBUILTIN(GCC_GET_ALIGN_VSI, "[genvec_support]genvec_support.VSI::VSI_align", \
                ATTR_CONST_NOTHROW_LIST,          \
                unsigned_type_node, \
@@ -1135,77 +1136,95 @@ DEF_CILBUILTIN(GCC_GET_ALIGN_VQI, "[genvec_support]genvec_support.VQI::VQI_align
                0)
 
 /* epilogues */
+DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VDF, "[genvec_support]genvec_support.VDF::VDF_reduc_max_epilogue", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               VDF_type_node, \
+               1,
+               VDF_type_node)
+
+DEF_CILBUILTIN(GCC_BUILD_REDUC_MIN_EPILOGUE_VDF, "[genvec_support]genvec_support.VDF::VDF_reduc_min_epilogue", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               VDF_type_node, \
+               1,
+               VDF_type_node)
+
+DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VDF, "[genvec_support]genvec_support.VDF::VDF_reduc_plus_epilogue", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               VDF_type_node, \
+               1,
+               VDF_type_node)
+
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VSF, "[genvec_support]genvec_support.VSF::VSF_reduc_max_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               float2_type_node, \
+               VSF_type_node, \
                1,
-               float2_type_node)
+               VSF_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MIN_EPILOGUE_VSF, "[genvec_support]genvec_support.VSF::VSF_reduc_min_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               float2_type_node, \
+               VSF_type_node, \
                1,
-               float2_type_node)
+               VSF_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VSF, "[genvec_support]genvec_support.VSF::VSF_reduc_plus_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               float2_type_node, \
+               VSF_type_node, \
                1,
-               float2_type_node)
-#if 0
+               VSF_type_node)
+
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VDI, "[genvec_support]genvec_support.VDI::VDI_reduc_max_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intDI2_type_node, \
+               VDI_type_node, \
                1,
-               intDI2_type_node)
+               VDI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MIN_EPILOGUE_VDI, "[genvec_support]genvec_support.VDI::VDI_reduc_min_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intDI2_type_node, \
+               VDI_type_node, \
                1,
-               intDI2_type_node)
+               VDI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VDI, "[genvec_support]genvec_support.VDI::VDI_reduc_plus_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intDI2_type_node, \
+               VDI_type_node, \
                1,
-               intDI2_type_node)
-#endif
+               VDI_type_node)
+
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VSI, "[genvec_support]genvec_support.VSI::VSI_reduc_max_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intSI2_type_node, \
+               VSI_type_node, \
                1,
-               intSI2_type_node)
+               VSI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MIN_EPILOGUE_VSI, "[genvec_support]genvec_support.VSI::VSI_reduc_min_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intSI2_type_node, \
+               VSI_type_node, \
                1,
-               intSI2_type_node)
+               VSI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VSI, "[genvec_support]genvec_support.VSI::VSI_reduc_plus_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intSI2_type_node, \
+               VSI_type_node, \
                1,
-               intSI2_type_node)
+               VSI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VHI, "[genvec_support]genvec_support.VHI::VHI_reduc_max_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intHI4_type_node, \
+               VHI_type_node, \
                1,
-               intHI4_type_node)
+               VHI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MIN_EPILOGUE_VHI, "[genvec_support]genvec_support.VHI::VHI_reduc_min_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intHI4_type_node, \
+               VHI_type_node, \
                1,
-               intHI4_type_node)
+               VHI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VHI, "[genvec_support]genvec_support.VHI::VHI_reduc_plus_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intHI4_type_node, \
+               VHI_type_node, \
                1,
-               intHI4_type_node)
+               VHI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_REDUC_MAX_EPILOGUE_VQI, "[genvec_support]genvec_support.VQI::VQI_reduc_max_epilogue", \
                ATTR_CONST_NOTHROW_LIST,          \
@@ -1228,16 +1247,26 @@ DEF_CILBUILTIN(GCC_BUILD_REDUC_PLUS_EPILOGUE_VQI, "[genvec_support]genvec_suppor
 /* mask */
 DEF_CILBUILTIN(GCC_MASK_FOR_LOAD, "[genvec_support]genvec_support.VQI::VQI_mask_for_load", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intQI16_type_node, \
+               VQI_type_node, \
                3,
-               V16QI_ptr_type_node, integer_type_node, integer_type_node)
+               VQI_ptr_type_node, integer_type_node, integer_type_node)
 
 /* realign offset */
+DEF_CILBUILTIN(GCC_REALIGN_OFFSET_VDF, "[genvec_support]genvec_support.VDF::VDF_realign_offset", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               unsigned_type_node, \
+               0)
+
 DEF_CILBUILTIN(GCC_REALIGN_OFFSET_VSF, "[genvec_support]genvec_support.VSF::VSF_realign_offset", \
                ATTR_CONST_NOTHROW_LIST,          \
                unsigned_type_node, \
                0)
 
+DEF_CILBUILTIN(GCC_REALIGN_OFFSET_VDI, "[genvec_support]genvec_support.VDI::VDI_realign_offset", \
+               ATTR_CONST_NOTHROW_LIST,          \
+               unsigned_type_node, \
+               0)
+
 DEF_CILBUILTIN(GCC_REALIGN_OFFSET_VSI, "[genvec_support]genvec_support.VSI::VSI_realign_offset", \
                ATTR_CONST_NOTHROW_LIST,          \
                unsigned_type_node, \
@@ -1264,9 +1293,9 @@ DEF_CILBUILTIN(GCC_GET_LOOP_NITERS, "[genvec_support]genvec_support.VQI::VI_get_
 
 DEF_CILBUILTIN(GEN_DOT_PRODUCT_VSI, "[genvec_support]genvec_support.VSI::VSI_dot_product", \
                ATTR_CONST_NOTHROW_LIST,          \
-               intSI4_type_node, \
+               VSI_type_node, \
                3,
-               intHI8_type_node, intHI8_type_node, intSI4_type_node)
+               VHI_type_node, VHI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_DOT_PRODUCT_VHI, "[genvec_support]genvec_support.VHI::VHI_dot_product", \
                ATTR_CONST_NOTHROW_LIST,          \
@@ -1275,320 +1304,405 @@ DEF_CILBUILTIN(GEN_DOT_PRODUCT_VHI, "[genvec_support]genvec_support.VHI::VHI_dot
                intQI16_type_node, intQI16_type_node, intHI8_type_node)
 
 /* init */
+DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VDF, "[genvec_support]genvec_support.VDF::VDF_init_vec", \
+               ATTR_CONST_NOTHROW_LIST,        \
+               VDF_type_node, \
+               2, \
+               double_type_node, double_type_node)
+
 DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VSF, "[genvec_support]genvec_support.VSF::VSF_init_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               float2_type_node, \
+               VSF_type_node, \
                2, \
                float_type_node, float_type_node)
 
+DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VDI, "[genvec_support]genvec_support.VDI::VDI_init_vec", \
+               ATTR_CONST_NOTHROW_LIST,        \
+               VDI_type_node, \
+               2, \
+               intDI_type_node, intDI_type_node)
+
 DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VSI, "[genvec_support]genvec_support.VSI::VSI_init_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intSI2_type_node, \
+               VSI_type_node, \
                2, \
                intSI_type_node, intSI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VHI, "[genvec_support]genvec_support.VHI::VHI_init_vec", \
                ATTR_CONST_NOTHROW_LIST,        \
-               intHI4_type_node, \
+               VHI_type_node, \
                2, \
                intHI_type_node, intHI_type_node)
 
 DEF_CILBUILTIN(GCC_BUILD_INIT_VEC_VQI, "[genvec_support]genvec_support.VQI::VQI_init_vec", \
                ATTR_CONST_NOTHROW_LIST,         \
-               intQI8_type_node, \
+               VQI_type_node, \
                2, \
                intQI_type_node, intQI_type_node)
 
+/* V DF */
+DEF_CILBUILTIN(GEN_VDF_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenDF::.ctor", \
+               ATTR_CONST_NOTHROW_LIST, \
+	       VDF_type_node,   \
+	       1, double_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_LOAD_ALIGNED, \
+	       "[Xxxx.Simd]Xxxx.Simd.VecGenDF::LoadAligned", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       1, \
+	       VDF_ptr_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_REALIGN_LOAD, \
+	       "[genvec_support]genvec_support.VDF::RealignLoad", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       6, \
+	       VDF_type_node, VDF_type_node, VDF_type_node, VDF_ptr_type_node, integer_type_node, integer_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_STORE_ALIGNED,
+	       "[Xxxx.Simd]Xxxx.Simd.VecGenDF::StoreAligned", \
+               ATTR_NULL,      \
+	       void_type_node, \
+	       2, \
+	       VDF_ptr_type_node, VDF_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_ALOAD, \
+	       "[genvec_support]genvec_support.VDF::ALoad", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       1, \
+	       VDF_ptr_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_ADD, "[Xxxx.Simd]Xxxx.Simd.VecGenDF::op_Addition", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       2, \
+	       VDF_type_node, VDF_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_SUB, "[Xxxx.Simd]Xxxx.Simd.VecGenDF::op_Subtraction", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       2, \
+	       VDF_type_node, VDF_type_node)
+
+DEF_CILBUILTIN(GEN_VDF_MUL, "[Xxxx.Simd]Xxxx.Simd.VecGenDF::op_Multiply", \
+               ATTR_NULL,        \
+	       VDF_type_node, \
+	       2, \
+	       VDF_type_node, VDF_type_node)
+
 
 /* V SF */
 DEF_CILBUILTIN(GEN_VSF_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenSF::.ctor", \
                ATTR_CONST_NOTHROW_LIST, \
-	       float2_type_node,   \
+	       VSF_type_node,   \
 	       1, float_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_LOAD_ALIGNED, \
 	       "[Xxxx.Simd]Xxxx.Simd.VecGenSF::LoadAligned", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       1, \
-	       V2SF_ptr_type_node)
+	       VSF_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_ALOAD, \
 	       "[genvec_support]genvec_support.VSF::ALoad", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       1, \
-	       V2SF_ptr_type_node)
+	       VSF_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_REALIGN_LOAD, \
 	       "[genvec_support]genvec_support.VSF::RealignLoad", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       6, \
-	       float2_type_node, float2_type_node, float2_type_node, V2SF_ptr_type_node, integer_type_node, integer_type_node)
+	       VSF_type_node, VSF_type_node, VSF_type_node, VSF_ptr_type_node, integer_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_STORE_ALIGNED,
 	       "[Xxxx.Simd]Xxxx.Simd.VecGenSF::StoreAligned", \
                ATTR_NULL,      \
 	       void_type_node, \
 	       2, \
-	       V2SF_ptr_type_node, float2_type_node)
+	       VSF_ptr_type_node, VSF_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_ADD, "[Xxxx.Simd]Xxxx.Simd.VecGenSF::op_Addition", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       2, \
-	       float2_type_node, float2_type_node)
+	       VSF_type_node, VSF_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_SUB, "[Xxxx.Simd]Xxxx.Simd.VecGenSF::op_Subtraction", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       2, \
-	       float2_type_node, float2_type_node)
+	       VSF_type_node, VSF_type_node)
 DEF_CILBUILTIN(GEN_VSF_MUL, "[Xxxx.Simd]Xxxx.Simd.VecGenSF::op_Multiply", \
                ATTR_NULL,        \
-	       float2_type_node, \
+	       VSF_type_node, \
 	       2, \
-	       float2_type_node, float2_type_node)
+	       VSF_type_node, VSF_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_MIN, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Min", \
                ATTR_NULL,                                               \
-               float2_type_node,                                        \
-               2, float2_type_node, float2_type_node)
+               VSF_type_node,                                        \
+               2, VSF_type_node, VSF_type_node)
 
 DEF_CILBUILTIN(GEN_VSF_MAX, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Max", \
                ATTR_NULL,                                               \
-               float2_type_node,                                        \
-               2, float2_type_node, float2_type_node)
+               VSF_type_node,                                        \
+               2, VSF_type_node, VSF_type_node)
+
+/* V DI */
+DEF_CILBUILTIN(GEN_VDI_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenDI::.ctor", \
+               ATTR_NULL,        \
+	       VDI_type_node, \
+	       1, intDI_type_node)
+
+DEF_CILBUILTIN(GEN_VDI_LOAD_ALIGNED, \
+	       "[Xxxx.Simd]Xxxx.Simd.VecGenDI::LoadAligned", \
+               ATTR_NULL,        \
+	       VDI_type_node, \
+	       1, \
+	       VDI_ptr_type_node)
+
+DEF_CILBUILTIN(GEN_VDI_ALOAD, \
+	       "[genvec_support]genvec_support.VDI::ALoad", \
+               ATTR_NULL,        \
+	       VDI_type_node, \
+	       1, \
+	       VDI_ptr_type_node)
+
 
 /* V SI */
 DEF_CILBUILTIN(GEN_VSI_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::.ctor", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       1, intSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_LOAD_ALIGNED, \
 	       "[Xxxx.Simd]Xxxx.Simd.VecGenSI::LoadAligned", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       1, \
-	       V2SI_ptr_type_node)
+	       VSI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_ALOAD, \
 	       "[genvec_support]genvec_support.VSI::ALoad", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       1, \
-	       V2SI_ptr_type_node)
+	       VSI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_REALIGN_LOAD, \
 	       "[genvec_support]genvec_support.VSI::RealignLoad", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       6, \
-	       intSI2_type_node, intSI2_type_node, intSI2_type_node, V2SI_ptr_type_node, integer_type_node, integer_type_node)
+	       VSI_type_node, VSI_type_node, VSI_type_node, VSI_ptr_type_node, integer_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_STORE_ALIGNED,
 	       "[Xxxx.Simd]Xxxx.Simd.VecGenSI::StoreAligned", \
                ATTR_NULL,      \
 	       void_type_node, \
 	       2, \
-	       V2SI_ptr_type_node, intSI2_type_node)
+	       VSI_ptr_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_ADD, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_Addition", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_SUB, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_Subtraction", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_MUL, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_Multiply", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_AND, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_BitwiseAnd", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_OR, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_BitwiseOr", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_XOR, "[Xxxx.Simd]Xxxx.Simd.VecGenSI::op_ExclusiveOr", \
                ATTR_NULL,        \
-	       intSI2_type_node, \
+	       VSI_type_node, \
 	       2, \
-	       intSI2_type_node, intSI2_type_node)
+	       VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_MIN, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Min ", \
                ATTR_NULL,                                               \
-               intSI2_type_node,                                        \
-               2, intSI2_type_node, intSI2_type_node)
+               VSI_type_node,                                        \
+               2, VSI_type_node, VSI_type_node)
 
 DEF_CILBUILTIN(GEN_VSI_MAX, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Max ", \
                ATTR_NULL,                                               \
-               intSI2_type_node,                                        \
-               2, intSI2_type_node, intSI2_type_node)
+               VSI_type_node,                                        \
+               2, VSI_type_node, VSI_type_node)
 
 /* V HI */
 DEF_CILBUILTIN(GEN_VHI_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::.ctor", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       1, intHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_LOAD_ALIGNED, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::LoadAligned", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       1, \
-	       V4HI_ptr_type_node)
+	       VHI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_ALOAD, "[genvec_support]genvec_support.VHI::ALoad", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       1, \
-	       V4HI_ptr_type_node)
+	       VHI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_REALIGN_LOAD, \
 	       "[genvec_support]genvec_support.VHI::RealignLoad", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       6, \
-	       intHI4_type_node, intHI4_type_node, intHI4_type_node, V4HI_ptr_type_node, integer_type_node, integer_type_node)
+	       VHI_type_node, VHI_type_node, VHI_type_node, VHI_ptr_type_node, integer_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_STORE_ALIGNED, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::StoreAligned", \
                ATTR_NULL,      \
 	       void_type_node, \
 	       2, \
-	       V4HI_ptr_type_node, intHI4_type_node)
+	       VHI_ptr_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_ADD, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_Addition", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_SUB, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_Subtraction", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_MUL, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_Multiply",\
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_AND, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_BitwiseAnd",\
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_OR, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_BitwiseOr", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_XOR, "[Xxxx.Simd]Xxxx.Simd.VecGenHI::op_ExclusiveOr", \
                ATTR_NULL,        \
-	       intHI4_type_node, \
+	       VHI_type_node, \
 	       2, \
-	       intHI4_type_node, intHI4_type_node)
+	       VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_MIN, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Min  ", \
                ATTR_NULL,                                               \
-               intHI4_type_node,                                        \
-               2, intHI4_type_node, intHI4_type_node)
+               VHI_type_node,                                        \
+               2, VHI_type_node, VHI_type_node)
 
 DEF_CILBUILTIN(GEN_VHI_MAX, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Max  ", \
                ATTR_NULL,                                               \
-               intHI4_type_node,                                        \
-               2, intHI4_type_node, intHI4_type_node)
+               VHI_type_node,                                        \
+               2, VHI_type_node, VHI_type_node)
 
 /* V QI */
 DEF_CILBUILTIN(GEN_VQI_CTOR, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::.ctor", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       1, intQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_LOAD_ALIGNED, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::LoadAligned", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
-	       1, V8QI_ptr_type_node)
+	       VQI_type_node, \
+	       1, VQI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_ALOAD, "[genvec_support]genvec_support.VQI::ALoad", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
-	       1, V8QI_ptr_type_node)
+	       VQI_type_node, \
+	       1, VQI_ptr_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_REALIGN_LOAD, \
 	       "[genvec_support]genvec_support.VQI::RealignLoad", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       6, \
-	       intQI8_type_node, intQI8_type_node, intQI8_type_node, V8QI_ptr_type_node, integer_type_node, integer_type_node)
+	       VQI_type_node, VQI_type_node, VQI_type_node, VQI_ptr_type_node, integer_type_node, integer_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_STORE_ALIGNED, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::StoreAligned", \
                ATTR_NULL,      \
 	       void_type_node, \
 	       2, \
-	       V8QI_ptr_type_node, intQI8_type_node)
+	       VQI_ptr_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_ADD, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_Addition", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_SUB, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_Subtraction", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_MUL, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_Multiply",\
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_AND, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_BitwiseAnd",\
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_OR, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_BitwiseOr", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_XOR, "[Xxxx.Simd]Xxxx.Simd.VecGenQQQI::op_ExclusiveOr", \
                ATTR_NULL,        \
-	       intQI8_type_node, \
+	       VQI_type_node, \
 	       2, \
-	       intQI8_type_node, intQI8_type_node)
+	       VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_MIN, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Min   ", \
                ATTR_NULL,                                               \
-               intQI8_type_node,                                        \
-               2, intQI8_type_node, intQI8_type_node)
+               VQI_type_node,                                        \
+               2, VQI_type_node, VQI_type_node)
 
 DEF_CILBUILTIN(GEN_VQI_MAX, "[Xxxx.Simd]Xxxx.Simd.VectorOperations::Max   ", \
                ATTR_NULL,                                               \
-               intQI8_type_node,                                        \
-               2, intQI8_type_node, intQI8_type_node)
+               VQI_type_node,                                        \
+               2, VQI_type_node, VQI_type_node)
diff --git a/gcc/config/cil32/cil-dump.c b/gcc/config/cil32/cil-dump.c
index 80e1d99dcb4..8e8fd4727f3 100644
--- a/gcc/config/cil32/cil-dump.c
+++ b/gcc/config/cil32/cil-dump.c
@@ -1,6 +1,6 @@
 /* CIL IR dump.
 
-   Copyright (C) 2009 Free Software Foundation, Inc.
+   Copyright (C) 2009-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -59,7 +59,7 @@ static const char* const cil_names[] = {
 #undef CIL_INSTRDEF
 };
 
-static const char* const cil_type_names[] = {
+const char* const cil_type_names[] = {
 #define CIL_TYPEDEF(A,B) B,
 #include "cil-types.def"
 #undef CIL_TYPEDEF
diff --git a/gcc/config/cil32/cil-lower.c b/gcc/config/cil32/cil-lower.c
index 1a93f17a161..45b402609fe 100644
--- a/gcc/config/cil32/cil-lower.c
+++ b/gcc/config/cil32/cil-lower.c
@@ -54,6 +54,8 @@ Erven Rohou             <erven.rohou@inria.fr>
 
 enum simd_backend simd_type = UNDEF_SIMD;
 
+extern const char* const cil_type_names[];
+
 /******************************************************************************
  * Local function prototypes                                                  *
  ******************************************************************************/
@@ -109,7 +111,8 @@ lower_cil_vector_ctor (const_cil_stmt ctor)
             case CIL_V8QI: builtin = CIL32_GCC_V8QI_CTOR_U; break;
             case CIL_V2SF: builtin = CIL32_GCC_V2SF_CTOR_U; break;
             default:
-              internal_error ("Vector type expected, seen %d", cil_type);
+              internal_error ("Vector type expected, seen %s",
+                              cil_type_names [cil_type]);
             }
         }
       else
@@ -178,23 +181,37 @@ lower_cil_vector_ctor (const_cil_stmt ctor)
         {
         case CIL_V2SI:
 	case CIL_V4SI:
+        case CIL_V8SI:
+        case CIL_V16SI:
           builtin = CIL32_GEN_VSI_CTOR;
           break;
         case CIL_V4HI:
 	case CIL_V8HI:
+        case CIL_V16HI:
+	case CIL_V32HI:
           builtin = CIL32_GEN_VHI_CTOR;
           break;
         case CIL_V8QI:
 	case CIL_V16QI:
+        case CIL_V32QI:
+	case CIL_V64QI:
           builtin = CIL32_GEN_VQI_CTOR;
           break;
         case CIL_V2SF:
 	case CIL_V4SF:
+	case CIL_V8SF:
+	case CIL_V16SF:
           builtin = CIL32_GEN_VSF_CTOR;
           break;
 
+        case CIL_V2DF:
+        case CIL_V4DF:
+          builtin = CIL32_GEN_VDF_CTOR;
+          break;
+
 	default:
-	  internal_error ("Vector type expected, seen %d", cil_type);
+	  internal_error ("Vector type expected, seen %s",
+                          cil_type_names [cil_type]);
 	}
 
       return cil_build_newobj (cil32_builtins[builtin]);
@@ -233,11 +250,41 @@ lower_cil_ldvec (const_cil_stmt stmt)
     {
       switch (cil_type)
         {
-        case CIL_V2SF: builtin = CIL32_GEN_VSF_LOAD_ALIGNED; break;
-        case CIL_V2SI: builtin = CIL32_GEN_VSI_LOAD_ALIGNED; break;
-        case CIL_V4HI: builtin = CIL32_GEN_VHI_LOAD_ALIGNED; break;
-        case CIL_V8QI: builtin = CIL32_GEN_VQI_LOAD_ALIGNED; break;
+        case CIL_V2SF:
+        case CIL_V4SF:
+        case CIL_V8SF:
+        case CIL_V16SF:
+          builtin = CIL32_GEN_VSF_LOAD_ALIGNED;
+          break;
+
+        case CIL_V2DF:
+        case CIL_V4DF:
+          builtin = CIL32_GEN_VDF_LOAD_ALIGNED;
+          break;
+
+        case CIL_V2SI:
+        case CIL_V4SI:
+        case CIL_V8SI:
+        case CIL_V16SI:
+          builtin = CIL32_GEN_VSI_LOAD_ALIGNED;
+          break;
+
+        case CIL_V4HI:
+        case CIL_V8HI:
+        case CIL_V16HI:
+        case CIL_V32HI:
+          builtin = CIL32_GEN_VHI_LOAD_ALIGNED;
+          break;
+
+        case CIL_V8QI:
+        case CIL_V16QI:
+        case CIL_V32QI:
+        case CIL_V64QI:
+          builtin = CIL32_GEN_VQI_LOAD_ALIGNED;
+          break;
+
         default:
+          fprintf (stderr, "In lower_cil_ldvec: %s\n", cil_type_names [cil_type]);
           gcc_unreachable ();
         }
 
@@ -263,35 +310,46 @@ lower_cil_aldvec (const_cil_stmt stmt)
 
   switch (cil_type)
     {
-    /* case CIL_V2DF: */
-    /*   builtin = CIL32_GEN_VDF_ALOAD; */
-    /*   break; */
+    case CIL_V2DF:
+    case CIL_V4DF:
+      builtin = CIL32_GEN_VDF_ALOAD;
+      break;
 
     case CIL_V2SF:
     case CIL_V4SF:
+    case CIL_V8SF:
+    case CIL_V16SF:
       builtin = CIL32_GEN_VSF_ALOAD;
       break;
 
-    /* case CIL_V2DI: */
-    /*   builtin = CIL32_GEN_VDI_ALOAD; */
-    /*   break; */
+    case CIL_V2DI:
+    case CIL_V4DI:
+      builtin = CIL32_GEN_VDI_ALOAD;
+      break;
 
     case CIL_V2SI:
     case CIL_V4SI:
+    case CIL_V8SI:
+    case CIL_V16SI:
       builtin = CIL32_GEN_VSI_ALOAD;
       break;
 
     case CIL_V4HI:
     case CIL_V8HI:
+    case CIL_V16HI:
+    case CIL_V32HI:
       builtin = CIL32_GEN_VHI_ALOAD;
       break;
 
     case CIL_V8QI:
     case CIL_V16QI:
+    case CIL_V32QI:
+    case CIL_V64QI:
       builtin = CIL32_GEN_VQI_ALOAD;
       break;
 
     default:
+      fprintf (stderr, "In lower_cil_aldvec: %s\n", cil_type_names [cil_type]);
       gcc_unreachable ();
     }
 
@@ -330,11 +388,42 @@ lower_cil_stvec (const_cil_stmt stmt)
     {
       switch (cil_type)
 	{
-	case CIL_V2SF: builtin = CIL32_GEN_VSF_STORE_ALIGNED; break;
-	case CIL_V2SI: builtin = CIL32_GEN_VSI_STORE_ALIGNED; break;
-	case CIL_V4HI: builtin = CIL32_GEN_VHI_STORE_ALIGNED; break;
-	case CIL_V8QI: builtin = CIL32_GEN_VQI_STORE_ALIGNED; break;
+	case CIL_V2DF:
+        case CIL_V4DF:
+          builtin = CIL32_GEN_VDF_STORE_ALIGNED;
+          break;
+
+	case CIL_V2SF:
+        case CIL_V4SF:
+        case CIL_V8SF:
+        case CIL_V16SF:
+          builtin = CIL32_GEN_VSF_STORE_ALIGNED;
+          break;
+
+	case CIL_V2SI:
+        case CIL_V4SI:
+        case CIL_V8SI:
+        case CIL_V16SI:
+          builtin = CIL32_GEN_VSI_STORE_ALIGNED;
+          break;
+
+	case CIL_V4HI:
+	case CIL_V8HI:
+	case CIL_V16HI:
+	case CIL_V32HI:
+          builtin = CIL32_GEN_VHI_STORE_ALIGNED;
+          break;
+
+	case CIL_V8QI:
+	case CIL_V16QI:
+	case CIL_V32QI:
+	case CIL_V64QI:
+          builtin = CIL32_GEN_VQI_STORE_ALIGNED;
+          break;
+
 	default:
+          fprintf (stderr, "In lower_cil_stvec: %s\n",
+                   cil_type_names [cil_type]);
 	  gcc_unreachable ();
 	}
 
@@ -387,19 +476,29 @@ lower_cil_vector_add (cil_type_t type)
   else  /* simd_type == GENERIC_SIMD */
     switch (type)
       {
-        /* 64-bit vectors */
+        /* 64-bit */
       case CIL_V2SF: builtin = CIL32_GEN_VSF_ADD; break;
       case CIL_V2SI: builtin = CIL32_GEN_VSI_ADD; break;
       case CIL_V4HI: builtin = CIL32_GEN_VHI_ADD; break;
       case CIL_V8QI: builtin = CIL32_GEN_VQI_ADD; break;
 
-        /* if in 128-bit mode */
+        /* 128-bit */
       case CIL_V4SI: builtin = CIL32_GEN_VSI_ADD; break;
       case CIL_V8HI: builtin = CIL32_GEN_VHI_ADD; break;
       case CIL_V16QI: builtin = CIL32_GEN_VQI_ADD; break;
       case CIL_V4SF: builtin = CIL32_GEN_VSF_ADD; break;
+      case CIL_V2DF: builtin = CIL32_GEN_VDF_ADD; break;
+
+        /* 256-bit */
+      case CIL_V8SI: builtin = CIL32_GEN_VSI_ADD; break;
+      case CIL_V16HI: builtin = CIL32_GEN_VHI_ADD; break;
+      case CIL_V32QI: builtin = CIL32_GEN_VQI_ADD; break;
+      case CIL_V8SF: builtin = CIL32_GEN_VSF_ADD; break;
+      case CIL_V4DF: builtin = CIL32_GEN_VDF_ADD; break;
 
       default:
+        fprintf (stderr, "In lower_cil_vector_add: %s\n",
+                 cil_type_names [type]);
         gcc_unreachable ();
       }
 
@@ -449,18 +548,29 @@ lower_cil_vector_sub (cil_type_t type)
   else  /* simd_type == GENERIC_SIMD */
     switch (type)
       {
-        /* 64-bit vectors */
+        /* 64-bit */
       case CIL_V2SF: builtin = CIL32_GEN_VSF_SUB; break;
       case CIL_V2SI: builtin = CIL32_GEN_VSI_SUB; break;
       case CIL_V4HI: builtin = CIL32_GEN_VHI_SUB; break;
       case CIL_V8QI: builtin = CIL32_GEN_VQI_SUB; break;
 
-        /* if in 128-bit mode */
+        /* 128-bit */
       case CIL_V4SI: builtin = CIL32_GEN_VSI_SUB; break;
       case CIL_V8HI: builtin = CIL32_GEN_VHI_SUB; break;
       case CIL_V16QI: builtin = CIL32_GEN_VQI_SUB; break;
       case CIL_V4SF: builtin = CIL32_GEN_VSF_SUB; break;
+      case CIL_V2DF: builtin = CIL32_GEN_VDF_SUB; break;
+
+        /* 256-bit */
+      case CIL_V8SI: builtin = CIL32_GEN_VSI_SUB; break;
+      case CIL_V16HI: builtin = CIL32_GEN_VHI_SUB; break;
+      case CIL_V32QI: builtin = CIL32_GEN_VQI_SUB; break;
+      case CIL_V8SF: builtin = CIL32_GEN_VSF_SUB; break;
+      case CIL_V4DF: builtin = CIL32_GEN_VDF_SUB; break;
+
       default:
+        fprintf (stderr, "In lower_cil_vector_sub: %s\n",
+                 cil_type_names [type]);
         gcc_unreachable ();
       }
 
@@ -510,18 +620,29 @@ lower_cil_vector_mul (cil_type_t type)
   else  /* simd_type == GENERIC_SIMD */
     switch (type)
       {
-        /* 64-bit vectors */
+        /* 64-bit */
       case CIL_V2SF: builtin = CIL32_GEN_VSF_MUL; break;
       case CIL_V2SI: builtin = CIL32_GEN_VSI_MUL; break;
       case CIL_V4HI: builtin = CIL32_GEN_VHI_MUL; break;
       case CIL_V8QI: builtin = CIL32_GEN_VQI_MUL; break;
 
-        /* if in 128-bit mode */
+        /* 128-bit */
       case CIL_V4SI: builtin = CIL32_GEN_VSI_MUL; break;
       case CIL_V8HI: builtin = CIL32_GEN_VHI_MUL; break;
       case CIL_V16QI: builtin = CIL32_GEN_VQI_MUL; break;
       case CIL_V4SF: builtin = CIL32_GEN_VSF_MUL; break;
+      case CIL_V2DF: builtin = CIL32_GEN_VDF_MUL; break;
+
+        /* 256-bit */
+      case CIL_V8SI: builtin = CIL32_GEN_VSI_MUL; break;
+      case CIL_V16HI: builtin = CIL32_GEN_VHI_MUL; break;
+      case CIL_V32QI: builtin = CIL32_GEN_VQI_MUL; break;
+      case CIL_V8SF: builtin = CIL32_GEN_VSF_MUL; break;
+      case CIL_V4DF: builtin = CIL32_GEN_VDF_MUL; break;
+
       default:
+        fprintf (stderr, "In lower_cil_vector_mul: %s\n",
+                 cil_type_names [type]);
         gcc_unreachable ();
       }
 
@@ -564,7 +685,10 @@ lower_cil_vector_and (cil_type_t type)
         gcc_unreachable ();
       }
   else
-    internal_error ("AND operator not defined yet\n");
+    {
+      fprintf (stderr, "In lower_cil_vector_and: %s\n", cil_type_names [type]);
+      internal_error ("AND operator not defined yet\n");
+    }
 
   return cil_build_call (cil32_builtins[builtin]);
 }
@@ -605,7 +729,10 @@ lower_cil_vector_or (cil_type_t type)
         gcc_unreachable ();
       }
   else
-    internal_error ("OR operator not defined yet\n");
+    {
+      fprintf (stderr, "In lower_cil_vector_or: %s\n", cil_type_names [type]);
+      internal_error ("OR operator not defined yet\n");
+    }
 
   return cil_build_call (cil32_builtins[builtin]);
 }
@@ -646,7 +773,10 @@ lower_cil_vector_xor (cil_type_t type)
         gcc_unreachable ();
       }
   else
-    internal_error ("XOR operator not defined yet\n");
+    {
+      fprintf (stderr, "In lower_cil_vector_xor: %s\n", cil_type_names [type]);
+      internal_error ("XOR operator not defined yet\n");
+    }
 
   return cil_build_call (cil32_builtins[builtin]);
 }
diff --git a/gcc/config/cil32/cil-stack.c b/gcc/config/cil32/cil-stack.c
index 8f542ce9065..21e559c8320 100644
--- a/gcc/config/cil32/cil-stack.c
+++ b/gcc/config/cil32/cil-stack.c
@@ -1,6 +1,6 @@
 /* Implementation of the stack information functionality.
 
-   Copyright (C) 2006-2009 Free Software Foundation, Inc.
+   Copyright (C) 2006-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -505,16 +505,32 @@ cil_vector_p (cil_type_t type)
 {
   switch (type)
     {
+      /* 8-byte */
     case CIL_V2SI:
     case CIL_V4HI:
     case CIL_V8QI:
     case CIL_V2SF:
+      /* 16-byte */
     case CIL_V2DI:
     case CIL_V4SI:
     case CIL_V8HI:
     case CIL_V16QI:
     case CIL_V4SF:
     case CIL_V2DF:
+      /* 32-byte */
+    case CIL_V4DI:
+    case CIL_V8SI:
+    case CIL_V16HI:
+    case CIL_V32QI:
+    case CIL_V8SF:
+    case CIL_V4DF:
+      /* 64-byte */
+    case CIL_V8DI:
+    case CIL_V16SI:
+    case CIL_V32HI:
+    case CIL_V64QI:
+    case CIL_V16SF:
+    case CIL_V8DF:
       return true;
 
     default:
@@ -695,40 +711,63 @@ vector_to_cil (const_tree type)
   if ((TREE_CODE (innertype) == INTEGER_TYPE) ||
       (TREE_CODE (innertype) == POINTER_TYPE))
     {
-      if (vec_size == 128)  /* 16-byte vectors */
-	{
-	  switch (innersize)
-	    {
-	    case  8: ret = CIL_V16QI; break;
-	    case 16: ret = CIL_V8HI;  break;
-	    case 32: ret = CIL_V4SI;  break;
-	    case 64: ret = CIL_V2DI;  break;
-	    default: break;
-	    }
-	}
-      else if (vec_size == 64)  /* 8-byte vectors */
-	{
-	  switch (innersize)
-	    {
-	    case  8: ret = CIL_V8QI; break;
-	    case 16: ret = CIL_V4HI;  break;
-	    case 32: ret = CIL_V2SI;  break;
-	    default: break;
-	    }
-	}
-      else if (vec_size == 32)  /* 4-byte vectors */
-	{
-	  switch (innersize)
-	    {
-	    case  8: ret = CIL_V4QI; break;
-	    case 16: ret = CIL_V2HI;  break;
-	    default: break;
-	    }
-	}
+      switch (vec_size)
+        {
+        case 256:  /* 32-byte vectors */
+          switch (innersize)
+            {
+            case  8: ret = CIL_V32QI; break;
+            case 16: ret = CIL_V16HI; break;
+            case 32: ret = CIL_V8SI;  break;
+            case 64: ret = CIL_V4DI;  break;
+            default: break;
+            }
+          break;
+
+        case 128:  /* 16-byte vectors */
+          switch (innersize)
+            {
+            case  8: ret = CIL_V16QI; break;
+            case 16: ret = CIL_V8HI;  break;
+            case 32: ret = CIL_V4SI;  break;
+            case 64: ret = CIL_V2DI;  break;
+            default: break;
+            }
+          break;
+
+        case 64:  /* 8-byte vectors */
+          switch (innersize)
+            {
+            case  8: ret = CIL_V8QI; break;
+            case 16: ret = CIL_V4HI; break;
+            case 32: ret = CIL_V2SI; break;
+            default: break;
+            }
+          break;
+
+        case 32:  /* 4-byte vectors */
+          switch (innersize)
+            {
+            case  8: ret = CIL_V4QI; break;
+            case 16: ret = CIL_V2HI; break;
+            default: break;
+            }
+          break;
+
+        default:
+          break;
+        }
     }
   else if (TREE_CODE (innertype) == REAL_TYPE)
     {
-      if (vec_size == 128)
+      if (vec_size == 256)
+        {
+	  if (innersize == 32)
+	    ret = CIL_V8SF;
+	  else if (innersize == 64)
+	    ret = CIL_V4DF;
+        }
+      else if (vec_size == 128)
 	{
 	  if (innersize == 32)
 	    ret = CIL_V4SF;
diff --git a/gcc/config/cil32/cil-types.def b/gcc/config/cil32/cil-types.def
index 720095c02ce..5ea68233853 100644
--- a/gcc/config/cil32/cil-types.def
+++ b/gcc/config/cil32/cil-types.def
@@ -1,6 +1,6 @@
 /*
 
-   Copyright (C) 2006-2009 Free Software Foundation, Inc.
+   Copyright (C) 2006-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -84,6 +84,22 @@ CIL_TYPEDEF(CIL_V16QI,"V16QI")  /* Vector of 16 8-bit integers */
 CIL_TYPEDEF(CIL_V2DF,"V2DF")    /* Vector of 2 64-bit double precision floats */
 CIL_TYPEDEF(CIL_V4SF,"V4SF")    /* Vector of 4 32-bit single precision floats */
 
+/* 32-byte vector types */
+CIL_TYPEDEF(CIL_V4DI,"V4DI")    /* Vector of 4 64-bit integers */
+CIL_TYPEDEF(CIL_V8SI,"V8SI")    /* Vector of 8 32-bit integers */
+CIL_TYPEDEF(CIL_V16HI,"V16HI")  /* Vector of 16 16-bit integers */
+CIL_TYPEDEF(CIL_V32QI,"V32QI")  /* Vector of 32 8-bit integers */
+CIL_TYPEDEF(CIL_V4DF,"V4DF")    /* Vector of 4 64-bit double precision floats */
+CIL_TYPEDEF(CIL_V8SF,"V8SF")    /* Vector of 8 32-bit single precision floats */
+
+/* 64-byte vector types */
+CIL_TYPEDEF(CIL_V8DI,"V8DI")    /* Vector of 8 64-bit integers */
+CIL_TYPEDEF(CIL_V16SI,"V16SI")  /* Vector of 16 32-bit integers */
+CIL_TYPEDEF(CIL_V32HI,"V32HI")  /* Vector of 32 16-bit integers */
+CIL_TYPEDEF(CIL_V64QI,"V64QI")  /* Vector of 64 8-bit integers */
+CIL_TYPEDEF(CIL_V8DF,"V8DF")    /* Vector of 8 64-bit double precision floats */
+CIL_TYPEDEF(CIL_V16SF,"V16SF")  /* Vector of 16 32-bit single precision floats */
+
 /* Integer Complex Types*/
 /* Complex of Signed 8-bit integer */
 CIL_TYPEDEF(CIL_CMPLXI8,"valuetype [gcc4net]gcc4net.complex_char")
diff --git a/gcc/config/cil32/cil32-modes.def b/gcc/config/cil32/cil32-modes.def
index dccb77df965..89a7a702fe2 100644
--- a/gcc/config/cil32/cil32-modes.def
+++ b/gcc/config/cil32/cil32-modes.def
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GCC for CIL32.
 
-   Copyright (C) 2006, 2009 Free Software Foundation, Inc.
+   Copyright (C) 2006, 2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -35,11 +35,21 @@ Erven Rohou             <erven.rohou@inria.fr>
 VECTOR_MODES (INT, 4);        /*            V4QI V2HI */
 VECTOR_MODES (INT, 8);        /*       V8QI V4HI V2SI */
 VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI */
+VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
+VECTOR_MODES (INT, 64);       /* V64QI V32HI V16SI V8DI */
+
 VECTOR_MODES (FLOAT, 8);      /*            V4HF V2SF */
 VECTOR_MODES (FLOAT, 16);     /*       V8HF V4SF V2DF */
+
+#if 0
 VECTOR_MODE (INT, DI, 4);     /*                 V4DI */
 VECTOR_MODE (INT, SI, 8);     /*                 V8SI */
 VECTOR_MODE (INT, HI, 16);    /*                V16HI */
 VECTOR_MODE (INT, QI, 32);    /*                V32QI */
+#endif
+
 VECTOR_MODE (FLOAT, DF, 4);   /*                 V4DF */
+VECTOR_MODE (FLOAT, DF, 8);   /*                 V8DF */
+
 VECTOR_MODE (FLOAT, SF, 8);   /*                 V8SF */
+VECTOR_MODE (FLOAT, SF, 16);  /*                 V16SF */
diff --git a/gcc/config/cil32/cil32.h b/gcc/config/cil32/cil32.h
index 4a99636ae6c..a82cd7757c3 100644
--- a/gcc/config/cil32/cil32.h
+++ b/gcc/config/cil32/cil32.h
@@ -1,6 +1,6 @@
 /* Definitions for GCC.  Part of the machine description for cil32.
 
-   Copyright (C) 2006-2009 Free Software Foundation, Inc.
+   Copyright (C) 2006-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -93,7 +93,13 @@ extern int target_flags;
 #define WORDS_BIG_ENDIAN 0
 
 #define UNITS_PER_WORD 4
-#define UNITS_PER_SIMD_WORD(mode) 8
+
+
+/* When changing UNITS_PER_SIMD_WORD, need to change the defines in
+   cil-builtins.c accordingly. */
+#define UNITS_PER_SIMD_WORD(mode) 32  /* 256-bit vectors */
+
+
 
 /* Unused by cil32 machine */
 #define PARM_BOUNDARY 32
diff --git a/gcc/config/cil32/cil32.md b/gcc/config/cil32/cil32.md
index 776d5061b02..a0de9f8df99 100644
--- a/gcc/config/cil32/cil32.md
+++ b/gcc/config/cil32/cil32.md
@@ -43,8 +43,10 @@
 (define_mode_iterator ALLEVALMODES [SI DI SF DF])
 (define_mode_iterator ALLINTEVALMODES [SI DI])
 
-(define_mode_iterator VECMODES [V16QI V8HI V4SI V2DI V4SF V2DF 
-                                 V8QI V4HI V2SI V2SF])
+(define_mode_iterator VECMODES [ V64QI V32HI V16SI V8DI V16SF V8DF
+                                 V32QI V16HI V8SI  V4DI V8SF  V4DF
+                                 V16QI V8HI  V4SI  V2DI V4SF  V2DF 
+                                 V8QI  V4HI  V2SI  V2SF])
 
 ;; NOP
 
diff --git a/gcc/config/cil32/emit-cil.c b/gcc/config/cil32/emit-cil.c
index c8a2df3ea37..5b112ac289e 100644
--- a/gcc/config/cil32/emit-cil.c
+++ b/gcc/config/cil32/emit-cil.c
@@ -1,6 +1,6 @@
 /* Dump of CIL code into assembly.
 
-   Copyright (C) 2006-2009 Free Software Foundation, Inc.
+   Copyright (C) 2006-2010 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -521,33 +521,41 @@ dump_vector_type (FILE *file, cil_type_t cil_type)
 
   else  /* Generic SIMD */
     {
-      /* Generic SIMD is based on 64-bit vectors (from machine model). */
-      /* if not??? */
+      /* Generic SIMD vectors can have various sizes (from cil32.h). */
       const char* suffix;
       switch (cil_type)
         {
-        case CIL_V2HI:
         case CIL_V4HI:
         case CIL_V8HI:
+        case CIL_V16HI:
+        case CIL_V32HI:
           suffix = "HI";
           break;
         case CIL_V4QI:
         case CIL_V8QI:
         case CIL_V16QI:
+        case CIL_V32QI:
+        case CIL_V64QI:
           suffix = "QQQI";
           break;
         case CIL_V2SI:
         case CIL_V4SI:
+        case CIL_V8SI:
+        case CIL_V16SI:
           suffix = "SI";
           break;
         case CIL_V2SF:
         case CIL_V4SF:
+        case CIL_V8SF:
+        case CIL_V16SF:
           suffix = "SF";
           break;
         case CIL_V2DI:
+        case CIL_V4DI:
           suffix = "DI";
           break;
         case CIL_V2DF:
+        case CIL_V4DF:
           suffix = "DF";
           break;
 
diff --git a/gcc/config/cil32/gimple-to-cil.c b/gcc/config/cil32/gimple-to-cil.c
index ac8f7098df4..eed2d003243 100644
--- a/gcc/config/cil32/gimple-to-cil.c
+++ b/gcc/config/cil32/gimple-to-cil.c
@@ -2707,6 +2707,9 @@ gen_minmax_expr (cil_stmt_iterator *csi, tree node)
       switch (cil_type)
         {
         case CIL_V8QI:
+        case CIL_V16QI:
+        case CIL_V32QI:
+        case CIL_V64QI:
           if (max)
             builtin = CIL32_GEN_VQI_MAX;
           else
@@ -2714,6 +2717,9 @@ gen_minmax_expr (cil_stmt_iterator *csi, tree node)
           break;
 
         case CIL_V4HI:
+        case CIL_V8HI:
+        case CIL_V16HI:
+        case CIL_V32HI:
           if (max)
             builtin = CIL32_GEN_VHI_MAX;
           else
@@ -2721,6 +2727,9 @@ gen_minmax_expr (cil_stmt_iterator *csi, tree node)
           break;
 
         case CIL_V2SI:
+        case CIL_V4SI:
+        case CIL_V8SI:
+        case CIL_V16SI:
           if (max)
             builtin = CIL32_GEN_VSI_MAX;
           else
@@ -2728,6 +2737,9 @@ gen_minmax_expr (cil_stmt_iterator *csi, tree node)
           break;
 
         case CIL_V2SF:
+        case CIL_V4SF:
+        case CIL_V8SF:
+        case CIL_V16SF:
           if (max)
             builtin = CIL32_GEN_VSF_MAX;
           else
@@ -3910,6 +3922,8 @@ gimple_to_cil_node (cil_stmt_iterator *csi, tree node)
         cil_type_t cil_type;
         enum cil32_builtin builtin = 0;
 
+  fprintf (stderr, "REALIGN_LOAD_EXPR\n");
+
         op0 = TREE_OPERAND (node, 0);
         op1 = TREE_OPERAND (node, 1);
         op2 = TREE_OPERAND (node, 2);
@@ -4365,6 +4379,8 @@ gimple_to_cil (void)
   /* Add the initializers to the entry block */
   process_initializers ();
 
+  /* dump_cil (); */
+
   return 0;
 }