diff options
| author | naveenh <naveenh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-02-08 02:54:17 +0000 |
|---|---|---|
| committer | naveenh <naveenh@138bc75d-0d04-0410-961f-82ee72b054a4> | 2017-02-08 02:54:17 +0000 |
| commit | 89249afa9a06efc44e754dcbba53c0fe7446bc23 (patch) | |
| tree | e7d29bf8f776ca98aaa1aba4c0e7275969cbad18 | |
| parent | d57a0b8ad60612f4f0fd9fbab7301d9d367c547e (diff) | |
2016-02-07 Andrew Pinski <apinski@cavium.com>
gcc
* config/aarch64/aarch64.md (popcount<mode>2): New pattern.
gcc/testsuite
* gcc.target/aarch64/popcount.c : New Testcase.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@245267 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 33 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/popcnt.c | 23 |
4 files changed, 64 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ead1661df3b..527143ac944 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2017-02-07 Andrew Pinski <apinski@cavium.com> + * config/aarch64/aarch64.md (popcount<mode>2): New pattern. + +2017-02-07 Andrew Pinski <apinski@cavium.com> + * config/aarch64/aarch64-cores.def (thunderx): Disable LSE. (thunderxt88): Likewise. (thunderxt81): Disable LSE and change v8.1 to v8. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7550c3e7c2b..5adc5edb8dd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3779,6 +3779,39 @@ } ) +;; Pop count be done via the "CNT" instruction in AdvSIMD. +;; +;; MOV v.1d, x0 +;; CNT v1.8b, v.8b +;; ADDV b2, v1.8b +;; MOV w0, v2.b[0] + +(define_expand "popcount<mode>2" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "register_operand")] + "TARGET_SIMD" +{ + rtx v = gen_reg_rtx (V8QImode); + rtx v1 = gen_reg_rtx (V8QImode); + rtx r = gen_reg_rtx (QImode); + rtx in = operands[1]; + rtx out = operands[0]; + if(<MODE>mode == SImode) + { + rtx tmp; + tmp = gen_reg_rtx (DImode); + /* If we have SImode, zero extend to DImode, pop count does + not change if we have extra zeros. */ + emit_insn (gen_zero_extendsidi2 (tmp, in)); + in = tmp; + } + emit_move_insn (v, gen_lowpart (V8QImode, in)); + emit_insn (gen_popcountv8qi2 (v1, v)); + emit_insn (gen_reduc_plus_scal_v8qi (r, v1)); + emit_insn (gen_zero_extendqi<mode>2 (out, r)); + DONE; +}) + (define_insn "clrsb<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 7d793de238f..81b25807dd0 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2017-02-07 Andrew Pinski <apinski@cavium.com> + + * gcc.target/aarch64/popcount.c : New Testcase. + 2017-02-07 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/79386 diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt.c b/gcc/testsuite/gcc.target/aarch64/popcnt.c new file mode 100644 index 00000000000..7e957966d8e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/popcnt.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int x) +{ + return __builtin_popcount (x); +} + +long +foo1 (long x) +{ + return __builtin_popcountl (x); +} + +long long +foo2 (long long x) +{ + return __builtin_popcountll (x); +} + +/* { dg-final { scan-assembler-not "popcount" } } */ +/* { dg-final { scan-assembler-times "cnt\t" 3 } } */ |