diff options
| author | ciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-03-24 16:02:57 +0000 |
|---|---|---|
| committer | ciceron <ciceron@138bc75d-0d04-0410-961f-82ee72b054a4> | 2002-03-24 16:02:57 +0000 |
| commit | 38735756fd476d41052c17543f53868413c5dba8 (patch) | |
| tree | 875e8e56c94345cde18db4c8b0e602a12faa623f /gcc/config/m68hc11 | |
| parent | e85db6f8ce634f2818ed74af59ce21ebd9751574 (diff) | |
* config/m68hc11/m68hc11.md ("*subsi3_zero_extendhi"): Allow address
register for operand 2.
("*subsi3_zero_extendqi"): Likewise.
("*iorhi3_gen"): Do the operation on the upper bits and then lower
bits so that it is compatible with a pop.
("*andhi3_gen"): Likewise.
("xorhi3"): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@51262 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/m68hc11')
| -rw-r--r-- | gcc/config/m68hc11/m68hc11.md | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/gcc/config/m68hc11/m68hc11.md b/gcc/config/m68hc11/m68hc11.md index ea68c8a07ed..6cad95162a9 100644 --- a/gcc/config/m68hc11/m68hc11.md +++ b/gcc/config/m68hc11/m68hc11.md @@ -2509,13 +2509,31 @@ (define_insn "*subsi3_zero_extendhi" [(set (match_operand:SI 0 "register_operand" "=D") (minus:SI (match_operand:SI 1 "register_operand" "0") - (zero_extend:SI (match_operand:HI 2 "general_operand" "d!mui")))) + (zero_extend:SI (match_operand:HI 2 "general_operand" "dmui*A")))) (clobber (match_scratch:HI 3 "=X"))] "" "* { rtx ops[2]; + if (A_REG_P (operands[2])) + { + if (TARGET_M6812) + ops[0] = gen_rtx (MEM, HImode, + gen_rtx (PRE_DEC, HImode, + gen_rtx (REG, HImode, HARD_SP_REGNUM))); + else + ops[0] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM); + + ops[1] = operands[2]; + m68hc11_gen_movhi (insn, ops); + if (TARGET_M6812) + operands[2] = gen_rtx (MEM, HImode, + gen_rtx (POST_INC, HImode, + gen_rtx (REG, HImode, HARD_SP_REGNUM))); + else + operands[2] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM); + } ops[0] = gen_label_rtx (); output_asm_insn (\"subd\\t%2\", operands); output_asm_insn (\"bcc\\t%l0\", ops); @@ -2528,13 +2546,20 @@ (define_insn "*subsi3_zero_extendqi" [(set (match_operand:SI 0 "register_operand" "=D") (minus:SI (match_operand:SI 1 "register_operand" "0") - (zero_extend:SI (match_operand:QI 2 "general_operand" "!dmui")))) + (zero_extend:SI (match_operand:QI 2 "general_operand" "dmui*A")))) (clobber (match_scratch:HI 3 "=X"))] "" "* { rtx ops[2]; + if (A_REG_P (operands[2])) + { + ops[0] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM); + ops[1] = operands[2]; + m68hc11_gen_movhi (insn, ops); + operands[2] = gen_rtx (REG, QImode, SOFT_TMP_REGNUM); + } ops[0] = gen_label_rtx (); output_asm_insn (\"subb\\t%b2\", operands); output_asm_insn (\"sbca\\t#0\", operands); @@ -3174,7 +3199,7 @@ return \"#\"; CC_STATUS_INIT; - return \"andb\\t%b2\\n\\tanda\\t%h2\"; + return \"anda\\t%h2\\n\\tandb\\t%b2\"; }") (define_expand "andqi3" @@ -3395,7 +3420,7 @@ return \"#\"; CC_STATUS_INIT; - return \"orab\\t%b2\\n\\toraa\\t%h2\"; + return \"oraa\\t%h2\\n\\torab\\t%b2\"; }") (define_expand "iorqi3" @@ -3548,7 +3573,7 @@ } CC_STATUS_INIT; - return \"eorb\\t%b2\\n\\teora\\t%h2\"; + return \"eora\\t%h2\\n\\teorb\\t%b2\"; }") (define_insn "xorqi3" |