This commit was manufactured by cvs2svn to create tagobjc-improvements-candidate-20030922

'objc-improvements-candidate-20030922'.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/tags/objc-improvements-candidate-20030922@71666 138bc75d-0d04-0410-961f-82ee72b054a4

219 files changed, 17700 insertions, 15805 deletions

diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index df386deb937..72d01af2f15 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -233,7 +233,7 @@ override_options (void)
       flag_pic = 0;
     }
 
-  /* On Unicos/Mk, the native compiler consistenly generates /d suffices for 
+  /* On Unicos/Mk, the native compiler consistently generates /d suffices for 
      floating-point instructions.  Make that the default for this target.  */
   if (TARGET_ABI_UNICOSMK)
     alpha_fprm = ALPHA_FPRM_DYN;
@@ -3481,7 +3481,7 @@ alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
      be shared.  */
 
   if (f == 0 && exact_log2 (diff) > 0
-      /* On EV6, we've got enough shifters to make non-arithmatic shifts
+      /* On EV6, we've got enough shifters to make non-arithmetic shifts
 	 viable over a longer latency cmove.  On EV5, the E0 slot is a
 	 scarce resource, and on EV4 shift has the same latency as a cmove.  */
       && (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
@@ -5120,7 +5120,7 @@ alpha_use_dfa_pipeline_interface (void)
 
    For EV4, loads can be issued to either IB0 or IB1, thus we have 2
    alternative schedules.  For EV5, we can choose between E0/E1 and
-   FA/FM.  For EV6, an arithmatic insn can be issued to U0/U1/L0/L1.  */
+   FA/FM.  For EV6, an arithmetic insn can be issued to U0/U1/L0/L1.  */
 
 static int
 alpha_multipass_dfa_lookahead (void)
@@ -7799,7 +7799,7 @@ alpha_output_mi_thunk_osf (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
 
   /* Find the "this" pointer.  If the function returns a structure,
      the structure return pointer is in $16.  */
-  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     this = gen_rtx_REG (Pmode, 17);
   else
     this = gen_rtx_REG (Pmode, 16);
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index 067f3fdf839..a7680d9ac99 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -120,7 +120,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 
 ;; The ROUND_SUFFIX attribute marks which instructions require a
 ;; rounding-mode suffix.  The value NONE indicates no suffix,
-;; the value NORMAL indicates a suffix controled by alpha_fprm.
+;; the value NORMAL indicates a suffix controlled by alpha_fprm.
 
 (define_attr "round_suffix" "none,normal,c"
   (const_string "none"))
@@ -133,7 +133,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
 ;;   V_SV_SVI	accepts /v, /sv and /svi (cvttq only)
 ;;   U_SU_SUI	accepts /u, /su and /sui (most fp instructions)
 ;;
-;; The actual suffix emitted is controled by alpha_fptm.
+;; The actual suffix emitted is controlled by alpha_fptm.
 
 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
   (const_string "none"))
@@ -7171,7 +7171,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extxl_be;
   else
@@ -7186,7 +7186,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extxl_be;
   else
@@ -7201,7 +7201,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extxl_be;
   else
@@ -7216,7 +7216,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extxl_be;
   else
@@ -7231,7 +7231,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extwh_be;
   else
@@ -7246,7 +7246,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extlh_be;
   else
@@ -7261,7 +7261,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_extqh_be;
   else
@@ -7276,7 +7276,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_insbl_be;
   else
@@ -7292,7 +7292,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_inswl_be;
   else
@@ -7308,7 +7308,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_insll_be;
   else
@@ -7325,7 +7325,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx);
   if (WORDS_BIG_ENDIAN)
     gen = gen_insql_be;
   else
@@ -7370,7 +7370,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   rtx mask;
   if (WORDS_BIG_ENDIAN)
     gen = gen_mskxl_be;
@@ -7387,7 +7387,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   rtx mask;
   if (WORDS_BIG_ENDIAN)
     gen = gen_mskxl_be;
@@ -7404,7 +7404,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   rtx mask;
   if (WORDS_BIG_ENDIAN)
     gen = gen_mskxl_be;
@@ -7421,7 +7421,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
    (match_operand:DI 2 "reg_or_8bit_operand" "")]
   ""
 {
-  rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx));
+  rtx (*gen) (rtx, rtx, rtx, rtx);
   rtx mask;
   if (WORDS_BIG_ENDIAN)
     gen = gen_mskxl_be;
diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
index bad20a6b204..87d62eb551e 100644
--- a/gcc/config/alpha/linux.h
+++ b/gcc/config/alpha/linux.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler,
    for Alpha Linux-based GNU systems.
-   Copyright (C) 1996, 1997, 1998, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1996, 1997, 1998, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Richard Henderson.
 
 This file is part of GNU CC.
@@ -65,6 +65,9 @@ Boston, MA 02111-1307, USA.  */
 
 #define TARGET_HAS_F_SETLKW
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Do code reading to identify a signal frame, and set the frame
    state data appropriately.  See unwind-dw2.c for the structs.  */
 
diff --git a/gcc/config/alpha/openbsd.h b/gcc/config/alpha/openbsd.h
index f574e8da1f7..fa9a5111173 100644
--- a/gcc/config/alpha/openbsd.h
+++ b/gcc/config/alpha/openbsd.h
@@ -1,5 +1,5 @@
 /* Configuration file for an alpha OpenBSD target.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2003 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -21,16 +21,6 @@ Boston, MA 02111-1307, USA.  */
 /* We settle for little endian for now.  */
 #define TARGET_ENDIAN_DEFAULT 0
 
-#define OBSD_NO_DYNAMIC_LIBRARIES
-#define OBSD_HAS_DECLARE_FUNCTION_NAME
-#define OBSD_HAS_DECLARE_FUNCTION_SIZE
-#define OBSD_HAS_DECLARE_OBJECT
-
-/* alpha ecoff supports only weak aliases, see below.  */
-#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS (FILE,NAME,0)
-
-#include <openbsd.h>
-
 /* Controlling the compilation driver.  */
 
 /* alpha needs __start.  */
@@ -90,6 +80,10 @@ Boston, MA 02111-1307, USA.  */
 
 /* Assembler format: label output.  */
 
+/* alpha ecoff supports only weak aliases.  */
+#undef ASM_WEAKEN_LABEL
+#define ASM_WEAKEN_LABEL(FILE,NAME) ASM_OUTPUT_WEAK_ALIAS (FILE,NAME,0)
+
 #define ASM_OUTPUT_WEAK_ALIAS(FILE,NAME,VALUE)	\
  do {						\
   fputs ("\t.weakext\t", FILE);			\
diff --git a/gcc/config/alpha/t-osf-pthread b/gcc/config/alpha/t-osf-pthread
new file mode 100644
index 00000000000..968e65cce9e
--- /dev/null
+++ b/gcc/config/alpha/t-osf-pthread
@@ -0,0 +1,5 @@
+# Provide dummy POSIX threads functions
+LIB2FUNCS_EXTRA += $(srcdir)/gthr-posix.c
+
+# Compile libgcc2 with POSIX threads supports
+TARGET_LIBGCC2_CFLAGS=-pthread
diff --git a/gcc/config/alpha/t-osf4 b/gcc/config/alpha/t-osf4
index 0525d617662..fe747a3d521 100644
--- a/gcc/config/alpha/t-osf4
+++ b/gcc/config/alpha/t-osf4
@@ -10,7 +10,11 @@ SHLIB_NAME = @shlib_base_name@.so
 SHLIB_SONAME = @shlib_base_name@.so.1
 SHLIB_OBJS = @shlib_objs@
 
+# Hide all POSIX threads related symbols provided by gthr-posix.c.  This
+# only has an effect if t-osf-pthread is in use.
 SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
+	-Wl,-hidden_symbol,pthread\* -Wl,-hidden_symbol,__pthread\* \
+	-Wl,-hidden_symbol,sched_get_\* -Wl,-hidden_symbol,sched_yield \
 	-Wl,-msym -Wl,-set_version,gcc.1 -Wl,-soname,$(SHLIB_SONAME) \
 	-o $(SHLIB_NAME) @multilib_flags@ $(SHLIB_OBJS) -lc && \
 	rm -f $(SHLIB_SONAME) && \
diff --git a/gcc/config/arc/t-arc b/gcc/config/arc/t-arc
index bbf4257c7b9..9f949f6c438 100644
--- a/gcc/config/arc/t-arc
+++ b/gcc/config/arc/t-arc
@@ -26,15 +26,15 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
 
 # .init/.fini section routines
 
-x-crtinit.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
+crtinit.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
 	  -DCRT_INIT -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/arc/initfini.c -o $(dir)/crtinit.o
+	  -g0 -c $(srcdir)/config/arc/initfini.c -o crtinit.o
 
-x-crtfini.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
+crtfini.o: $(srcdir)/config/arc/initfini.c $(GCC_PASSES) $(CONFIG_H)
 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(CRTSTUFF_T_CFLAGS) \
 	  -DCRT_FINI -finhibit-size-directive -fno-inline-functions \
-	  -g0 -c $(srcdir)/config/arc/initfini.c -o $(dir)/crtfini.o
+	  -g0 -c $(srcdir)/config/arc/initfini.c -o crtfini.o
 
 MULTILIB_OPTIONS = EB
 MULTILIB_DIRNAMES = be
@@ -54,7 +54,7 @@ stmp-multilib-arc: stmp-multilib
 	    BUILD_PREFIX="$(BUILD_PREFIX)" BUILD_PREFIX_1="$(BUILD_PREFIX_1)" \
 	    GCC_CFLAGS="$(GCC_CFLAGS) $${flags}" \
 	    INCLUDES="$(INCLUDES)" CRTSTUFF_T_CFLAGS=$(CRTSTUFF_T_CFLAGS) \
-	    dir="$${dir}" x-crtinit.o x-crtfini.o; \
+	    dir="$${dir}" crtinit.o crtfini.o; \
 	  if [ $$? -eq 0 ] ; then true; else exit 1; fi; \
 	done
 	touch stmp-multilib-arc
diff --git a/gcc/config/arm/README-interworking b/gcc/config/arm/README-interworking
index de8b27841b2..0a03cdc3c9d 100644
--- a/gcc/config/arm/README-interworking
+++ b/gcc/config/arm/README-interworking
@@ -404,7 +404,7 @@ Instead the pseudo op is attached to a new label .real_start_of_<name>
 (where <name> is the name of the function) which indicates the start
 of the Thumb code.  This does have the interesting side effect in that
 if this function is now called from a Thumb mode piece of code
-outsside of the current file, the linker will generate a calling stub
+outside of the current file, the linker will generate a calling stub
 to switch from Thumb mode into ARM mode, and then this is immediately
 overridden by the function's header which switches back into Thumb
 mode. 
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 6b6a718557d..5e92b28b79b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -452,7 +452,7 @@ static const struct processors all_architectures[] =
   { NULL, 0 }
 };
 
-/* This is a magic stucture.  The 'string' field is magically filled in
+/* This is a magic structure.  The 'string' field is magically filled in
    with a pointer to the value specified by the user on the command line
    assuming that the user has specified such a value.  */
 
@@ -1968,7 +1968,7 @@ arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
 			  tree fndecl ATTRIBUTE_UNUSED)
 {
   /* On the ARM, the offset starts at 0.  */
-  pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0);
+  pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0);
   pcum->iwmmxt_nregs = 0;
   
   pcum->call_cookie = CALL_NORMAL;
@@ -10248,7 +10248,7 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
     return VALID_IWMMXT_REG_MODE (mode);
 
   if (regno <= LAST_ARM_REGNUM)
-    /* We allow any value to be stored in the general regisetrs.  */
+    /* We allow any value to be stored in the general registers.  */
     return 1;
 
   if (   regno == FRAME_POINTER_REGNUM
@@ -10715,7 +10715,7 @@ arm_init_iwmmxt_builtins (void)
 
   /* Add all builtins that are more or less simple operations on two
      operands.  */
-  for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
     {
       /* Use one of the operands; the target can have a different mode for
 	 mask-generating compares.  */
@@ -11155,11 +11155,11 @@ arm_expand_builtin (tree exp,
       break;
     }
 
-  for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
     if (d->code == (const enum arm_builtins) fcode)
       return arm_expand_binop_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
     if (d->code == (const enum arm_builtins) fcode)
       return arm_expand_unop_builtin (d->icode, arglist, target, 0);
 
@@ -11648,7 +11648,7 @@ thumb_far_jump_used_p (int in_prologue)
 	  && get_attr_far_jump (insn) == FAR_JUMP_YES
 	  )
 	{
-	  /* Record the fact that we have decied that
+	  /* Record the fact that we have decided that
 	     the function does use far jumps.  */
 	  cfun->machine->far_jump_used = 1;
 	  return 1;
@@ -12962,7 +12962,7 @@ arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
   int mi_delta = delta;
   const char *const mi_op = mi_delta < 0 ? "sub" : "add";
   int shift = 0;
-  int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)))
+  int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)
                     ? 1 : 0);
   if (mi_delta < 0)
     mi_delta = - mi_delta;
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index dc649ccfd1d..958cbcb29f6 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -172,9 +172,13 @@ extern GTY(()) rtx aof_pic_label;
 #ifdef  TARGET_DEFAULT
 #undef  TARGET_DEFAULT
 #define TARGET_DEFAULT	(ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME)
-#endif /* TARGET_CPU_DEFAULT */
+#endif
+#else
+#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt
+#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__"
 #else
-Unrecognized value in TARGET_CPU_DEFAULT.
+#error Unrecognized value in TARGET_CPU_DEFAULT.
+#endif
 #endif
 #endif
 #endif
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 94e2c65edd6..4a72c69ef3c 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -75,18 +75,18 @@
    			; and stack frame generation.  Operand 0 is the
    			; register to "use".
    (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
-   (UNSPEC_WSHUFH    8) ; Used by the instrinsic form of the iWMMXt WSHUFH instruction.
-   (UNSPEC_WACC      9) ; Used by the instrinsic form of the iWMMXt WACC instruction.
-   (UNSPEC_TMOVMSK  10) ; Used by the instrinsic form of the iWMMXt TMOVMSK instruction.
-   (UNSPEC_WSAD     11) ; Used by the instrinsic form of the iWMMXt WSAD instruction.
-   (UNSPEC_WSADZ    12) ; Used by the instrinsic form of the iWMMXt WSADZ instruction.
-   (UNSPEC_WMACS    13) ; Used by the instrinsic form of the iWMMXt WMACS instruction.
-   (UNSPEC_WMACU    14) ; Used by the instrinsic form of the iWMMXt WMACU instruction.
-   (UNSPEC_WMACSZ   15) ; Used by the instrinsic form of the iWMMXt WMACSZ instruction.
-   (UNSPEC_WMACUZ   16) ; Used by the instrinsic form of the iWMMXt WMACUZ instruction.
-   (UNSPEC_CLRDI    17) ; Used by the instrinsic form of the iWMMXt CLRDI instruction.
-   (UNSPEC_WMADDS   18) ; Used by the instrinsic form of the iWMMXt WMADDS instruction.
-   (UNSPEC_WMADDU   19) ; Used by the instrinsic form of the iWMMXt WMADDU instruction.
+   (UNSPEC_WSHUFH    8) ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
+   (UNSPEC_WACC      9) ; Used by the intrinsic form of the iWMMXt WACC instruction.
+   (UNSPEC_TMOVMSK  10) ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
+   (UNSPEC_WSAD     11) ; Used by the intrinsic form of the iWMMXt WSAD instruction.
+   (UNSPEC_WSADZ    12) ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
+   (UNSPEC_WMACS    13) ; Used by the intrinsic form of the iWMMXt WMACS instruction.
+   (UNSPEC_WMACU    14) ; Used by the intrinsic form of the iWMMXt WMACU instruction.
+   (UNSPEC_WMACSZ   15) ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
+   (UNSPEC_WMACUZ   16) ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
+   (UNSPEC_CLRDI    17) ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
+   (UNSPEC_WMADDS   18) ; Used by the intrinsic form of the iWMMXt WMADDS instruction.
+   (UNSPEC_WMADDU   19) ; Used by the intrinsic form of the iWMMXt WMADDU instruction.
   ]
 )
 
@@ -243,7 +243,7 @@
 
 ; Only model the write buffer for ARM6 and ARM7.  Earlier processors don't
 ; have one.  Later ones, such as StrongARM, have write-back caches, so don't
-; suffer blockages enough to warrent modelling this (and it can adversely
+; suffer blockages enough to warrant modelling this (and it can adversely
 ; affect the schedule).
 (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
 
@@ -5106,7 +5106,7 @@
 
 
 ;; Compare & branch insns
-;; The range calcualations are based as follows:
+;; The range calculations are based as follows:
 ;; For forward branches, the address calculation returns the address of
 ;; the next instruction.  This is 2 beyond the branch instruction.
 ;; For backward branches, the address calculation returns the address of
diff --git a/gcc/config/arm/coff.h b/gcc/config/arm/coff.h
index c4f0932e9ce..310c4fba8ec 100644
--- a/gcc/config/arm/coff.h
+++ b/gcc/config/arm/coff.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler.
    For ARM with COFF object format.
-   Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002
+   Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Doug Evans (devans@cygnus.com).
    
@@ -43,7 +43,6 @@
 
 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
 
-#include "dbxcoff.h"
 
 #define TARGET_ASM_FILE_START_APP_OFF true
 
diff --git a/gcc/config/arm/ieee754-df.S b/gcc/config/arm/ieee754-df.S
new file mode 100644
index 00000000000..2d5f487ff60
--- /dev/null
+++ b/gcc/config/arm/ieee754-df.S
@@ -0,0 +1,1214 @@
+/* ieee754-df.S double-precision floating point support for ARM
+
+   Copyright (C) 2003  Free Software Foundation, Inc.
+   Contributed by Nicolas Pitre (nico@cam.org)
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   In addition to the permissions in the GNU General Public License, the
+   Free Software Foundation gives you unlimited permission to link the
+   compiled version of this file into combinations with other programs,
+   and to distribute those combinations without any restriction coming
+   from the use of this file.  (The General Public License restrictions
+   do apply in other respects; for example, they cover modification of
+   the file, and distribution when not linked into a combine
+   executable.)
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/*
+ * Notes: 
+ * 
+ * The goal of this code is to be as fast as possible.  This is
+ * not meant to be easy to understand for the casual reader.
+ * For slightly simpler code please see the single precision version
+ * of this file.
+ * 
+ * Only the default rounding mode is intended for best performances.
+ * Exceptions aren't supported yet, but that can be added quite easily
+ * if necessary without impacting performances.
+ */
+
+
+@ For FPA, float words are always big-endian.
+@ For VFP, floats words follow the memory system mode.
+#if defined(__VFP_FP__) && !defined(__ARMEB__)
+#define xl r0
+#define xh r1
+#define yl r2
+#define yh r3
+#else
+#define xh r0
+#define xl r1
+#define yh r2
+#define yl r3
+#endif
+
+
+#ifdef L_negdf2
+
+ARM_FUNC_START negdf2
+	@ flip sign bit
+	eor	xh, xh, #0x80000000
+	RET
+
+	FUNC_END negdf2
+
+#endif
+
+#ifdef L_addsubdf3
+
+ARM_FUNC_START subdf3
+	@ flip sign bit of second arg
+	eor	yh, yh, #0x80000000
+#if defined(__thumb__) && !defined(__THUMB_INTERWORK__)
+	b	1f			@ Skip Thumb-code prologue
+#endif
+
+ARM_FUNC_START adddf3
+
+1:	@ Compare both args, return zero if equal but the sign.
+	teq	xl, yl
+	eoreq	ip, xh, yh
+	teqeq	ip, #0x80000000
+	beq	LSYM(Lad_z)
+
+	@ If first arg is 0 or -0, return second arg.
+	@ If second arg is 0 or -0, return first arg.
+	orrs	ip, xl, xh, lsl #1
+	moveq	xl, yl
+	moveq	xh, yh
+	orrnes	ip, yl, yh, lsl #1
+	RETc(eq)
+
+	stmfd	sp!, {r4, r5, lr}
+
+	@ Mask out exponents.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r4, xh, ip
+	and	r5, yh, ip
+
+	@ If either of them is 0x7ff, result will be INF or NAN
+	teq	r4, ip
+	teqne	r5, ip
+	beq	LSYM(Lad_i)
+
+	@ Compute exponent difference.  Make largest exponent in r4,
+	@ corresponding arg in xh-xl, and positive exponent difference in r5.
+	subs	r5, r5, r4
+	rsblt	r5, r5, #0
+	ble	1f
+	add	r4, r4, r5
+	eor	yl, xl, yl
+	eor	yh, xh, yh
+	eor	xl, yl, xl
+	eor	xh, yh, xh
+	eor	yl, xl, yl
+	eor	yh, xh, yh
+1:
+
+	@ If exponent difference is too large, return largest argument
+	@ already in xh-xl.  We need up to 54 bit to handle proper rounding
+	@ of 0x1p54 - 1.1.
+	cmp	r5, #(54 << 20)
+	RETLDM	"r4, r5" hi
+
+	@ Convert mantissa to signed integer.
+	tst	xh, #0x80000000
+	bic	xh, xh, ip, lsl #1
+	orr	xh, xh, #0x00100000
+	beq	1f
+	rsbs	xl, xl, #0
+	rsc	xh, xh, #0
+1:
+	tst	yh, #0x80000000
+	bic	yh, yh, ip, lsl #1
+	orr	yh, yh, #0x00100000
+	beq	1f
+	rsbs	yl, yl, #0
+	rsc	yh, yh, #0
+1:
+	@ If exponent == difference, one or both args were denormalized.
+	@ Since this is not common case, rescale them off line.
+	teq	r4, r5
+	beq	LSYM(Lad_d)
+LSYM(Lad_x):
+	@ Scale down second arg with exponent difference.
+	@ Apply shift one bit left to first arg and the rest to second arg
+	@ to simplify things later, but only if exponent does not become 0.
+	mov	ip, #0
+	movs	r5, r5, lsr #20
+	beq	3f
+	teq	r4, #(1 << 20)
+	beq	1f
+	movs	xl, xl, lsl #1
+	adc	xh, ip, xh, lsl #1
+	sub	r4, r4, #(1 << 20)
+	subs	r5, r5, #1
+	beq	3f
+
+	@ Shift yh-yl right per r5, keep leftover bits into ip.
+1:	rsbs	lr, r5, #32
+	blt	2f
+	mov	ip, yl, lsl lr
+	mov	yl, yl, lsr r5
+	orr	yl, yl, yh, lsl lr
+	mov	yh, yh, asr r5
+	b	3f
+2:	sub	r5, r5, #32
+	add	lr, lr, #32
+	cmp	yl, #1
+	adc	ip, ip, yh, lsl lr
+	mov	yl, yh, asr r5
+	mov	yh, yh, asr #32
+3:
+	@ the actual addition
+	adds	xl, xl, yl
+	adc	xh, xh, yh
+
+	@ We now have a result in xh-xl-ip.
+	@ Keep absolute value in xh-xl-ip, sign in r5.
+	ands	r5, xh, #0x80000000
+	bpl	LSYM(Lad_p)
+	rsbs	ip, ip, #0
+	rscs	xl, xl, #0
+	rsc	xh, xh, #0
+
+	@ Determine how to normalize the result.
+LSYM(Lad_p):
+	cmp	xh, #0x00100000
+	bcc	LSYM(Lad_l)
+	cmp	xh, #0x00200000
+	bcc	LSYM(Lad_r0)
+	cmp	xh, #0x00400000
+	bcc	LSYM(Lad_r1)
+
+	@ Result needs to be shifted right.
+	movs	xh, xh, lsr #1
+	movs	xl, xl, rrx
+	movs	ip, ip, rrx
+	orrcs	ip, ip, #1
+	add	r4, r4, #(1 << 20)
+LSYM(Lad_r1):
+	movs	xh, xh, lsr #1
+	movs	xl, xl, rrx
+	movs	ip, ip, rrx
+	orrcs	ip, ip, #1
+	add	r4, r4, #(1 << 20)
+
+	@ Our result is now properly aligned into xh-xl, remaining bits in ip.
+	@ Round with MSB of ip. If halfway between two numbers, round towards
+	@ LSB of xl = 0.
+LSYM(Lad_r0):
+	adds	xl, xl, ip, lsr #31
+	adc	xh, xh, #0
+	teq	ip, #0x80000000
+	biceq	xl, xl, #1
+
+	@ One extreme rounding case may add a new MSB.  Adjust exponent.
+	@ That MSB will be cleared when exponent is merged below. 
+	tst	xh, #0x00200000
+	addne	r4, r4, #(1 << 20)
+
+	@ Make sure we did not bust our exponent.
+	adds	ip, r4, #(1 << 20)
+	bmi	LSYM(Lad_o)
+
+	@ Pack final result together.
+LSYM(Lad_e):
+	bic	xh, xh, #0x00300000
+	orr	xh, xh, r4
+	orr	xh, xh, r5
+	RETLDM	"r4, r5"
+
+LSYM(Lad_l):
+	@ Result must be shifted left and exponent adjusted.
+	@ No rounding necessary since ip will always be 0.
+#if __ARM_ARCH__ < 5
+
+	teq	xh, #0
+	movne	r3, #-11
+	moveq	r3, #21
+	moveq	xh, xl
+	moveq	xl, #0
+	mov	r2, xh
+	movs	ip, xh, lsr #16
+	moveq	r2, r2, lsl #16
+	addeq	r3, r3, #16
+	tst	r2, #0xff000000
+	moveq	r2, r2, lsl #8
+	addeq	r3, r3, #8
+	tst	r2, #0xf0000000
+	moveq	r2, r2, lsl #4
+	addeq	r3, r3, #4
+	tst	r2, #0xc0000000
+	moveq	r2, r2, lsl #2
+	addeq	r3, r3, #2
+	tst	r2, #0x80000000
+	addeq	r3, r3, #1
+
+#else
+
+	teq	xh, #0
+	moveq	xh, xl
+	moveq	xl, #0
+	clz	r3, xh
+	addeq	r3, r3, #32
+	sub	r3, r3, #11
+
+#endif
+
+	@ determine how to shift the value.
+	subs	r2, r3, #32
+	bge	2f
+	adds	r2, r2, #12
+	ble	1f
+
+	@ shift value left 21 to 31 bits, or actually right 11 to 1 bits
+	@ since a register switch happened above.
+	add	ip, r2, #20
+	rsb	r2, r2, #12
+	mov	xl, xh, lsl ip
+	mov	xh, xh, lsr r2
+	b	3f
+
+	@ actually shift value left 1 to 20 bits, which might also represent
+	@ 32 to 52 bits if counting the register switch that happened earlier.
+1:	add	r2, r2, #20
+2:	rsble	ip, r2, #32
+	mov	xh, xh, lsl r2
+	orrle	xh, xh, xl, lsr ip
+	movle	xl, xl, lsl r2
+
+	@ adjust exponent accordingly.
+3:	subs	r4, r4, r3, lsl #20
+	bgt	LSYM(Lad_e)
+
+	@ Exponent too small, denormalize result.
+	@ Find out proper shift value.
+	mvn	r4, r4, asr #20
+	subs	r4, r4, #30
+	bge	2f
+	adds	r4, r4, #12
+	bgt	1f
+
+	@ shift result right of 1 to 20 bits, sign is in r5.
+	add	r4, r4, #20
+	rsb	r2, r4, #32
+	mov	xl, xl, lsr r4
+	orr	xl, xl, xh, lsl r2
+	orr	xh, r5, xh, lsr r4
+	RETLDM	"r4, r5"
+
+	@ shift result right of 21 to 31 bits, or left 11 to 1 bits after
+	@ a register switch from xh to xl.
+1:	rsb	r4, r4, #12
+	rsb	r2, r4, #32
+	mov	xl, xl, lsr r2
+	orr	xl, xl, xh, lsl r4
+	mov	xh, r5
+	RETLDM	"r4, r5"
+
+	@ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch
+	@ from xh to xl.
+2:	mov	xl, xh, lsr r4
+	mov	xh, r5
+	RETLDM	"r4, r5"
+
+	@ Adjust exponents for denormalized arguments.
+LSYM(Lad_d):
+	teq	r4, #0
+	eoreq	xh, xh, #0x00100000
+	addeq	r4, r4, #(1 << 20)
+	eor	yh, yh, #0x00100000
+	subne	r5, r5, #(1 << 20)
+	b	LSYM(Lad_x)
+
+	@ Result is x - x = 0, unless x = INF or NAN.
+LSYM(Lad_z):
+	sub	ip, ip, #0x00100000	@ ip becomes 0x7ff00000
+	and	r2, xh, ip
+	teq	r2, ip
+	orreq	xh, ip, #0x00080000
+	movne	xh, #0
+	mov	xl, #0
+	RET
+
+	@ Overflow: return INF.
+LSYM(Lad_o):
+	orr	xh, r5, #0x7f000000
+	orr	xh, xh, #0x00f00000
+	mov	xl, #0
+	RETLDM	"r4, r5"
+
+	@ At least one of x or y is INF/NAN.
+	@   if xh-xl != INF/NAN: return yh-yl (which is INF/NAN)
+	@   if yh-yl != INF/NAN: return xh-xl (which is INF/NAN)
+	@   if either is NAN: return NAN
+	@   if opposite sign: return NAN
+	@   return xh-xl (which is INF or -INF)
+LSYM(Lad_i):
+	teq	r4, ip
+	movne	xh, yh
+	movne	xl, yl
+	teqeq	r5, ip
+	RETLDM	"r4, r5" ne
+
+	orrs	r4, xl, xh, lsl #12
+	orreqs	r4, yl, yh, lsl #12
+	teqeq	xh, yh
+	orrne	xh, r5, #0x00080000
+	movne	xl, #0
+	RETLDM	"r4, r5"
+
+	FUNC_END subdf3
+	FUNC_END adddf3
+
+ARM_FUNC_START floatunsidf
+	teq	r0, #0
+	moveq	r1, #0
+	RETc(eq)
+	stmfd	sp!, {r4, r5, lr}
+	mov	r4, #(0x400 << 20)	@ initial exponent
+	add	r4, r4, #((52-1) << 20)
+	mov	r5, #0			@ sign bit is 0
+	mov	xl, r0
+	mov	xh, #0
+	b	LSYM(Lad_l)
+
+	FUNC_END floatunsidf
+
+ARM_FUNC_START floatsidf
+	teq	r0, #0
+	moveq	r1, #0
+	RETc(eq)
+	stmfd	sp!, {r4, r5, lr}
+	mov	r4, #(0x400 << 20)	@ initial exponent
+	add	r4, r4, #((52-1) << 20)
+	ands	r5, r0, #0x80000000	@ sign bit in r5
+	rsbmi	r0, r0, #0		@ absolute value
+	mov	xl, r0
+	mov	xh, #0
+	b	LSYM(Lad_l)
+
+	FUNC_END floatsidf
+
+ARM_FUNC_START extendsfdf2
+	movs	r2, r0, lsl #1
+	beq	1f			@ value is 0.0 or -0.0
+	mov	xh, r2, asr #3		@ stretch exponent
+	mov	xh, xh, rrx		@ retrieve sign bit
+	mov	xl, r2, lsl #28		@ retrieve remaining bits
+	ands	r2, r2, #0xff000000	@ isolate exponent
+	beq	2f			@ exponent was 0 but not mantissa
+	teq	r2, #0xff000000		@ check if INF or NAN
+	eorne	xh, xh, #0x38000000	@ fixup exponent otherwise.
+	RET
+
+1:	mov	xh, r0
+	mov	xl, #0
+	RET
+
+2:	@ value was denormalized.  We can normalize it now.
+	stmfd	sp!, {r4, r5, lr}
+	mov	r4, #(0x380 << 20)	@ setup corresponding exponent
+	add	r4, r4, #(1 << 20)
+	and	r5, xh, #0x80000000	@ move sign bit in r5
+	bic	xh, xh, #0x80000000
+	b	LSYM(Lad_l)
+
+	FUNC_END extendsfdf2
+
+#endif /* L_addsubdf3 */
+
+#ifdef L_muldivdf3
+
+ARM_FUNC_START muldf3
+
+	stmfd	sp!, {r4, r5, r6, lr}
+
+	@ Mask out exponents.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r4, xh, ip
+	and	r5, yh, ip
+
+	@ Trap any INF/NAN.
+	teq	r4, ip
+	teqne	r5, ip
+	beq	LSYM(Lml_s)
+
+	@ Trap any multiplication by 0.
+	orrs	r6, xl, xh, lsl #1
+	orrnes	r6, yl, yh, lsl #1
+	beq	LSYM(Lml_z)
+
+	@ Shift exponents right one bit to make room for overflow bit.
+	@ If either of them is 0, scale denormalized arguments off line.
+	@ Then add both exponents together.
+	movs	r4, r4, lsr #1
+	teqne	r5, #0
+	beq	LSYM(Lml_d)
+LSYM(Lml_x):
+	add	r4, r4, r5, asr #1
+
+	@ Preserve final sign in r4 along with exponent for now.
+	teq	xh, yh
+	orrmi	r4, r4, #0x8000
+
+	@ Convert mantissa to unsigned integer.
+	bic	xh, xh, ip, lsl #1
+	bic	yh, yh, ip, lsl #1
+	orr	xh, xh, #0x00100000
+	orr	yh, yh, #0x00100000
+
+#if __ARM_ARCH__ < 4
+
+	@ Well, no way to make it shorter without the umull instruction.
+	@ We must perform that 53 x 53 bit multiplication by hand.
+	stmfd	sp!, {r7, r8, r9, sl, fp}
+	mov	r7, xl, lsr #16
+	mov	r8, yl, lsr #16
+	mov	r9, xh, lsr #16
+	mov	sl, yh, lsr #16
+	bic	xl, xl, r7, lsl #16
+	bic	yl, yl, r8, lsl #16
+	bic	xh, xh, r9, lsl #16
+	bic	yh, yh, sl, lsl #16
+	mul	ip, xl, yl
+	mul	fp, xl, r8
+	mov	lr, #0
+	adds	ip, ip, fp, lsl #16
+	adc	lr, lr, fp, lsr #16
+	mul	fp, r7, yl
+	adds	ip, ip, fp, lsl #16
+	adc	lr, lr, fp, lsr #16
+	mul	fp, xl, sl
+	mov	r5, #0
+	adds	lr, lr, fp, lsl #16
+	adc	r5, r5, fp, lsr #16
+	mul	fp, r7, yh
+	adds	lr, lr, fp, lsl #16
+	adc	r5, r5, fp, lsr #16
+	mul	fp, xh, r8
+	adds	lr, lr, fp, lsl #16
+	adc	r5, r5, fp, lsr #16
+	mul	fp, r9, yl
+	adds	lr, lr, fp, lsl #16
+	adc	r5, r5, fp, lsr #16
+	mul	fp, xh, sl
+	mul	r6, r9, sl
+	adds	r5, r5, fp, lsl #16
+	adc	r6, r6, fp, lsr #16
+	mul	fp, r9, yh
+	adds	r5, r5, fp, lsl #16
+	adc	r6, r6, fp, lsr #16
+	mul	fp, xl, yh
+	adds	lr, lr, fp
+	mul	fp, r7, sl
+	adcs	r5, r5, fp
+	mul	fp, xh, yl
+	adc	r6, r6, #0
+	adds	lr, lr, fp
+	mul	fp, r9, r8
+	adcs	r5, r5, fp
+	mul	fp, r7, r8
+	adc	r6, r6, #0
+	adds	lr, lr, fp
+	mul	fp, xh, yh
+	adcs	r5, r5, fp
+	adc	r6, r6, #0
+	ldmfd	sp!, {r7, r8, r9, sl, fp}
+
+#else
+
+	@ Here is the actual multiplication: 53 bits * 53 bits -> 106 bits.
+	umull	ip, lr, xl, yl
+	mov	r5, #0
+	umlal	lr, r5, xl, yh
+	umlal	lr, r5, xh, yl
+	mov	r6, #0
+	umlal	r5, r6, xh, yh
+
+#endif
+
+	@ The LSBs in ip are only significant for the final rounding.
+	@ Fold them into one bit of lr.
+	teq	ip, #0
+	orrne	lr, lr, #1
+
+	@ Put final sign in xh.
+	mov	xh, r4, lsl #16
+	bic	r4, r4, #0x8000
+
+	@ Adjust result if one extra MSB appeared (one of four times).
+	tst	r6, #(1 << 9)
+	beq	1f
+	add	r4, r4, #(1 << 19)
+	movs	r6, r6, lsr #1
+	movs	r5, r5, rrx
+	movs	lr, lr, rrx
+	orrcs	lr, lr, #1
+1:
+	@ Scale back to 53 bits.
+	@ xh contains sign bit already.
+	orr	xh, xh, r6, lsl #12
+	orr	xh, xh, r5, lsr #20
+	mov	xl, r5, lsl #12
+	orr	xl, xl, lr, lsr #20
+
+	@ Apply exponent bias, check range for underflow.
+	sub	r4, r4, #0x00f80000
+	subs	r4, r4, #0x1f000000
+	ble	LSYM(Lml_u)
+
+	@ Round the result.
+	movs	lr, lr, lsl #12
+	bpl	1f
+	adds	xl, xl, #1
+	adc	xh, xh, #0
+	teq	lr, #0x80000000
+	biceq	xl, xl, #1
+
+	@ Rounding may have produced an extra MSB here.
+	@ The extra bit is cleared before merging the exponent below.
+	tst	xh, #0x00200000
+	addne	r4, r4, #(1 << 19)
+1:
+	@ Check exponent for overflow.
+	adds	ip, r4, #(1 << 19)
+	tst	ip, #(1 << 30)
+	bne	LSYM(Lml_o)
+
+	@ Add final exponent.
+	bic	xh, xh, #0x00300000
+	orr	xh, xh, r4, lsl #1
+	RETLDM	"r4, r5, r6"
+
+	@ Result is 0, but determine sign anyway.
+LSYM(Lml_z):
+	eor	xh, xh, yh
+LSYM(Ldv_z):
+	bic	xh, xh, #0x7fffffff
+	mov	xl, #0
+	RETLDM	"r4, r5, r6"
+
+	@ Check if denormalized result is possible, otherwise return signed 0.
+LSYM(Lml_u):
+	cmn	r4, #(53 << 19)
+	movle	xl, #0
+	bicle	xh, xh, #0x7fffffff
+	RETLDM	"r4, r5, r6" le
+
+	@ Find out proper shift value.
+LSYM(Lml_r):
+	mvn	r4, r4, asr #19
+	subs	r4, r4, #30
+	bge	2f
+	adds	r4, r4, #12
+	bgt	1f
+
+	@ shift result right of 1 to 20 bits, preserve sign bit, round, etc.
+	add	r4, r4, #20
+	rsb	r5, r4, #32
+	mov	r3, xl, lsl r5
+	mov	xl, xl, lsr r4
+	orr	xl, xl, xh, lsl r5
+	movs	xh, xh, lsl #1
+	mov	xh, xh, lsr r4
+	mov	xh, xh, rrx
+	adds	xl, xl, r3, lsr #31
+	adc	xh, xh, #0
+	teq	lr, #0
+	teqeq	r3, #0x80000000
+	biceq	xl, xl, #1
+	RETLDM	"r4, r5, r6"
+
+	@ shift result right of 21 to 31 bits, or left 11 to 1 bits after
+	@ a register switch from xh to xl. Then round.
+1:	rsb	r4, r4, #12
+	rsb	r5, r4, #32
+	mov	r3, xl, lsl r4
+	mov	xl, xl, lsr r5
+	orr	xl, xl, xh, lsl r4
+	bic	xh, xh, #0x7fffffff
+	adds	xl, xl, r3, lsr #31
+	adc	xh, xh, #0
+	teq	lr, #0
+	teqeq	r3, #0x80000000
+	biceq	xl, xl, #1
+	RETLDM	"r4, r5, r6"
+
+	@ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch
+	@ from xh to xl.  Leftover bits are in r3-r6-lr for rounding.
+2:	rsb	r5, r4, #32
+	mov	r6, xl, lsl r5
+	mov	r3, xl, lsr r4
+	orr	r3, r3, xh, lsl r5
+	mov	xl, xh, lsr r4
+	bic	xh, xh, #0x7fffffff
+	adds	xl, xl, r3, lsr #31
+	adc	xh, xh, #0
+	orrs	r6, r6, lr
+	teqeq	r3, #0x80000000
+	biceq	xl, xl, #1
+	RETLDM	"r4, r5, r6"
+
+	@ One or both arguments are denormalized.
+	@ Scale them leftwards and preserve sign bit.
+LSYM(Lml_d):
+	mov	lr, #0
+	teq	r4, #0
+	bne	2f
+	and	r6, xh, #0x80000000
+1:	movs	xl, xl, lsl #1
+	adc	xh, lr, xh, lsl #1
+	tst	xh, #0x00100000
+	subeq	r4, r4, #(1 << 19)
+	beq	1b
+	orr	xh, xh, r6
+	teq	r5, #0
+	bne	LSYM(Lml_x)
+2:	and	r6, yh, #0x80000000
+3:	movs	yl, yl, lsl #1
+	adc	yh, lr, yh, lsl #1
+	tst	yh, #0x00100000
+	subeq	r5, r5, #(1 << 20)
+	beq	3b
+	orr	yh, yh, r6
+	b	LSYM(Lml_x)
+
+	@ One or both args are INF or NAN.
+LSYM(Lml_s):
+	orrs	r6, xl, xh, lsl #1
+	orrnes	r6, yl, yh, lsl #1
+	beq	LSYM(Lml_n)		@ 0 * INF or INF * 0 -> NAN
+	teq	r4, ip
+	bne	1f
+	orrs	r6, xl, xh, lsl #12
+	bne	LSYM(Lml_n)		@ NAN * <anything> -> NAN
+1:	teq	r5, ip
+	bne	LSYM(Lml_i)
+	orrs	r6, yl, yh, lsl #12
+	bne	LSYM(Lml_n)		@ <anything> * NAN -> NAN
+
+	@ Result is INF, but we need to determine its sign.
+LSYM(Lml_i):
+	eor	xh, xh, yh
+
+	@ Overflow: return INF (sign already in xh).
+LSYM(Lml_o):
+	and	xh, xh, #0x80000000
+	orr	xh, xh, #0x7f000000
+	orr	xh, xh, #0x00f00000
+	mov	xl, #0
+	RETLDM	"r4, r5, r6"
+
+	@ Return NAN.
+LSYM(Lml_n):
+	mov	xh, #0x7f000000
+	orr	xh, xh, #0x00f80000
+	RETLDM	"r4, r5, r6"
+
+	FUNC_END muldf3
+
+ARM_FUNC_START divdf3
+
+	stmfd	sp!, {r4, r5, r6, lr}
+
+	@ Mask out exponents.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r4, xh, ip
+	and	r5, yh, ip
+
+	@ Trap any INF/NAN or zeroes.
+	teq	r4, ip
+	teqne	r5, ip
+	orrnes	r6, xl, xh, lsl #1
+	orrnes	r6, yl, yh, lsl #1
+	beq	LSYM(Ldv_s)
+
+	@ Shift exponents right one bit to make room for overflow bit.
+	@ If either of them is 0, scale denormalized arguments off line.
+	@ Then substract divisor exponent from dividend''s.
+	movs	r4, r4, lsr #1
+	teqne	r5, #0
+	beq	LSYM(Ldv_d)
+LSYM(Ldv_x):
+	sub	r4, r4, r5, asr #1
+
+	@ Preserve final sign into lr.
+	eor	lr, xh, yh
+
+	@ Convert mantissa to unsigned integer.
+	@ Dividend -> r5-r6, divisor -> yh-yl.
+	mov	r5, #0x10000000
+	mov	yh, yh, lsl #12
+	orr	yh, r5, yh, lsr #4
+	orr	yh, yh, yl, lsr #24
+	movs	yl, yl, lsl #8
+	mov	xh, xh, lsl #12
+	teqeq	yh, r5
+	beq	LSYM(Ldv_1)
+	orr	r5, r5, xh, lsr #4
+	orr	r5, r5, xl, lsr #24
+	mov	r6, xl, lsl #8
+
+	@ Initialize xh with final sign bit.
+	and	xh, lr, #0x80000000
+
+	@ Ensure result will land to known bit position.
+	cmp	r5, yh
+	cmpeq	r6, yl
+	bcs	1f
+	sub	r4, r4, #(1 << 19)
+	movs	yh, yh, lsr #1
+	mov	yl, yl, rrx
+1:
+	@ Apply exponent bias, check range for over/underflow.
+	add	r4, r4, #0x1f000000
+	add	r4, r4, #0x00f80000
+	cmn	r4, #(53 << 19)
+	ble	LSYM(Ldv_z)
+	cmp	r4, ip, lsr #1
+	bge	LSYM(Lml_o)
+
+	@ Perform first substraction to align result to a nibble.
+	subs	r6, r6, yl
+	sbc	r5, r5, yh
+	movs	yh, yh, lsr #1
+	mov	yl, yl, rrx
+	mov	xl, #0x00100000
+	mov	ip, #0x00080000
+
+	@ The actual division loop.
+1:	subs	lr, r6, yl
+	sbcs	lr, r5, yh
+	subcs	r6, r6, yl
+	movcs	r5, lr
+	orrcs	xl, xl, ip
+	movs	yh, yh, lsr #1
+	mov	yl, yl, rrx
+	subs	lr, r6, yl
+	sbcs	lr, r5, yh
+	subcs	r6, r6, yl
+	movcs	r5, lr
+	orrcs	xl, xl, ip, lsr #1
+	movs	yh, yh, lsr #1
+	mov	yl, yl, rrx
+	subs	lr, r6, yl
+	sbcs	lr, r5, yh
+	subcs	r6, r6, yl
+	movcs	r5, lr
+	orrcs	xl, xl, ip, lsr #2
+	movs	yh, yh, lsr #1
+	mov	yl, yl, rrx
+	subs	lr, r6, yl
+	sbcs	lr, r5, yh
+	subcs	r6, r6, yl
+	movcs	r5, lr
+	orrcs	xl, xl, ip, lsr #3
+
+	orrs	lr, r5, r6
+	beq	2f
+	mov	r5, r5, lsl #4
+	orr	r5, r5, r6, lsr #28
+	mov	r6, r6, lsl #4
+	mov	yh, yh, lsl #3
+	orr	yh, yh, yl, lsr #29
+	mov	yl, yl, lsl #3
+	movs	ip, ip, lsr #4
+	bne	1b
+
+	@ We are done with a word of the result.
+	@ Loop again for the low word if this pass was for the high word.
+	tst	xh, #0x00100000
+	bne	3f
+	orr	xh, xh, xl
+	mov	xl, #0
+	mov	ip, #0x80000000
+	b	1b
+2:
+	@ Be sure result starts in the high word.
+	tst	xh, #0x00100000
+	orreq	xh, xh, xl
+	moveq	xl, #0
+3:
+	@ Check if denormalized result is needed.
+	cmp	r4, #0
+	ble	LSYM(Ldv_u)
+
+	@ Apply proper rounding.
+	subs	ip, r5, yh
+	subeqs	ip, r6, yl
+	adcs	xl, xl, #0
+	adc	xh, xh, #0
+	teq	ip, #0
+	biceq	xl, xl, #1
+
+	@ Add exponent to result.
+	bic	xh, xh, #0x00100000
+	orr	xh, xh, r4, lsl #1
+	RETLDM	"r4, r5, r6"
+
+	@ Division by 0x1p*: shortcut a lot of code.
+LSYM(Ldv_1):
+	and	lr, lr, #0x80000000
+	orr	xh, lr, xh, lsr #12
+	add	r4, r4, #0x1f000000
+	add	r4, r4, #0x00f80000
+	cmp	r4, ip, lsr #1
+	bge	LSYM(Lml_o)
+	cmp	r4, #0
+	orrgt	xh, xh, r4, lsl #1
+	RETLDM	"r4, r5, r6" gt
+
+	cmn	r4, #(53 << 19)
+	ble	LSYM(Ldv_z)
+	orr	xh, xh, #0x00100000
+	mov	lr, #0
+	b	LSYM(Lml_r)
+
+	@ Result must be denormalized: put remainder in lr for
+	@ rounding considerations.
+LSYM(Ldv_u):
+	orr	lr, r5, r6
+	b	LSYM(Lml_r)
+
+	@ One or both arguments are denormalized.
+	@ Scale them leftwards and preserve sign bit.
+LSYM(Ldv_d):
+	mov	lr, #0
+	teq	r4, #0
+	bne	2f
+	and	r6, xh, #0x80000000
+1:	movs	xl, xl, lsl #1
+	adc	xh, lr, xh, lsl #1
+	tst	xh, #0x00100000
+	subeq	r4, r4, #(1 << 19)
+	beq	1b
+	orr	xh, xh, r6
+	teq	r5, #0
+	bne	LSYM(Ldv_x)
+2:	and	r6, yh, #0x80000000
+3:	movs	yl, yl, lsl #1
+	adc	yh, lr, yh, lsl #1
+	tst	yh, #0x00100000
+	subeq	r5, r5, #(1 << 20)
+	beq	3b
+	orr	yh, yh, r6
+	b	LSYM(Ldv_x)
+
+	@ One or both arguments is either INF, NAN or zero.
+LSYM(Ldv_s):
+	teq	r4, ip
+	teqeq	r5, ip
+	beq	LSYM(Lml_n)		@ INF/NAN / INF/NAN -> NAN
+	teq	r4, ip
+	bne	1f
+	orrs	r4, xl, xh, lsl #12
+	bne	LSYM(Lml_n)		@ NAN / <anything> -> NAN
+	b	LSYM(Lml_i)		@ INF / <anything> -> INF
+1:	teq	r5, ip
+	bne	2f
+	orrs	r5, yl, yh, lsl #12
+	bne	LSYM(Lml_n)		@ <anything> / NAN -> NAN
+	b	LSYM(Lml_z)		@ <anything> / INF -> 0
+2:	@ One or both arguments are 0.
+	orrs	r4, xl, xh, lsl #1
+	bne	LSYM(Lml_i)		@ <non_zero> / 0 -> INF
+	orrs	r5, yl, yh, lsl #1
+	bne	LSYM(Lml_z)		@ 0 / <non_zero> -> 0
+	b	LSYM(Lml_n)		@ 0 / 0 -> NAN
+
+	FUNC_END divdf3
+
+#endif /* L_muldivdf3 */
+
+#ifdef L_cmpdf2
+
+FUNC_START gedf2
+ARM_FUNC_START gtdf2
+	mov	ip, #-1
+	b	1f
+
+FUNC_START ledf2
+ARM_FUNC_START ltdf2
+	mov	ip, #1
+	b	1f
+
+FUNC_START nedf2
+FUNC_START eqdf2
+ARM_FUNC_START cmpdf2
+	mov	ip, #1			@ how should we specify unordered here?
+
+1:	stmfd	sp!, {r4, r5, lr}
+
+	@ Trap any INF/NAN first.
+	mov	lr, #0x7f000000
+	orr	lr, lr, #0x00f00000
+	and	r4, xh, lr
+	and	r5, yh, lr
+	teq	r4, lr
+	teqne	r5, lr
+	beq	3f
+
+	@ Test for equality.
+	@ Note that 0.0 is equal to -0.0.
+2:	orrs	ip, xl, xh, lsl #1	@ if x == 0.0 or -0.0
+	orreqs	ip, yl, yh, lsl #1	@ and y == 0.0 or -0.0
+	teqne	xh, yh			@ or xh == yh
+	teqeq	xl, yl			@ and xl == yl
+	moveq	r0, #0			@ then equal.
+	RETLDM	"r4, r5" eq
+
+	@ Check for sign difference.
+	teq	xh, yh
+	movmi	r0, xh, asr #31
+	orrmi	r0, r0, #1
+	RETLDM	"r4, r5" mi
+
+	@ Compare exponents.
+	cmp	r4, r5
+
+	@ Compare mantissa if exponents are equal.
+	moveq	xh, xh, lsl #12
+	cmpeq	xh, yh, lsl #12
+	cmpeq	xl, yl
+	movcs	r0, yh, asr #31
+	mvncc	r0, yh, asr #31
+	orr	r0, r0, #1
+	RETLDM	"r4, r5"
+
+	@ Look for a NAN.
+3:	teq	r4, lr
+	bne	4f
+	orrs	xl, xl, xh, lsl #12
+	bne	5f			@ x is NAN
+4:	teq	r5, lr
+	bne	2b
+	orrs	yl, yl, yh, lsl #12
+	beq	2b			@ y is not NAN
+5:	mov	r0, ip			@ return unordered code from ip
+	RETLDM	"r4, r5"
+
+	FUNC_END gedf2
+	FUNC_END gtdf2
+	FUNC_END ledf2
+	FUNC_END ltdf2
+	FUNC_END nedf2
+	FUNC_END eqdf2
+	FUNC_END cmpdf2
+
+#endif /* L_cmpdf2 */
+
+#ifdef L_unorddf2
+
+ARM_FUNC_START unorddf2
+	str	lr, [sp, #-4]!
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	lr, xh, ip
+	teq	lr, ip
+	bne	1f
+	orrs	xl, xl, xh, lsl #12
+	bne	3f			@ x is NAN
+1:	and	lr, yh, ip
+	teq	lr, ip
+	bne	2f
+	orrs	yl, yl, yh, lsl #12
+	bne	3f			@ y is NAN
+2:	mov	r0, #0			@ arguments are ordered.
+	RETLDM
+
+3:	mov	r0, #1			@ arguments are unordered.
+	RETLDM
+
+	FUNC_END unorddf2
+
+#endif /* L_unorddf2 */
+
+#ifdef L_fixdfsi
+
+ARM_FUNC_START fixdfsi
+	orrs	ip, xl, xh, lsl #1
+	beq	1f			@ value is 0.
+
+	mov	r3, r3, rrx		@ preserve C flag (the actual sign)
+
+	@ check exponent range.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r2, xh, ip
+	teq	r2, ip
+	beq	2f			@ value is INF or NAN
+	bic	ip, ip, #0x40000000
+	cmp	r2, ip
+	bcc	1f			@ value is too small
+	add	ip, ip, #(31 << 20)
+	cmp	r2, ip
+	bcs	3f			@ value is too large
+
+	rsb	r2, r2, ip
+	mov	ip, xh, lsl #11
+	orr	ip, ip, #0x80000000
+	orr	ip, ip, xl, lsr #21
+	mov	r2, r2, lsr #20
+	tst	r3, #0x80000000		@ the sign bit
+	mov	r0, ip, lsr r2
+	rsbne	r0, r0, #0
+	RET
+
+1:	mov	r0, #0
+	RET
+
+2:	orrs	xl, xl, xh, lsl #12
+	bne	4f			@ r0 is NAN.
+3:	ands	r0, r3, #0x80000000	@ the sign bit
+	moveq	r0, #0x7fffffff		@ maximum signed positive si
+	RET
+
+4:	mov	r0, #0			@ How should we convert NAN?
+	RET
+
+	FUNC_END fixdfsi
+
+ARM_FUNC_START fixunsdfsi
+	orrs	ip, xl, xh, lsl #1
+	movcss	r0, #0			@ value is negative
+	RETc(eq)			@ or 0 (xl, xh overlap r0)
+
+	@ check exponent range.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r2, xh, ip
+	teq	r2, ip
+	beq	1f			@ value is INF or NAN
+	bic	ip, ip, #0x40000000
+	cmp	r2, ip
+	bcc	1b			@ value is too small
+	add	ip, ip, #(31 << 20)
+	cmp	r2, ip
+	bhi	2f			@ value is too large
+
+	rsb	r2, r2, ip
+	mov	ip, xh, lsl #11
+	orr	ip, ip, #0x80000000
+	orr	ip, ip, xl, lsr #21
+	mov	r2, r2, lsr #20
+	mov	r0, ip, lsr r2
+	RET
+
+1:	orrs	xl, xl, xh, lsl #12
+	bne	4b			@ value is NAN.
+2:	mov	r0, #0xffffffff		@ maximum unsigned si
+	RET
+
+	FUNC_END fixunsdfsi
+
+#endif /* L_fixunsdfdi */
+
+#ifdef L_truncdfsf2
+
+ARM_FUNC_START truncdfsf2
+	orrs	r2, xl, xh, lsl #1
+	moveq	r0, r2, rrx
+	RETc(eq)			@ value is 0.0 or -0.0
+	
+	@ check exponent range.
+	mov	ip, #0x7f000000
+	orr	ip, ip, #0x00f00000
+	and	r2, ip, xh
+	teq	r2, ip
+	beq	2f			@ value is INF or NAN
+	bic	xh, xh, ip
+	cmp	r2, #(0x380 << 20)
+	bls	4f			@ value is too small
+
+	@ shift and round mantissa
+1:	movs	r3, xl, lsr #29
+	adc	r3, r3, xh, lsl #3
+
+	@ if halfway between two numbers, round towards LSB = 0.
+	mov	xl, xl, lsl #3
+	teq	xl, #0x80000000
+	biceq	r3, r3, #1
+
+	@ rounding might have created an extra MSB.  If so adjust exponent.
+	tst	r3, #0x00800000
+	addne	r2, r2, #(1 << 20)
+	bicne	r3, r3, #0x00800000
+
+	@ check exponent for overflow
+	mov	ip, #(0x400 << 20)
+	orr	ip, ip, #(0x07f << 20)
+	cmp	r2, ip
+	bcs	3f			@ overflow
+
+	@ adjust exponent, merge with sign bit and mantissa.
+	movs	xh, xh, lsl #1
+	mov	r2, r2, lsl #4
+	orr	r0, r3, r2, rrx
+	eor	r0, r0, #0x40000000
+	RET
+
+2:	@ chech for NAN
+	orrs	xl, xl, xh, lsl #12
+	movne	r0, #0x7f000000
+	orrne	r0, r0, #0x00c00000
+	RETc(ne)			@ return NAN
+
+3:	@ return INF with sign
+	and	r0, xh, #0x80000000
+	orr	r0, r0, #0x7f000000
+	orr	r0, r0, #0x00800000
+	RET
+
+4:	@ check if denormalized value is possible
+	subs	r2, r2, #((0x380 - 24) << 20)
+	andle	r0, xh, #0x80000000	@ too small, return signed 0.
+	RETc(le)
+	
+	@ denormalize value so we can resume with the code above afterwards.
+	orr	xh, xh, #0x00100000
+	mov	r2, r2, lsr #20
+	rsb	r2, r2, #25
+	cmp	r2, #20
+	bgt	6f
+
+	rsb	ip, r2, #32
+	mov	r3, xl, lsl ip
+	mov	xl, xl, lsr r2
+	orr	xl, xl, xh, lsl ip
+	movs	xh, xh, lsl #1
+	mov	xh, xh, lsr r2
+	mov	xh, xh, rrx
+5:	teq	r3, #0			@ fold r3 bits into the LSB
+	orrne	xl, xl, #1		@ for rounding considerations. 
+	mov	r2, #(0x380 << 20)	@ equivalent to the 0 float exponent
+	b	1b
+
+6:	rsb	r2, r2, #(12 + 20)
+	rsb	ip, r2, #32
+	mov	r3, xl, lsl r2
+	mov	xl, xl, lsr ip
+	orr	xl, xl, xh, lsl r2
+	and	xh, xh, #0x80000000
+	b	5b
+
+	FUNC_END truncdfsf2
+
+#endif /* L_truncdfsf2 */
diff --git a/gcc/config/arm/ieee754-sf.S b/gcc/config/arm/ieee754-sf.S
new file mode 100644
index 00000000000..904b536f2ff
--- /dev/null
+++ b/gcc/config/arm/ieee754-sf.S
@@ -0,0 +1,815 @@
+/* ieee754-sf.S single-precision floating point support for ARM
+
+   Copyright (C) 2003  Free Software Foundation, Inc.
+   Contributed by Nicolas Pitre (nico@cam.org)
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
+
+   In addition to the permissions in the GNU General Public License, the
+   Free Software Foundation gives you unlimited permission to link the
+   compiled version of this file into combinations with other programs,
+   and to distribute those combinations without any restriction coming
+   from the use of this file.  (The General Public License restrictions
+   do apply in other respects; for example, they cover modification of
+   the file, and distribution when not linked into a combine
+   executable.)
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/*
+ * Notes:
+ *
+ * The goal of this code is to be as fast as possible.  This is
+ * not meant to be easy to understand for the casual reader.
+ *
+ * Only the default rounding mode is intended for best performances.
+ * Exceptions aren't supported yet, but that can be added quite easily
+ * if necessary without impacting performances.
+ */
+
+#ifdef L_negsf2
+	
+ARM_FUNC_START negsf2
+	eor	r0, r0, #0x80000000	@ flip sign bit
+	RET
+
+	FUNC_END negsf2
+
+#endif
+
+#ifdef L_addsubsf3
+
+ARM_FUNC_START subsf3
+	eor	r1, r1, #0x80000000	@ flip sign bit of second arg
+#if defined(__thumb__) && !defined(__THUMB_INTERWORK__)
+	b	1f			@ Skip Thumb-code prologue
+#endif
+
+ARM_FUNC_START addsf3
+
+1:	@ Compare both args, return zero if equal but the sign.
+	eor	r2, r0, r1
+	teq	r2, #0x80000000
+	beq	LSYM(Lad_z)
+
+	@ If first arg is 0 or -0, return second arg.
+	@ If second arg is 0 or -0, return first arg.
+	bics	r2, r0, #0x80000000
+	moveq	r0, r1
+	bicnes	r2, r1, #0x80000000
+	RETc(eq)
+
+	@ Mask out exponents.
+	mov	ip, #0xff000000
+	and	r2, r0, ip, lsr #1
+	and	r3, r1, ip, lsr #1
+
+	@ If either of them is 255, result will be INF or NAN
+	teq	r2, ip, lsr #1
+	teqne	r3, ip, lsr #1
+	beq	LSYM(Lad_i)
+
+	@ Compute exponent difference.  Make largest exponent in r2,
+	@ corresponding arg in r0, and positive exponent difference in r3.
+	subs	r3, r3, r2
+	addgt	r2, r2, r3
+	eorgt	r1, r0, r1
+	eorgt	r0, r1, r0
+	eorgt	r1, r0, r1
+	rsblt	r3, r3, #0
+
+	@ If exponent difference is too large, return largest argument
+	@ already in r0.  We need up to 25 bit to handle proper rounding
+	@ of 0x1p25 - 1.1.
+	cmp	r3, #(25 << 23)
+	RETc(hi)
+
+	@ Convert mantissa to signed integer.
+	tst	r0, #0x80000000
+	orr	r0, r0, #0x00800000
+	bic	r0, r0, #0xff000000
+	rsbne	r0, r0, #0
+	tst	r1, #0x80000000
+	orr	r1, r1, #0x00800000
+	bic	r1, r1, #0xff000000
+	rsbne	r1, r1, #0
+
+	@ If exponent == difference, one or both args were denormalized.
+	@ Since this is not common case, rescale them off line.
+	teq	r2, r3
+	beq	LSYM(Lad_d)
+LSYM(Lad_x):
+
+	@ Scale down second arg with exponent difference.
+	@ Apply shift one bit left to first arg and the rest to second arg
+	@ to simplify things later, but only if exponent does not become 0.
+	movs	r3, r3, lsr #23
+	teqne	r2, #(1 << 23)
+	movne	r0, r0, lsl #1
+	subne	r2, r2, #(1 << 23)
+	subne	r3, r3, #1
+
+	@ Shift second arg into ip, keep leftover bits into r1.
+	mov	ip, r1, asr r3
+	rsb	r3, r3, #32
+	mov	r1, r1, lsl r3
+
+	add	r0, r0, ip		@ the actual addition
+
+	@ We now have a 64 bit result in r0-r1.
+	@ Keep absolute value in r0-r1, sign in r3.
+	ands	r3, r0, #0x80000000
+	bpl	LSYM(Lad_p)
+	rsbs	r1, r1, #0
+	rsc	r0, r0, #0
+
+	@ Determine how to normalize the result.
+LSYM(Lad_p):
+	cmp	r0, #0x00800000
+	bcc	LSYM(Lad_l)
+	cmp	r0, #0x01000000
+	bcc	LSYM(Lad_r0)
+	cmp	r0, #0x02000000
+	bcc	LSYM(Lad_r1)
+
+	@ Result needs to be shifted right.
+	movs	r0, r0, lsr #1
+	mov	r1, r1, rrx
+	add	r2, r2, #(1 << 23)
+LSYM(Lad_r1):
+	movs	r0, r0, lsr #1
+	mov	r1, r1, rrx
+	add	r2, r2, #(1 << 23)
+
+	@ Our result is now properly aligned into r0, remaining bits in r1.
+	@ Round with MSB of r1. If halfway between two numbers, round towards
+	@ LSB of r0 = 0. 
+LSYM(Lad_r0):
+	add	r0, r0, r1, lsr #31
+	teq	r1, #0x80000000
+	biceq	r0, r0, #1
+
+	@ Rounding may have added a new MSB.  Adjust exponent.
+	@ That MSB will be cleared when exponent is merged below.
+	tst	r0, #0x01000000
+	addne	r2, r2, #(1 << 23)
+
+	@ Make sure we did not bust our exponent.
+	cmp	r2, #(254 << 23)
+	bhi	LSYM(Lad_o)
+
+	@ Pack final result together.
+LSYM(Lad_e):
+	bic	r0, r0, #0x01800000
+	orr	r0, r0, r2
+	orr	r0, r0, r3
+	RET
+
+	@ Result must be shifted left.
+	@ No rounding necessary since r1 will always be 0.
+LSYM(Lad_l):
+
+#if __ARM_ARCH__ < 5
+
+	movs	ip, r0, lsr #12
+	moveq	r0, r0, lsl #12
+	subeq	r2, r2, #(12 << 23)
+	tst	r0, #0x00ff0000
+	moveq	r0, r0, lsl #8
+	subeq	r2, r2, #(8 << 23)
+	tst	r0, #0x00f00000
+	moveq	r0, r0, lsl #4
+	subeq	r2, r2, #(4 << 23)
+	tst	r0, #0x00c00000
+	moveq	r0, r0, lsl #2
+	subeq	r2, r2, #(2 << 23)
+	tst	r0, #0x00800000
+	moveq	r0, r0, lsl #1
+	subeq	r2, r2, #(1 << 23)
+	cmp	r2, #0
+	bgt	LSYM(Lad_e)
+
+#else
+
+	clz	ip, r0
+	sub	ip, ip, #8
+	mov	r0, r0, lsl ip
+	subs	r2, r2, ip, lsl #23
+	bgt	LSYM(Lad_e)
+
+#endif
+
+	@ Exponent too small, denormalize result.
+	mvn	r2, r2, asr #23
+	add	r2, r2, #2
+	orr	r0, r3, r0, lsr r2
+	RET
+
+	@ Fixup and adjust bit position for denormalized arguments.
+	@ Note that r2 must not remain equal to 0.
+LSYM(Lad_d):
+	teq	r2, #0
+	eoreq	r0, r0, #0x00800000
+	addeq	r2, r2, #(1 << 23)
+	eor	r1, r1, #0x00800000
+	subne	r3, r3, #(1 << 23)
+	b	LSYM(Lad_x)
+
+	@ Result is x - x = 0, unless x is INF or NAN.
+LSYM(Lad_z):
+	mov	ip, #0xff000000
+	and	r2, r0, ip, lsr #1
+	teq	r2, ip, lsr #1
+	moveq	r0, ip, asr #2
+	movne	r0, #0
+	RET
+
+	@ Overflow: return INF.
+LSYM(Lad_o):
+	orr	r0, r3, #0x7f000000
+	orr	r0, r0, #0x00800000
+	RET
+
+	@ At least one of r0/r1 is INF/NAN.
+	@   if r0 != INF/NAN: return r1 (which is INF/NAN)
+	@   if r1 != INF/NAN: return r0 (which is INF/NAN)
+	@   if r0 or r1 is NAN: return NAN
+	@   if opposite sign: return NAN
+	@   return r0 (which is INF or -INF)
+LSYM(Lad_i):
+	teq	r2, ip, lsr #1
+	movne	r0, r1
+	teqeq	r3, ip, lsr #1
+	RETc(ne)
+	movs	r2, r0, lsl #9
+	moveqs	r2, r1, lsl #9
+	teqeq	r0, r1
+	orrne	r0, r3, #0x00400000	@ NAN
+	RET
+
+	FUNC_END addsf3
+	FUNC_END subsf3
+
+ARM_FUNC_START floatunsisf
+	mov	r3, #0
+	b	1f
+
+ARM_FUNC_START floatsisf
+	ands	r3, r0, #0x80000000
+	rsbmi	r0, r0, #0
+
+1:	teq	r0, #0
+	RETc(eq)
+
+	mov	r1, #0
+	mov	r2, #((127 + 23) << 23)
+	tst	r0, #0xfc000000
+	beq	LSYM(Lad_p)
+
+	@ We need to scale the value a little before branching to code above.
+	tst	r0, #0xf0000000
+	movne	r1, r0, lsl #28
+	movne	r0, r0, lsr #4
+	addne	r2, r2, #(4 << 23)
+	tst	r0, #0x0c000000
+	beq	LSYM(Lad_p)
+	mov	r1, r1, lsr #2
+	orr	r1, r1, r0, lsl #30
+	mov	r0, r0, lsr #2
+	add	r2, r2, #(2 << 23)
+	b	LSYM(Lad_p)
+
+	FUNC_END floatsisf
+	FUNC_END floatunsisf
+
+#endif /* L_addsubsf3 */
+
+#ifdef L_muldivsf3
+
+ARM_FUNC_START mulsf3
+
+	@ Mask out exponents.
+	mov	ip, #0xff000000
+	and	r2, r0, ip, lsr #1
+	and	r3, r1, ip, lsr #1
+
+	@ Trap any INF/NAN.
+	teq	r2, ip, lsr #1
+	teqne	r3, ip, lsr #1
+	beq	LSYM(Lml_s)
+
+	@ Trap any multiplication by 0.
+	bics	ip, r0, #0x80000000
+	bicnes	ip, r1, #0x80000000
+	beq	LSYM(Lml_z)
+
+	@ Shift exponents right one bit to make room for overflow bit.
+	@ If either of them is 0, scale denormalized arguments off line.
+	@ Then add both exponents together.
+	movs	r2, r2, lsr #1
+	teqne	r3, #0
+	beq	LSYM(Lml_d)
+LSYM(Lml_x):
+	add	r2, r2, r3, asr #1
+
+	@ Preserve final sign in r2 along with exponent for now.
+	teq	r0, r1
+	orrmi	r2, r2, #0x8000
+
+	@ Convert mantissa to unsigned integer.
+	bic	r0, r0, #0xff000000
+	bic	r1, r1, #0xff000000
+	orr	r0, r0, #0x00800000
+	orr	r1, r1, #0x00800000
+
+#if __ARM_ARCH__ < 4
+
+	@ Well, no way to make it shorter without the umull instruction.
+	@ We must perform that 24 x 24 -> 48 bit multiplication by hand.
+	stmfd	sp!, {r4, r5}
+	mov	r4, r0, lsr #16
+	mov	r5, r1, lsr #16
+	bic	r0, r0, #0x00ff0000
+	bic	r1, r1, #0x00ff0000
+	mul	ip, r4, r5
+	mul	r3, r0, r1
+	mul	r0, r5, r0
+	mla	r0, r4, r1, r0
+	adds	r3, r3, r0, lsl #16
+	adc	ip, ip, r0, lsr #16
+	ldmfd	sp!, {r4, r5}
+
+#else
+
+	umull	r3, ip, r0, r1		@ The actual multiplication.
+
+#endif
+
+	@ Put final sign in r0.
+	mov	r0, r2, lsl #16
+	bic	r2, r2, #0x8000
+
+	@ Adjust result if one extra MSB appeared.
+	@ The LSB may be lost but this never changes the result in this case.
+	tst	ip, #(1 << 15)
+	addne	r2, r2, #(1 << 22)
+	movnes	ip, ip, lsr #1
+	movne	r3, r3, rrx
+
+	@ Apply exponent bias, check range for underflow.
+	subs	r2, r2, #(127 << 22)
+	ble	LSYM(Lml_u)
+
+	@ Scale back to 24 bits with rounding.
+	@ r0 contains sign bit already.
+	orrs	r0, r0, r3, lsr #23
+	adc	r0, r0, ip, lsl #9
+
+	@ If halfway between two numbers, rounding should be towards LSB = 0.
+	mov	r3, r3, lsl #9
+	teq	r3, #0x80000000
+	biceq	r0, r0, #1
+
+	@ Note: rounding may have produced an extra MSB here.
+	@ The extra bit is cleared before merging the exponent below.
+	tst	r0, #0x01000000
+	addne	r2, r2, #(1 << 22)
+
+	@ Check for exponent overflow
+	cmp	r2, #(255 << 22)
+	bge	LSYM(Lml_o)
+
+	@ Add final exponent.
+	bic	r0, r0, #0x01800000
+	orr	r0, r0, r2, lsl #1
+	RET
+
+	@ Result is 0, but determine sign anyway.
+LSYM(Lml_z):	eor	r0, r0, r1
+	bic	r0, r0, #0x7fffffff
+	RET
+
+	@ Check if denormalized result is possible, otherwise return signed 0.
+LSYM(Lml_u):
+	cmn	r2, #(24 << 22)
+	RETc(le)
+
+	@ Find out proper shift value.
+	mvn	r1, r2, asr #22
+	subs	r1, r1, #7
+	bgt	LSYM(Lml_ur)
+
+	@ Shift value left, round, etc.
+	add	r1, r1, #32
+	orrs	r0, r0, r3, lsr r1
+	rsb	r1, r1, #32
+	adc	r0, r0, ip, lsl r1
+	mov	ip, r3, lsl r1
+	teq	ip, #0x80000000
+	biceq	r0, r0, #1
+	RET
+
+	@ Shift value right, round, etc.
+	@ Note: r1 must not be 0 otherwise carry does not get set.
+LSYM(Lml_ur):
+	orrs	r0, r0, ip, lsr r1
+	adc	r0, r0, #0
+	rsb	r1, r1, #32
+	mov	ip, ip, lsl r1
+	teq	r3, #0
+	teqeq	ip, #0x80000000
+	biceq	r0, r0, #1
+	RET
+
+	@ One or both arguments are denormalized.
+	@ Scale them leftwards and preserve sign bit.
+LSYM(Lml_d):
+	teq	r2, #0
+	and	ip, r0, #0x80000000
+1:	moveq	r0, r0, lsl #1
+	tsteq	r0, #0x00800000
+	subeq	r2, r2, #(1 << 22)
+	beq	1b
+	orr	r0, r0, ip
+	teq	r3, #0
+	and	ip, r1, #0x80000000
+2:	moveq	r1, r1, lsl #1
+	tsteq	r1, #0x00800000
+	subeq	r3, r3, #(1 << 23)
+	beq	2b
+	orr	r1, r1, ip
+	b	LSYM(Lml_x)
+
+	@ One or both args are INF or NAN.
+LSYM(Lml_s):
+	teq	r0, #0x0
+	teqne	r1, #0x0
+	teqne	r0, #0x80000000
+	teqne	r1, #0x80000000
+	beq	LSYM(Lml_n)		@ 0 * INF or INF * 0 -> NAN
+	teq	r2, ip, lsr #1
+	bne	1f
+	movs	r2, r0, lsl #9
+	bne	LSYM(Lml_n)		@ NAN * <anything> -> NAN
+1:	teq	r3, ip, lsr #1
+	bne	LSYM(Lml_i)
+	movs	r3, r1, lsl #9
+	bne	LSYM(Lml_n)		@ <anything> * NAN -> NAN
+
+	@ Result is INF, but we need to determine its sign.
+LSYM(Lml_i):
+	eor	r0, r0, r1
+
+	@ Overflow: return INF (sign already in r0).
+LSYM(Lml_o):
+	and	r0, r0, #0x80000000
+	orr	r0, r0, #0x7f000000
+	orr	r0, r0, #0x00800000
+	RET
+
+	@ Return NAN.
+LSYM(Lml_n):
+	mov	r0, #0x7f000000
+	orr	r0, r0, #0x00c00000
+	RET
+
+	FUNC_END mulsf3
+
+ARM_FUNC_START divsf3
+
+	@ Mask out exponents.
+	mov	ip, #0xff000000
+	and	r2, r0, ip, lsr #1
+	and	r3, r1, ip, lsr #1
+
+	@ Trap any INF/NAN or zeroes.
+	teq	r2, ip, lsr #1
+	teqne	r3, ip, lsr #1
+	bicnes	ip, r0, #0x80000000
+	bicnes	ip, r1, #0x80000000
+	beq	LSYM(Ldv_s)
+
+	@ Shift exponents right one bit to make room for overflow bit.
+	@ If either of them is 0, scale denormalized arguments off line.
+	@ Then substract divisor exponent from dividend''s.
+	movs	r2, r2, lsr #1
+	teqne	r3, #0
+	beq	LSYM(Ldv_d)
+LSYM(Ldv_x):
+	sub	r2, r2, r3, asr #1
+
+	@ Preserve final sign into ip.
+	eor	ip, r0, r1
+
+	@ Convert mantissa to unsigned integer.
+	@ Dividend -> r3, divisor -> r1.
+	mov	r3, #0x10000000
+	movs	r1, r1, lsl #9
+	mov	r0, r0, lsl #9
+	beq	LSYM(Ldv_1)
+	orr	r1, r3, r1, lsr #4
+	orr	r3, r3, r0, lsr #4
+
+	@ Initialize r0 (result) with final sign bit.
+	and	r0, ip, #0x80000000
+
+	@ Ensure result will land to known bit position.
+	cmp	r3, r1
+	subcc	r2, r2, #(1 << 22)
+	movcc	r3, r3, lsl #1
+
+	@ Apply exponent bias, check range for over/underflow.
+	add	r2, r2, #(127 << 22)
+	cmn	r2, #(24 << 22)
+	RETc(le)
+	cmp	r2, #(255 << 22)
+	bge	LSYM(Lml_o)
+
+	@ The actual division loop.
+	mov	ip, #0x00800000
+1:	cmp	r3, r1
+	subcs	r3, r3, r1
+	orrcs	r0, r0, ip
+	cmp	r3, r1, lsr #1
+	subcs	r3, r3, r1, lsr #1
+	orrcs	r0, r0, ip, lsr #1
+	cmp	r3, r1, lsr #2
+	subcs	r3, r3, r1, lsr #2
+	orrcs	r0, r0, ip, lsr #2
+	cmp	r3, r1, lsr #3
+	subcs	r3, r3, r1, lsr #3
+	orrcs	r0, r0, ip, lsr #3
+	movs	r3, r3, lsl #4
+	movnes	ip, ip, lsr #4
+	bne	1b
+
+	@ Check if denormalized result is needed.
+	cmp	r2, #0
+	ble	LSYM(Ldv_u)
+
+	@ Apply proper rounding.
+	cmp	r3, r1
+	addcs	r0, r0, #1
+	biceq	r0, r0, #1
+
+	@ Add exponent to result.
+	bic	r0, r0, #0x00800000
+	orr	r0, r0, r2, lsl #1
+	RET
+
+	@ Division by 0x1p*: let''s shortcut a lot of code.
+LSYM(Ldv_1):
+	and	ip, ip, #0x80000000
+	orr	r0, ip, r0, lsr #9
+	add	r2, r2, #(127 << 22)
+	cmp	r2, #(255 << 22)
+	bge	LSYM(Lml_o)
+	cmp	r2, #0
+	orrgt	r0, r0, r2, lsl #1
+	RETc(gt)
+	cmn	r2, #(24 << 22)
+	movle	r0, ip
+	RETc(le)
+	orr	r0, r0, #0x00800000
+	mov	r3, #0
+
+	@ Result must be denormalized: prepare parameters to use code above.
+	@ r3 already contains remainder for rounding considerations.
+LSYM(Ldv_u):
+	bic	ip, r0, #0x80000000
+	and	r0, r0, #0x80000000
+	mvn	r1, r2, asr #22
+	add	r1, r1, #2
+	b	LSYM(Lml_ur)
+
+	@ One or both arguments are denormalized.
+	@ Scale them leftwards and preserve sign bit.
+LSYM(Ldv_d):
+	teq	r2, #0
+	and	ip, r0, #0x80000000
+1:	moveq	r0, r0, lsl #1
+	tsteq	r0, #0x00800000
+	subeq	r2, r2, #(1 << 22)
+	beq	1b
+	orr	r0, r0, ip
+	teq	r3, #0
+	and	ip, r1, #0x80000000
+2:	moveq	r1, r1, lsl #1
+	tsteq	r1, #0x00800000
+	subeq	r3, r3, #(1 << 23)
+	beq	2b
+	orr	r1, r1, ip
+	b	LSYM(Ldv_x)
+
+	@ One or both arguments is either INF, NAN or zero.
+LSYM(Ldv_s):
+	mov	ip, #0xff000000
+	teq	r2, ip, lsr #1
+	teqeq	r3, ip, lsr #1
+	beq	LSYM(Lml_n)		@ INF/NAN / INF/NAN -> NAN
+	teq	r2, ip, lsr #1
+	bne	1f
+	movs	r2, r0, lsl #9
+	bne	LSYM(Lml_n)		@ NAN / <anything> -> NAN
+	b	LSYM(Lml_i)		@ INF / <anything> -> INF
+1:	teq	r3, ip, lsr #1
+	bne	2f
+	movs	r3, r1, lsl #9
+	bne	LSYM(Lml_n)		@ <anything> / NAN -> NAN
+	b	LSYM(Lml_z)		@ <anything> / INF -> 0
+2:	@ One or both arguments are 0.
+	bics	r2, r0, #0x80000000
+	bne	LSYM(Lml_i)		@ <non_zero> / 0 -> INF
+	bics	r3, r1, #0x80000000
+	bne	LSYM(Lml_z)		@ 0 / <non_zero> -> 0
+	b	LSYM(Lml_n)		@ 0 / 0 -> NAN
+
+	FUNC_END divsf3
+
+#endif /* L_muldivsf3 */
+
+#ifdef L_cmpsf2
+
+FUNC_START gesf2
+ARM_FUNC_START gtsf2
+	mov	r3, #-1
+	b	1f
+
+FUNC_START lesf2
+ARM_FUNC_START ltsf2
+	mov	r3, #1
+	b	1f
+
+FUNC_START nesf2
+FUNC_START eqsf2
+ARM_FUNC_START cmpsf2
+	mov	r3, #1			@ how should we specify unordered here?
+
+1:	@ Trap any INF/NAN first.
+	mov	ip, #0xff000000
+	and	r2, r1, ip, lsr #1
+	teq	r2, ip, lsr #1
+	and	r2, r0, ip, lsr #1
+	teqne	r2, ip, lsr #1
+	beq	3f
+
+	@ Test for equality.
+	@ Note that 0.0 is equal to -0.0.
+2:	orr	r3, r0, r1
+	bics	r3, r3, #0x80000000	@ either 0.0 or -0.0
+	teqne	r0, r1			@ or both the same
+	moveq	r0, #0
+	RETc(eq)
+
+	@ Check for sign difference.  The N flag is set if it is the case.
+	@ If so, return sign of r0.
+	movmi	r0, r0, asr #31
+	orrmi	r0, r0, #1
+	RETc(mi)
+
+	@ Compare exponents.
+	and	r3, r1, ip, lsr #1
+	cmp	r2, r3
+
+	@ Compare mantissa if exponents are equal
+	moveq	r0, r0, lsl #9
+	cmpeq	r0, r1, lsl #9
+	movcs	r0, r1, asr #31
+	mvncc	r0, r1, asr #31
+	orr	r0, r0, #1
+	RET
+
+	@ Look for a NAN. 
+3:	and	r2, r1, ip, lsr #1
+	teq	r2, ip, lsr #1
+	bne	4f
+	movs	r2, r1, lsl #9
+	bne	5f			@ r1 is NAN
+4:	and	r2, r0, ip, lsr #1
+	teq	r2, ip, lsr #1
+	bne	2b
+	movs	ip, r0, lsl #9
+	beq	2b			@ r0 is not NAN
+5:	mov	r0, r3			@ return unordered code from r3.
+	RET
+
+	FUNC_END gesf2
+	FUNC_END gtsf2
+	FUNC_END lesf2
+	FUNC_END ltsf2
+	FUNC_END nesf2
+	FUNC_END eqsf2
+	FUNC_END cmpsf2
+
+#endif /* L_cmpsf2 */
+
+#ifdef L_unordsf2
+
+ARM_FUNC_START unordsf2
+	mov	ip, #0xff000000
+	and	r2, r1, ip, lsr #1
+	teq	r2, ip, lsr #1
+	bne	1f
+	movs	r2, r1, lsl #9
+	bne	3f			@ r1 is NAN
+1:	and	r2, r0, ip, lsr #1
+	teq	r2, ip, lsr #1
+	bne	2f
+	movs	r2, r0, lsl #9
+	bne	3f			@ r0 is NAN
+2:	mov	r0, #0			@ arguments are ordered.
+	RET
+3:	mov	r0, #1			@ arguments are unordered.
+	RET
+
+	FUNC_END unordsf2
+
+#endif /* L_unordsf2 */
+
+#ifdef L_fixsfsi
+
+ARM_FUNC_START fixsfsi
+	movs	r0, r0, lsl #1
+	RETc(eq)			@ value is 0.
+
+	mov	r1, r1, rrx		@ preserve C flag (the actual sign)
+
+	@ check exponent range.
+	and	r2, r0, #0xff000000
+	cmp	r2, #(127 << 24)
+	movcc	r0, #0			@ value is too small
+	RETc(cc)
+	cmp	r2, #((127 + 31) << 24)
+	bcs	1f			@ value is too large
+
+	mov	r0, r0, lsl #7
+	orr	r0, r0, #0x80000000
+	mov	r2, r2, lsr #24
+	rsb	r2, r2, #(127 + 31)
+	tst	r1, #0x80000000		@ the sign bit
+	mov	r0, r0, lsr r2
+	rsbne	r0, r0, #0
+	RET
+
+1:	teq	r2, #0xff000000
+	bne	2f
+	movs	r0, r0, lsl #8
+	bne	3f			@ r0 is NAN.
+2:	ands	r0, r1, #0x80000000	@ the sign bit
+	moveq	r0, #0x7fffffff		@ the maximum signed positive si
+	RET
+
+3:	mov	r0, #0			@ What should we convert NAN to?
+	RET
+
+	FUNC_END fixsfsi
+
+#endif /* L_fixsfsi */
+
+#ifdef L_fixunssfsi
+
+ARM_FUNC_START fixunssfsi
+	movs	r0, r0, lsl #1
+	movcss	r0, #0			@ value is negative...
+	RETc(eq)			@ ... or 0.
+
+
+	@ check exponent range.
+	and	r2, r0, #0xff000000
+	cmp	r2, #(127 << 24)
+	movcc	r0, #0			@ value is too small
+	RETc(cc)
+	cmp	r2, #((127 + 32) << 24)
+	bcs	1f			@ value is too large
+
+	mov	r0, r0, lsl #7
+	orr	r0, r0, #0x80000000
+	mov	r2, r2, lsr #24
+	rsb	r2, r2, #(127 + 31)
+	mov	r0, r0, lsr r2
+	RET
+
+1:	teq	r2, #0xff000000
+	bne	2f
+	movs	r0, r0, lsl #8
+	bne	3f			@ r0 is NAN.
+2:	mov	r0, #0xffffffff		@ maximum unsigned si
+	RET
+
+3:	mov	r0, #0			@ What should we convert NAN to?
+	RET
+
+	FUNC_END fixunssfsi
+
+#endif /* L_fixunssfsi */
diff --git a/gcc/config/arm/lib1funcs.asm b/gcc/config/arm/lib1funcs.asm
index f80af2dd60e..34cf986d03e 100644
--- a/gcc/config/arm/lib1funcs.asm
+++ b/gcc/config/arm/lib1funcs.asm
@@ -61,66 +61,107 @@ Boston, MA 02111-1307, USA.  */
 
 /* Function end macros.  Variants for 26 bit APCS and interworking.  */
 
+@ This selects the minimum architecture level required.
+#define __ARM_ARCH__ 3
+
+#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \
+	|| defined(__ARM_ARCH_4T__)
+/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with
+   long multiply instructions.  That includes v3M.  */
+# undef __ARM_ARCH__
+# define __ARM_ARCH__ 4
+#endif
+	
+#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \
+	|| defined(__ARM_ARCH_5TE__)
+# undef __ARM_ARCH__
+# define __ARM_ARCH__ 5
+#endif
+
+/* How to return from a function call depends on the architecture variant.  */
+
 #ifdef __APCS_26__
+
 # define RET		movs	pc, lr
 # define RETc(x)	mov##x##s	pc, lr
-# define RETCOND 	^
+
+#elif (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__)
+
+# define RET		bx	lr
+# define RETc(x)	bx##x	lr
+
+# if (__ARM_ARCH__ == 4) \
+	&& (defined(__thumb__) || defined(__THUMB_INTERWORK__))
+#  define __INTERWORKING__
+# endif
+
+#else
+
+# define RET		mov	pc, lr
+# define RETc(x)	mov##x	pc, lr
+
+#endif
+
+/* Don't pass dirn, it's there just to get token pasting right.  */
+
+.macro	RETLDM	regs=, cond=, dirn=ia
+#ifdef __APCS_26__
+	.ifc "\regs",""
+	ldm\cond\dirn	sp!, {pc}^
+	.else
+	ldm\cond\dirn	sp!, {\regs, pc}^
+	.endif
+#elif defined (__INTERWORKING__)
+	.ifc "\regs",""
+	ldr\cond	lr, [sp], #4
+	.else
+	ldm\cond\dirn	sp!, {\regs, lr}
+	.endif
+	bx\cond	lr
+#else
+	.ifc "\regs",""
+	ldr\cond	pc, [sp], #4
+	.else
+	ldm\cond\dirn	sp!, {\regs, pc}
+	.endif
+#endif
+.endm
+
+
 .macro ARM_LDIV0
 LSYM(Ldiv0):
 	str	lr, [sp, #-4]!
 	bl	SYM (__div0) __PLT__
 	mov	r0, #0			@ About as wrong as it could be.
-	ldmia	sp!, {pc}^
+	RETLDM
 .endm
-#else
-# ifdef __THUMB_INTERWORK__
-#  define RET		bx	lr
-#  define RETc(x)	bx##x	lr
+
+
 .macro THUMB_LDIV0
 LSYM(Ldiv0):
 	push	{ lr }
 	bl	SYM (__div0)
 	mov	r0, #0			@ About as wrong as it could be.
+#if defined (__INTERWORKING__)
 	pop	{ r1 }
 	bx	r1
-.endm
-.macro ARM_LDIV0
-LSYM(Ldiv0):
-	str	lr, [sp, #-4]!
-	bl	SYM (__div0) __PLT__
-	mov	r0, #0			@ About as wrong as it could be.
-	ldr	lr, [sp], #4
-	bx	lr
-.endm	
-# else
-#  define RET		mov	pc, lr
-#  define RETc(x)	mov##x	pc, lr
-.macro THUMB_LDIV0
-LSYM(Ldiv0):
-	push	{ lr }
-	bl	SYM (__div0)
-	mov	r0, #0			@ About as wrong as it could be.
+#else
 	pop	{ pc }
-.endm
-.macro ARM_LDIV0
-LSYM(Ldiv0):
-	str	lr, [sp, #-4]!
-	bl	SYM (__div0) __PLT__
-	mov	r0, #0			@ About as wrong as it could be.
-	ldmia	sp!, {pc}
-.endm	
-# endif
-# define RETCOND
 #endif
+.endm
 
 .macro FUNC_END name
+	SIZE (__\name)
+.endm
+
+.macro DIV_FUNC_END name
 LSYM(Ldiv0):
 #ifdef __thumb__
 	THUMB_LDIV0
 #else
 	ARM_LDIV0
 #endif
-	SIZE (__\name)	
+	FUNC_END \name
 .endm
 
 .macro THUMB_FUNC_START name
@@ -149,7 +190,24 @@ SYM (\name):
 	THUMB_FUNC
 SYM (__\name):
 .endm
-		
+
+/* Special function that will always be coded in ARM assembly, even if
+   in Thumb-only compilation.  */
+
+#if defined(__thumb__) && !defined(__THUMB_INTERWORK__)
+.macro	ARM_FUNC_START name
+	FUNC_START \name
+	bx	pc
+	nop
+	.arm
+_L__\name:		/* A hook to tell gdb that we've switched to ARM */
+.endm
+#else
+.macro	ARM_FUNC_START name
+	FUNC_START \name
+.endm
+#endif
+
 /* Register aliases.  */
 
 work		.req	r4	@ XXXX is this safe ?
@@ -165,7 +223,7 @@ lr		.req	r14
 pc		.req	r15
 #endif
 /* ------------------------------------------------------------------------ */
-/*		Bodies of the divsion and modulo routines.		    */
+/*		Bodies of the division and modulo routines.		    */
 /* ------------------------------------------------------------------------ */	
 .macro ARM_DIV_MOD_BODY modulo
 LSYM(Loop1):
@@ -452,7 +510,7 @@ LSYM(Lgot_result):
 
 #endif /* ARM version */
 
-	FUNC_END udivsi3
+	DIV_FUNC_END udivsi3
 
 #endif /* L_udivsi3 */
 /* ------------------------------------------------------------------------ */
@@ -493,7 +551,7 @@ LSYM(Lover10):
 
 #endif /* ARM version.  */
 	
-	FUNC_END umodsi3
+	DIV_FUNC_END umodsi3
 
 #endif /* L_umodsi3 */
 /* ------------------------------------------------------------------------ */
@@ -555,7 +613,7 @@ LSYM(Lover12):
 
 #endif /* ARM version */
 	
-	FUNC_END divsi3
+	DIV_FUNC_END divsi3
 
 #endif /* L_divsi3 */
 /* ------------------------------------------------------------------------ */
@@ -616,7 +674,7 @@ LSYM(Lover12):
 
 #endif /* ARM version */
 	
-	FUNC_END modsi3
+	DIV_FUNC_END modsi3
 
 #endif /* L_modsi3 */
 /* ------------------------------------------------------------------------ */
@@ -626,7 +684,7 @@ LSYM(Lover12):
 
 	RET
 
-	SIZE	(__div0)
+	FUNC_END div0
 	
 #endif /* L_divmodsi_tools */
 /* ------------------------------------------------------------------------ */
@@ -639,22 +697,18 @@ LSYM(Lover12):
 #define __NR_getpid			(__NR_SYSCALL_BASE+ 20)
 #define __NR_kill			(__NR_SYSCALL_BASE+ 37)
 
+	.code	32
 	FUNC_START div0
 
 	stmfd	sp!, {r1, lr}
 	swi	__NR_getpid
 	cmn	r0, #1000
-	ldmhsfd	sp!, {r1, pc}RETCOND	@ not much we can do
+	RETLDM	r1 hs
 	mov	r1, #SIGFPE
 	swi	__NR_kill
-#ifdef __THUMB_INTERWORK__
-	ldmfd	sp!, {r1, lr}
-	bx	lr
-#else
-	ldmfd	sp!, {r1, pc}RETCOND
-#endif
+	RETLDM	r1
 
-	SIZE 	(__div0)
+	FUNC_END div0
 	
 #endif /* L_dvmd_lnx */
 /* ------------------------------------------------------------------------ */
@@ -723,24 +777,23 @@ LSYM(Lover12):
 
 	.code   32
 	.globl _arm_return
-_arm_return:		
-	ldmia 	r13!, {r12}
-	bx 	r12
+_arm_return:
+	RETLDM
 	.code   16
 
-.macro interwork register					
-	.code   16
+.macro interwork register
+	.code	16
 
 	THUMB_FUNC_START _interwork_call_via_\register
 
-	bx 	pc
+	bx	pc
 	nop
-	
-	.code   32
-	.globl .Lchange_\register
-.Lchange_\register:
+
+	.code	32
+	.globl LSYM(Lchange_\register)
+LSYM(Lchange_\register):
 	tst	\register, #1
-	stmeqdb	r13!, {lr}
+	streq	lr, [sp, #-4]!
 	adreq	lr, _arm_return
 	bx	\register
 
@@ -782,3 +835,7 @@ _arm_return:
 	SIZE	(_interwork_call_via_lr)
 	
 #endif /* L_interwork_call_via_rX */
+
+#include "ieee754-df.S"
+#include "ieee754-sf.S"
+
diff --git a/gcc/config/arm/linux-elf.h b/gcc/config/arm/linux-elf.h
index 1a86e458927..f55a42562cb 100644
--- a/gcc/config/arm/linux-elf.h
+++ b/gcc/config/arm/linux-elf.h
@@ -1,5 +1,5 @@
 /* Definitions for ARM running Linux-based GNU systems using ELF
-   Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002 
+   Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Philip Blundell <philb@gnu.org>
 
@@ -127,3 +127,6 @@
 
 #undef  CC1_SPEC
 #define CC1_SPEC "%{profile:-p}"
+
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
diff --git a/gcc/config/arm/pe.c b/gcc/config/arm/pe.c
index 1413eeeb51d..d25fd0da977 100644
--- a/gcc/config/arm/pe.c
+++ b/gcc/config/arm/pe.c
@@ -167,7 +167,7 @@ arm_mark_dllimport (decl)
       && !DECL_VIRTUAL_P (decl)
       && DECL_INITIAL (decl))
     {
-      error_with_decl (decl, "initialized variable `%s' is marked dllimport");
+      error ("%Jinitialized variable '%D' is marked dllimport", decl, decl);
       return;
     }
   /* Nor can they be static.  */
@@ -176,7 +176,7 @@ arm_mark_dllimport (decl)
       && !DECL_VIRTUAL_P (decl)
       && 0 /*???*/)
     {
-      error_with_decl (decl, "static variable `%s' is marked dllimport");
+      error ("%Jstatic variable '%D' is marked dllimport", decl, decl);
       return;
     }
 
diff --git a/gcc/config/arm/t-arm-elf b/gcc/config/arm/t-arm-elf
index 79506fb5a62..1b8f719b949 100644
--- a/gcc/config/arm/t-arm-elf
+++ b/gcc/config/arm/t-arm-elf
@@ -1,29 +1,14 @@
 LIB1ASMSRC = arm/lib1funcs.asm
-LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX
+LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \
+	_call_via_rX _interwork_call_via_rX \
+	_negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi \
+	_truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \
+	_fixsfsi _fixunssfsi
 
-# We want fine grained libraries, so use the new code to build the
-# floating point emulation libraries.
-FPBIT = fp-bit.c
-DPBIT = dp-bit.c
-
-fp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#define FLOAT' > fp-bit.c
-	echo '#ifndef __ARMEB__' >> fp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c
-	echo '#endif' >> fp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
-
-dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#ifndef __ARMEB__' > dp-bit.c
-	echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c
-	echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c
-	echo '#endif' >> dp-bit.c
-	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
-
-	
 MULTILIB_OPTIONS     = marm/mthumb
 MULTILIB_DIRNAMES    = arm thumb
 MULTILIB_EXCEPTIONS  = 
+MULTILIB_MATCHES     =
 
 # MULTILIB_OPTIONS    += mcpu=ep9312
 # MULTILIB_DIRNAMES   += ep9312
@@ -31,8 +16,7 @@ MULTILIB_EXCEPTIONS  =
 	
 # MULTILIB_OPTIONS     += mlittle-endian/mbig-endian
 # MULTILIB_DIRNAMES    += le be
-# MULTILIB_EXCEPTIONS  = 
-# MULTILIB_MATCHES     = mbig-endian=mbe mlittle-endian=mle
+# MULTILIB_MATCHES     += mbig-endian=mbe mlittle-endian=mle
 # 
 # MULTILIB_OPTIONS    += mhard-float/msoft-float
 # MULTILIB_DIRNAMES   += fpu soft
@@ -97,3 +81,4 @@ $(T)crti.o: $(srcdir)/config/arm/crti.asm $(GCC_PASSES)
 $(T)crtn.o: $(srcdir)/config/arm/crtn.asm $(GCC_PASSES)
 	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
 	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/arm/crtn.asm
+
diff --git a/gcc/config/arm/t-linux b/gcc/config/arm/t-linux
index 7dbd0c0e277..1c5f48ae6f5 100644
--- a/gcc/config/arm/t-linux
+++ b/gcc/config/arm/t-linux
@@ -3,9 +3,6 @@
 TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC
 LIBGCC2_DEBUG_CFLAGS = -g0
 
-# Don't build enquire
-ENQUIRE=
-
 LIB1ASMSRC = arm/lib1funcs.asm
 LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx
 
diff --git a/gcc/config/arm/t-netbsd b/gcc/config/arm/t-netbsd
index 76e431bfb11..77e622716f2 100644
--- a/gcc/config/arm/t-netbsd
+++ b/gcc/config/arm/t-netbsd
@@ -19,8 +19,3 @@ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
 SHLIB_INSTALL = $(INSTALL_DATA) $(SHLIB_NAME) $$(DESTDIR)$$(slibdir)/$(SHLIB_SONAME); \
 	rm -f $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME); \
 	$(LN_S) $(SHLIB_SONAME) $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME)
-
-# Don't build enquire
-ENQUIRE=
-
-
diff --git a/gcc/config/arm/t-semi b/gcc/config/arm/t-semi
index ce394606386..072691a9e21 100644
--- a/gcc/config/arm/t-semi
+++ b/gcc/config/arm/t-semi
@@ -3,9 +3,6 @@
 TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer
 LIBGCC2_DEBUG_CFLAGS = -g0
 
-# Don't build enquire
-ENQUIRE=
-
 LIB1ASMSRC = arm/lib1funcs.asm
 LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _call_via_rX _interwork_call_via_rX
 
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 432dd538ae6..16701d1b550 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -281,20 +281,17 @@ avr_override_options ()
 void
 avr_init_once ()
 {
-  tmp_reg_rtx = xmalloc (sizeof (struct rtx_def) + 1 * sizeof (rtunion));
-  memset (tmp_reg_rtx, 0, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
+  tmp_reg_rtx = xcalloc (1, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
   PUT_CODE (tmp_reg_rtx, REG);
   PUT_MODE (tmp_reg_rtx, QImode);
   XINT (tmp_reg_rtx, 0) = TMP_REGNO;
 
-  zero_reg_rtx = xmalloc (sizeof (struct rtx_def) + 1 * sizeof (rtunion));
-  memset (zero_reg_rtx, 0, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
+  zero_reg_rtx = xcalloc (1, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
   PUT_CODE (zero_reg_rtx, REG);
   PUT_MODE (zero_reg_rtx, QImode);
   XINT (zero_reg_rtx, 0) = ZERO_REGNO;
 
-  ldi_reg_rtx = xmalloc (sizeof (struct rtx_def) + 1 * sizeof (rtunion));
-  memset (ldi_reg_rtx, 0, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
+  ldi_reg_rtx = xcalloc (1, sizeof (struct rtx_def) + 1 * sizeof (rtunion));
   PUT_CODE (ldi_reg_rtx, REG);
   PUT_MODE (ldi_reg_rtx, QImode);
   XINT (ldi_reg_rtx, 0) = LDI_REG_REGNO;
diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h
index 83c91ee6240..e2063c7abde 100644
--- a/gcc/config/avr/avr.h
+++ b/gcc/config/avr/avr.h
@@ -2499,6 +2499,3 @@ extern struct rtx_def *zero_reg_rtx;
 extern struct rtx_def *ldi_reg_rtx;
 
 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
-
-/* Get the standard ELF stabs definitions.  */
-#include "dbxelf.h"
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md
index 86ab6c72829..ef449158c44 100644
--- a/gcc/config/avr/avr.md
+++ b/gcc/config/avr/avr.md
@@ -2255,7 +2255,7 @@
 
 
 ;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-;; This instructin sets Z flag
+;; This instruction sets Z flag
 
 (define_insn "sez"
   [(set (cc0) (const_int 0))]
diff --git a/gcc/config/darwin-c.c b/gcc/config/darwin-c.c
index 045530d7b5b..c92c12f2ff9 100644
--- a/gcc/config/darwin-c.c
+++ b/gcc/config/darwin-c.c
@@ -1,6 +1,5 @@
 /* Darwin support needed only by C/C++ frontends.
-   Copyright (C) 2001
-   Free Software Foundation, Inc.
+   Copyright (C) 2001, 2003  Free Software Foundation, Inc.
    Contributed by Apple Computer Inc.
 
 This file is part of GNU CC.
@@ -38,8 +37,8 @@ Boston, MA 02111-1307, USA.  */
 /* Maintain a small stack of alignments.  This is similar to pragma
    pack's stack, but simpler.  */
 
-static void push_field_alignment PARAMS ((int));
-static void pop_field_alignment PARAMS ((void));
+static void push_field_alignment (int);
+static void pop_field_alignment (void);
 
 typedef struct align_stack
 {
@@ -50,8 +49,7 @@ typedef struct align_stack
 static struct align_stack * field_align_stack = NULL;
 
 static void
-push_field_alignment (bit_alignment)
-     int bit_alignment;
+push_field_alignment (int bit_alignment)
 {
   align_stack *entry = (align_stack *) xmalloc (sizeof (align_stack));
 
@@ -63,7 +61,7 @@ push_field_alignment (bit_alignment)
 }
 
 static void
-pop_field_alignment ()
+pop_field_alignment (void)
 {
   if (field_align_stack)
     {
@@ -80,8 +78,7 @@ pop_field_alignment ()
 /* Handlers for Darwin-specific pragmas.  */
 
 void
-darwin_pragma_ignore (pfile)
-     cpp_reader *pfile ATTRIBUTE_UNUSED;
+darwin_pragma_ignore (cpp_reader *pfile ATTRIBUTE_UNUSED)
 {
   /* Do nothing.  */
 }
@@ -89,8 +86,7 @@ darwin_pragma_ignore (pfile)
 /* #pragma options align={mac68k|power|reset} */
 
 void
-darwin_pragma_options (pfile)
-     cpp_reader *pfile ATTRIBUTE_UNUSED;
+darwin_pragma_options (cpp_reader *pfile ATTRIBUTE_UNUSED)
 {
   const char *arg;
   tree t, x;
@@ -122,8 +118,7 @@ darwin_pragma_options (pfile)
 /* #pragma unused ([var {, var}*]) */
 
 void
-darwin_pragma_unused (pfile)
-     cpp_reader *pfile ATTRIBUTE_UNUSED;
+darwin_pragma_unused (cpp_reader *pfile ATTRIBUTE_UNUSED)
 {
   tree decl, x;
   int tok;
diff --git a/gcc/config/darwin-protos.h b/gcc/config/darwin-protos.h
index ad8b2340ae6..68ae21c44a7 100644
--- a/gcc/config/darwin-protos.h
+++ b/gcc/config/darwin-protos.h
@@ -18,104 +18,105 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-extern int name_needs_quotes PARAMS ((const char *));
+extern int name_needs_quotes (const char *);
 
-extern void machopic_validate_stub_or_non_lazy_ptr PARAMS ((const char *, int));
+extern void machopic_validate_stub_or_non_lazy_ptr (const char *, int);
 
-extern const char *machopic_function_base_name PARAMS ((void));
-extern const char *machopic_non_lazy_ptr_name PARAMS ((const char*));
-extern const char *machopic_stub_name PARAMS ((const char*));
+extern const char *machopic_function_base_name (void);
+extern void machopic_output_function_base_name (FILE *);
+extern const char *machopic_non_lazy_ptr_name (const char*);
+extern const char *machopic_stub_name (const char*);
 
-extern void machopic_picsymbol_stub_section PARAMS ((void));
-extern void machopic_picsymbol_stub1_section PARAMS ((void));
-extern void machopic_symbol_stub_section PARAMS ((void));
-extern void machopic_symbol_stub1_section PARAMS ((void));
-extern void machopic_lazy_symbol_ptr_section PARAMS ((void));
-extern void machopic_nl_symbol_ptr_section PARAMS ((void));
+extern void machopic_picsymbol_stub_section (void);
+extern void machopic_picsymbol_stub1_section (void);
+extern void machopic_symbol_stub_section (void);
+extern void machopic_symbol_stub1_section (void);
+extern void machopic_lazy_symbol_ptr_section (void);
+extern void machopic_nl_symbol_ptr_section (void);
 
-extern void constructor_section PARAMS ((void));
-extern void destructor_section PARAMS ((void));
-extern void mod_init_section PARAMS ((void));
-extern void mod_term_section PARAMS ((void));
+extern void constructor_section (void);
+extern void destructor_section (void);
+extern void mod_init_section (void);
+extern void mod_term_section (void);
 
 #ifdef RTX_CODE
 
-extern int machopic_operand_p PARAMS ((rtx));
-extern enum machopic_addr_class machopic_classify_name PARAMS ((const char*));
+extern int machopic_operand_p (rtx);
+extern enum machopic_addr_class machopic_classify_name (const char*);
 
-extern rtx machopic_indirect_data_reference PARAMS ((rtx, rtx));
-extern rtx machopic_indirect_call_target PARAMS ((rtx));
-extern rtx machopic_legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx));
+extern rtx machopic_indirect_data_reference (rtx, rtx);
+extern rtx machopic_indirect_call_target (rtx);
+extern rtx machopic_legitimize_pic_address (rtx, enum machine_mode, rtx);
 
-extern void machopic_asm_out_constructor PARAMS ((rtx, int));
-extern void machopic_asm_out_destructor PARAMS ((rtx, int));
+extern void machopic_asm_out_constructor (rtx, int);
+extern void machopic_asm_out_destructor (rtx, int);
 #endif /* RTX_CODE */
 
 #ifdef TREE_CODE
 
-extern enum machopic_addr_class machopic_classify_ident PARAMS ((tree));
-extern void machopic_define_ident PARAMS ((tree));
-extern void machopic_define_name PARAMS ((const char*));
-extern int machopic_name_defined_p PARAMS ((const char*));
-extern int machopic_ident_defined_p PARAMS ((tree));
-extern void darwin_encode_section_info PARAMS ((tree, rtx, int));
-extern const char *darwin_strip_name_encoding PARAMS ((const char *));
+extern enum machopic_addr_class machopic_classify_ident (tree);
+extern void machopic_define_ident (tree);
+extern void machopic_define_name (const char*);
+extern int machopic_name_defined_p (const char*);
+extern int machopic_ident_defined_p (tree);
+extern void darwin_encode_section_info (tree, rtx, int);
+extern const char *darwin_strip_name_encoding (const char *);
 
 #endif /* TREE_CODE */
 
-extern void machopic_finish PARAMS ((FILE *));
+extern void machopic_finish (FILE *);
 
-extern void machopic_output_possible_stub_label PARAMS ((FILE *, const char*));
+extern void machopic_output_possible_stub_label (FILE *, const char*);
 
-extern void darwin_exception_section PARAMS ((void));
-extern void darwin_eh_frame_section PARAMS ((void));
-extern void machopic_select_section PARAMS ((tree, int,
-					     unsigned HOST_WIDE_INT));
-extern void machopic_select_rtx_section PARAMS ((enum machine_mode, rtx,
-						 unsigned HOST_WIDE_INT));
+extern void darwin_exception_section (void);
+extern void darwin_eh_frame_section (void);
+extern void machopic_select_section (tree, int, unsigned HOST_WIDE_INT);
+extern void machopic_select_rtx_section (enum machine_mode, rtx,
+					 unsigned HOST_WIDE_INT);
 
-extern void darwin_pragma_ignore PARAMS ((struct cpp_reader *));
-extern void darwin_pragma_options PARAMS ((struct cpp_reader *));
-extern void darwin_pragma_unused PARAMS ((struct cpp_reader *));
+extern void darwin_pragma_ignore (struct cpp_reader *);
+extern void darwin_pragma_options (struct cpp_reader *);
+extern void darwin_pragma_unused (struct cpp_reader *);
 
-extern void darwin_file_end PARAMS ((void));
+extern void darwin_file_end (void);
 
 /* Expanded by EXTRA_SECTION_FUNCTIONS into varasm.o.  */
-extern void const_section PARAMS ((void));
-extern void const_data_section PARAMS ((void));
-extern void cstring_section PARAMS ((void));
-extern void literal4_section PARAMS ((void));
-extern void literal8_section PARAMS ((void));
-extern void constructor_section PARAMS ((void));
-extern void mod_init_section PARAMS ((void));
-extern void mod_term_section PARAMS ((void));
-extern void destructor_section PARAMS ((void));
-extern void objc_class_section PARAMS ((void));
-extern void objc_meta_class_section PARAMS ((void));
-extern void objc_category_section PARAMS ((void));
-extern void objc_class_vars_section PARAMS ((void));
-extern void objc_instance_vars_section PARAMS ((void));
-extern void objc_cls_meth_section PARAMS ((void));
-extern void objc_inst_meth_section PARAMS ((void));
-extern void objc_cat_cls_meth_section PARAMS ((void));
-extern void objc_cat_inst_meth_section PARAMS ((void));
-extern void objc_selector_refs_section PARAMS ((void));
-extern void objc_selector_fixup_section PARAMS ((void));
-extern void objc_symbols_section PARAMS ((void));
-extern void objc_module_info_section PARAMS ((void));
-extern void objc_protocol_section PARAMS ((void));
-extern void objc_string_object_section PARAMS ((void));
-extern void objc_constant_string_object_section PARAMS ((void));
-extern void objc_class_names_section PARAMS ((void));
-extern void objc_meth_var_names_section PARAMS ((void));
-extern void objc_meth_var_types_section PARAMS ((void));
-extern void objc_cls_refs_section PARAMS ((void));
-extern void machopic_lazy_symbol_ptr_section PARAMS ((void));
-extern void machopic_nl_symbol_ptr_section PARAMS ((void));
-extern void machopic_symbol_stub_section PARAMS ((void));
-extern void machopic_picsymbol_stub_section PARAMS ((void));
-extern void machopic_output_stub PARAMS ((FILE *, const char *, const char *));
-extern void darwin_exception_section PARAMS ((void));
-extern void darwin_eh_frame_section PARAMS ((void));
-extern void darwin_globalize_label PARAMS ((FILE *, const char *));
-extern void darwin_asm_output_dwarf_delta PARAMS ((FILE *, int, const char *, const char *));
+extern void const_section (void);
+extern void const_data_section (void);
+extern void cstring_section (void);
+extern void literal4_section (void);
+extern void literal8_section (void);
+extern void constructor_section (void);
+extern void mod_init_section (void);
+extern void mod_term_section (void);
+extern void destructor_section (void);
+extern void objc_class_section (void);
+extern void objc_meta_class_section (void);
+extern void objc_category_section (void);
+extern void objc_class_vars_section (void);
+extern void objc_instance_vars_section (void);
+extern void objc_cls_meth_section (void);
+extern void objc_inst_meth_section (void);
+extern void objc_cat_cls_meth_section (void);
+extern void objc_cat_inst_meth_section (void);
+extern void objc_selector_refs_section (void);
+extern void objc_selector_fixup_section (void);
+extern void objc_symbols_section (void);
+extern void objc_module_info_section (void);
+extern void objc_protocol_section (void);
+extern void objc_string_object_section (void);
+extern void objc_constant_string_object_section (void);
+extern void objc_class_names_section (void);
+extern void objc_meth_var_names_section (void);
+extern void objc_meth_var_types_section (void);
+extern void objc_cls_refs_section (void);
+extern void machopic_lazy_symbol_ptr_section (void);
+extern void machopic_nl_symbol_ptr_section (void);
+extern void machopic_symbol_stub_section (void);
+extern void machopic_picsymbol_stub_section (void);
+extern void machopic_output_stub (FILE *, const char *, const char *);
+extern void darwin_exception_section (void);
+extern void darwin_eh_frame_section (void);
+extern void darwin_globalize_label (FILE *, const char *);
+extern void darwin_asm_output_dwarf_delta (FILE *, int, const char *,
+					   const char *);
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index c17fc74ba08..dc864628a20 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -42,13 +42,12 @@ Boston, MA 02111-1307, USA.  */
 #include "langhooks.h"
 #include "tm_p.h"
 
-static int machopic_data_defined_p PARAMS ((const char *));
-static void update_non_lazy_ptrs PARAMS ((const char *));
-static void update_stubs PARAMS ((const char *));
+static int machopic_data_defined_p (const char *);
+static void update_non_lazy_ptrs (const char *);
+static void update_stubs (const char *);
 
 int
-name_needs_quotes (name)
-     const char *name;
+name_needs_quotes (const char *name)
 {
   int c;
   while ((c = *name++) != '\0')
@@ -57,7 +56,7 @@ name_needs_quotes (name)
   return 0;
 }
 
-/* 
+/*
  * flag_pic = 1 ... generate only indirections
  * flag_pic = 2 ... generate indirections and pure code
  */
@@ -68,20 +67,23 @@ name_needs_quotes (name)
 static GTY(()) tree machopic_defined_list;
 
 enum machopic_addr_class
-machopic_classify_ident (ident)
-     tree ident;
+machopic_classify_ident (tree ident)
 {
   const char *name = IDENTIFIER_POINTER (ident);
   int lprefix = (((name[0] == '*' || name[0] == '&')
 		  && (name[1] == 'L' || (name[1] == '"' && name[2] == 'L')))
-		 || (   name[0] == '_' 
-		     && name[1] == 'O' 
-		     && name[2] == 'B' 
+		 || (   name[0] == '_'
+		     && name[1] == 'O'
+		     && name[2] == 'B'
 		     && name[3] == 'J'
 		     && name[4] == 'C'
 		     && name[5] == '_'));
   tree temp;
 
+  /* The PIC base symbol is always defined. */
+  if (! strcmp (name, "<pic base>"))
+    return MACHOPIC_DEFINED_DATA;
+
   if (name[0] != '!')
     {
       /* Here if no special encoding to be found.  */
@@ -142,7 +144,7 @@ machopic_classify_ident (ident)
 	    return MACHOPIC_DEFINED_DATA;
 	}
     }
-  
+
   if (name[1] == 't' || name[1] == 'T')
     {
       if (lprefix)
@@ -159,17 +161,15 @@ machopic_classify_ident (ident)
     }
 }
 
-     
+
 enum machopic_addr_class
-machopic_classify_name (name)
-     const char *name;
+machopic_classify_name (const char *name)
 {
   return machopic_classify_ident (get_identifier (name));
 }
 
 int
-machopic_ident_defined_p (ident)
-     tree ident;
+machopic_ident_defined_p (tree ident)
 {
   switch (machopic_classify_ident (ident))
     {
@@ -183,8 +183,7 @@ machopic_ident_defined_p (ident)
 }
 
 static int
-machopic_data_defined_p (name)
-     const char *name;
+machopic_data_defined_p (const char *name)
 {
   switch (machopic_classify_ident (get_identifier (name)))
     {
@@ -196,76 +195,65 @@ machopic_data_defined_p (name)
 }
 
 int
-machopic_name_defined_p (name)
-     const char *name;
+machopic_name_defined_p (const char *name)
 {
   return machopic_ident_defined_p (get_identifier (name));
 }
 
 void
-machopic_define_ident (ident)
-     tree ident;
+machopic_define_ident (tree ident)
 {
   if (!machopic_ident_defined_p (ident))
-    machopic_defined_list = 
+    machopic_defined_list =
       tree_cons (NULL_TREE, ident, machopic_defined_list);
 }
 
 void
-machopic_define_name (name)
-     const char *name;
+machopic_define_name (const char *name)
 {
   machopic_define_ident (get_identifier (name));
 }
 
-/* This is a static to make inline functions work.  The rtx
-   representing the PIC base symbol always points to here.  
+static GTY(()) char * function_base;
 
-   FIXME: The rest of the compiler doesn't expect strings to change.  */
+const char *
+machopic_function_base_name (void)
+{
+  const char *current_name;
+  /* if dynamic-no-pic is on, we should not get here */
+  if (MACHO_DYNAMIC_NO_PIC_P)
+    abort ();
+  current_name =
+    IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (current_function_decl));
+
+  if (function_base == NULL)
+    function_base =
+      (char *) ggc_alloc_string ("<pic base>", sizeof ("<pic base>"));
+
+  current_function_uses_pic_offset_table = 1;
+
+  return function_base;
+}
 
-static GTY(()) char * function_base;
 static GTY(()) const char * function_base_func_name;
 static GTY(()) int current_pic_label_num;
 
-const char *
-machopic_function_base_name ()
+void
+machopic_output_function_base_name (FILE *file)
 {
   const char *current_name;
 
-  /* if dynamic-no-pic is on, we should not get here */
+  /* If dynamic-no-pic is on, we should not get here. */
   if (MACHO_DYNAMIC_NO_PIC_P)
     abort ();
-  current_name = 
+  current_name =
     IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (current_function_decl));
-
   if (function_base_func_name != current_name)
     {
-      current_function_uses_pic_offset_table = 1;
-
-      /* Save mucho space and time.  Some of the C++ mangled names are over
-	 700 characters long!  Note that we produce a label containing a '-'
-	 if the function we're compiling is an Objective-C method, as evinced
-	 by the incredibly scientific test below.  This is because code in
-	 rs6000.c makes the same ugly test when loading the PIC reg.  */
- 
-      /* It's hard to describe just how ugly this is.  The reason for
-         the '%011d' is that after a PCH load, we can't change the
-         size of the string, because PCH will have uniqued it and
-         allocated it in the string pool.  */
-      if (function_base == NULL)
-	function_base = 
-	  (char *) ggc_alloc_string ("", sizeof ("*\"L12345678901$pb\""));
-
       ++current_pic_label_num;
-      if (*current_name == '+' || *current_name == '-')
-	sprintf (function_base, "*\"L-%010d$pb\"", current_pic_label_num);
-      else
-	sprintf (function_base, "*\"L%011d$pb\"", current_pic_label_num);
-
       function_base_func_name = current_name;
     }
-
-  return function_base;
+  fprintf (file, "\"L%011d$pb\"", current_pic_label_num);
 }
 
 static GTY(()) tree machopic_non_lazy_pointers;
@@ -274,15 +262,14 @@ static GTY(()) tree machopic_non_lazy_pointers;
    either by finding it in our list of pointer names, or by generating
    a new one.  */
 
-const char * 
-machopic_non_lazy_ptr_name (name)
-     const char *name;
+const char *
+machopic_non_lazy_ptr_name (const char *name)
 {
   const char *temp_name;
   tree temp, ident = get_identifier (name);
-  
+
   for (temp = machopic_non_lazy_pointers;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       if (ident == TREE_VALUE (temp))
@@ -293,7 +280,7 @@ machopic_non_lazy_ptr_name (name)
 
   /* Try again, but comparing names this time.  */
   for (temp = machopic_non_lazy_pointers;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       if (TREE_VALUE (temp))
@@ -319,11 +306,11 @@ machopic_non_lazy_ptr_name (name)
 	strcat (buffer, "_");
 	strcat (buffer, name);
       }
-      
+
     strcat (buffer, "$non_lazy_ptr");
     ptr_name = get_identifier (buffer);
 
-    machopic_non_lazy_pointers 
+    machopic_non_lazy_pointers
       = tree_cons (ptr_name, ident, machopic_non_lazy_pointers);
 
     TREE_USED (machopic_non_lazy_pointers) = 0;
@@ -337,15 +324,14 @@ static GTY(()) tree machopic_stubs;
 /* Return the name of the stub corresponding to the given name,
    generating a new stub name if necessary.  */
 
-const char * 
-machopic_stub_name (name)
-     const char *name;
+const char *
+machopic_stub_name (const char *name)
 {
   tree temp, ident = get_identifier (name);
   const char *tname;
 
   for (temp = machopic_stubs;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       if (ident == TREE_VALUE (temp))
@@ -398,9 +384,7 @@ machopic_stub_name (name)
 }
 
 void
-machopic_validate_stub_or_non_lazy_ptr (name, validate_stub)
-     const char *name;
-     int validate_stub;
+machopic_validate_stub_or_non_lazy_ptr (const char *name, int validate_stub)
 {
   const char *real_name;
   tree temp, ident = get_identifier (name), id2;
@@ -414,12 +398,12 @@ machopic_validate_stub_or_non_lazy_ptr (name, validate_stub)
 	     original symbol as being referenced.  */
           TREE_USED (temp) = 1;
 	  if (TREE_CODE (TREE_VALUE (temp)) == IDENTIFIER_NODE)
-	    TREE_SYMBOL_REFERENCED (TREE_VALUE (temp)) = 1;
+	    mark_referenced (TREE_VALUE (temp));
 	  real_name = IDENTIFIER_POINTER (TREE_VALUE (temp));
 	  real_name = darwin_strip_name_encoding (real_name);
 	  id2 = maybe_get_identifier (real_name);
 	  if (id2)
-	    TREE_SYMBOL_REFERENCED (id2) = 1;
+	    mark_referenced (id2);
 	}
 }
 
@@ -427,11 +411,10 @@ machopic_validate_stub_or_non_lazy_ptr (name, validate_stub)
    source using indirections.  */
 
 rtx
-machopic_indirect_data_reference (orig, reg)
-     rtx orig, reg;
+machopic_indirect_data_reference (rtx orig, rtx reg)
 {
   rtx ptr_ref = orig;
-  
+
   if (! MACHOPIC_INDIRECT)
     return orig;
 
@@ -444,7 +427,7 @@ machopic_indirect_data_reference (orig, reg)
       if (defined && MACHO_DYNAMIC_NO_PIC_P)
 	{
 #if defined (TARGET_TOC)
-           emit_insn (gen_macho_high (reg, orig));  
+           emit_insn (gen_macho_high (reg, orig));
            emit_insn (gen_macho_low (reg, reg, orig));
 #else
 	   /* some other cpu -- writeme!  */
@@ -455,7 +438,7 @@ machopic_indirect_data_reference (orig, reg)
       else if (defined)
 	{
 #if defined (TARGET_TOC) || defined (HAVE_lo_sum)
-	  rtx pic_base = gen_rtx (SYMBOL_REF, Pmode, 
+	  rtx pic_base = gen_rtx (SYMBOL_REF, Pmode,
 				  machopic_function_base_name ());
 	  rtx offset = gen_rtx (CONST, Pmode,
 				gen_rtx (MINUS, Pmode, orig, pic_base));
@@ -511,7 +494,7 @@ machopic_indirect_data_reference (orig, reg)
 	  orig = machopic_indirect_data_reference (XEXP (XEXP (orig, 0), 1),
 						   (base == reg ? 0 : reg));
 	}
-      else 
+      else
 	return orig;
 
       if (MACHOPIC_PURE && GET_CODE (orig) == CONST_INT)
@@ -561,14 +544,13 @@ machopic_indirect_data_reference (orig, reg)
    corresponding symbol_stub if necessary.  Return a new MEM.  */
 
 rtx
-machopic_indirect_call_target (target)
-     rtx target;
+machopic_indirect_call_target (rtx target)
 {
   if (GET_CODE (target) != MEM)
     return target;
 
   if (MACHOPIC_INDIRECT && GET_CODE (XEXP (target, 0)) == SYMBOL_REF)
-    { 
+    {
       enum machine_mode mode = GET_MODE (XEXP (target, 0));
       const char *name = XSTR (XEXP (target, 0), 0);
 
@@ -582,16 +564,14 @@ machopic_indirect_call_target (target)
 
 	  XEXP (target, 0) = gen_rtx (SYMBOL_REF, mode, stub_name);
 	  RTX_UNCHANGING_P (target) = 1;
-	} 
+	}
     }
 
   return target;
 }
 
 rtx
-machopic_legitimize_pic_address (orig, mode, reg)
-     rtx orig, reg;
-     enum machine_mode mode;
+machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
 {
   rtx pic_ref = orig;
 
@@ -608,7 +588,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 
       orig = machopic_indirect_data_reference (orig, reg);
 
-      if (GET_CODE (orig) == PLUS 
+      if (GET_CODE (orig) == PLUS
 	  && GET_CODE (XEXP (orig, 0)) == REG)
 	{
 	  if (reg == 0)
@@ -616,7 +596,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 
 	  emit_move_insn (reg, orig);
 	  return reg;
-	}  
+	}
 
       /* if dynamic-no-pic then use 0 as the pic base  */
       if (MACHO_DYNAMIC_NO_PIC_P)
@@ -633,7 +613,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 	      else
 		reg = gen_reg_rtx (Pmode);
 	    }
-	
+
 #ifdef HAVE_lo_sum
 	  if (MACHO_DYNAMIC_NO_PIC_P
 	      && (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
@@ -656,7 +636,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 	      pic_ref = reg;
 	    }
 	  else
-	  if (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF 
+	  if (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
 	      || GET_CODE (XEXP (orig, 0)) == LABEL_REF)
 	    {
 	      rtx offset = gen_rtx (CONST, Pmode,
@@ -674,7 +654,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 					   gen_rtx (HIGH, Pmode, offset))));
 	      emit_insn (gen_rtx (SET, VOIDmode, reg,
 				  gen_rtx (MEM, GET_MODE (orig),
-					   gen_rtx (LO_SUM, Pmode, 
+					   gen_rtx (LO_SUM, Pmode,
 						    hi_sum_reg, offset))));
 	      pic_ref = reg;
 
@@ -683,10 +663,10 @@ machopic_legitimize_pic_address (orig, mode, reg)
 			      gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM)));
 
 	      emit_insn (gen_rtx (SET, VOIDmode, reg,
-				  gen_rtx (HIGH, Pmode, 
+				  gen_rtx (HIGH, Pmode,
 					   gen_rtx (CONST, Pmode, offset))));
 	      emit_insn (gen_rtx (SET, VOIDmode, reg,
-				  gen_rtx (LO_SUM, Pmode, reg, 
+				  gen_rtx (LO_SUM, Pmode, reg,
 					   gen_rtx (CONST, Pmode, offset))));
 	      pic_ref = gen_rtx (PLUS, Pmode,
 				 pic_offset_table_rtx, reg);
@@ -707,13 +687,13 @@ machopic_legitimize_pic_address (orig, mode, reg)
 #endif
 
 	      pic_ref = gen_rtx (PLUS, Pmode,
-				 pic, 
-				 gen_rtx (CONST, Pmode, 
+				 pic,
+				 gen_rtx (CONST, Pmode,
 					  gen_rtx (MINUS, Pmode,
-						   XEXP (orig, 0), 
+						   XEXP (orig, 0),
 						   pic_base)));
 	    }
-	  
+
 #if !defined (TARGET_TOC)
 	  emit_move_insn (reg, pic_ref);
 	  pic_ref = gen_rtx (MEM, GET_MODE (orig), reg);
@@ -724,7 +704,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 	{
 
 #ifdef HAVE_lo_sum
-	  if (GET_CODE (orig) == SYMBOL_REF 
+	  if (GET_CODE (orig) == SYMBOL_REF
 	      || GET_CODE (orig) == LABEL_REF)
 	    {
 	      rtx offset = gen_rtx (CONST, Pmode,
@@ -739,7 +719,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 		  else
 		    reg = gen_reg_rtx (SImode);
 		}
-	
+
 	      hi_sum_reg = reg;
 
 	      emit_insn (gen_rtx (SET, Pmode, hi_sum_reg,
@@ -784,7 +764,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 #endif
 		  pic_ref = gen_rtx (PLUS, Pmode,
 				     pic,
-				     gen_rtx (CONST, Pmode, 
+				     gen_rtx (CONST, Pmode,
 					      gen_rtx (MINUS, Pmode,
 						       orig, pic_base)));
 		}
@@ -818,7 +798,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 	       || GET_CODE (XEXP (orig, 0)) == LABEL_REF)
 	   && XEXP (orig, 0) != pic_offset_table_rtx
 	   && GET_CODE (XEXP (orig, 1)) != REG)
-    
+
     {
       rtx base;
       int is_complex = (GET_CODE (XEXP (orig, 0)) == MEM);
@@ -866,8 +846,7 @@ machopic_legitimize_pic_address (orig, mode, reg)
 
 
 void
-machopic_finish (asm_out_file)
-     FILE *asm_out_file;
+machopic_finish (FILE *asm_out_file)
 {
   tree temp;
 
@@ -893,7 +872,7 @@ machopic_finish (asm_out_file)
       if (sym_name[0] == '*' || sym_name[0] == '&')
 	strcpy (sym, sym_name + 1);
       else if (sym_name[0] == '-' || sym_name[0] == '+')
-	strcpy (sym, sym_name);	  
+	strcpy (sym, sym_name);
       else
 	sym[0] = '_', strcpy (sym + 1, sym_name);
 
@@ -907,7 +886,7 @@ machopic_finish (asm_out_file)
     }
 
   for (temp = machopic_non_lazy_pointers;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       const char *const sym_name = IDENTIFIER_POINTER (TREE_VALUE (temp));
@@ -928,11 +907,11 @@ machopic_finish (asm_out_file)
       else
 	{
 	  machopic_nl_symbol_ptr_section ();
-	  assemble_name (asm_out_file, lazy_name); 
+	  assemble_name (asm_out_file, lazy_name);
 	  fprintf (asm_out_file, ":\n");
 
 	  fprintf (asm_out_file, "\t.indirect_symbol ");
-	  assemble_name (asm_out_file, sym_name); 
+	  assemble_name (asm_out_file, sym_name);
 	  fprintf (asm_out_file, "\n");
 
 	  assemble_integer (const0_rtx, GET_MODE_SIZE (Pmode),
@@ -941,9 +920,8 @@ machopic_finish (asm_out_file)
     }
 }
 
-int 
-machopic_operand_p (op)
-     rtx op;
+int
+machopic_operand_p (rtx op)
 {
   if (MACHOPIC_JUST_INDIRECT)
     {
@@ -974,10 +952,7 @@ machopic_operand_p (op)
    use later.  */
 
 void
-darwin_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first ATTRIBUTE_UNUSED;
+darwin_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
 {
   char code = '\0';
   int defined = 0;
@@ -1047,8 +1022,7 @@ darwin_encode_section_info (decl, rtl, first)
 /* Undo the effects of the above.  */
 
 const char *
-darwin_strip_name_encoding (str)
-     const char *str;
+darwin_strip_name_encoding (const char *str)
 {
   return str[0] == '!' ? str + 4 : str;
 }
@@ -1057,8 +1031,7 @@ darwin_strip_name_encoding (str)
    stripped name matches the argument.  */
 
 static void
-update_non_lazy_ptrs (name)
-     const char *name;
+update_non_lazy_ptrs (const char *name)
 {
   const char *name1, *name2;
   tree temp;
@@ -1066,7 +1039,7 @@ update_non_lazy_ptrs (name)
   name1 = darwin_strip_name_encoding (name);
 
   for (temp = machopic_non_lazy_pointers;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       const char *sym_name = IDENTIFIER_POINTER (TREE_VALUE (temp));
@@ -1077,7 +1050,7 @@ update_non_lazy_ptrs (name)
 	  if (strcmp (name1, name2) == 0)
 	    {
 	      /* FIXME: This breaks the identifier hash table.  */
-	      IDENTIFIER_NODE_CHECK (TREE_VALUE (temp))->identifier.id.str 
+	      IDENTIFIER_NODE_CHECK (TREE_VALUE (temp))->identifier.id.str
 		= (unsigned char *) name;
 	      break;
 	    }
@@ -1090,9 +1063,7 @@ update_non_lazy_ptrs (name)
    just emit the stub label now and we don't bother emitting the stub later.  */
 
 void
-machopic_output_possible_stub_label (file, name)
-     FILE *file;
-     const char *name;
+machopic_output_possible_stub_label (FILE *file, const char *name)
 {
   tree temp;
 
@@ -1123,8 +1094,7 @@ machopic_output_possible_stub_label (file, name)
    stripped name matches the argument.  */
 
 static void
-update_stubs (name)
-     const char *name;
+update_stubs (const char *name)
 {
   const char *name1, *name2;
   tree temp;
@@ -1132,7 +1102,7 @@ update_stubs (name)
   name1 = darwin_strip_name_encoding (name);
 
   for (temp = machopic_stubs;
-       temp != NULL_TREE; 
+       temp != NULL_TREE;
        temp = TREE_CHAIN (temp))
     {
       const char *sym_name = IDENTIFIER_POINTER (TREE_VALUE (temp));
@@ -1143,7 +1113,7 @@ update_stubs (name)
 	  if (strcmp (name1, name2) == 0)
 	    {
 	      /* FIXME: This breaks the identifier hash table.  */
-	      IDENTIFIER_NODE_CHECK (TREE_VALUE (temp))->identifier.id.str 
+	      IDENTIFIER_NODE_CHECK (TREE_VALUE (temp))->identifier.id.str
 		= (unsigned char *) name;
 	      break;
 	    }
@@ -1152,23 +1122,25 @@ update_stubs (name)
 }
 
 void
-machopic_select_section (exp, reloc, align)
-     tree exp;
-     int reloc;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+machopic_select_section (tree exp, int reloc,
+			 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
-  if (TREE_CODE (exp) == STRING_CST)
-    {
-      if (flag_writable_strings)
-	data_section ();
-      else if ((size_t) TREE_STRING_LENGTH (exp) !=
-	       strlen (TREE_STRING_POINTER (exp)) + 1)
-	readonly_data_section ();
-      else
-	cstring_section ();
-    }
-  else if (TREE_CODE (exp) == INTEGER_CST
-	   || TREE_CODE (exp) == REAL_CST)
+  void (*base_function)(void);
+
+  if (decl_readonly_section_1 (exp, reloc, MACHOPIC_INDIRECT))
+    base_function = readonly_data_section;
+  else if (TREE_READONLY (exp) || TREE_CONSTANT (exp))
+    base_function = const_data_section;
+  else
+    base_function = data_section;
+
+  if (TREE_CODE (exp) == STRING_CST
+      && ((size_t) TREE_STRING_LENGTH (exp)
+	  == strlen (TREE_STRING_POINTER (exp)) + 1)
+      && ! flag_writable_strings)
+    cstring_section ();
+  else if ((TREE_CODE (exp) == INTEGER_CST || TREE_CODE (exp) == REAL_CST)
+	   && flag_merge_constants)
     {
       tree size = TYPE_SIZE (TREE_TYPE (exp));
 
@@ -1181,7 +1153,7 @@ machopic_select_section (exp, reloc, align)
 	       TREE_INT_CST_HIGH (size) == 0)
 	literal8_section ();
       else
-	readonly_data_section ();
+	base_function ();
     }
   else if (TREE_CODE (exp) == CONSTRUCTOR
 	   && TREE_TYPE (exp)
@@ -1195,16 +1167,8 @@ machopic_select_section (exp, reloc, align)
 	objc_constant_string_object_section ();
       else if (!strcmp (IDENTIFIER_POINTER (name), "NXConstantString"))
 	objc_string_object_section ();
-      else if (TREE_READONLY (exp) || TREE_CONSTANT (exp))
-	{
-	  
-	  if (TREE_SIDE_EFFECTS (exp) || (MACHOPIC_INDIRECT && reloc))
-	    const_data_section ();
-	  else
-	    readonly_data_section ();
-	}
       else
-	data_section ();
+	base_function ();
     }
   else if (TREE_CODE (exp) == VAR_DECL &&
 	   DECL_NAME (exp) &&
@@ -1250,6 +1214,8 @@ machopic_select_section (exp, reloc, align)
 	objc_symbols_section ();
       else if (!strncmp (name, "_OBJC_MODULES", 13))
 	objc_module_info_section ();
+      else if (!strncmp (name, "_OBJC_IMAGE_INFO", 16))
+	objc_image_info_section ();
       else if (!strncmp (name, "_OBJC_PROTOCOL_INSTANCE_METHODS_", 32))
 	objc_cat_inst_meth_section ();
       else if (!strncmp (name, "_OBJC_PROTOCOL_CLASS_METHODS_", 29))
@@ -1258,38 +1224,19 @@ machopic_select_section (exp, reloc, align)
 	objc_cat_cls_meth_section ();
       else if (!strncmp (name, "_OBJC_PROTOCOL_", 15))
 	objc_protocol_section ();
-      else if ((TREE_READONLY (exp) || TREE_CONSTANT (exp))
-	       && !TREE_SIDE_EFFECTS (exp))
-	{
-	  
-	  if (MACHOPIC_INDIRECT && reloc)
-	    const_data_section ();
-	  else
-	    readonly_data_section ();
-	}
       else
-	data_section ();
-    }
-  else if (TREE_READONLY (exp) || TREE_CONSTANT (exp))
-    {
-     
-      if (TREE_SIDE_EFFECTS (exp) || (MACHOPIC_INDIRECT && reloc))
-	const_data_section ();
-      else
-	readonly_data_section ();
+	base_function ();
     }
   else
-    data_section ();
+    base_function ();
 }
 
 /* This can be called with address expressions as "rtx".
    They must go in "const".  */
 
 void
-machopic_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+machopic_select_rtx_section (enum machine_mode mode, rtx x,
+			     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
   if (GET_MODE_SIZE (mode) == 8)
     literal8_section ();
@@ -1297,16 +1244,19 @@ machopic_select_rtx_section (mode, x, align)
 	   && (GET_CODE (x) == CONST_INT
 	       || GET_CODE (x) == CONST_DOUBLE))
     literal4_section ();
+  else if (MACHOPIC_INDIRECT
+	   && (GET_CODE (x) == SYMBOL_REF
+	       || GET_CODE (x) == CONST
+	       || GET_CODE (x) == LABEL_REF))
+    const_data_section ();
   else
     const_section ();
 }
 
 void
-machopic_asm_out_constructor (symbol, priority)
-     rtx symbol;
-     int priority ATTRIBUTE_UNUSED;
+machopic_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
 {
-  
+
   if (MACHOPIC_INDIRECT)
     mod_init_section ();
   else
@@ -1314,17 +1264,15 @@ machopic_asm_out_constructor (symbol, priority)
   assemble_align (POINTER_SIZE);
   assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
 
- 
+
   if (! MACHOPIC_INDIRECT)
     fprintf (asm_out_file, ".reference .constructors_used\n");
 }
 
 void
-machopic_asm_out_destructor (symbol, priority)
-     rtx symbol;
-     int priority ATTRIBUTE_UNUSED;
+machopic_asm_out_destructor (rtx symbol, int priority ATTRIBUTE_UNUSED)
 {
-  
+
   if (MACHOPIC_INDIRECT)
     mod_term_section ();
   else
@@ -1337,9 +1285,7 @@ machopic_asm_out_destructor (symbol, priority)
 }
 
 void
-darwin_globalize_label (stream, name)
-     FILE *stream;
-     const char *name;
+darwin_globalize_label (FILE *stream, const char *name)
 {
   if (!!strncmp (name, "_OBJC_", 6))
     default_globalize_label (stream, name);
@@ -1355,10 +1301,8 @@ darwin_globalize_label (stream, name)
 static int darwin_dwarf_label_counter;
 
 void
-darwin_asm_output_dwarf_delta (file, size, lab1, lab2)
-     FILE *file;
-     int size ATTRIBUTE_UNUSED;
-     const char *lab1, *lab2;
+darwin_asm_output_dwarf_delta (FILE *file, int size ATTRIBUTE_UNUSED,
+			       const char *lab1, const char *lab2)
 {
   const char *p = lab1 + (lab1[0] == '*');
   int islocaldiff = (p[0] == 'L');
@@ -1375,7 +1319,7 @@ darwin_asm_output_dwarf_delta (file, size, lab1, lab2)
 }
 
 void
-darwin_file_end ()
+darwin_file_end (void)
 {
   machopic_finish (asm_out_file);
   if (strcmp (lang_hooks.name, "GNU C++") == 0)
@@ -1387,4 +1331,3 @@ darwin_file_end ()
 }
 
 #include "gt-darwin.h"
-
diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h
index 8a959090c56..35415159e49 100644
--- a/gcc/config/darwin.h
+++ b/gcc/config/darwin.h
@@ -186,6 +186,8 @@ Boston, MA 02111-1307, USA.  */
 #define LINK_COMMAND_SPEC "\
 %{!fdump=*:%{!fsyntax-only:%{!precomp:%{!c:%{!M:%{!MM:%{!E:%{!S:\
     %{!Zdynamiclib:%(linker)}%{Zdynamiclib:/usr/bin/libtool} \
+    %{!Zdynamiclib:-arch %(darwin_arch)} \
+    %{Zdynamiclib:-arch_only %(darwin_arch)} \
     %l %X %{d} %{s} %{t} %{Z} \
     %{!Zdynamiclib:%{A} %{e*} %{m} %{N} %{n} %{r} %{u*} %{x} %{z}} \
     %{@:-o %f%u.out}%{!@:%{o*}%{!o:-o a.out}} \
@@ -244,7 +246,7 @@ Boston, MA 02111-1307, USA.  */
    %{Zmulti_module:-multi_module} %{Zsingle_module:-single_module} \
    %{Zmultiply_defined*:-multiply_defined %*} \
    %{Zmultiplydefinedunused*:-multiply_defined_unused %*} \
-   %{prebind} %{noprebind} %{prebind_all_twolevel_modules} \
+   %{prebind} %{noprebind} %{nofixprebinding} %{prebind_all_twolevel_modules} \
    %{read_only_relocs} \
    %{sectcreate*} %{sectorder*} %{seg1addr*} %{segprot*} %{seg_addr_table*} \
    %{Zseg_addr_table_filename*:-seg_addr_table_filename %*} \
@@ -356,18 +358,22 @@ do { text_section ();							\
 #undef ASM_DECLARE_OBJECT_NAME
 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
   do {									\
-    const char *xname = NAME;                                           \
-    if (GET_CODE (XEXP (DECL_RTL (DECL), 0)) != SYMBOL_REF)             \
-      xname = IDENTIFIER_POINTER (DECL_NAME (DECL));                    \
-    if ((TREE_STATIC (DECL)                                             \
-	 && (!DECL_COMMON (DECL) || !TREE_PUBLIC (DECL)))               \
-        || DECL_INITIAL (DECL))                                         \
-      machopic_define_name (xname);                                     \
-    if ((TREE_STATIC (DECL)                                             \
-	 && (!DECL_COMMON (DECL) || !TREE_PUBLIC (DECL)))               \
-        || DECL_INITIAL (DECL))                                         \
+    const char *xname = NAME;						\
+    if (GET_CODE (XEXP (DECL_RTL (DECL), 0)) != SYMBOL_REF)		\
+      xname = IDENTIFIER_POINTER (DECL_NAME (DECL));			\
+    if ((TREE_STATIC (DECL)						\
+	 && (!DECL_COMMON (DECL) || !TREE_PUBLIC (DECL)))		\
+        || DECL_INITIAL (DECL))						\
+      machopic_define_name (xname);					\
+    if ((TREE_STATIC (DECL)						\
+	 && (!DECL_COMMON (DECL) || !TREE_PUBLIC (DECL)))		\
+        || DECL_INITIAL (DECL))						\
       (* targetm.encode_section_info) (DECL, DECL_RTL (DECL), false);	\
-    ASM_OUTPUT_LABEL (FILE, xname);                                     \
+    ASM_OUTPUT_LABEL (FILE, xname);					\
+    /* Darwin doesn't support zero-size objects, so give them a	\
+       byte.  */							\
+    if (tree_low_cst (DECL_SIZE_UNIT (DECL), 1) == 0)			\
+      assemble_zeros (1);						\
   } while (0)
 
 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL)                     \
@@ -389,6 +395,15 @@ do { text_section ();							\
     machopic_output_possible_stub_label (FILE, xname);			\
   } while (0)
 
+#define ASM_DECLARE_CONSTANT_NAME(FILE, NAME, EXP, SIZE)	\
+  do {								\
+    ASM_OUTPUT_LABEL (FILE, NAME);				\
+    /* Darwin doesn't support zero-size objects, so give them a	\
+       byte.  */						\
+    if ((SIZE) == 0)						\
+      assemble_zeros (1);					\
+  } while (0)
+
 /* Wrap new method names in quotes so the assembler doesn't gag.
    Make Objective-C internal symbols local.  */
 
@@ -396,7 +411,9 @@ do { text_section ();							\
 #define ASM_OUTPUT_LABELREF(FILE,NAME)					     \
   do {									     \
        const char *xname = darwin_strip_name_encoding (NAME);		     \
-       if (xname[0] == '&' || xname[0] == '*')				     \
+       if (! strcmp (xname, "<pic base>"))				     \
+         machopic_output_function_base_name(FILE);                           \
+       else if (xname[0] == '&' || xname[0] == '*')			     \
          {								     \
            int len = strlen (xname);					     \
 	   if (len > 6 && !strcmp ("$stub", xname + len - 5))		     \
@@ -463,9 +480,9 @@ do { text_section ();							\
 
 #undef	SECTION_FUNCTION
 #define SECTION_FUNCTION(FUNCTION, SECTION, DIRECTIVE, OBJC)		\
-extern void FUNCTION PARAMS ((void));					\
+extern void FUNCTION (void);						\
 void									\
-FUNCTION ()								\
+FUNCTION (void)								\
 {									\
   if (in_section != SECTION)						\
     {									\
@@ -493,8 +510,9 @@ FUNCTION ()								\
   in_objc_symbols, in_objc_module_info,			\
   in_objc_protocol, in_objc_string_object,		\
   in_objc_constant_string_object,			\
+  in_objc_image_info,					\
   in_objc_class_names, in_objc_meth_var_names,		\
-  in_objc_meth_var_types, in_objc_cls_refs, 		\
+  in_objc_meth_var_types, in_objc_cls_refs,		\
   in_machopic_nl_symbol_ptr,				\
   in_machopic_lazy_symbol_ptr,				\
   in_machopic_symbol_stub,				\
@@ -506,7 +524,7 @@ FUNCTION ()								\
 
 #undef	EXTRA_SECTION_FUNCTIONS
 #define EXTRA_SECTION_FUNCTIONS			\
-static void objc_section_init PARAMS ((void));	\
+static void objc_section_init (void);		\
 SECTION_FUNCTION (const_section,		\
                   in_const,			\
                   ".const", 0)			\
@@ -582,6 +600,10 @@ SECTION_FUNCTION (objc_string_object_section,	\
 SECTION_FUNCTION (objc_constant_string_object_section,	\
 		  in_objc_constant_string_object,	\
 		  ".section __OBJC, __cstring_object", 1)	\
+/* Fix-and-Continue image marker.  */		\
+SECTION_FUNCTION (objc_image_info_section,	\
+                  in_objc_image_info,		\
+                  ".section __OBJC, __image_info", 1)	\
 SECTION_FUNCTION (objc_class_names_section,	\
 		in_objc_class_names,		\
 		".objc_class_names", 1)	\
@@ -597,19 +619,19 @@ SECTION_FUNCTION (objc_cls_refs_section,	\
 						\
 SECTION_FUNCTION (machopic_lazy_symbol_ptr_section,	\
 		in_machopic_lazy_symbol_ptr,		\
-		".lazy_symbol_pointer", 0)      	\
+		".lazy_symbol_pointer", 0)	\
 SECTION_FUNCTION (machopic_nl_symbol_ptr_section,	\
 		in_machopic_nl_symbol_ptr,		\
-		".non_lazy_symbol_pointer", 0)      	\
+		".non_lazy_symbol_pointer", 0)	\
 SECTION_FUNCTION (machopic_symbol_stub_section,		\
 		in_machopic_symbol_stub,		\
-		".symbol_stub", 0)      		\
+		".symbol_stub", 0)		\
 SECTION_FUNCTION (machopic_symbol_stub1_section,	\
 		in_machopic_symbol_stub1,		\
 		".section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16", 0)\
 SECTION_FUNCTION (machopic_picsymbol_stub_section,	\
 		in_machopic_picsymbol_stub,		\
-		".picsymbol_stub", 0)      		\
+		".picsymbol_stub", 0)		\
 SECTION_FUNCTION (machopic_picsymbol_stub1_section,	\
 		in_machopic_picsymbol_stub1,		\
 		".section __TEXT,__picsymbolstub1,symbol_stubs,pure_instructions,32", 0)\
@@ -621,7 +643,7 @@ SECTION_FUNCTION (darwin_eh_frame_section,		\
 		".section __TEXT,__eh_frame", 0)	\
 							\
 static void					\
-objc_section_init ()				\
+objc_section_init (void)			\
 {						\
   static int been_here = 0;			\
 						\
@@ -638,7 +660,7 @@ objc_section_init ()				\
       objc_cls_refs_section ();			\
       objc_class_section ();			\
       objc_meta_class_section ();		\
-          /* shared, hot -> cold */    		\
+          /* shared, hot -> cold */		\
       objc_cls_meth_section ();			\
       objc_inst_meth_section ();		\
       objc_protocol_section ();			\
@@ -661,7 +683,7 @@ objc_section_init ()				\
 #define TARGET_ASM_SELECT_RTX_SECTION machopic_select_rtx_section
 
 #define ASM_DECLARE_UNRESOLVED_REFERENCE(FILE,NAME)			\
-    do { 								\
+    do {								\
 	 if (FILE) {							\
 	   if (MACHOPIC_INDIRECT)					\
 	     fprintf (FILE, "\t.lazy_reference ");			\
@@ -676,7 +698,7 @@ objc_section_init ()				\
     do {								\
 	 if (FILE) {							\
 	   fprintf (FILE, "\t");					\
-	   assemble_name (FILE, NAME); 					\
+	   assemble_name (FILE, NAME);					\
 	   fprintf (FILE, "=0\n");					\
 	   (*targetm.asm_out.globalize_label) (FILE, NAME);		\
 	 }								\
@@ -778,7 +800,7 @@ enum machopic_addr_class {
 #define TARGET_ASM_EXCEPTION_SECTION darwin_exception_section
 
 #define TARGET_ASM_EH_FRAME_SECTION darwin_eh_frame_section
-  
+
 #undef ASM_PREFERRED_EH_DATA_FORMAT
 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL)  \
   (((CODE) == 2 && (GLOBAL) == 1) \
diff --git a/gcc/config/fp-bit.c b/gcc/config/fp-bit.c
index 6640f7ad1b4..51c67430535 100644
--- a/gcc/config/fp-bit.c
+++ b/gcc/config/fp-bit.c
@@ -46,7 +46,7 @@ Boston, MA 02111-1307, USA.  */
 #include "tconfig.h"
 #include "coretypes.h"
 #include "tm.h"
-#include "fp-bit.h"
+#include "config/fp-bit.h"
 
 /* The following macros can be defined to change the behavior of this file:
    FLOAT: Implement a `float', aka SFmode, fp library.  If this is not
diff --git a/gcc/config/frv/frv-asm.h b/gcc/config/frv/frv-asm.h
index e8447a6093d..46814278522 100644
--- a/gcc/config/frv/frv-asm.h
+++ b/gcc/config/frv/frv-asm.h
@@ -1,19 +1,19 @@
 /* Assembler Support.
    Copyright (C) 2000 Free Software Foundation, Inc.
    Contributed by Red Hat, Inc.
-  
+
    This file is part of GNU CC.
-  
+
    GNU CC is free software ; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation * either version 2, or (at your option)
    any later version.
-  
+
    GNU CC is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY ; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
-  
+
    You should have received a copy of the GNU General Public License
    along with GNU CC; see the file COPYING.  If not, write to
    the Free Software Foundation, 59 Temple Place - Suite 330,
@@ -23,7 +23,7 @@
    P2(INSN): Emit INSN.P on the FR500 and above, otherwise emit plain INSN.  */
 #ifdef __FRV_VLIW__
 #ifdef __STDC__
-#define P(A) A##.p
+#define P(A) A.p
 #else
 #define P(A) A/**/.p
 #endif
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 5caf13d7c52..84d6d357a57 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -9649,53 +9649,38 @@ frv_expand_builtin (exp, target, subtarget, mode, ignore)
 
   /* Expand groups of builtins. */
 
-  for (i = 0, d = bdesc_set; i < sizeof (bdesc_set) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_set; i < ARRAY_SIZE (bdesc_set); i++, d++)
     if (d->code == fcode)
       return frv_expand_set_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_1arg; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
     if (d->code == fcode)
       return frv_expand_unop_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_2arg; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
     if (d->code == fcode)
       return frv_expand_binop_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_cut; i < sizeof (bdesc_cut) / sizeof *d; i++, d++)
+  for (i = 0, d = bdesc_cut; i < ARRAY_SIZE (bdesc_cut); i++, d++)
     if (d->code == fcode)
       return frv_expand_cut_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_2argimm;
-       i < sizeof (bdesc_2argimm) / sizeof *d;
-       i++, d++)
-    {
-      if (d->code == fcode)
-	return frv_expand_binopimm_builtin (d->icode, arglist, target);
-    }
+  for (i = 0, d = bdesc_2argimm; i < ARRAY_SIZE (bdesc_2argimm); i++, d++)
+    if (d->code == fcode)
+      return frv_expand_binopimm_builtin (d->icode, arglist, target);
 
-  for (i = 0, d = bdesc_void2arg;
-       i < sizeof (bdesc_void2arg) / sizeof *d;
-       i++, d++)
-    {
-      if (d->code == fcode)
-	return frv_expand_voidbinop_builtin (d->icode, arglist);
-    }
+  for (i = 0, d = bdesc_void2arg; i < ARRAY_SIZE (bdesc_void2arg); i++, d++)
+    if (d->code == fcode)
+      return frv_expand_voidbinop_builtin (d->icode, arglist);
 
-  for (i = 0, d = bdesc_void3arg;
-       i < sizeof (bdesc_void3arg) / sizeof *d;
-       i++, d++)
-    {
-      if (d->code == fcode)
-	return frv_expand_voidtriop_builtin (d->icode, arglist);
-    }
+  for (i = 0, d = bdesc_void3arg; i < ARRAY_SIZE (bdesc_void3arg); i++, d++)
+    if (d->code == fcode)
+      return frv_expand_voidtriop_builtin (d->icode, arglist);
+
+  for (i = 0, d = bdesc_voidacc; i < ARRAY_SIZE (bdesc_voidacc); i++, d++)
+    if (d->code == fcode)
+      return frv_expand_voidaccop_builtin (d->icode, arglist);
 
-  for (i = 0, d = bdesc_voidacc;
-       i < sizeof (bdesc_voidacc) / sizeof *d;
-       i++, d++)
-    {
-      if (d->code == fcode)
-	return frv_expand_voidaccop_builtin (d->icode, arglist);
-    }
   return 0;
 }
 
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index dda5a059e8e..feadc791b9c 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1,5 +1,5 @@
 /* Target macros for the FRV port of GCC.
-   Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Red Hat Inc.
 
    This file is part of GCC.
@@ -22,10 +22,6 @@
 #ifndef __FRV_H__
 #define __FRV_H__
 
-/* Set up System V.4 (aka ELF) defaults.  */
-#include "svr4.h"
-
-
 /* Frv general purpose macros.  */
 /* Align an address.  */
 #define ADDR_ALIGN(addr,align) (((addr) + (align) - 1) & ~((align) - 1))
diff --git a/gcc/config/frv/t-frv b/gcc/config/frv/t-frv
index eec05b1ea81..a9130ff0604 100644
--- a/gcc/config/frv/t-frv
+++ b/gcc/config/frv/t-frv
@@ -19,11 +19,11 @@ TARGET_LIBGCC2_CFLAGS =
 
 fp-bit.c: $(srcdir)/config/fp-bit.c
 	echo '#define FLOAT' > fp-bit.c
-	echo '#include "frv/frv-abi.h"' >> fp-bit.c
+	echo '#include "config/frv/frv-abi.h"' >> fp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
 
 dp-bit.c: $(srcdir)/config/fp-bit.c
-	echo '#include "frv/frv-abi.h"' > dp-bit.c
+	echo '#include "config/frv/frv-abi.h"' > dp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
 
 cmovh.c: $(srcdir)/config/frv/cmovh.c
diff --git a/gcc/config/h8300/coff.h b/gcc/config/h8300/coff.h
new file mode 100644
index 00000000000..7b56a494ac6
--- /dev/null
+++ b/gcc/config/h8300/coff.h
@@ -0,0 +1,56 @@
+/* Definitions of target machine for GNU compiler.
+   Hitachi H8/300 version generating coff
+   Copyright (C) 2003 Free Software Foundation, Inc.
+   Contributed by Steve Chamberlain (sac@cygnus.com),
+   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef GCC_H8300_COFF_H
+#define GCC_H8300_COFF_H
+
+#define SDB_DEBUGGING_INFO 1
+#define SDB_DELIM	"\n"
+
+/* Override definition in dbxcoff.h.  */
+/* Generate a blank trailing N_SO to mark the end of the .o file, since
+   we can't depend upon the linker to mark .o file boundaries with
+   embedded stabs.  */
+
+#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
+#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
+  fprintf (FILE,							\
+	   "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
+
+/* This is how to output an assembler line
+   that says to advance the location counter by SIZE bytes.  */
+
+#define ASM_OUTPUT_IDENT(FILE, NAME)			\
+  fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME)
+
+#define IDENT_ASM_OP "\t.ident\t"
+#define INIT_SECTION_ASM_OP "\t.section .init"
+#define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata"
+
+/* Switch into a generic section.  */
+#define TARGET_ASM_NAMED_SECTION h8300_asm_named_section
+
+/* A bit-field declared as `int' forces `int' alignment for the struct.  */
+#define PCC_BITFIELD_TYPE_MATTERS  0
+
+#endif /* h8300/coff.h */
diff --git a/gcc/config/h8300/elf.h b/gcc/config/h8300/elf.h
index 7f67a3a78b1..bae8c265040 100644
--- a/gcc/config/h8300/elf.h
+++ b/gcc/config/h8300/elf.h
@@ -1,25 +1,28 @@
-/* Undefine some macros defined in h8300 that conflict with elfos.h .  */
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef ASM_OUTPUT_IDENT
-#undef IDENT_ASM_OP
-#undef CTORS_SECTION_ASM_OP
-#undef DTORS_SECTION_ASM_OP
-#undef INIT_SECTION_ASM_OP
-#undef READONLY_DATA_SECTION_ASM_OP
-#undef TARGET_ASM_NAMED_SECTION
-#undef TARGET_MEM_FUNCTIONS
-#undef PREFERRED_DEBUGGING_TYPE
-/* ??? h8300.h defines PCC_BITFIELD_TYPE_MATTERS to 0, but it
-   doesn't define STRUCTURE_SIZE_BOUNDARY, nor does h8300.md
-   have a full set of bit field instructions.  */
-#undef PCC_BITFIELD_TYPE_MATTERS
-
-#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
-
-#include "dbxelf.h"
-#include "elfos.h"
+/* Definitions of target machine for GNU compiler.
+   Hitachi H8/300 version generating elf
+   Copyright (C) 2001, 2002, 2003 Free Software Foundation, Inc.
+   Contributed by Steve Chamberlain (sac@cygnus.com),
+   Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
 
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#ifndef GCC_H8300_ELF_H
+#define GCC_H8300_ELF_H
 
 #undef  ENDFILE_SPEC
 #define ENDFILE_SPEC "crtend.o%s %{pg:gcrtn.o%s}%{!pg:crtn.o%s}"
@@ -38,3 +41,5 @@
 
 #undef LINK_SPEC
 #define LINK_SPEC "%{mh:%{mn:-m h8300hnelf}} %{mh:%{!mn:-m h8300helf}} %{ms:%{mn:-m h8300snelf}} %{ms:%{!mn:-m h8300self}}"
+
+#endif /* h8300/elf.h */
diff --git a/gcc/config/h8300/h8300-protos.h b/gcc/config/h8300/h8300-protos.h
index d99f0dca0b9..e36ae4b719c 100644
--- a/gcc/config/h8300/h8300-protos.h
+++ b/gcc/config/h8300/h8300-protos.h
@@ -98,6 +98,7 @@ extern void h8300_expand_prologue (void);
 extern void h8300_expand_epilogue (void);
 extern int h8300_current_function_interrupt_function_p (void);
 extern int h8300_initial_elimination_offset (int, int);
+extern int h8300_hard_regno_rename_ok (unsigned int, unsigned int);
 
 struct cpp_reader;
 extern void h8300_pr_interrupt (struct cpp_reader *);
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 5ab2bfac04d..3d874c2c085 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -4489,6 +4489,23 @@ same_cmp_preceding_p (rtx i3)
   return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3))
 	  && any_condjump_p (i2) && onlyjump_p (i2));
 }
+
+/* Return nonzero if register OLD_REG can be renamed to register NEW_REG.  */
+
+int
+h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
+			    unsigned int new_reg)
+{
+  /* Interrupt functions can only use registers that have already been
+     saved by the prologue, even if they would normally be
+     call-clobbered.  */
+
+  if (h8300_current_function_interrupt_function_p ()
+      && !regs_ever_live[new_reg])
+    return 0;
+
+   return 1;
+}
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ATTRIBUTE_TABLE
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index ba8dcffdeb1..c4103d0464f 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler.
-   Hitachi H8/300 version generating coff
+   Hitachi H8/300 (generic)
    Copyright (C) 1992, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999,
    2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain (sac@cygnus.com),
@@ -257,9 +257,6 @@ extern int target_flags;
    structure layouts.  */
 #define EMPTY_FIELD_BOUNDARY 16
 
-/* A bit-field declared as `int' forces `int' alignment for the struct.  */
-#define PCC_BITFIELD_TYPE_MATTERS  0
-
 /* No data type wants to be aligned rounder than this.
    32 bit values are aligned as such on the H8/300H and H8S for speed.  */
 #define BIGGEST_ALIGNMENT \
@@ -353,6 +350,12 @@ extern int target_flags;
        &&  ((MODE2) == QImode || (MODE2) == HImode			  \
 	    || ((TARGET_H8300H || TARGET_H8300S) && (MODE2) == SImode))))
 
+/* A C expression that is nonzero if hard register NEW_REG can be
+   considered for use as a rename register for OLD_REG register */
+
+#define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG)		\
+   h8300_hard_regno_rename_ok (OLD_REG, NEW_REG)
+
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
 
@@ -1038,7 +1041,6 @@ struct cum_arg
 #define ASM_APP_OFF "; #NO_APP\n"
 
 #define FILE_ASM_OP "\t.file\n"
-#define IDENT_ASM_OP "\t.ident\t"
 
 /* The assembler op to get a word, 2 bytes for the H8/300, 4 for H8/300H.  */
 #define ASM_WORD_OP							\
@@ -1047,8 +1049,6 @@ struct cum_arg
 #define TEXT_SECTION_ASM_OP "\t.section .text"
 #define DATA_SECTION_ASM_OP "\t.section .data"
 #define BSS_SECTION_ASM_OP "\t.section .bss"
-#define INIT_SECTION_ASM_OP "\t.section .init"
-#define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata"
 
 #undef DO_GLOBAL_CTORS_BODY
 #define DO_GLOBAL_CTORS_BODY			\
@@ -1086,26 +1086,6 @@ struct cum_arg
 { {"er0", 0}, {"er1", 1}, {"er2", 2}, {"er3", 3}, {"er4", 4}, \
   {"er5", 5}, {"er6", 6}, {"er7", 7}, {"r7", 7} }
 
-#define SDB_DEBUGGING_INFO 1
-#define SDB_DELIM	"\n"
-
-/* Support -gstabs.  */
-
-#include "dbxcoff.h"
-
-/* Override definition in dbxcoff.h.  */
-/* Generate a blank trailing N_SO to mark the end of the .o file, since
-   we can't depend upon the linker to mark .o file boundaries with
-   embedded stabs.  */
-
-#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
-#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)			\
-  fprintf (FILE,							\
-	   "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
-
-/* Switch into a generic section.  */
-#define TARGET_ASM_NAMED_SECTION h8300_asm_named_section
-
 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME)
 
 /* Globalizing directive for a label.  */
@@ -1158,12 +1138,6 @@ struct cum_arg
   if ((LOG) != 0)				\
     fprintf (FILE, "\t.align %d\n", (LOG))
 
-/* This is how to output an assembler line
-   that says to advance the location counter by SIZE bytes.  */
-
-#define ASM_OUTPUT_IDENT(FILE, NAME)			\
-  fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME)
-
 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
   fprintf (FILE, "\t.space %d\n", (int)(SIZE))
 
@@ -1221,7 +1195,7 @@ struct cum_arg
    (and ANSI C) library functions `memcpy' and `memset' rather than
    the BSD functions `bcopy' and `bzero'.  */
 
-#define TARGET_MEM_FUNCTIONS 1
+#define TARGET_MEM_FUNCTIONS
 
 #define MULHI3_LIBCALL	"__mulhi3"
 #define DIVHI3_LIBCALL	"__divhi3"
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 4ae445c31e6..b17a03ead80 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -652,43 +652,6 @@
 			 (match_dup 3)))]
   "operands[3] = GEN_INT (INTVAL (operands[1]) - 16);")
 
-(define_insn ""
-  [(set (cc0)
-	(and:HI (match_operand:HI 0 "register_operand" "r")
-		(match_operand:HI 1 "single_one_operand" "n")))]
-  ""
-  "*
-{
-  operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
-  if (INTVAL (operands[1]) > 128)
-    {
-      operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
-      return \"btst\\t%V1,%t0\";
-    }
-  return \"btst\\t%V1,%s0\";
-}"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
-(define_insn ""
-  [(set (cc0)
-	(and:SI (match_operand:SI 0 "register_operand" "r")
-		(match_operand:SI 1 "single_one_operand" "n")))]
-  "(TARGET_H8300H || TARGET_H8300S)
-   && (INTVAL (operands[1]) & 0xffff) != 0"
-  "*
-{
-  operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
-  if (INTVAL (operands[1]) > 128)
-    {
-      operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
-      return \"btst\\t%V1,%x0\";
-    }
-  return \"btst\\t%V1,%w0\";
-}"
-  [(set_attr "length" "2")
-   (set_attr "cc" "set_zn")])
-
 (define_insn "tstqi"
   [(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
   ""
@@ -4120,6 +4083,8 @@
 ;;
 ;; dead 0xffffff?? except -1 and -2 eq/ne   xor.b and not.l
 ;; dead 0xffff??ff                  eq/ne   xor.b and not.l
+;; dead 0x40000000 (H8S)            eq/ne   rotl.l and dec.l
+;; dead 0x80000000                  eq/ne   rotl.l and dec.l
 ;;
 ;; live     1                       geu/ltu copy and shar.l
 ;; live     3 (H8S)                 geu/ltu copy and shar.l
@@ -4248,6 +4213,34 @@
 		      (pc)))]
   "operands[4] = GEN_INT (INTVAL (operands[1]) ^ -1);")
 
+(define_peephole2
+  [(set (cc0)
+	(compare (match_operand:SI 0 "register_operand" "")
+		 (match_operand:SI 1 "const_int_operand" "")))
+   (set (pc)
+	(if_then_else (match_operator 3 "eqne_operator"
+			[(cc0) (const_int 0)])
+		      (label_ref (match_operand 2 "" ""))
+		      (pc)))]
+  "(TARGET_H8300H || TARGET_H8300S)
+   && peep2_reg_dead_p (1, operands[0])
+   && (INTVAL (operands[1]) == -2147483648
+       || (TARGET_H8300S && INTVAL (operands[1]) == 1073741824))"
+  [(set (match_dup 0)
+	(rotate:SI (match_dup 0)
+		   (match_dup 4)))
+   (set (match_dup 0)
+	(unspec:SI [(match_dup 0)
+		    (const_int -1)]
+		   UNSPEC_INCDEC))
+   (set (cc0)
+	(match_dup 0))
+   (set (pc)
+	(if_then_else (match_op_dup 3 [(cc0) (const_int 0)])
+		      (label_ref (match_dup 2))
+		      (pc)))]
+  "operands[4] = GEN_INT (INTVAL (operands[1]) == -2147483648 ? 1 : 2);")
+
 ;; Transform
 ;;
 ;;	cmp.l	#1,er0
diff --git a/gcc/config/i370/i370.md b/gcc/config/i370/i370.md
index 5bdbec80abe..081c62dd8fa 100644
--- a/gcc/config/i370/i370.md
+++ b/gcc/config/i370/i370.md
@@ -474,10 +474,10 @@ check_label_emit ();
 )
 
 ;
-; cmpstrsi instruction pattern(s).
+; cmpmemsi instruction pattern(s).
 ;
 
-(define_expand "cmpstrsi"
+(define_expand "cmpmemsi"
   [(set (match_operand:SI 0 "general_operand" "")
 	  (compare (match_operand:BLK 1 "general_operand" "")
 		   (match_operand:BLK 2 "general_operand" "")))
@@ -545,7 +545,7 @@ check_label_emit ();
         emit_move_insn (gen_rtx_SUBREG (SImode, reg2, GET_MODE_SIZE (SImode)), len);
 
         /* Compare! */
-        emit_insn (gen_cmpstrsi_1 (result, reg1, reg2));
+        emit_insn (gen_cmpmemsi_1 (result, reg1, reg2));
     }
   DONE;
 }")
@@ -569,7 +569,7 @@ check_label_emit ();
 
 ; Compare a block that is larger than 255 bytes in length.
 
-(define_insn "cmpstrsi_1"
+(define_insn "cmpmemsi_1"
   [(set (match_operand:SI 0 "register_operand" "+d")
         (compare
         (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "+d") 0))
diff --git a/gcc/config/i370/linux.h b/gcc/config/i370/linux.h
index 730d6b0e996..adc14105947 100644
--- a/gcc/config/i370/linux.h
+++ b/gcc/config/i370/linux.h
@@ -1,5 +1,6 @@
 /* Definitions of target machine for GNU compiler.  System/370 version.
-   Copyright (C) 1989, 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1989, 1993, 1995, 1996, 1997, 2003
+   Free Software Foundation, Inc.
    Contributed by Jan Stein (jan@cd.chalmers.se).
    Modified for Linux/390 by Linas Vepstas (linas@linas.org)
 
@@ -26,11 +27,6 @@ Boston, MA 02111-1307, USA.  */
 /* Specify that we're generating code for a Linux port to 370 */
 
 #define TARGET_ELF_ABI
-#define LINUX_DEFAULT_ELF
-
-/* Include system common definitions */
-/* TODO: convert include to ${tm_file} list in config.gcc.  */
-#include "i370/i370.h"
 
 /* Target OS preprocessor built-ins.  */
 #define TARGET_OS_CPP_BUILTINS()		\
diff --git a/gcc/config/i370/mvs.h b/gcc/config/i370/mvs.h
index 0e29fa4c8f1..0b8a374375f 100644
--- a/gcc/config/i370/mvs.h
+++ b/gcc/config/i370/mvs.h
@@ -1,5 +1,6 @@
 /* Definitions of target machine for GNU compiler.  System/370 version.
-   Copyright (C) 1989, 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1989, 1993, 1995, 1996, 1997, 2003
+   Free Software Foundation, Inc.
    Contributed by Jan Stein (jan@cd.chalmers.se).
    Modified for OS/390 LanguageEnvironment C by Dave Pitts (dpitts@cozx.com)
 
@@ -46,8 +47,3 @@ Boston, MA 02111-1307, USA.  */
 #else
 # define MAYBE_LE370_MACROS()
 #endif
-
-/* Include system common definitions */
-
-#include "config/i370/i370.h"
-
diff --git a/gcc/config/i370/oe.h b/gcc/config/i370/oe.h
index afc9bd3073d..9d36ea9bbf5 100644
--- a/gcc/config/i370/oe.h
+++ b/gcc/config/i370/oe.h
@@ -1,5 +1,6 @@
 /* Definitions of target machine for GNU compiler.  System/370 version.
-   Copyright (C) 1989, 1993, 1995, 1996, 1997 Free Software Foundation, Inc.
+   Copyright (C) 1989, 1993, 1995, 1996, 1997, 2003
+   Free Software Foundation, Inc.
    Contributed by Jan Stein (jan@cd.chalmers.se).
    Modified for OS/390 OpenEdition by Dave Pitts (dpitts@cozx.com)
 
@@ -50,7 +51,3 @@ Boston, MA 02111-1307, USA.  */
 	builtin_assert ("system=unix");		\
     } while (0)
 
-/* Include system common definitions */
-
-#include "config/i370/i370.h"
-
diff --git a/gcc/config/i386/cygming.h b/gcc/config/i386/cygming.h
index 2f9b0a1920e..95b894ad217 100644
--- a/gcc/config/i386/cygming.h
+++ b/gcc/config/i386/cygming.h
@@ -45,7 +45,7 @@ Boston, MA 02111-1307, USA.  */
 { "console",		  0, N_("Create console application") },\
 { "dll",		  0, N_("Generate code for a DLL") },	\
 { "nop-fun-dllimport",	  MASK_NOP_FUN_DLLIMPORT,		\
-  N_("Ignore dllimport for functions") }, 			\
+  N_("Ignore dllimport for functions") },			\
 { "no-nop-fun-dllimport", -MASK_NOP_FUN_DLLIMPORT, "" },	\
 { "threads",		  0, N_("Use Mingw-specific thread support") },
 
@@ -94,7 +94,7 @@ Boston, MA 02111-1307, USA.  */
    Do not define this macro if it does not need to do anything.  */
 
 #undef  SUBTARGET_EXTRA_SPECS
-#define SUBTARGET_EXTRA_SPECS 						\
+#define SUBTARGET_EXTRA_SPECS						\
   { "mingw_include_path", DEFAULT_TARGET_MACHINE }
 
 #undef MATH_LIBRARY
@@ -130,7 +130,7 @@ drectve_section ()							\
       in_section = in_drectve;						\
     }									\
 }
-void drectve_section PARAMS ((void));
+void drectve_section (void);
 
 /* Switch to SECTION (an `enum in_section').
 
@@ -138,21 +138,19 @@ void drectve_section PARAMS ((void));
    The problem is that we want to temporarily switch sections in
    ASM_DECLARE_OBJECT_NAME and then switch back to the original section
    afterwards.  */
-#define SWITCH_TO_SECTION_FUNCTION 				\
-void switch_to_section PARAMS ((enum in_section, tree));        \
-void 								\
-switch_to_section (section, decl) 				\
-     enum in_section section; 					\
-     tree decl; 						\
-{ 								\
-  switch (section) 						\
-    { 								\
-      case in_text: text_section (); break; 			\
-      case in_data: data_section (); break; 			\
-      case in_named: named_section (decl, NULL, 0); break; 	\
-      case in_drectve: drectve_section (); break; 		\
-      default: abort (); break; 				\
-    } 								\
+#define SWITCH_TO_SECTION_FUNCTION				\
+void switch_to_section (enum in_section, tree);			\
+void								\
+switch_to_section (enum in_section section, tree decl)		\
+{								\
+  switch (section)						\
+    {								\
+      case in_text: text_section (); break;			\
+      case in_data: data_section (); break;			\
+      case in_named: named_section (decl, NULL, 0); break;	\
+      case in_drectve: drectve_section (); break;		\
+      default: abort (); break;				\
+    }								\
 }
 
 /* Don't allow flag_pic to propagate since gas may produce invalid code
@@ -173,15 +171,15 @@ do {									\
    differently depending on something about the variable or
    function named by the symbol (such as what section it is in).
 
-   On i386 running Windows NT, modify the assembler name with a suffix 
+   On i386 running Windows NT, modify the assembler name with a suffix
    consisting of an atsign (@) followed by string of digits that represents
-   the number of bytes of arguments passed to the function, if it has the 
+   the number of bytes of arguments passed to the function, if it has the
    attribute STDCALL.
 
-   In addition, we must mark dll symbols specially. Definitions of 
-   dllexport'd objects install some info in the .drectve section.  
+   In addition, we must mark dll symbols specially. Definitions of
+   dllexport'd objects install some info in the .drectve section.
    References to dllimport'd objects are fetched indirectly via
-   _imp__.  If both are declared, dllexport overrides.  This is also 
+   _imp__.  If both are declared, dllexport overrides.  This is also
    needed to implement one-only vtables: they go into their own
    section and we need to set DECL_SECTION_NAME so we do that here.
    Note that we can be called twice on the same decl.  */
@@ -203,7 +201,7 @@ do {							\
     i386_pe_record_exported_symbol (NAME, 1);		\
   if (! i386_pe_dllimport_name_p (NAME))		\
     {							\
-      fprintf ((STREAM), "\t.comm\t"); 			\
+      fprintf ((STREAM), "\t.comm\t");			\
       assemble_name ((STREAM), (NAME));			\
       fprintf ((STREAM), ", %d\t%s %d\n",		\
 	       (int)(ROUNDED), ASM_COMMENT_START, (int)(SIZE));	\
@@ -212,7 +210,7 @@ do {							\
 
 /* Output the label for an initialized variable.  */
 #undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) 	\
+#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)	\
 do {							\
   if (i386_pe_dllexport_name_p (NAME))			\
     i386_pe_record_exported_symbol (NAME, 1);		\
@@ -248,7 +246,7 @@ do {							\
    symbols must be explicitly imported from shared libraries (DLLs).  */
 #define MULTIPLE_SYMBOL_SPACES
 
-extern void i386_pe_unique_section PARAMS ((TREE, int));
+extern void i386_pe_unique_section (TREE, int);
 #define TARGET_ASM_UNIQUE_SECTION i386_pe_unique_section
 
 #define SUPPORTS_ONE_ONLY 1
@@ -328,12 +326,12 @@ extern void i386_pe_unique_section PARAMS ((TREE, int));
 
 /* External function declarations.  */
 
-extern void i386_pe_record_external_function PARAMS ((const char *));
-extern void i386_pe_declare_function_type PARAMS ((FILE *, const char *, int));
-extern void i386_pe_record_exported_symbol PARAMS ((const char *, int));
-extern void i386_pe_file_end PARAMS ((void));
-extern int i386_pe_dllexport_name_p PARAMS ((const char *));
-extern int i386_pe_dllimport_name_p PARAMS ((const char *));
+extern void i386_pe_record_external_function (const char *);
+extern void i386_pe_declare_function_type (FILE *, const char *, int);
+extern void i386_pe_record_exported_symbol (const char *, int);
+extern void i386_pe_file_end (void);
+extern int i386_pe_dllexport_name_p (const char *);
+extern int i386_pe_dllimport_name_p (const char *);
 
 /* For Win32 ABI compatibility */
 #undef DEFAULT_PCC_STRUCT_RETURN
diff --git a/gcc/config/i386/cygwin.h b/gcc/config/i386/cygwin.h
index ea505741f3c..6fe7e197e58 100644
--- a/gcc/config/i386/cygwin.h
+++ b/gcc/config/i386/cygwin.h
@@ -20,7 +20,7 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define TARGET_VERSION fprintf (stderr, " (x86 Cygwin)"); 
+#define TARGET_VERSION fprintf (stderr, " (x86 Cygwin)");
 
 #define EXTRA_OS_CPP_BUILTINS()  /* Nothing.  */
 
@@ -81,7 +81,7 @@ Boston, MA 02111-1307, USA.  */
 
 #ifndef CYGWIN_MINGW_SUBDIR
 #define CYGWIN_MINGW_SUBDIR "/mingw"
-#endif 
+#endif
 #define CYGWIN_MINGW_SUBDIR_LEN (sizeof (CYGWIN_MINGW_SUBDIR) - 1)
 
 #ifdef GPLUSPLUS_INCLUDE_DIR
@@ -199,7 +199,7 @@ char *cvt_to_mingw[] =
 #undef GEN_CVT_ARRAY
 #endif /*GEN_CVT_ARRAY*/
 
-void mingw_scan PARAMS ((int, const char * const *, char **));
+void mingw_scan (int, const char * const *, char **);
 #if 1
 #define GCC_DRIVER_HOST_INITIALIZATION \
 do \
diff --git a/gcc/config/i386/cygwin2.c b/gcc/config/i386/cygwin2.c
index 39bcd71ecd6..598aa0fec16 100644
--- a/gcc/config/i386/cygwin2.c
+++ b/gcc/config/i386/cygwin2.c
@@ -28,13 +28,13 @@ Boston, MA 02111-1307, USA.  */
 #include <string.h>
 
 /*
-static void remove_w32api PARAMS ((void));
+static void remove_w32api (void);
 */
-static void add_mingw PARAMS ((void));
-static void set_mingw PARAMS((void)) __attribute__ ((constructor));
+static void add_mingw (void);
+static void set_mingw (void) __attribute__ ((constructor));
 
 static void
-add_mingw ()
+add_mingw (void)
 {
   char **av;
   char *p;
@@ -59,7 +59,7 @@ add_mingw ()
 
 
 static void
-set_mingw ()
+set_mingw (void)
 {
   char *env = getenv ("GCC_CYGWIN_MINGW");
   if (env && *env == '1')
diff --git a/gcc/config/i386/darwin.h b/gcc/config/i386/darwin.h
index 2e68be81c6f..3b70de4f1bc 100644
--- a/gcc/config/i386/darwin.h
+++ b/gcc/config/i386/darwin.h
@@ -41,6 +41,16 @@ Boston, MA 02111-1307, USA.  */
 #undef CC1_SPEC
 #define CC1_SPEC "%{!static:-fPIC}"
 
+#define ASM_SPEC "-arch i386 \
+  %{Zforce_cpusubtype_ALL:-force_cpusubtype_ALL} \
+  %{!Zforce_cpusubtype_ALL:%{mmmx:-force_cpusubtype_ALL}\
+			   %{msse:-force_cpusubtype_ALL}\
+			   %{msse2:-force_cpusubtype_ALL}}"
+
+#undef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS			\
+  { "darwin_arch", "i386" },
+
 /* The Darwin assembler mostly follows AT&T syntax.  */
 #undef ASSEMBLER_DIALECT
 #define ASSEMBLER_DIALECT ASM_ATT
diff --git a/gcc/config/i386/freebsd.h b/gcc/config/i386/freebsd.h
index 52dcf1bc4c2..9cd46f28167 100644
--- a/gcc/config/i386/freebsd.h
+++ b/gcc/config/i386/freebsd.h
@@ -26,19 +26,16 @@ Boston, MA 02111-1307, USA.  */
 #define TARGET_VERSION fprintf (stderr, " (i386 FreeBSD/ELF)");
 
 /* Override the default comment-starter of "/".  */
-#undef ASM_COMMENT_START
+#undef  ASM_COMMENT_START
 #define ASM_COMMENT_START "#"
 
-#undef ASM_APP_ON
+#undef  ASM_APP_ON
 #define ASM_APP_ON "#APP\n"
 
-#undef ASM_APP_OFF
+#undef  ASM_APP_OFF
 #define ASM_APP_OFF "#NO_APP\n"
 
-#undef SET_ASM_OP
-#define SET_ASM_OP	"\t.set\t"
-
-#undef DBX_REGISTER_NUMBER
+#undef  DBX_REGISTER_NUMBER
 #define DBX_REGISTER_NUMBER(n) \
   (TARGET_64BIT ? dbx64_register_map[n] : svr4_dbx_register_map[n])
 
@@ -47,19 +44,19 @@ Boston, MA 02111-1307, USA.  */
 
 /* Tell final.c that we don't need a label passed to mcount.  */
 
-#undef MCOUNT_NAME
+#undef  MCOUNT_NAME
 #define MCOUNT_NAME ".mcount"
 
 /* Make gcc agree with <machine/ansi.h>.  */
 
-#undef SIZE_TYPE
-#define SIZE_TYPE "unsigned int"
+#undef  SIZE_TYPE
+#define SIZE_TYPE	(TARGET_64BIT ? "long unsigned int" : "unsigned int")
  
-#undef PTRDIFF_TYPE
-#define PTRDIFF_TYPE "int"
+#undef  PTRDIFF_TYPE
+#define PTRDIFF_TYPE	(TARGET_64BIT ? "long int" : "int")
   
-#undef WCHAR_TYPE_SIZE
-#define WCHAR_TYPE_SIZE BITS_PER_WORD
+#undef  WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE	(TARGET_64BIT ? 32 : BITS_PER_WORD)
     
 /* Provide a STARTFILE_SPEC appropriate for FreeBSD.  Here we add
    the magical crtbegin.o file (see crtstuff.c) which provides part 
@@ -119,6 +116,7 @@ Boston, MA 02111-1307, USA.  */
    This is used to align code labels according to Intel recommendations.  */
 
 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
+#undef  ASM_OUTPUT_MAX_SKIP_ALIGN
 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP)					\
   if ((LOG) != 0) {														\
     if ((MAX_SKIP) == 0) fprintf ((FILE), "\t.p2align %d\n", (LOG));	\
@@ -138,8 +136,10 @@ Boston, MA 02111-1307, USA.  */
    compiler get the contents of <float.h> and std::numeric_limits correct.  */
 #define SUBTARGET_OVERRIDE_OPTIONS			\
   do {							\
-    real_format_for_mode[XFmode - QFmode]		\
-      = &ieee_extended_intel_96_round_53_format;	\
-    real_format_for_mode[TFmode - QFmode]		\
-      = &ieee_extended_intel_96_round_53_format;	\
+    if (!TARGET_64BIT) {				\
+      real_format_for_mode[XFmode - QFmode]		\
+	= &ieee_extended_intel_96_round_53_format;	\
+      real_format_for_mode[TFmode - QFmode]		\
+	= &ieee_extended_intel_96_round_53_format;	\
+    }							\
   } while (0)
diff --git a/gcc/config/i386/gthr-win32.c b/gcc/config/i386/gthr-win32.c
index 06dc2045d24..5510f108ca4 100644
--- a/gcc/config/i386/gthr-win32.c
+++ b/gcc/config/i386/gthr-win32.c
@@ -32,7 +32,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 
 
 #ifndef __GTHREAD_HIDE_WIN32API
-# define __GTHREAD_HIDE_WIN32API
+# define __GTHREAD_HIDE_WIN32API 1
 #endif
 #include <gthr-win32.h>
 #include <windows.h>
diff --git a/gcc/config/i386/i386-interix.h b/gcc/config/i386/i386-interix.h
index 5507649ac42..664cda19b30 100644
--- a/gcc/config/i386/i386-interix.h
+++ b/gcc/config/i386/i386-interix.h
@@ -1,5 +1,5 @@
 /* Target definitions for GNU compiler for Intel 80386 running Interix
-   Parts Copyright (C) 1991, 1999, 2000, 2002 Free Software Foundation, Inc.
+   Parts Copyright (C) 1991, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
 
    Parts:
      by Douglas B. Rupp (drupp@cs.washington.edu).
@@ -341,7 +341,7 @@ while (0)
    symbols must be explicitly imported from shared libraries (DLLs).  */
 #define MULTIPLE_SYMBOL_SPACES
 
-extern void i386_pe_unique_section PARAMS ((tree, int));
+extern void i386_pe_unique_section (tree, int);
 #define TARGET_ASM_UNIQUE_SECTION i386_pe_unique_section
 
 #define SUPPORTS_ONE_ONLY 1
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 2e13624af1a..c1e8ac6c894 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -866,7 +866,7 @@ static unsigned int ix86_select_alt_pic_regnum (void);
 static int ix86_save_reg (unsigned int, int);
 static void ix86_compute_frame_layout (struct ix86_frame *);
 static int ix86_comp_type_attributes (tree, tree);
-static int ix86_fntype_regparm (tree);
+static int ix86_function_regparm (tree, tree);
 const struct attribute_spec ix86_attribute_table[];
 static bool ix86_function_ok_for_sibcall (tree, tree);
 static tree ix86_handle_cdecl_attribute (tree *, tree, tree, int, bool *);
@@ -1532,19 +1532,14 @@ ix86_function_ok_for_sibcall (tree decl, tree exp)
      such registers are not used for passing parameters.  */
   if (!decl && !TARGET_64BIT)
     {
-      int regparm = ix86_regparm;
-      tree attr, type;
+      tree type;
 
       /* We're looking at the CALL_EXPR, we need the type of the function.  */
       type = TREE_OPERAND (exp, 0);		/* pointer expression */
       type = TREE_TYPE (type);			/* pointer type */
       type = TREE_TYPE (type);			/* function type */
 
-      attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
-      if (attr)
-        regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
-
-      if (regparm >= 3)
+      if (ix86_function_regparm (type, NULL) >= 3)
 	{
 	  /* ??? Need to count the actual number of registers to be used,
 	     not the possible number of registers.  Fix later.  */
@@ -1637,9 +1632,9 @@ ix86_handle_regparm_attribute (tree *node, tree name, tree args,
 	}
 
       if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node)))
-    {
-      error ("fastcall and regparm attributes are not compatible");
-    }
+	{
+	  error ("fastcall and regparm attributes are not compatible");
+	}
     }
 
   return NULL_TREE;
@@ -1670,18 +1665,49 @@ ix86_comp_type_attributes (tree type1, tree type2)
   return 1;
 }
 
-/* Return the regparm value for a fuctio with the indicated TYPE.  */
+/* Return the regparm value for a fuctio with the indicated TYPE and DECL.
+   DECL may be NULL when calling function indirectly
+   or considerling a libcall.  */
 
 static int
-ix86_fntype_regparm (tree type)
+ix86_function_regparm (tree type, tree decl)
 {
   tree attr;
+  int regparm = ix86_regparm;
+  bool user_convention = false;
 
-  attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
-  if (attr)
-    return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
-  else
-    return ix86_regparm;
+  if (!TARGET_64BIT)
+    {
+      attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (type));
+      if (attr)
+	{
+	  regparm = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
+	  user_convention = true;
+	}
+
+      if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
+	{
+	  regparm = 2;
+	  user_convention = true;
+	}
+
+      /* Use register calling convention for local functions when possible.  */
+      if (!TARGET_64BIT && !user_convention && decl
+	  && flag_unit_at_a_time)
+	{
+	  struct cgraph_local_info *i = cgraph_local_info (decl);
+	  if (i && i->local)
+	    {
+	      /* We can't use regparm(3) for nested functions as these use
+		 static chain pointer in third argument.  */
+	      if (DECL_CONTEXT (decl) && !DECL_NO_STATIC_CHAIN (decl))
+		regparm = 2;
+	      else
+		regparm = 3;
+	    }
+	}
+    }
+  return regparm;
 }
 
 /* Value is the number of bytes of arguments automatically
@@ -1722,10 +1748,10 @@ ix86_return_pops_args (tree fundecl, tree funtype, int size)
   }
 
   /* Lose any fake structure return argument if it is passed on the stack.  */
-  if (aggregate_value_p (TREE_TYPE (funtype))
+  if (aggregate_value_p (TREE_TYPE (funtype), fundecl)
       && !TARGET_64BIT)
     {
-      int nregs = ix86_fntype_regparm (funtype);
+      int nregs = ix86_function_regparm (funtype, fundecl);
 
       if (!nregs)
 	return GET_MODE_SIZE (Pmode);
@@ -1767,7 +1793,6 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Argument info to initialize */
 {
   static CUMULATIVE_ARGS zero_cum;
   tree param, next_param;
-  bool user_convention = false;
 
   if (TARGET_DEBUG_ARG)
     {
@@ -1786,18 +1811,11 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Argument info to initialize */
   *cum = zero_cum;
 
   /* Set up the number of registers to use for passing arguments.  */
-  cum->nregs = ix86_regparm;
+  if (fntype)
+    cum->nregs = ix86_function_regparm (fntype, fndecl);
+  else
+    cum->nregs = ix86_regparm;
   cum->sse_nregs = SSE_REGPARM_MAX;
-  if (fntype && !TARGET_64BIT)
-    {
-      tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype));
-
-      if (attr)
-	{
-	  cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr)));
-	  user_convention = true;
-	}
-    }
   cum->maybe_vaarg = false;
 
   /* Use ecx and edx registers if function has fastcall attribute */
@@ -1807,23 +1825,6 @@ init_cumulative_args (CUMULATIVE_ARGS *cum,  /* Argument info to initialize */
 	{
 	  cum->nregs = 2;
 	  cum->fastcall = 1;
-	  user_convention = true;
-	}
-    }
-
-  /* Use register calling convention for local functions when possible.  */
-  if (!TARGET_64BIT && !user_convention && fndecl
-      && flag_unit_at_a_time)
-    {
-      struct cgraph_local_info *i = cgraph_local_info (fndecl);
-      if (i && i->local)
-	{
-	  /* We can't use regparm(3) for nested functions as these use
-	     static chain pointer in third argument.  */
-	  if (DECL_CONTEXT (fndecl) && !DECL_NO_STATIC_CHAIN (fndecl))
-	    cum->nregs = 2;
-	  else
-	    cum->nregs = 3;
 	}
     }
 
@@ -2501,7 +2502,7 @@ function_arg (CUMULATIVE_ARGS *cum,	/* current arg information */
 
 	        /* ECX not EAX is the first allocated register.  */
 	        if (regno == 0)
-		      regno = 2;
+		  regno = 2;
 	      }
 	    ret = gen_rtx_REG (mode, regno);
 	  }
@@ -2610,8 +2611,8 @@ contains_128bit_aligned_vector_p (tree type)
   return false;
 }
 
-/* Gives the alignment boundary, in bits, of an argument with the specified mode
-   and type.   */
+/* Gives the alignment boundary, in bits, of an argument with the
+   specified mode and type.  */
 
 int
 ix86_function_arg_boundary (enum machine_mode mode, tree type)
@@ -2642,8 +2643,6 @@ ix86_function_arg_boundary (enum machine_mode mode, tree type)
 	  if (!contains_128bit_aligned_vector_p (type))
 	    align = PARM_BOUNDARY;
 	}
-      if (align != PARM_BOUNDARY && !TARGET_SSE)
-	abort();
     }
   if (align > 128)
     align = 128;
@@ -2692,29 +2691,59 @@ ix86_function_value (tree valtype)
 int
 ix86_return_in_memory (tree type)
 {
-  int needed_intregs, needed_sseregs;
+  int needed_intregs, needed_sseregs, size;
+  enum machine_mode mode = TYPE_MODE (type);
+
   if (TARGET_64BIT)
+    return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs);
+
+  if (mode == BLKmode)
+    return 1;
+
+  size = int_size_in_bytes (type);
+
+  if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8)
+    return 0;
+
+  if (VECTOR_MODE_P (mode) || mode == TImode)
     {
-      return !examine_argument (TYPE_MODE (type), type, 1,
-				&needed_intregs, &needed_sseregs);
-    }
-  else
-    {
-      if (TYPE_MODE (type) == BLKmode)
-	return 1;
-      else if (MS_AGGREGATE_RETURN
-	       && AGGREGATE_TYPE_P (type)
-	       && int_size_in_bytes(type) <= 8)
+      /* User-created vectors small enough to fit in EAX.  */
+      if (size < 8)
 	return 0;
-      else if ((VECTOR_MODE_P (TYPE_MODE (type))
-	        && int_size_in_bytes (type) == 8)
-	       || (int_size_in_bytes (type) > 12
-		   && TYPE_MODE (type) != TImode
-		   && TYPE_MODE (type) != TFmode
-		   && !VECTOR_MODE_P (TYPE_MODE (type))))
+
+      /* MMX/3dNow values are returned on the stack, since we've
+	 got to EMMS/FEMMS before returning.  */
+      if (size == 8)
 	return 1;
-      return 0;
+
+      /* SSE values are returned in XMM0.  */
+      /* ??? Except when it doesn't exist?  We have a choice of
+	 either (1) being abi incompatible with a -march switch,
+	 or (2) generating an error here.  Given no good solution,
+	 I think the safest thing is one warning.  The user won't
+	 be able to use -Werror, but...  */
+      if (size == 16)
+	{
+	  static bool warned;
+
+	  if (TARGET_SSE)
+	    return 0;
+
+	  if (!warned)
+	    {
+	      warned = true;
+	      warning ("SSE vector return without SSE enabled "
+		       "changes the ABI");
+	    }
+	  return 1;
+	}
     }
+
+  if (mode == TFmode)
+    return 0;
+  if (size > 12)
+    return 1;
+  return 0;
 }
 
 /* Define how to find the value returned by a library function
@@ -2747,10 +2776,14 @@ ix86_libcall_value (enum machine_mode mode)
 static int
 ix86_value_regno (enum machine_mode mode)
 {
+  /* Floating point return values in %st(0).  */
   if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_FLOAT_RETURNS_IN_80387)
     return FIRST_FLOAT_REG;
-  if (mode == TImode || VECTOR_MODE_P (mode))
+  /* 16-byte vector modes in %xmm0.  See ix86_return_in_memory for where
+     we prevent this case when sse is not available.  */
+  if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16))
     return FIRST_SSE_REG;
+  /* Everything else in %eax.  */
   return 0;
 }
 
@@ -3344,7 +3377,7 @@ x86_64_zext_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 int
 const_int_1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
-  return (GET_CODE (op) == CONST_INT && INTVAL (op) == 1);
+  return op == const1_rtx;
 }
 
 /* Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
@@ -3412,7 +3445,12 @@ pic_symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
   op = XEXP (op, 0);
   if (TARGET_64BIT)
     {
-      if (GET_CODE (XEXP (op, 0)) == UNSPEC)
+      if (GET_CODE (op) == UNSPEC
+	  && XINT (op, 1) == UNSPEC_GOTPCREL)
+	return 1;
+      if (GET_CODE (op) == PLUS
+	  && GET_CODE (XEXP (op, 0)) == UNSPEC
+	  && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL)
 	return 1;
     }
   else
@@ -3592,6 +3630,32 @@ const248_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 	  && (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8));
 }
 
+int
+const_0_to_3_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 4);
+}
+
+int
+const_0_to_7_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 8);
+}
+
+int
+const_0_to_15_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 16);
+}
+
+int
+const_0_to_255_operand (register rtx op,
+			enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256);
+}
+
+
 /* True if this is a constant appropriate for an increment or decrement.  */
 
 int
@@ -5658,15 +5722,23 @@ legitimate_pic_address_disp_p (register rtx disp)
       if (GET_CODE (disp) == LABEL_REF)
 	return 1;
       if (GET_CODE (disp) == CONST
-	  && GET_CODE (XEXP (disp, 0)) == PLUS
-	  && ((GET_CODE (XEXP (XEXP (disp, 0), 0)) == SYMBOL_REF
-	       && ix86_cmodel == CM_SMALL_PIC
-	       && SYMBOL_REF_LOCAL_P (XEXP (XEXP (disp, 0), 0)))
-	      || GET_CODE (XEXP (XEXP (disp, 0), 0)) == LABEL_REF)
-	  && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT
-	  && INTVAL (XEXP (XEXP (disp, 0), 1)) < 16*1024*1024
-	  && INTVAL (XEXP (XEXP (disp, 0), 1)) >= -16*1024*1024)
-	return 1;
+	  && GET_CODE (XEXP (disp, 0)) == PLUS)
+	{
+	  rtx op0 = XEXP (XEXP (disp, 0), 0);
+	  rtx op1 = XEXP (XEXP (disp, 0), 1);
+
+	  /* TLS references should always be enclosed in UNSPEC.  */
+	  if (tls_symbolic_operand (op0, GET_MODE (op0)))
+	    return 0;
+	  if (((GET_CODE (op0) == SYMBOL_REF
+		&& ix86_cmodel == CM_SMALL_PIC
+		&& SYMBOL_REF_LOCAL_P (op0))
+	       || GET_CODE (op0) == LABEL_REF)
+	      && GET_CODE (op1) == CONST_INT
+	      && INTVAL (op1) < 16*1024*1024
+	      && INTVAL (op1) >= -16*1024*1024)
+	    return 1;
+	}
     }
   if (GET_CODE (disp) != CONST)
     return 0;
@@ -5703,7 +5775,7 @@ legitimate_pic_address_disp_p (register rtx disp)
         if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF)
           {
             const char *sym_name = XSTR (XEXP (disp, 1), 0);
-            if (strstr (sym_name, "$pb") != 0)
+            if (! strcmp (sym_name, "<pic base>"))
               return 1;
           }
     }
@@ -6948,8 +7020,8 @@ get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
    C -- print opcode suffix for set/cmov insn.
    c -- like C, but print reversed condition
    F,f -- likewise, but for floating-point.
-   O -- if CMOV_SUN_AS_SYNTAX, expand to "w.", "l." or "q.", otherwise
-        nothing
+   O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
+        otherwise nothing
    R -- print the prefix for register names.
    z -- print the opcode suffix for the size of the current operand.
    * -- print a star (in certain assembler syntax)
@@ -7150,7 +7222,7 @@ print_operand (FILE *file, rtx x, int code)
 	    }
 	  return;
 	case 'O':
-#ifdef CMOV_SUN_AS_SYNTAX
+#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
 	  if (ASSEMBLER_DIALECT == ASM_ATT)
 	    {
 	      switch (GET_MODE (x))
@@ -7170,7 +7242,7 @@ print_operand (FILE *file, rtx x, int code)
 	  put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
 	  return;
 	case 'F':
-#ifdef CMOV_SUN_AS_SYNTAX
+#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
 	  if (ASSEMBLER_DIALECT == ASM_ATT)
 	    putc ('.', file);
 #endif
@@ -7189,7 +7261,7 @@ print_operand (FILE *file, rtx x, int code)
 	  put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 0, file);
 	  return;
 	case 'f':
-#ifdef CMOV_SUN_AS_SYNTAX
+#ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
 	  if (ASSEMBLER_DIALECT == ASM_ATT)
 	    putc ('.', file);
 #endif
@@ -8015,8 +8087,11 @@ ix86_output_addr_diff_elt (FILE *file, int value, int rel)
     fprintf (file, "%s%s%d@GOTOFF\n", ASM_LONG, LPREFIX, value);
 #if TARGET_MACHO
   else if (TARGET_MACHO)
-    fprintf (file, "%s%s%d-%s\n", ASM_LONG, LPREFIX, value,
-	     machopic_function_base_name () + 1);
+    {
+      fprintf (file, "%s%s%d-", ASM_LONG, LPREFIX, value);
+      machopic_output_function_base_name (file);
+      fprintf(file, "\n");
+    }
 #endif
   else
     asm_fprintf (file, "%s%U%s+[.-%s%d]\n",
@@ -9394,25 +9469,32 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop)
 	}
       break;
 
-    /* Convert a>0 into (unsigned)a<0x7fffffff.  */
+    /* Convert a>=0 into (unsigned)a<0x80000000.  */
     case LT:
     case GE:
       if (mode == DImode || op1 != const0_rtx)
 	return false;
-      op1 = gen_int_mode (~(1 << (GET_MODE_BITSIZE (mode) - 1)), mode);
+      op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
       code = (code == LT ? GEU : LTU);
       break;
     case LE:
     case GT:
       if (mode == DImode || op1 != constm1_rtx)
 	return false;
-      op1 = gen_int_mode (~(1 << (GET_MODE_BITSIZE (mode) - 1)), mode);
+      op1 = gen_int_mode (1 << (GET_MODE_BITSIZE (mode) - 1), mode);
       code = (code == LE ? GEU : LTU);
       break;
 
     default:
       return false;
     }
+  /* Swapping operands may cause constant to appear as first operand.  */
+  if (!nonimmediate_operand (op0, VOIDmode))
+    {
+      if (no_new_pseudos)
+	return false;
+      op0 = force_reg (mode, op0);
+    }
   ix86_compare_op0 = op0;
   ix86_compare_op1 = op1;
   *pop = ix86_expand_compare (code, NULL, NULL);
@@ -11572,10 +11654,15 @@ memory_address_length (rtx addr)
   disp = parts.disp;
   len = 0;
 
+  /* Rule of thumb:
+       - esp as the base always wants an index,
+       - ebp as the base always wants a displacement.  */
+
   /* Register Indirect.  */
   if (base && !index && !disp)
     {
-      /* Special cases: ebp and esp need the two-byte modrm form.  */
+      /* esp (for its index) and ebp (for its displacement) need
+	 the two-byte modrm form.  */
       if (addr == stack_pointer_rtx
 	  || addr == arg_pointer_rtx
 	  || addr == frame_pointer_rtx
@@ -11599,9 +11686,16 @@ memory_address_length (rtx addr)
 	  else
 	    len = 4;
 	}
+      /* ebp always wants a displacement.  */
+      else if (base == hard_frame_pointer_rtx)
+        len = 1;
 
-      /* An index requires the two-byte modrm form.  */
-      if (index)
+      /* An index requires the two-byte modrm form...  */
+      if (index
+	  /* ...like esp, which always wants an index.  */
+	  || base == stack_pointer_rtx
+	  || base == arg_pointer_rtx
+	  || base == frame_pointer_rtx)
 	len += 1;
     }
 
@@ -13488,7 +13582,8 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
 
   /* In case the insn wants input operands in modes different from
      the result, abort.  */
-  if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1)
+  if ((GET_MODE (op0) != mode0 && GET_MODE (op0) != VOIDmode)
+      || (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode))
     abort ();
 
   if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
@@ -13753,8 +13848,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 	op0 = copy_to_mode_reg (mode0, op0);
       if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
 	{
-	  /* @@@ better error message */
-	  error ("selector must be an immediate");
+	  error ("selector must be an integer constant in the range 0..%i",
+		  fcode == IX86_BUILTIN_PEXTRW ? 3:7);
 	  return gen_reg_rtx (tmode);
 	}
       if (target == 0
@@ -13789,8 +13884,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
 	op1 = copy_to_mode_reg (mode1, op1);
       if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
 	{
-	  /* @@@ better error message */
-	  error ("selector must be an immediate");
+	  error ("selector must be an integer constant in the range 0..%i",
+		  fcode == IX86_BUILTIN_PINSRW ? 15:255);
 	  return const0_rtx;
 	}
       if (target == 0
@@ -15067,11 +15162,11 @@ x86_this_parameter (tree function)
 
   if (TARGET_64BIT)
     {
-      int n = aggregate_value_p (TREE_TYPE (type)) != 0;
+      int n = aggregate_value_p (TREE_TYPE (type), type) != 0;
       return gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
     }
 
-  if (ix86_fntype_regparm (type) > 0)
+  if (ix86_function_regparm (type, function) > 0)
     {
       tree parm;
 
@@ -15081,12 +15176,17 @@ x86_this_parameter (tree function)
       for (; parm; parm = TREE_CHAIN (parm))
 	if (TREE_VALUE (parm) == void_type_node)
 	  break;
-      /* If not, the this parameter is in %eax.  */
+      /* If not, the this parameter is in the first argument.  */
       if (parm)
-	return gen_rtx_REG (SImode, 0);
+	{
+	  int regno = 0;
+	  if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type)))
+	    regno = 2;
+	  return gen_rtx_REG (SImode, 0);
+	}
     }
 
-  if (aggregate_value_p (TREE_TYPE (type)))
+  if (aggregate_value_p (TREE_TYPE (type), type))
     return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
   else
     return gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
@@ -15104,7 +15204,7 @@ x86_can_output_mi_thunk (tree thunk ATTRIBUTE_UNUSED,
     return true;
 
   /* For 32-bit, everything's fine if we have one free register.  */
-  if (ix86_fntype_regparm (TREE_TYPE (function)) < 3)
+  if (ix86_function_regparm (TREE_TYPE (function), function) < 3)
     return true;
 
   /* Need a free register for vcall_offset.  */
@@ -15175,7 +15275,13 @@ x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
       if (TARGET_64BIT)
 	tmp = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 2 /* R10 */);
       else
-	tmp = gen_rtx_REG (SImode, 2 /* ECX */);
+	{
+	  int tmp_regno = 2 /* ECX */;
+	  if (lookup_attribute ("fastcall",
+	      TYPE_ATTRIBUTES (TREE_TYPE (function))))
+	    tmp_regno = 0 /* EAX */;
+	  tmp = gen_rtx_REG (SImode, tmp_regno);
+	}
 
       xops[0] = gen_rtx_MEM (Pmode, this_reg);
       xops[1] = tmp;
@@ -15515,17 +15621,22 @@ x86_extended_reg_mentioned_p (rtx insn)
   return for_each_rtx (&PATTERN (insn), extended_reg_mentioned_1, NULL);
 }
 
-/* Generate an unsigned DImode to FP conversion.  This is the same code
+/* Generate an unsigned DImode/SImode to FP conversion.  This is the same code
    optabs would emit if we didn't have TFmode patterns.  */
 
 void
 x86_emit_floatuns (rtx operands[2])
 {
   rtx neglab, donelab, i0, i1, f0, in, out;
-  enum machine_mode mode;
+  enum machine_mode mode, inmode;
+
+  inmode = GET_MODE (operands[1]);
+  if (inmode != SImode
+      && inmode != DImode)
+    abort ();
 
   out = operands[0];
-  in = force_reg (DImode, operands[1]);
+  in = force_reg (inmode, operands[1]);
   mode = GET_MODE (out);
   neglab = gen_label_rtx ();
   donelab = gen_label_rtx ();
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 343cfd17472..718c52530e2 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1135,7 +1135,7 @@ do {									\
 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)			\
   (CC_REGNO_P (REGNO) ? VOIDmode					\
    : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode			\
-   : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS))	\
+   : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false)\
    : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode		\
    : (MODE) == QImode && (REGNO) >= 4 && !TARGET_64BIT ? SImode 	\
    : (MODE))
@@ -3018,6 +3018,10 @@ do {						\
   {"const0_operand", {CONST_INT, CONST_DOUBLE}},			\
   {"const1_operand", {CONST_INT}},					\
   {"const248_operand", {CONST_INT}},					\
+  {"const_0_to_3_operand", {CONST_INT}},				\
+  {"const_0_to_7_operand", {CONST_INT}},				\
+  {"const_0_to_15_operand", {CONST_INT}},				\
+  {"const_0_to_255_operand", {CONST_INT}},				\
   {"incdec_operand", {CONST_INT}},					\
   {"mmx_reg_operand", {REG}},						\
   {"reg_no_sp_operand", {SUBREG, REG}},					\
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 32da30a19c9..9ee1d7d6c50 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -351,7 +351,7 @@
 	   (if_then_else (match_operand 1 "constant_call_address_operand" "")
 	     (const_string "none")
 	     (const_string "load"))
-	 (and (eq_attr "type" "alu1,negnot")
+	 (and (eq_attr "type" "alu1,negnot,ishift1")
 	      (match_operand 1 "memory_operand" ""))
 	   (const_string "both")
 	 (and (match_operand 0 "memory_operand" "")
@@ -362,7 +362,7 @@
 	 (match_operand 1 "memory_operand" "")
 	   (const_string "load")
 	 (and (eq_attr "type"
-		 "!alu1,negnot,
+		 "!alu1,negnot,ishift1,
 		   imov,imovx,icmp,test,
 		   fmov,fcmp,fsgn,
 		   sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,
@@ -1166,8 +1166,8 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operand:SI 1 "immediate_operand" "i"))
    (clobber (reg:CC 17))]
-  "reload_completed && GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) == -1
+  "reload_completed
+   && operands[1] == constm1_rtx
    && (TARGET_PENTIUM || optimize_size)"
 {
   operands[1] = constm1_rtx;
@@ -1930,8 +1930,7 @@
    (clobber (reg:CC 17))]
   "TARGET_64BIT && (TARGET_PENTIUM || optimize_size)
    && reload_completed
-   && GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) == -1"
+   && operands[1] == constm1_rtx"
 {
   operands[1] = constm1_rtx;
   return "or{q}\t{%1, %0|%0, %1}";
@@ -3279,22 +3278,56 @@
   ")
 
 (define_insn "zero_extendsidi2_32"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o")
-	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r")))
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,m,m")))
    (clobber (reg:CC 17))]
-  "!TARGET_64BIT"
-  "#"
-  [(set_attr "mode" "SI")])
+  "!TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
+  "@
+   #
+   #
+   #
+   movd\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}"
+  [(set_attr "mode" "SI,SI,SI,DI,TI")
+   (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
+
+(define_insn "*zero_extendsidi2_32_1"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?*o,!?y,!?Y")
+	(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,rm,r,rm,rm")))
+   (clobber (reg:CC 17))]
+  "!TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
+  "@
+   #
+   #
+   #
+   movd\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}"
+  [(set_attr "mode" "SI,SI,SI,DI,TI")
+   (set_attr "type" "multi,multi,multi,mmxmov,ssemov")])
 
 (define_insn "zero_extendsidi2_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
-     (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0")))]
-  "TARGET_64BIT"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!?Y")
+     (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,m,m")))]
+  "TARGET_64BIT && !TARGET_INTER_UNIT_MOVES"
   "@
    mov\t{%k1, %k0|%k0, %k1}
-   #"
-  [(set_attr "type" "imovx,imov")
-   (set_attr "mode" "SI,DI")])
+   #
+   movd\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}"
+  [(set_attr "type" "imovx,imov,mmxmov,ssemov")
+   (set_attr "mode" "SI,DI,DI,TI")])
+
+(define_insn "*zero_extendsidi2_rex64_1"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,!?y,!*?")
+     (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "rm,0,rm,rm")))]
+  "TARGET_64BIT && TARGET_INTER_UNIT_MOVES"
+  "@
+   mov\t{%k1, %k0|%k0, %k1}
+   #
+   movd\t{%1, %0|%0, %1}
+   movd\t{%1, %0|%0, %1}"
+  [(set_attr "type" "imovx,imov,mmxmov,ssemov")
+   (set_attr "mode" "SI,DI,SI,SI")])
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -3316,7 +3349,8 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
    (clobber (reg:CC 17))]
-  "!TARGET_64BIT && reload_completed"
+  "!TARGET_64BIT && reload_completed
+   && !SSE_REG_P (operands[0]) && !MMX_REG_P (operands[0])"
   [(set (match_dup 3) (match_dup 1))
    (set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
@@ -14416,7 +14450,7 @@
 (define_insn_and_split "*ffs_no_cmove"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r") 
 	(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
-   (clobber (match_scratch:SI 2 "=&r"))
+   (clobber (match_scratch:SI 2 "=&q"))
    (clobber (reg:CC 17))]
   ""
   "#"
@@ -21229,7 +21263,7 @@
         (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0")
 			(vec_duplicate:V4HI
 			 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "rm")))
-			(match_operand:SI 3 "immediate_operand" "i")))]
+			(match_operand:SI 3 "const_0_to_15_operand" "N")))]
   "TARGET_SSE || TARGET_3DNOW_A"
   "pinsrw\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "mmxcvt")
@@ -21239,7 +21273,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
         (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
 				       (parallel
-					[(match_operand:SI 2 "immediate_operand" "i")]))))]
+					[(match_operand:SI 2 "const_0_to_3_operand" "N")]))))]
   "TARGET_SSE || TARGET_3DNOW_A"
   "pextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "mmxcvt")
@@ -22925,7 +22959,7 @@
 			(vec_duplicate:V8HI
 			 (truncate:HI
 			   (match_operand:SI 2 "nonimmediate_operand" "rm")))
-			(match_operand:SI 3 "immediate_operand" "i")))]
+			(match_operand:SI 3 "const_0_to_255_operand" "N")))]
   "TARGET_SSE2"
   "pinsrw\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecvt")
@@ -22936,7 +22970,7 @@
         (zero_extend:SI
 	  (vec_select:HI (match_operand:V8HI 1 "register_operand" "x")
 			 (parallel
-			  [(match_operand:SI 2 "immediate_operand" "i")]))))]
+			  [(match_operand:SI 2 "const_0_to_7_operand" "N")]))))]
   "TARGET_SSE2"
   "pextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
index 98a25a95eaf..c199fb3ce8f 100644
--- a/gcc/config/i386/linux.h
+++ b/gcc/config/i386/linux.h
@@ -21,8 +21,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define LINUX_DEFAULT_ELF
-
 /* Output at beginning of assembler file.  */
 /* The .file command should always begin the output.  */
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
@@ -115,15 +113,6 @@ Boston, MA 02111-1307, USA.  */
 
 #undef	LINK_SPEC
 #ifdef USE_GNULIBC_1
-#ifndef LINUX_DEFAULT_ELF
-#define LINK_SPEC "-m elf_i386 %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-	%{rdynamic:-export-dynamic} \
-	%{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \
-	%{!rpath:-rpath /lib/elf/}} %{static:-static}}}"
-#else
 #define LINK_SPEC "-m elf_i386 %{shared:-shared} \
   %{!shared: \
     %{!ibcs: \
@@ -131,7 +120,6 @@ Boston, MA 02111-1307, USA.  */
 	%{rdynamic:-export-dynamic} \
 	%{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \
 	%{static:-static}}}"
-#endif
 #else
 #define LINK_SPEC "-m elf_i386 %{shared:-shared} \
   %{!shared: \
diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
index 582a22bacd4..ea329803322 100644
--- a/gcc/config/i386/linux64.h
+++ b/gcc/config/i386/linux64.h
@@ -19,8 +19,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define LINUX_DEFAULT_ELF
-
 #define TARGET_VERSION fprintf (stderr, " (x86-64 Linux/ELF)");
 
 #define TARGET_OS_CPP_BUILTINS()				\
diff --git a/gcc/config/i386/nto.h b/gcc/config/i386/nto.h
new file mode 100644
index 00000000000..db60ad6ab08
--- /dev/null
+++ b/gcc/config/i386/nto.h
@@ -0,0 +1,99 @@
+/* Definitions for Intel 386 running QNX/Neutrino.
+   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#undef  DEFAULT_PCC_STRUCT_RETURN
+#define DEFAULT_PCC_STRUCT_RETURN 1
+
+#undef TARGET_VERSION
+#define TARGET_VERSION	fprintf (stderr, " (QNX/Neutrino/i386 ELF)");
+
+#undef TARGET_OS_CPP_BUILTINS
+#define TARGET_OS_CPP_BUILTINS()		\
+  do						\
+    {						\
+        builtin_define_std ("__X86__");		\
+        builtin_define_std ("__QNXNTO__");	\
+        builtin_define_std ("__QNX__");		\
+        builtin_define_std ("__ELF__");		\
+        builtin_define_std ("__LITTLEENDIAN__");\
+        builtin_assert ("system=qnx");		\
+        builtin_assert ("system=qnxnto");	\
+        builtin_assert ("system=nto");		\
+        builtin_assert ("system=unix");		\
+        if (flag_pic)				\
+          {					\
+            builtin_define ("__PIC__");		\
+            builtin_define ("__pic__");		\
+          }					\
+    }						\
+  while (0)
+
+#undef THREAD_MODEL_SPEC
+#define THREAD_MODEL_SPEC "posix"
+
+#ifdef CROSS_COMPILE
+#define SYSROOT_SUFFIX_SPEC "x86"
+#endif
+
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC \
+"%{!shared: \
+  %{!symbolic: \
+    %{pg:mcrt1.o%s} \
+    %{!pg:%{p:mcrt1.o%s} \
+    %{!p:crt1.o%s}}}} \
+crti.o%s \
+%{fexceptions: crtbegin.o%s} \
+%{!fexceptions: %R/lib/crtbegin.o}"
+
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC \
+  "crtend.o%s crtn.o%s"
+
+#undef LINK_SPEC
+#define LINK_SPEC \
+  "%{h*} %{v:-V} \
+   %{b} \
+   %{static:-dn -Bstatic} \
+   %{shared:-G -dy -z text} \
+   %{symbolic:-Bsymbolic -G -dy -z text} \
+   %{G:-G} \
+   %{YP,*} \
+   %{!YP,*:%{p:-Y P,%R/lib} \
+    %{!p:-Y P,%R/lib}} \
+   %{Qy:} %{!Qn:-Qy} \
+   -m i386nto \
+   %{!shared: --dynamic-linker /usr/lib/ldqnx.so.2}"
+
+
+#undef SIZE_TYPE
+#define SIZE_TYPE "unsigned int"
+
+#undef PTRDIFF_TYPE
+#define PTRDIFF_TYPE "int"
+
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "long unsigned int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE BITS_PER_WORD
+
+#define NO_IMPLICIT_EXTERN_C 1
+
diff --git a/gcc/config/i386/scodbx.h b/gcc/config/i386/scodbx.h
deleted file mode 100644
index 7da93053256..00000000000
--- a/gcc/config/i386/scodbx.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Definitions for Intel 386 running SCO Unix System V,
-   using dbx-in-coff encapsulation.
-   Copyright (C) 1992, 1995, 1996, 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#include "i386/svr3dbx.h"
-
-/* Overridden defines for SCO systems from sco.h. */
-
-/* By default, target has a 80387, uses IEEE compatible arithmetic,
-   and returns float values in the 387, ie,
-   (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387)
-
-   SCO's software emulation of a 387 fails to handle the `fucomp'
-   opcode.  fucomp is only used when generating IEEE compliant code.
-   So don't make TARGET_IEEE_FP default for SCO. */
-
-#undef TARGET_SUBTARGET_DEFAULT
-#define TARGET_SUBTARGET_DEFAULT (MASK_80387 | MASK_FLOAT_RETURNS)
-
-/* Use crt1.o as a startup file and crtn.o as a closing file.  */
-
-#undef STARTFILE_SPEC
-#define STARTFILE_SPEC \
-  "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\
-   %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}"
-
-/* Library spec, including SCO international language support. */
-
-#undef LIB_SPEC
-#define LIB_SPEC \
- "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc"
-
-/* Specify predefined symbols in preprocessor.  */
-
-#undef CPP_PREDEFINES
-#define CPP_PREDEFINES "-Dunix -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem=svr3"
-
-#undef CPP_SPEC
-#define CPP_SPEC "%(cpp_cpu) %{scointl:-DM_INTERNAT}"
-
-/* This spec is used for telling cpp whether char is signed or not.  */
-
-#undef SIGNED_CHAR_SPEC
-#if DEFAULT_SIGNED_CHAR
-#define SIGNED_CHAR_SPEC \
- "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#else
-#define SIGNED_CHAR_SPEC \
- "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}"
-#endif
-
-/* caller has to pop the extra argument passed to functions that return
-   structures. */
-
-#undef RETURN_POPS_ARGS
-#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE)   \
-  ((FUNDECL) && TREE_CODE (FUNDECL) == IDENTIFIER_NODE ? 0	\
-   : (TARGET_RTD						\
-      && (TYPE_ARG_TYPES (FUNTYPE) == 0				\
-	  || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE)))	\
-	      == void_type_node))) ? (SIZE)			\
-   : 0)
-/* On other 386 systems, the last line looks like this:
-   : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0)  */
-
-/* Handle #pragma pack. */
-#define HANDLE_SYSV_PRAGMA
diff --git a/gcc/config/i386/sol2.h b/gcc/config/i386/sol2.h
index fb5a184d65b..9089a1dce6c 100644
--- a/gcc/config/i386/sol2.h
+++ b/gcc/config/i386/sol2.h
@@ -1,5 +1,5 @@
 /* Target definitions for GNU compiler for Intel 80386 running Solaris 2
-   Copyright (C) 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright (C) 1993, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Fred Fish (fnf@cygnus.com).
 
@@ -20,8 +20,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define CMOV_SUN_AS_SYNTAX 1
-
 /* The Solaris 2.0 x86 linker botches alignment of code sections.
    It tries to align to a 16 byte boundary by padding with 0x00000090
    ints, rather than 0x90 bytes (nop).  This generates trash in the
diff --git a/gcc/config/i386/t-nto b/gcc/config/i386/t-nto
new file mode 100644
index 00000000000..314c2609f8b
--- /dev/null
+++ b/gcc/config/i386/t-nto
@@ -0,0 +1,7 @@
+# Don't run fixproto
+STMP_FIXPROTO =
+
+CRTSTUFF_T_CFLAGS = -fno-omit-frame-pointer -fPIC
+TARGET_LIBGCC2_CFLAGS = -fPIC -fexceptions
+
+EXTRA_PARTS = crtbegin.o
diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c
index 2c1e47fdd56..f376bc4c710 100644
--- a/gcc/config/i386/winnt.c
+++ b/gcc/config/i386/winnt.c
@@ -16,10 +16,9 @@ FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 for more details.
 
 You should have received a copy of the GNU General Public License
-
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
+along with GCC; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
 
 #include "config.h"
 #include "system.h"
@@ -47,13 +46,13 @@ Boston, MA 02111-1307, USA.  */
    multiple times.
 */
 
-static tree associated_type PARAMS ((tree));
-const char * gen_stdcall_suffix PARAMS ((tree));
-const char * gen_fastcall_suffix PARAMS ((tree));
-int i386_pe_dllexport_p PARAMS ((tree));
-int i386_pe_dllimport_p PARAMS ((tree));
-void i386_pe_mark_dllexport PARAMS ((tree));
-void i386_pe_mark_dllimport PARAMS ((tree));
+static tree associated_type (tree);
+const char * gen_stdcall_suffix (tree);
+const char * gen_fastcall_suffix (tree);
+int i386_pe_dllexport_p (tree);
+int i386_pe_dllimport_p (tree);
+void i386_pe_mark_dllexport (tree);
+void i386_pe_mark_dllimport (tree);
 
 /* This is we how mark internal identifiers with dllimport or dllexport
    attributes.  */
@@ -67,12 +66,8 @@ void i386_pe_mark_dllimport PARAMS ((tree));
 /* Handle a "dllimport" or "dllexport" attribute;
    arguments as in struct attribute_spec.handler.  */
 tree
-ix86_handle_dll_attribute (pnode, name, args, flags, no_add_attrs)
-     tree * pnode;
-     tree name;
-     tree args;
-     int flags;
-     bool *no_add_attrs;
+ix86_handle_dll_attribute (tree * pnode, tree name, tree args, int flags,
+			   bool *no_add_attrs)
 {
   tree node = *pnode;
 
@@ -106,7 +101,7 @@ ix86_handle_dll_attribute (pnode, name, args, flags, no_add_attrs)
       if (TREE_CODE (node) == FUNCTION_DECL  && DECL_INITIAL (node)
           && !DECL_INLINE (node))
 	{
-	  error_with_decl (node, "function `%s' definition is marked dllimport.");
+	  error ("%Jfunction `%D' definition is marked dllimport.", node, node);
 	  *no_add_attrs = true;
 	}
 
@@ -114,27 +109,28 @@ ix86_handle_dll_attribute (pnode, name, args, flags, no_add_attrs)
 	{
 	  if (DECL_INITIAL (node))
 	    {
-	      error_with_decl (node,"variable `%s' definition is marked dllimport.");
+	      error ("%Jvariable `%D' definition is marked dllimport.",
+		     node, node);
 	      *no_add_attrs = true;
 	    }
 
 	  /* `extern' needn't be specified with dllimport.
 	     Specify `extern' now and hope for the best.  Sigh.  */
-	  DECL_EXTERNAL (node) = 1; 
+	  DECL_EXTERNAL (node) = 1;
 	  /* Also, implicitly give dllimport'd variables declared within
 	     a function global scope, unless declared static.  */
 	  if (current_function_decl != NULL_TREE && !TREE_STATIC (node))
-  	    TREE_PUBLIC (node) = 1;
+	    TREE_PUBLIC (node) = 1;
 	}
     }
 
   /*  Report error if symbol is not accessible at global scope. */
   if (!TREE_PUBLIC (node)
       && (TREE_CODE (node) == VAR_DECL
-	  || TREE_CODE (node) == FUNCTION_DECL)) 
+	  || TREE_CODE (node) == FUNCTION_DECL))
     {
-      error_with_decl (node, "external linkage required for symbol '%s' because of '%s' attribute.",
-		       IDENTIFIER_POINTER (name));
+      error ("%Jexternal linkage required for symbol '%D' because of "
+	     "'%s' attribute.", node, node, IDENTIFIER_POINTER (name));
       *no_add_attrs = true;
     }
 
@@ -144,12 +140,9 @@ ix86_handle_dll_attribute (pnode, name, args, flags, no_add_attrs)
 /* Handle a "shared" attribute;
    arguments as in struct attribute_spec.handler.  */
 tree
-ix86_handle_shared_attribute (node, name, args, flags, no_add_attrs)
-     tree *node;
-     tree name;
-     tree args ATTRIBUTE_UNUSED;
-     int flags ATTRIBUTE_UNUSED;
-     bool *no_add_attrs;
+ix86_handle_shared_attribute (tree *node, tree name,
+			      tree args ATTRIBUTE_UNUSED,
+			      int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
 {
   if (TREE_CODE (*node) != VAR_DECL)
     {
@@ -165,8 +158,7 @@ ix86_handle_shared_attribute (node, name, args, flags, no_add_attrs)
    imported or exported.  */
 
 static tree
-associated_type (decl)
-     tree decl;
+associated_type (tree decl)
 {
   tree t = NULL_TREE;
 
@@ -174,9 +166,11 @@ associated_type (decl)
      to the containing class.  So we look at the 'this' arg.  */
   if (TREE_CODE (TREE_TYPE (decl)) == METHOD_TYPE)
     {
-      /* Artificial methods are not affected by the import/export status of
-	 their class unless they are virtual.  */
-      if (! DECL_ARTIFICIAL (decl) || DECL_VINDEX (decl))
+      /* Artificial methods are not affected by the import/export status
+	 of their class unless they are COMDAT.  Implicit copy ctor's and
+	 dtor's are not affected by class status but virtual and
+	 non-virtual thunks are.  */
+      if (!DECL_ARTIFICIAL (decl) || DECL_COMDAT (decl))
 	t = TREE_TYPE (TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (decl))));
     }
   else if (DECL_CONTEXT (decl)
@@ -189,8 +183,7 @@ associated_type (decl)
 /* Return nonzero if DECL is a dllexport'd object.  */
 
 int
-i386_pe_dllexport_p (decl)
-     tree decl;
+i386_pe_dllexport_p (tree decl)
 {
   tree exp;
 
@@ -216,8 +209,7 @@ i386_pe_dllexport_p (decl)
 /* Return nonzero if DECL is a dllimport'd object.  */
 
 int
-i386_pe_dllimport_p (decl)
-     tree decl;
+i386_pe_dllimport_p (tree decl)
 {
   tree imp;
   int context_imp = 0;
@@ -252,17 +244,19 @@ i386_pe_dllimport_p (decl)
 	{
 	   /* Don't warn about artificial methods.  */
 	  if (!DECL_ARTIFICIAL (decl))
-	    warning_with_decl (decl,"function '%s' is defined after prior declaration as dllimport: attribute ignored.");
+	    warning ("%Jfunction '%D' is defined after prior declaration "
+		     "as dllimport: attribute ignored", decl, decl);
 	  return 0;
 	}
 
       /* We ignore the dllimport attribute for inline member functions.
 	 This differs from MSVC behavior which treats it like GNUC
-     	 'extern inline' extension.   */
+	 'extern inline' extension.   */
       else if (TREE_CODE (decl) == FUNCTION_DECL && DECL_INLINE (decl))
         {
 	  if (extra_warnings)
-	    warning_with_decl (decl, "inline function '%s' is declared as dllimport: attribute ignored.");
+	    warning ("%Jinline function '%D' is declared as dllimport: "
+		     "attribute ignored.", decl, decl);
 	  return 0;
 	}
 
@@ -273,15 +267,18 @@ i386_pe_dllimport_p (decl)
 	       && !DECL_EXTERNAL (decl) && context_imp)
 	{
 	  if (!DECL_VIRTUAL_P (decl))
-	      error_with_decl (decl, "definition of static data member '%s' of dllimport'd class.");
-           return 0;
+            error ("%Jdefinition of static data member '%D' of "
+		   "dllimport'd class.", decl, decl);
+	  return 0;
 	}
 
       /* Since we can't treat a pointer to a dllimport'd symbol as a
 	 constant address, we turn off the attribute on C++ virtual
-	 methods to allow creation of vtables using thunks.  */
+	 methods to allow creation of vtables using thunks.  Don't mark
+	 artificial methods either (in associated_type, only COMDAT
+	 artificial method get import status from class context).  */
       else if (TREE_CODE (TREE_TYPE (decl)) == METHOD_TYPE
-	       && (DECL_VIRTUAL_P (decl)))
+	       && (DECL_VIRTUAL_P (decl) || DECL_ARTIFICIAL (decl)))
 	return 0;
 
       return 1;
@@ -293,8 +290,7 @@ i386_pe_dllimport_p (decl)
 /* Return nonzero if SYMBOL is marked as being dllexport'd.  */
 
 int
-i386_pe_dllexport_name_p (symbol)
-     const char *symbol;
+i386_pe_dllexport_name_p (const char *symbol)
 {
   return (strncmp (DLL_EXPORT_PREFIX, symbol,
 		   strlen (DLL_EXPORT_PREFIX)) == 0);
@@ -303,8 +299,7 @@ i386_pe_dllexport_name_p (symbol)
 /* Return nonzero if SYMBOL is marked as being dllimport'd.  */
 
 int
-i386_pe_dllimport_name_p (symbol)
-     const char *symbol;
+i386_pe_dllimport_name_p (const char *symbol)
 {
   return (strncmp (DLL_IMPORT_PREFIX, symbol,
 		   strlen (DLL_IMPORT_PREFIX)) == 0);
@@ -314,8 +309,7 @@ i386_pe_dllimport_name_p (symbol)
    Note that we override the previous setting (eg: dllimport).  */
 
 void
-i386_pe_mark_dllexport (decl)
-     tree decl;
+i386_pe_mark_dllexport (tree decl)
 {
   const char *oldname;
   char  *newname;
@@ -332,7 +326,8 @@ i386_pe_mark_dllexport (decl)
     abort ();
   if (i386_pe_dllimport_name_p (oldname))
     {
-      warning_with_decl (decl,"inconsistent dll linkage for '%s': dllexport assumed.");
+      warning ("%Jinconsistent dll linkage for '%D', dllexport assumed.",
+	       decl, decl);
      /* Remove DLL_IMPORT_PREFIX.  */
       oldname += strlen (DLL_IMPORT_PREFIX);
       DECL_NON_ADDR_CONST_P (decl) = 0;
@@ -356,8 +351,7 @@ i386_pe_mark_dllexport (decl)
 /* Mark a DECL as being dllimport'd.  */
 
 void
-i386_pe_mark_dllimport (decl)
-     tree decl;
+i386_pe_mark_dllimport (tree decl)
 {
   const char *oldname;
   char  *newname;
@@ -383,7 +377,8 @@ i386_pe_mark_dllimport (decl)
       /* Already done, but do a sanity check to prevent assembler errors. */
       if (!DECL_EXTERNAL (decl) || !TREE_PUBLIC (decl))
 	{
-	  error_with_decl (decl, "failure in redeclaration of '%s': dllimport'd symbol lacks external linkage.");
+	  error ("%Jfailure in redeclaration of '%D': dllimport'd "
+		 "symbol lacks external linkage.", decl, decl);
 	  abort();
 	}
       return;
@@ -407,13 +402,12 @@ i386_pe_mark_dllimport (decl)
   DECL_NON_ADDR_CONST_P (decl) = 1;
 }
 
-/* Return string which is the former assembler name modified with a 
+/* Return string which is the former assembler name modified with a
    prefix consisting of FASTCALL_PREFIX and a suffix consisting of an
    atsign (@) followed by the number of bytes of arguments.  */
 
 const char *
-gen_fastcall_suffix (decl)
-  tree decl;
+gen_fastcall_suffix (tree decl)
 {
   int total = 0;
 
@@ -426,7 +420,10 @@ gen_fastcall_suffix (decl)
       {
 	tree formal_type = TYPE_ARG_TYPES (TREE_TYPE (decl));
 
-	while (TREE_VALUE (formal_type) != void_type_node)
+	/* Quit if we hit an incomplete type.  Error is reported
+	   by convert_arguments in c-typeck.c or cp/typeck.c.  */
+	while (TREE_VALUE (formal_type) != void_type_node
+	       && COMPLETE_TYPE_P (TREE_VALUE (formal_type)))	
 	  {
 	    int parm_size
 	      = TREE_INT_CST_LOW (TYPE_SIZE (TREE_VALUE (formal_type)));
@@ -439,19 +436,18 @@ gen_fastcall_suffix (decl)
 	  }
       }
 
-  /* Assume max of 8 base 10 digits in the suffix.  */ 
+  /* Assume max of 8 base 10 digits in the suffix.  */
   newsym = xmalloc (1 + strlen (asmname) + 1 + 8 + 1);
   sprintf (newsym, "%c%s@%d", FASTCALL_PREFIX, asmname, total/BITS_PER_UNIT);
   return IDENTIFIER_POINTER (get_identifier (newsym));
 }
 
-/* Return string which is the former assembler name modified with a 
-   suffix consisting of an atsign (@) followed by the number of bytes of 
+/* Return string which is the former assembler name modified with a
+   suffix consisting of an atsign (@) followed by the number of bytes of
    arguments */
 
 const char *
-gen_stdcall_suffix (decl)
-  tree decl;
+gen_stdcall_suffix (tree decl)
 {
   int total = 0;
   /* ??? This probably should use XSTR (XEXP (DECL_RTL (decl), 0), 0) instead
@@ -460,12 +456,15 @@ gen_stdcall_suffix (decl)
   char *newsym;
 
   if (TYPE_ARG_TYPES (TREE_TYPE (decl)))
-    if (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (decl)))) 
+    if (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (decl))))
         == void_type_node)
       {
 	tree formal_type = TYPE_ARG_TYPES (TREE_TYPE (decl));
 
-	while (TREE_VALUE (formal_type) != void_type_node)
+	/* Quit if we hit an incomplete type.  Error is reported
+	   by convert_arguments in c-typeck.c or cp/typeck.c.  */
+	while (TREE_VALUE (formal_type) != void_type_node
+	       && COMPLETE_TYPE_P (TREE_VALUE (formal_type)))	
 	  {
 	    int parm_size
 	      = TREE_INT_CST_LOW (TYPE_SIZE (TREE_VALUE (formal_type)));
@@ -478,17 +477,14 @@ gen_stdcall_suffix (decl)
 	  }
       }
 
-  /* Assume max of 8 base 10 digits in the suffix.  */ 
+  /* Assume max of 8 base 10 digits in the suffix.  */
   newsym = xmalloc (strlen (asmname) + 1 + 8 + 1);
   sprintf (newsym, "%s@%d", asmname, total/BITS_PER_UNIT);
   return IDENTIFIER_POINTER (get_identifier (newsym));
 }
 
 void
-i386_pe_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+i386_pe_encode_section_info (tree decl, rtx rtl, int first)
 {
   default_encode_section_info (decl, rtl, first);
 
@@ -496,7 +492,7 @@ i386_pe_encode_section_info (decl, rtl, first)
     {
       if (lookup_attribute ("stdcall",
 			    TYPE_ATTRIBUTES (TREE_TYPE (decl))))
-        XEXP (DECL_RTL (decl), 0) = 
+        XEXP (DECL_RTL (decl), 0) =
 	  gen_rtx (SYMBOL_REF, Pmode, gen_stdcall_suffix (decl));
       else if (lookup_attribute ("fastcall",
 				 TYPE_ATTRIBUTES (TREE_TYPE (decl))))
@@ -525,13 +521,17 @@ i386_pe_encode_section_info (decl, rtl, first)
 	   && i386_pe_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
     {
       const char *oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
+
       /* Remove DLL_IMPORT_PREFIX.  */
       tree idp = get_identifier (oldname + strlen (DLL_IMPORT_PREFIX));
       rtx newrtl = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (idp));
 
-      warning_with_decl (decl, "'%s' %s after being referenced with dllimport linkage.",
-	         	 (DECL_INITIAL (decl) || !DECL_EXTERNAL (decl))
-			 ? "defined locally" : "redeclared without dllimport attribute");
+      if (DECL_INITIAL (decl) || !DECL_EXTERNAL (decl))
+	warning ("%J'%D' defined locally after being "
+		 "referenced with dllimport linkage", decl, decl);
+      else
+	warning ("%J'%D' redeclared without dllimport attribute "
+		 "after being referenced with dllimport linkage", decl, decl);
 
       XEXP (DECL_RTL (decl), 0) = newrtl;
 
@@ -546,8 +546,7 @@ i386_pe_encode_section_info (decl, rtl, first)
    prefix if it exists.  */
 
 const char *
-i386_pe_strip_name_encoding (str)
-     const char *str;
+i386_pe_strip_name_encoding (const char *str)
 {
   if (strncmp (str, DLL_IMPORT_PREFIX, strlen (DLL_IMPORT_PREFIX))
       == 0)
@@ -563,12 +562,11 @@ i386_pe_strip_name_encoding (str)
 /* Also strip the stdcall suffix.  */
 
 const char *
-i386_pe_strip_name_encoding_full (str)
-     const char *str;
+i386_pe_strip_name_encoding_full (const char *str)
 {
   const char *p;
   const char *name = i386_pe_strip_name_encoding (str);
- 
+
   p = strchr (name, '@');
   if (p)
     return ggc_alloc_string (name, p - name);
@@ -586,16 +584,16 @@ void i386_pe_output_labelref (stream, name)
 {
   if (strncmp (name, DLL_IMPORT_PREFIX, strlen (DLL_IMPORT_PREFIX))
       == 0)
-    /* A dll import */ 
+    /* A dll import */
     {
       if (name[strlen (DLL_IMPORT_PREFIX)] == FASTCALL_PREFIX)
-      /* A dllimport fastcall symbol.  */   
+      /* A dllimport fastcall symbol.  */
         {
           fprintf (stream, "__imp_%s",
                    i386_pe_strip_name_encoding (name));
         }
       else
-      /* A dllimport non-fastcall symbol.  */ 
+      /* A dllimport non-fastcall symbol.  */
         {
           fprintf (stream, "__imp__%s",
                    i386_pe_strip_name_encoding (name));
@@ -603,7 +601,7 @@ void i386_pe_output_labelref (stream, name)
     }
   else if ((name[0] == FASTCALL_PREFIX)
            || (strncmp (name, DLL_EXPORT_PREFIX, strlen (DLL_EXPORT_PREFIX)
-	       == 0 
+	       == 0
 	       && name[strlen (DLL_EXPORT_PREFIX)] == FASTCALL_PREFIX)))
     /* A fastcall symbol.  */
     {
@@ -619,9 +617,7 @@ void i386_pe_output_labelref (stream, name)
 }
 
 void
-i386_pe_unique_section (decl, reloc)
-     tree decl;
-     int reloc;
+i386_pe_unique_section (tree decl, int reloc)
 {
   int len;
   const char *name, *prefix;
@@ -633,7 +629,7 @@ i386_pe_unique_section (decl, reloc)
   /* The object is put in, for example, section .text$foo.
      The linker will then ultimately place them in .text
      (everything from the $ on is stripped). Don't put
-     read-only data in .rdata section to avoid a PE linker 
+     read-only data in .rdata section to avoid a PE linker
      bug when .rdata$* grouped sections are used in code
      without a .rdata section.  */
   if (TREE_CODE (decl) == FUNCTION_DECL)
@@ -667,10 +663,7 @@ i386_pe_unique_section (decl, reloc)
 #define SECTION_PE_SHARED	SECTION_MACH_DEP
 
 unsigned int
-i386_pe_section_type_flags (decl, name, reloc)
-     tree decl;
-     const char *name;
-     int reloc;
+i386_pe_section_type_flags (tree decl, const char *name, int reloc)
 {
   static htab_t htab;
   unsigned int flags;
@@ -708,16 +701,14 @@ i386_pe_section_type_flags (decl, name, reloc)
   else
     {
       if (decl && **slot != flags)
-	error_with_decl (decl, "%s causes a section type conflict");
+	error ("%J'%D' causes a section type conflict", decl, decl);
     }
 
   return flags;
 }
 
 void
-i386_pe_asm_named_section (name, flags)
-     const char *name;
-     unsigned int flags;
+i386_pe_asm_named_section (const char *name, unsigned int flags)
 {
   char flagchars[8], *f = flagchars;
 
@@ -754,10 +745,7 @@ i386_pe_asm_named_section (name, flags)
    visible.  */
 
 void
-i386_pe_declare_function_type (file, name, public)
-     FILE *file;
-     const char *name;
-     int public;
+i386_pe_declare_function_type (FILE *file, const char *name, int public)
 {
   fprintf (file, "\t.def\t");
   assemble_name (file, name);
@@ -783,8 +771,7 @@ static struct extern_list *extern_head;
    for it then.  */
 
 void
-i386_pe_record_external_function (name)
-     const char *name;
+i386_pe_record_external_function (const char *name)
 {
   struct extern_list *p;
 
@@ -808,13 +795,11 @@ static struct export_list *export_head;
 /* Assemble an export symbol entry.  We need to keep a list of
    these, so that we can output the export list at the end of the
    assembly.  We used to output these export symbols in each function,
-   but that causes problems with GNU ld when the sections are 
+   but that causes problems with GNU ld when the sections are
    linkonce.  */
 
 void
-i386_pe_record_exported_symbol (name, is_data)
-     const char *name;
-     int is_data;
+i386_pe_record_exported_symbol (const char *name, int is_data)
 {
   struct export_list *p;
 
@@ -830,7 +815,7 @@ i386_pe_record_exported_symbol (name, is_data)
    output the .drectve section.  */
 
 void
-i386_pe_file_end ()
+i386_pe_file_end (void)
 {
   struct extern_list *p;
 
@@ -847,7 +832,7 @@ i386_pe_file_end ()
 	{
 	  TREE_ASM_WRITTEN (decl) = 1;
 	  i386_pe_declare_function_type (asm_out_file, p->name,
-			  		 TREE_PUBLIC (decl));
+					 TREE_PUBLIC (decl));
 	}
     }
 
diff --git a/gcc/config/i386/xm-dgux.h b/gcc/config/i386/xm-dgux.h
deleted file mode 100644
index 881c5c7be9d..00000000000
--- a/gcc/config/i386/xm-dgux.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/* Configuration for GCC for Intel i386 running DG/ux */
-
-/* looks just like sysv4 for now */
-#include "xm-svr4.h"
diff --git a/gcc/config/i386/xm-mingw32.h b/gcc/config/i386/xm-mingw32.h
index 9984bf93cfb..81995e05d43 100644
--- a/gcc/config/i386/xm-mingw32.h
+++ b/gcc/config/i386/xm-mingw32.h
@@ -1,25 +1,29 @@
 /* Configuration for GNU C-compiler for hosting on Windows32.
    using GNU tools and the Windows32 API Library.
-   Copyright (C) 1997, 1998, 1999, 2001 Free Software Foundation, Inc.
+   Copyright (C) 1997, 1998, 1999, 2001, 2002, 2003 Free Software
+   Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
 
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
+along with GCC; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
 
 #define HOST_EXECUTABLE_SUFFIX ".exe"
 
 #undef PATH_SEPARATOR
 #define PATH_SEPARATOR ';'
+
+/* This is the name of the null device on windows. */ 
+#define HOST_BIT_BUCKET "nul"
diff --git a/gcc/config/i386/xm-sun.h b/gcc/config/i386/xm-sun.h
deleted file mode 100644
index 6c0f0a25630..00000000000
--- a/gcc/config/i386/xm-sun.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Configuration for GNU C-compiler for Intel 80386 running SunOS 4.0.
-   Copyright (C) 1988, 1997 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define USG
diff --git a/gcc/config/i386/xm-sysv3.h b/gcc/config/i386/xm-sysv3.h
deleted file mode 100644
index 9a655443ff5..00000000000
--- a/gcc/config/i386/xm-sysv3.h
+++ /dev/null
@@ -1,3 +0,0 @@
-/* Configuration for GCC for Intel i386 running System V Release 3.  */
-
-#include "xm-svr3.h"
diff --git a/gcc/config/i386/xm-vsta.h b/gcc/config/i386/xm-vsta.h
deleted file mode 100644
index 53943eaf7da..00000000000
--- a/gcc/config/i386/xm-vsta.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Use semicolons to separate elements of a path.  */
-#define PATH_SEPARATOR ';'
-
-#define TARGET_OS_CPP_BUILTINS()		\
-  do						\
-    {						\
-	builtin_define_std ("unix");		\
-    }						\
-  while (0)
-
-#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}"
diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c
index cb44ee3efe7..26443223ddc 100644
--- a/gcc/config/i960/i960.c
+++ b/gcc/config/i960/i960.c
@@ -1086,7 +1086,7 @@ i960_function_name_declare (file, name, fndecl)
       
   /* See if caller passes in an address to return value.  */
 
-  if (aggregate_value_p (DECL_RESULT (fndecl)))
+  if (aggregate_value_p (DECL_RESULT (fndecl), fndecl))
     {
       tail_call_ok = 0;
       leaf_proc_ok = 0;
diff --git a/gcc/config/ia64/hpux.h b/gcc/config/ia64/hpux.h
index 40094840719..b2b854b3fcb 100644
--- a/gcc/config/ia64/hpux.h
+++ b/gcc/config/ia64/hpux.h
@@ -26,9 +26,6 @@ Boston, MA 02111-1307, USA.  */
 #define TARGET_VERSION fprintf (stderr, " (IA-64) HP-UX");
 
 /* Target OS builtins.  */
-/* -D__fpreg=long double is needed to compensate for
-   the lack of __fpreg which is a primitive type in
-   HP C but does not exist in GNU C.  */
 #define TARGET_OS_CPP_BUILTINS()			\
 do {							\
 	builtin_assert("system=hpux");			\
@@ -39,9 +36,6 @@ do {							\
 	builtin_define("__IA64__");			\
 	builtin_define("_LONGLONG");			\
 	builtin_define("_UINT128_T");			\
-	builtin_define("__fpreg=long double");		\
-	builtin_define("__float80=long double");	\
-	builtin_define("__float128=long double");	\
 	if (c_dialect_cxx () || !flag_iso)		\
 	  {						\
 	    builtin_define("_HPUX_SOURCE");		\
@@ -49,6 +43,13 @@ do {							\
 	  }						\
 } while (0)
 
+#undef CPP_SPEC
+#define CPP_SPEC \
+  "%{mt|pthread:-D_REENTRANT -D_THREAD_SAFE -D_POSIX_C_SOURCE=199506L}"
+/* aCC defines also -DRWSTD_MULTI_THREAD, -DRW_MULTI_THREAD.  These
+   affect only aCC's C++ library (Rogue Wave-derived) which we do not
+   use, and they violate the user's name space.  */
+
 #undef  ASM_EXTRA_SPEC
 #define ASM_EXTRA_SPEC "%{milp32:-milp32} %{mlp64:-mlp64}"
 
@@ -68,6 +69,7 @@ do {							\
 #undef  LIB_SPEC
 #define LIB_SPEC \
   "%{!shared: \
+     %{mt|pthread:-lpthread} \
      %{p:%{!mlp64:-L/usr/lib/hpux32/libp} \
 	 %{mlp64:-L/usr/lib/hpux64/libp} -lprof} \
      %{pg:%{!mlp64:-L/usr/lib/hpux32/libp} \
@@ -134,6 +136,10 @@ do {								\
 #undef TARGET_HPUX_LD
 #define TARGET_HPUX_LD	1
 
+/* The HPUX dynamic linker objects to weak symbols with no
+   definitions, so do not use them in gthr-posix.h.  */
+#define GTHREAD_USE_WEAK 0
+
 /* Put out the needed function declarations at the end.  */
 
 #define TARGET_ASM_FILE_END ia64_hpux_file_end
@@ -144,6 +150,10 @@ do {								\
 #undef DTORS_SECTION_ASM_OP
 #define DTORS_SECTION_ASM_OP  "\t.section\t.fini_array,\t\"aw\",\"fini_array\""
 
+/* The init_array/fini_array technique does not permit the use of
+   initialization priorities.  */
+#define SUPPORTS_INIT_PRIORITY 0
+
 #undef READONLY_DATA_SECTION_ASM_OP
 #define READONLY_DATA_SECTION_ASM_OP "\t.section\t.rodata,\t\"a\",\t\"progbits\""
 
@@ -172,3 +182,8 @@ do {								\
 #define TARGET_ASM_SELECT_RTX_SECTION  ia64_rwreloc_select_rtx_section
 #undef  TARGET_SECTION_TYPE_FLAGS
 #define TARGET_SECTION_TYPE_FLAGS  ia64_rwreloc_section_type_flags
+
+/* ia64 HPUX has the float and long double forms of math functions.  */
+#undef TARGET_C99_FUNCTIONS
+#define TARGET_C99_FUNCTIONS  1
+
diff --git a/gcc/config/ia64/ia64-c.c b/gcc/config/ia64/ia64-c.c
index b95c21d4d9b..422fc865b2a 100644
--- a/gcc/config/ia64/ia64-c.c
+++ b/gcc/config/ia64/ia64-c.c
@@ -1,5 +1,5 @@
 /* Definitions of C specific functions for GNU compiler.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
    Contributed by Steve Ellcey <sje@cup.hp.com>
 
 This file is part of GCC.
@@ -30,11 +30,10 @@ Boston, MA 02111-1307, USA.  */
 #include "toplev.h"
 #include "tm_p.h"
 
-static void ia64_hpux_add_pragma_builtin PARAMS ((tree func));
+static void ia64_hpux_add_pragma_builtin (tree func);
 
 void
-ia64_hpux_handle_builtin_pragma (pfile)
-	cpp_reader *pfile ATTRIBUTE_UNUSED;
+ia64_hpux_handle_builtin_pragma (cpp_reader *pfile ATTRIBUTE_UNUSED)
 {
   /* #pragma builtin name, name, name */
 
@@ -173,8 +172,7 @@ static const c89_mathlib_names c89_mathlib_name_list [] =
 };
 
 static void
-ia64_hpux_add_pragma_builtin (func)
-	tree func;
+ia64_hpux_add_pragma_builtin (tree func)
 {
   size_t i;
 
diff --git a/gcc/config/ia64/ia64-protos.h b/gcc/config/ia64/ia64-protos.h
index 030c5ed667b..52dacb73e7a 100644
--- a/gcc/config/ia64/ia64-protos.h
+++ b/gcc/config/ia64/ia64-protos.h
@@ -1,5 +1,6 @@
 /* Definitions of target machine for GNU compiler for IA-64.
-   Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2002, 2003
+   Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -29,127 +30,125 @@ extern GTY(()) rtx ia64_compare_op1;
 
 extern int bundling_p;
 #ifdef RTX_CODE
-extern int ia64_st_address_bypass_p PARAMS((rtx, rtx));
-extern int ia64_ld_address_bypass_p PARAMS((rtx, rtx));
-extern int ia64_produce_address_p PARAMS((rtx));
-extern int call_operand PARAMS((rtx, enum machine_mode));
-extern int sdata_symbolic_operand PARAMS((rtx, enum machine_mode));
-extern int got_symbolic_operand PARAMS((rtx, enum machine_mode));
-extern int symbolic_operand PARAMS((rtx, enum machine_mode));
-extern int tls_symbolic_operand PARAMS((rtx, enum machine_mode));
-extern int function_operand PARAMS((rtx, enum machine_mode));
-extern int setjmp_operand PARAMS((rtx, enum machine_mode));
-extern int move_operand PARAMS((rtx, enum machine_mode));
-extern int gr_register_operand PARAMS((rtx, enum machine_mode));
-extern int fr_register_operand PARAMS((rtx, enum machine_mode));
-extern int grfr_register_operand PARAMS((rtx, enum machine_mode));
-extern int gr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
-extern int fr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
-extern int grfr_nonimmediate_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_0_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_5bit_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_6bit_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_8bit_operand PARAMS((rtx, enum machine_mode));
-extern int grfr_reg_or_8bit_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_8bit_adjusted_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_8bit_and_adjusted_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_14bit_operand PARAMS((rtx, enum machine_mode));
-extern int gr_reg_or_22bit_operand PARAMS((rtx, enum machine_mode));
-extern int shift_count_operand PARAMS((rtx, enum machine_mode));
-extern int shift_32bit_count_operand PARAMS((rtx, enum machine_mode));
-extern int shladd_operand PARAMS((rtx, enum machine_mode));
-extern int fetchadd_operand PARAMS((rtx, enum machine_mode));
-extern int fr_reg_or_fp01_operand PARAMS((rtx, enum machine_mode));
-extern int normal_comparison_operator PARAMS((rtx, enum machine_mode));
-extern int adjusted_comparison_operator PARAMS((rtx, enum machine_mode));
-extern int signed_inequality_operator PARAMS((rtx, enum machine_mode));
-extern int destination_operand PARAMS((rtx, enum machine_mode));
-extern int not_postinc_memory_operand PARAMS((rtx, enum machine_mode));
-extern int predicate_operator PARAMS((rtx, enum machine_mode));
-extern int ar_lc_reg_operand PARAMS((rtx, enum machine_mode));
-extern int ar_ccv_reg_operand PARAMS((rtx, enum machine_mode));
-extern int ar_pfs_reg_operand PARAMS((rtx, enum machine_mode));
-extern int general_tfmode_operand PARAMS((rtx, enum machine_mode));
-extern int destination_tfmode_operand PARAMS((rtx, enum machine_mode));
-extern int tfreg_or_fp01_operand PARAMS((rtx, enum machine_mode));
-extern int basereg_operand PARAMS((rtx, enum machine_mode));
-
-extern rtx ia64_expand_move PARAMS ((rtx, rtx));
-extern int ia64_move_ok PARAMS((rtx, rtx));
-extern int addp4_optimize_ok PARAMS((rtx, rtx));
-extern void ia64_emit_cond_move PARAMS((rtx, rtx, rtx));
-extern int ia64_depz_field_mask PARAMS((rtx, rtx));
-extern rtx ia64_split_timode PARAMS((rtx[], rtx, rtx));
-extern rtx spill_tfmode_operand PARAMS((rtx, int));
-extern rtx ia64_expand_compare PARAMS((enum rtx_code, enum machine_mode));
-extern void ia64_expand_call PARAMS((rtx, rtx, rtx, int));
-extern void ia64_split_call PARAMS((rtx, rtx, rtx, rtx, rtx, int, int));
-extern void ia64_reload_gp PARAMS((void));
-
-extern HOST_WIDE_INT ia64_initial_elimination_offset PARAMS((int, int));
-extern void ia64_expand_prologue PARAMS((void));
-extern void ia64_expand_epilogue PARAMS((int));
-
-extern int ia64_direct_return PARAMS((void));
-extern void ia64_expand_load_address PARAMS((rtx, rtx));
-extern int ia64_hard_regno_rename_ok PARAMS((int, int));
-
-extern void ia64_initialize_trampoline PARAMS((rtx, rtx, rtx));
-extern void ia64_print_operand_address PARAMS((FILE *, rtx));
-extern void ia64_print_operand PARAMS((FILE *, rtx, int));
-extern enum reg_class ia64_secondary_reload_class PARAMS((enum reg_class,
-							  enum machine_mode,
-							  rtx));
-extern void ia64_output_dwarf_dtprel PARAMS ((FILE*, int, rtx));
-extern void process_for_unwind_directive PARAMS ((FILE *, rtx));
-extern const char *get_bundle_name PARAMS ((int));
+extern int ia64_st_address_bypass_p (rtx, rtx);
+extern int ia64_ld_address_bypass_p (rtx, rtx);
+extern int ia64_produce_address_p (rtx);
+extern int call_operand (rtx, enum machine_mode);
+extern int sdata_symbolic_operand (rtx, enum machine_mode);
+extern int got_symbolic_operand (rtx, enum machine_mode);
+extern int symbolic_operand (rtx, enum machine_mode);
+extern int tls_symbolic_operand (rtx, enum machine_mode);
+extern int function_operand (rtx, enum machine_mode);
+extern int setjmp_operand (rtx, enum machine_mode);
+extern int move_operand (rtx, enum machine_mode);
+extern int gr_register_operand (rtx, enum machine_mode);
+extern int fr_register_operand (rtx, enum machine_mode);
+extern int grfr_register_operand (rtx, enum machine_mode);
+extern int gr_nonimmediate_operand (rtx, enum machine_mode);
+extern int fr_nonimmediate_operand (rtx, enum machine_mode);
+extern int grfr_nonimmediate_operand (rtx, enum machine_mode);
+extern int gr_reg_or_0_operand (rtx, enum machine_mode);
+extern int gr_reg_or_5bit_operand (rtx, enum machine_mode);
+extern int gr_reg_or_6bit_operand (rtx, enum machine_mode);
+extern int gr_reg_or_8bit_operand (rtx, enum machine_mode);
+extern int grfr_reg_or_8bit_operand (rtx, enum machine_mode);
+extern int gr_reg_or_8bit_adjusted_operand (rtx, enum machine_mode);
+extern int gr_reg_or_8bit_and_adjusted_operand (rtx, enum machine_mode);
+extern int gr_reg_or_14bit_operand (rtx, enum machine_mode);
+extern int gr_reg_or_22bit_operand (rtx, enum machine_mode);
+extern int shift_count_operand (rtx, enum machine_mode);
+extern int shift_32bit_count_operand (rtx, enum machine_mode);
+extern int shladd_operand (rtx, enum machine_mode);
+extern int fetchadd_operand (rtx, enum machine_mode);
+extern int fr_reg_or_fp01_operand (rtx, enum machine_mode);
+extern int normal_comparison_operator (rtx, enum machine_mode);
+extern int adjusted_comparison_operator (rtx, enum machine_mode);
+extern int signed_inequality_operator (rtx, enum machine_mode);
+extern int destination_operand (rtx, enum machine_mode);
+extern int not_postinc_memory_operand (rtx, enum machine_mode);
+extern int predicate_operator (rtx, enum machine_mode);
+extern int ar_lc_reg_operand (rtx, enum machine_mode);
+extern int ar_ccv_reg_operand (rtx, enum machine_mode);
+extern int ar_pfs_reg_operand (rtx, enum machine_mode);
+extern int general_tfmode_operand (rtx, enum machine_mode);
+extern int destination_tfmode_operand (rtx, enum machine_mode);
+extern int tfreg_or_fp01_operand (rtx, enum machine_mode);
+extern int basereg_operand (rtx, enum machine_mode);
+
+extern rtx ia64_expand_move (rtx, rtx);
+extern int ia64_move_ok (rtx, rtx);
+extern int addp4_optimize_ok (rtx, rtx);
+extern void ia64_emit_cond_move (rtx, rtx, rtx);
+extern int ia64_depz_field_mask (rtx, rtx);
+extern rtx ia64_split_timode (rtx[], rtx, rtx);
+extern rtx spill_tfmode_operand (rtx, int);
+extern rtx ia64_expand_compare (enum rtx_code, enum machine_mode);
+extern void ia64_expand_call (rtx, rtx, rtx, int);
+extern void ia64_split_call (rtx, rtx, rtx, rtx, rtx, int, int);
+extern void ia64_reload_gp (void);
+
+extern HOST_WIDE_INT ia64_initial_elimination_offset (int, int);
+extern void ia64_expand_prologue (void);
+extern void ia64_expand_epilogue (int);
+
+extern int ia64_direct_return (void);
+extern void ia64_expand_load_address (rtx, rtx);
+extern int ia64_hard_regno_rename_ok (int, int);
+
+extern void ia64_initialize_trampoline (rtx, rtx, rtx);
+extern void ia64_print_operand_address (FILE *, rtx);
+extern void ia64_print_operand (FILE *, rtx, int);
+extern enum reg_class ia64_secondary_reload_class (enum reg_class,
+						   enum machine_mode, rtx);
+extern void ia64_output_dwarf_dtprel (FILE*, int, rtx);
+extern void process_for_unwind_directive (FILE *, rtx);
+extern const char *get_bundle_name (int);
 #endif /* RTX_CODE */
 
 #ifdef TREE_CODE
 #ifdef RTX_CODE
-extern rtx ia64_function_arg PARAMS((CUMULATIVE_ARGS *, enum machine_mode,
-				     tree, int, int));
-extern rtx ia64_expand_builtin PARAMS((tree, rtx, rtx,
-				       enum machine_mode, int));
-extern rtx ia64_va_arg PARAMS((tree, tree));
-extern rtx ia64_function_value PARAMS((tree, tree));
+extern rtx ia64_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
+			      tree, int, int);
+extern rtx ia64_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+extern rtx ia64_va_arg (tree, tree);
+extern rtx ia64_function_value (tree, tree);
 #endif /* RTX_CODE */
 
-extern void ia64_setup_incoming_varargs PARAMS((CUMULATIVE_ARGS, int, tree,
-						int *, int));
-extern int ia64_function_arg_partial_nregs PARAMS((CUMULATIVE_ARGS *,
-						   enum machine_mode,
-						   tree, int));
-extern void ia64_function_arg_advance PARAMS((CUMULATIVE_ARGS *,
-					      enum machine_mode,
-					      tree, int));
-extern int ia64_function_arg_pass_by_reference PARAMS((CUMULATIVE_ARGS *,
-						       enum machine_mode,
-						       tree, int));
-extern int ia64_return_in_memory PARAMS((tree));
-extern void ia64_asm_output_external PARAMS((FILE *, tree, const char *));
+extern void ia64_setup_incoming_varargs (CUMULATIVE_ARGS, int, tree,
+					 int *, int);
+extern int ia64_function_arg_partial_nregs (CUMULATIVE_ARGS *,
+					    enum machine_mode, tree, int);
+extern void ia64_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
+				       tree, int);
+extern int ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS *,
+						enum machine_mode, tree, int);
+extern int ia64_return_in_memory (tree);
+extern void ia64_asm_output_external (FILE *, tree, const char *);
 #endif /* TREE_CODE */
 
-extern int ia64_register_move_cost PARAMS((enum machine_mode, enum reg_class,
-					   enum reg_class));
-extern int ia64_epilogue_uses PARAMS((int));
-extern int ia64_eh_uses PARAMS((int));
-extern void emit_safe_across_calls PARAMS((void));
-extern void ia64_init_builtins PARAMS((void));
-extern void ia64_override_options PARAMS((void));
-extern int ia64_dbx_register_number PARAMS((int));
+extern int ia64_register_move_cost (enum machine_mode, enum reg_class,
+				    enum reg_class);
+extern int ia64_epilogue_uses (int);
+extern int ia64_eh_uses (int);
+extern void emit_safe_across_calls (void);
+extern void ia64_init_builtins (void);
+extern void ia64_override_options (void);
+extern int ia64_dbx_register_number (int);
+
+extern rtx ia64_return_addr_rtx (HOST_WIDE_INT, rtx);
+extern void ia64_split_return_addr_rtx (rtx);
 
 #ifdef SDATA_SECTION_ASM_OP
-extern void sdata_section PARAMS ((void));
+extern void sdata_section (void);
 #endif
 
 #ifdef SBSS_SECTION_ASM_OP
-extern void sbss_section PARAMS ((void));
+extern void sbss_section (void);
 #endif
 
 #ifdef ARGS_SIZE_RTX
 /* expr.h defines ARGS_SIZE_RTX and `enum direction'.  */
-extern enum direction ia64_hpux_function_arg_padding PARAMS ((enum machine_mode, tree));
+extern enum direction ia64_hpux_function_arg_padding (enum machine_mode, tree);
 #endif /* ARGS_SIZE_RTX */
 
-extern void ia64_hpux_handle_builtin_pragma PARAMS ((struct cpp_reader *));
+extern void ia64_hpux_handle_builtin_pragma (struct cpp_reader *);
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 444e882457d..f82981b07bf 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1,7 +1,7 @@
 /* Definitions of target machine for GNU compiler.
    Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Contributed by James E. Wilson <wilson@cygnus.com> and
-   		  David Mosberger <davidm@hpl.hp.com>.
+		  David Mosberger <davidm@hpl.hp.com>.
 
 This file is part of GCC.
 
@@ -136,7 +136,7 @@ struct ia64_frame_info
   HOST_WIDE_INT spill_size;	/* size of the gr/br/fr spill area.  */
   HOST_WIDE_INT extra_spill_size;  /* size of spill area for others.  */
   HARD_REG_SET mask;		/* mask of saved registers.  */
-  unsigned int gr_used_mask;	/* mask of registers in use as gr spill 
+  unsigned int gr_used_mask;	/* mask of registers in use as gr spill
 				   registers or long-term scratches.  */
   int n_spilled;		/* number of spilled registers.  */
   int reg_fp;			/* register for fp.  */
@@ -158,117 +158,113 @@ struct ia64_frame_info
 /* Current frame information calculated by ia64_compute_frame_size.  */
 static struct ia64_frame_info current_frame_info;
 
-static int ia64_use_dfa_pipeline_interface PARAMS ((void));
-static int ia64_first_cycle_multipass_dfa_lookahead PARAMS ((void));
-static void ia64_dependencies_evaluation_hook PARAMS ((rtx, rtx));
-static void ia64_init_dfa_pre_cycle_insn PARAMS ((void));
-static rtx ia64_dfa_pre_cycle_insn PARAMS ((void));
-static int ia64_first_cycle_multipass_dfa_lookahead_guard PARAMS ((rtx));
-static int ia64_dfa_new_cycle PARAMS ((FILE *, int, rtx, int, int, int *));
-static rtx gen_tls_get_addr PARAMS ((void));
-static rtx gen_thread_pointer PARAMS ((void));
-static rtx ia64_expand_tls_address PARAMS ((enum tls_model, rtx, rtx));
-static int find_gr_spill PARAMS ((int));
-static int next_scratch_gr_reg PARAMS ((void));
-static void mark_reg_gr_used_mask PARAMS ((rtx, void *));
-static void ia64_compute_frame_size PARAMS ((HOST_WIDE_INT));
-static void setup_spill_pointers PARAMS ((int, rtx, HOST_WIDE_INT));
-static void finish_spill_pointers PARAMS ((void));
-static rtx spill_restore_mem PARAMS ((rtx, HOST_WIDE_INT));
-static void do_spill PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx));
-static void do_restore PARAMS ((rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT));
-static rtx gen_movdi_x PARAMS ((rtx, rtx, rtx));
-static rtx gen_fr_spill_x PARAMS ((rtx, rtx, rtx));
-static rtx gen_fr_restore_x PARAMS ((rtx, rtx, rtx));
-
-static enum machine_mode hfa_element_mode PARAMS ((tree, int));
-static bool ia64_function_ok_for_sibcall PARAMS ((tree, tree));
-static bool ia64_rtx_costs PARAMS ((rtx, int, int, int *));
-static void fix_range PARAMS ((const char *));
-static struct machine_function * ia64_init_machine_status PARAMS ((void));
-static void emit_insn_group_barriers PARAMS ((FILE *));
-static void emit_all_insn_group_barriers PARAMS ((FILE *));
-static void final_emit_insn_group_barriers PARAMS ((FILE *));
-static void emit_predicate_relation_info PARAMS ((void));
-static void ia64_reorg PARAMS ((void));
-static bool ia64_in_small_data_p PARAMS ((tree));
-static void process_epilogue PARAMS ((void));
-static int process_set PARAMS ((FILE *, rtx));
-
-static rtx ia64_expand_fetch_and_op PARAMS ((optab, enum machine_mode,
-					     tree, rtx));
-static rtx ia64_expand_op_and_fetch PARAMS ((optab, enum machine_mode,
-					     tree, rtx));
-static rtx ia64_expand_compare_and_swap PARAMS ((enum machine_mode,
-						 enum machine_mode,
-						 int, tree, rtx));
-static rtx ia64_expand_lock_test_and_set PARAMS ((enum machine_mode,
-						  tree, rtx));
-static rtx ia64_expand_lock_release PARAMS ((enum machine_mode, tree, rtx));
-static bool ia64_assemble_integer PARAMS ((rtx, unsigned int, int));
-static void ia64_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void ia64_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void ia64_output_function_end_prologue PARAMS ((FILE *));
-
-static int ia64_issue_rate PARAMS ((void));
-static int ia64_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static void ia64_sched_init PARAMS ((FILE *, int, int));
-static void ia64_sched_finish PARAMS ((FILE *, int));
-static int ia64_dfa_sched_reorder PARAMS ((FILE *, int, rtx *, int *,
-					   int, int));
-static int ia64_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
-static int ia64_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
-static int ia64_variable_issue PARAMS ((FILE *, int, rtx, int));
-
-static struct bundle_state *get_free_bundle_state PARAMS ((void));
-static void free_bundle_state PARAMS ((struct bundle_state *));
-static void initiate_bundle_states PARAMS ((void));
-static void finish_bundle_states PARAMS ((void));
-static unsigned bundle_state_hash PARAMS ((const void *));
-static int bundle_state_eq_p PARAMS ((const void *, const void *));
-static int insert_bundle_state PARAMS ((struct bundle_state *));
-static void initiate_bundle_state_table PARAMS ((void));
-static void finish_bundle_state_table PARAMS ((void));
-static int try_issue_nops PARAMS ((struct bundle_state *, int));
-static int try_issue_insn PARAMS ((struct bundle_state *, rtx));
-static void issue_nops_and_insn PARAMS ((struct bundle_state *, int,
-					 rtx, int, int));
-static int get_max_pos PARAMS ((state_t));
-static int get_template PARAMS ((state_t, int));
-
-static rtx get_next_important_insn PARAMS ((rtx, rtx));
-static void bundling PARAMS ((FILE *, int, rtx, rtx));
-
-static void ia64_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					  HOST_WIDE_INT, tree));
-static void ia64_file_start PARAMS ((void));
-
-static void ia64_select_rtx_section PARAMS ((enum machine_mode, rtx,
-					     unsigned HOST_WIDE_INT));
-static void ia64_rwreloc_select_section PARAMS ((tree, int,
-					         unsigned HOST_WIDE_INT))
+static int ia64_use_dfa_pipeline_interface (void);
+static int ia64_first_cycle_multipass_dfa_lookahead (void);
+static void ia64_dependencies_evaluation_hook (rtx, rtx);
+static void ia64_init_dfa_pre_cycle_insn (void);
+static rtx ia64_dfa_pre_cycle_insn (void);
+static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx);
+static int ia64_dfa_new_cycle (FILE *, int, rtx, int, int, int *);
+static rtx gen_tls_get_addr (void);
+static rtx gen_thread_pointer (void);
+static rtx ia64_expand_tls_address (enum tls_model, rtx, rtx);
+static int find_gr_spill (int);
+static int next_scratch_gr_reg (void);
+static void mark_reg_gr_used_mask (rtx, void *);
+static void ia64_compute_frame_size (HOST_WIDE_INT);
+static void setup_spill_pointers (int, rtx, HOST_WIDE_INT);
+static void finish_spill_pointers (void);
+static rtx spill_restore_mem (rtx, HOST_WIDE_INT);
+static void do_spill (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT, rtx);
+static void do_restore (rtx (*)(rtx, rtx, rtx), rtx, HOST_WIDE_INT);
+static rtx gen_movdi_x (rtx, rtx, rtx);
+static rtx gen_fr_spill_x (rtx, rtx, rtx);
+static rtx gen_fr_restore_x (rtx, rtx, rtx);
+
+static enum machine_mode hfa_element_mode (tree, int);
+static bool ia64_function_ok_for_sibcall (tree, tree);
+static bool ia64_rtx_costs (rtx, int, int, int *);
+static void fix_range (const char *);
+static struct machine_function * ia64_init_machine_status (void);
+static void emit_insn_group_barriers (FILE *);
+static void emit_all_insn_group_barriers (FILE *);
+static void final_emit_insn_group_barriers (FILE *);
+static void emit_predicate_relation_info (void);
+static void ia64_reorg (void);
+static bool ia64_in_small_data_p (tree);
+static void process_epilogue (void);
+static int process_set (FILE *, rtx);
+
+static rtx ia64_expand_fetch_and_op (optab, enum machine_mode, tree, rtx);
+static rtx ia64_expand_op_and_fetch (optab, enum machine_mode, tree, rtx);
+static rtx ia64_expand_compare_and_swap (enum machine_mode, enum machine_mode,
+					 int, tree, rtx);
+static rtx ia64_expand_lock_test_and_set (enum machine_mode, tree, rtx);
+static rtx ia64_expand_lock_release (enum machine_mode, tree, rtx);
+static bool ia64_assemble_integer (rtx, unsigned int, int);
+static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT);
+static void ia64_output_function_end_prologue (FILE *);
+
+static int ia64_issue_rate (void);
+static int ia64_adjust_cost (rtx, rtx, rtx, int);
+static void ia64_sched_init (FILE *, int, int);
+static void ia64_sched_finish (FILE *, int);
+static int ia64_dfa_sched_reorder (FILE *, int, rtx *, int *, int, int);
+static int ia64_sched_reorder (FILE *, int, rtx *, int *, int);
+static int ia64_sched_reorder2 (FILE *, int, rtx *, int *, int);
+static int ia64_variable_issue (FILE *, int, rtx, int);
+
+static struct bundle_state *get_free_bundle_state (void);
+static void free_bundle_state (struct bundle_state *);
+static void initiate_bundle_states (void);
+static void finish_bundle_states (void);
+static unsigned bundle_state_hash (const void *);
+static int bundle_state_eq_p (const void *, const void *);
+static int insert_bundle_state (struct bundle_state *);
+static void initiate_bundle_state_table (void);
+static void finish_bundle_state_table (void);
+static int try_issue_nops (struct bundle_state *, int);
+static int try_issue_insn (struct bundle_state *, rtx);
+static void issue_nops_and_insn (struct bundle_state *, int, rtx, int, int);
+static int get_max_pos (state_t);
+static int get_template (state_t, int);
+
+static rtx get_next_important_insn (rtx, rtx);
+static void bundling (FILE *, int, rtx, rtx);
+
+static void ia64_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+				  HOST_WIDE_INT, tree);
+static void ia64_file_start (void);
+
+static void ia64_select_rtx_section (enum machine_mode, rtx,
+				     unsigned HOST_WIDE_INT);
+static void ia64_rwreloc_select_section (tree, int, unsigned HOST_WIDE_INT)
      ATTRIBUTE_UNUSED;
-static void ia64_rwreloc_unique_section PARAMS ((tree, int))
+static void ia64_rwreloc_unique_section (tree, int)
      ATTRIBUTE_UNUSED;
-static void ia64_rwreloc_select_rtx_section PARAMS ((enum machine_mode, rtx,
-					             unsigned HOST_WIDE_INT))
+static void ia64_rwreloc_select_rtx_section (enum machine_mode, rtx,
+					     unsigned HOST_WIDE_INT)
      ATTRIBUTE_UNUSED;
-static unsigned int ia64_rwreloc_section_type_flags
-     PARAMS ((tree, const char *, int))
+static unsigned int ia64_rwreloc_section_type_flags (tree, const char *, int)
      ATTRIBUTE_UNUSED;
 
-static void ia64_hpux_add_extern_decl PARAMS ((const char *name))
+static void ia64_hpux_add_extern_decl (const char *name)
      ATTRIBUTE_UNUSED;
-static void ia64_hpux_file_end PARAMS ((void))
+static void ia64_hpux_file_end (void)
      ATTRIBUTE_UNUSED;
 
+static tree ia64_handle_model_attribute (tree *, tree, tree, int, bool *);
+static void ia64_encode_section_info (tree, rtx, int);
+
 
 /* Table of valid machine attributes.  */
 static const struct attribute_spec ia64_attribute_table[] =
 {
   /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
   { "syscall_linkage", 0, 0, false, true,  true,  NULL },
-  { NULL,              0, 0, false, false, false, NULL }
+  { "model",	       1, 1, true, false, false, ia64_handle_model_attribute },
+  { NULL,	       0, 0, false, false, false, NULL }
 };
 
 /* Initialize the GCC target structure.  */
@@ -368,14 +364,15 @@ static const struct attribute_spec ia64_attribute_table[] =
 #undef TARGET_MACHINE_DEPENDENT_REORG
 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
 
+#undef TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Return 1 if OP is a valid operand for the MEM of a CALL insn.  */
 
 int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+call_operand (rtx op, enum machine_mode mode)
 {
   if (mode != GET_MODE (op) && mode != VOIDmode)
     return 0;
@@ -387,9 +384,7 @@ call_operand (op, mode)
 /* Return 1 if OP refers to a symbol in the sdata section.  */
 
 int
-sdata_symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+sdata_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -413,12 +408,16 @@ sdata_symbolic_operand (op, mode)
   return 0;
 }
 
+int
+small_addr_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return SYMBOL_REF_SMALL_ADDR_P (op);
+}
+
 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load.  */
 
 int
-got_symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+got_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -449,6 +448,8 @@ got_symbolic_operand (op, mode)
       return (INTVAL (op) & 0x3fff) == 0;
 
     case SYMBOL_REF:
+      if (SYMBOL_REF_SMALL_ADDR_P (op))
+	return 0;
     case LABEL_REF:
       return 1;
 
@@ -461,9 +462,7 @@ got_symbolic_operand (op, mode)
 /* Return 1 if OP refers to a symbol.  */
 
 int
-symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -481,9 +480,7 @@ symbolic_operand (op, mode)
 /* Return tls_model if OP refers to a TLS symbol.  */
 
 int
-tls_symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != SYMBOL_REF)
     return 0;
@@ -494,9 +491,7 @@ tls_symbolic_operand (op, mode)
 /* Return 1 if OP refers to a function.  */
 
 int
-function_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+function_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (op))
     return 1;
@@ -509,9 +504,7 @@ function_operand (op, mode)
 /* ??? This is an unsatisfying solution.  Should rethink.  */
 
 int
-setjmp_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+setjmp_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   const char *name;
   int retval = 0;
@@ -557,9 +550,7 @@ setjmp_operand (op, mode)
 /* Return 1 if OP is a general operand, excluding tls symbolic operands.  */
 
 int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+move_operand (rtx op, enum machine_mode mode)
 {
   return general_operand (op, mode) && !tls_symbolic_operand (op, mode);
 }
@@ -567,9 +558,7 @@ move_operand (op, mode)
 /* Return 1 if OP is a register operand that is (or could be) a GR reg.  */
 
 int
-gr_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_register_operand (rtx op, enum machine_mode mode)
 {
   if (! register_operand (op, mode))
     return 0;
@@ -587,9 +576,7 @@ gr_register_operand (op, mode)
 /* Return 1 if OP is a register operand that is (or could be) an FR reg.  */
 
 int
-fr_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fr_register_operand (rtx op, enum machine_mode mode)
 {
   if (! register_operand (op, mode))
     return 0;
@@ -607,9 +594,7 @@ fr_register_operand (op, mode)
 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg.  */
 
 int
-grfr_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+grfr_register_operand (rtx op, enum machine_mode mode)
 {
   if (! register_operand (op, mode))
     return 0;
@@ -627,9 +612,7 @@ grfr_register_operand (op, mode)
 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg.  */
 
 int
-gr_nonimmediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_nonimmediate_operand (rtx op, enum machine_mode mode)
 {
   if (! nonimmediate_operand (op, mode))
     return 0;
@@ -647,9 +630,7 @@ gr_nonimmediate_operand (op, mode)
 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg.  */
 
 int
-fr_nonimmediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fr_nonimmediate_operand (rtx op, enum machine_mode mode)
 {
   if (! nonimmediate_operand (op, mode))
     return 0;
@@ -667,9 +648,7 @@ fr_nonimmediate_operand (op, mode)
 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg.  */
 
 int
-grfr_nonimmediate_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+grfr_nonimmediate_operand (rtx op, enum machine_mode mode)
 {
   if (! nonimmediate_operand (op, mode))
     return 0;
@@ -687,9 +666,7 @@ grfr_nonimmediate_operand (op, mode)
 /* Return 1 if OP is a GR register operand, or zero.  */
 
 int
-gr_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_0_operand (rtx op, enum machine_mode mode)
 {
   return (op == const0_rtx || gr_register_operand (op, mode));
 }
@@ -697,9 +674,7 @@ gr_reg_or_0_operand (op, mode)
 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand.  */
 
 int
-gr_reg_or_5bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_5bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 32)
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -709,9 +684,7 @@ gr_reg_or_5bit_operand (op, mode)
 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand.  */
 
 int
-gr_reg_or_6bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_6bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -721,9 +694,7 @@ gr_reg_or_6bit_operand (op, mode)
 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand.  */
 
 int
-gr_reg_or_8bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -733,9 +704,7 @@ gr_reg_or_8bit_operand (op, mode)
 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate.  */
 
 int
-grfr_reg_or_8bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+grfr_reg_or_8bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -746,9 +715,7 @@ grfr_reg_or_8bit_operand (op, mode)
    operand.  */
 
 int
-gr_reg_or_8bit_adjusted_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_8bit_adjusted_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_L (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -761,9 +728,7 @@ gr_reg_or_8bit_adjusted_operand (op, mode)
    so we need the union of the immediates accepted by GT and LT.  */
 
 int
-gr_reg_or_8bit_and_adjusted_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_8bit_and_adjusted_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op))
 	   && CONST_OK_FOR_L (INTVAL (op)))
@@ -774,9 +739,7 @@ gr_reg_or_8bit_and_adjusted_operand (op, mode)
 /* Return 1 if OP is a register operand, or a 14 bit immediate operand.  */
 
 int
-gr_reg_or_14bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_14bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_I (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -786,9 +749,7 @@ gr_reg_or_14bit_operand (op, mode)
 /* Return 1 if OP is a register operand, or a 22 bit immediate operand.  */
 
 int
-gr_reg_or_22bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gr_reg_or_22bit_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX
@@ -798,9 +759,7 @@ gr_reg_or_22bit_operand (op, mode)
 /* Return 1 if OP is a 6 bit immediate operand.  */
 
 int
-shift_count_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+shift_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ((GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
 	  || GET_CODE (op) == CONSTANT_P_RTX);
@@ -809,9 +768,7 @@ shift_count_operand (op, mode)
 /* Return 1 if OP is a 5 bit immediate operand.  */
 
 int
-shift_32bit_count_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+shift_32bit_count_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ((GET_CODE (op) == CONST_INT
 	   && (INTVAL (op) >= 0 && INTVAL (op) < 32))
@@ -821,9 +778,7 @@ shift_32bit_count_operand (op, mode)
 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand.  */
 
 int
-shladd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+shladd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && (INTVAL (op) == 2 || INTVAL (op) == 4
@@ -833,9 +788,7 @@ shladd_operand (op, mode)
 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand.  */
 
 int
-fetchadd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+fetchadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
           && (INTVAL (op) == -16 || INTVAL (op) == -8 ||
@@ -847,9 +800,7 @@ fetchadd_operand (op, mode)
 /* Return 1 if OP is a floating-point constant zero, one, or a register.  */
 
 int
-fr_reg_or_fp01_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fr_reg_or_fp01_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (op))
 	  || fr_register_operand (op, mode));
@@ -859,9 +810,7 @@ fr_reg_or_fp01_operand (op, mode)
    POST_MODIFY with a REG as displacement.  */
 
 int
-destination_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+destination_operand (rtx op, enum machine_mode mode)
 {
   if (! nonimmediate_operand (op, mode))
     return 0;
@@ -875,9 +824,7 @@ destination_operand (op, mode)
 /* Like memory_operand, but don't allow post-increments.  */
 
 int
-not_postinc_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+not_postinc_memory_operand (rtx op, enum machine_mode mode)
 {
   return (memory_operand (op, mode)
 	  && GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != 'a');
@@ -887,9 +834,7 @@ not_postinc_memory_operand (op, mode)
    signed immediate operand.  */
 
 int
-normal_comparison_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+normal_comparison_operator (register rtx op, enum machine_mode mode)
 {
   enum rtx_code code = GET_CODE (op);
   return ((mode == VOIDmode || GET_MODE (op) == mode)
@@ -901,9 +846,7 @@ normal_comparison_operator (op, mode)
    signed immediate operand.  */
 
 int
-adjusted_comparison_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+adjusted_comparison_operator (register rtx op, enum machine_mode mode)
 {
   enum rtx_code code = GET_CODE (op);
   return ((mode == VOIDmode || GET_MODE (op) == mode)
@@ -913,9 +856,7 @@ adjusted_comparison_operator (op, mode)
 /* Return 1 if this is a signed inequality operator.  */
 
 int
-signed_inequality_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+signed_inequality_operator (register rtx op, enum machine_mode mode)
 {
   enum rtx_code code = GET_CODE (op);
   return ((mode == VOIDmode || GET_MODE (op) == mode)
@@ -926,9 +867,7 @@ signed_inequality_operator (op, mode)
 /* Return 1 if this operator is valid for predication.  */
 
 int
-predicate_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+predicate_operator (register rtx op, enum machine_mode mode)
 {
   enum rtx_code code = GET_CODE (op);
   return ((GET_MODE (op) == mode || mode == VOIDmode)
@@ -938,9 +877,7 @@ predicate_operator (op, mode)
 /* Return 1 if this operator can be used in a conditional operation.  */
 
 int
-condop_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+condop_operator (register rtx op, enum machine_mode mode)
 {
   enum rtx_code code = GET_CODE (op);
   return ((GET_MODE (op) == mode || mode == VOIDmode)
@@ -951,9 +888,7 @@ condop_operator (op, mode)
 /* Return 1 if this is the ar.lc register.  */
 
 int
-ar_lc_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+ar_lc_reg_operand (register rtx op, enum machine_mode mode)
 {
   return (GET_MODE (op) == DImode
 	  && (mode == DImode || mode == VOIDmode)
@@ -964,9 +899,7 @@ ar_lc_reg_operand (op, mode)
 /* Return 1 if this is the ar.ccv register.  */
 
 int
-ar_ccv_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+ar_ccv_reg_operand (register rtx op, enum machine_mode mode)
 {
   return ((GET_MODE (op) == mode || mode == VOIDmode)
 	  && GET_CODE (op) == REG
@@ -976,9 +909,7 @@ ar_ccv_reg_operand (op, mode)
 /* Return 1 if this is the ar.pfs register.  */
 
 int
-ar_pfs_reg_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+ar_pfs_reg_operand (register rtx op, enum machine_mode mode)
 {
   return ((GET_MODE (op) == mode || mode == VOIDmode)
 	  && GET_CODE (op) == REG
@@ -988,9 +919,7 @@ ar_pfs_reg_operand (op, mode)
 /* Like general_operand, but don't allow (mem (addressof)).  */
 
 int
-general_tfmode_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+general_tfmode_operand (rtx op, enum machine_mode mode)
 {
   if (! general_operand (op, mode))
     return 0;
@@ -1002,9 +931,7 @@ general_tfmode_operand (op, mode)
 /* Similarly.  */
 
 int
-destination_tfmode_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+destination_tfmode_operand (rtx op, enum machine_mode mode)
 {
   if (! destination_operand (op, mode))
     return 0;
@@ -1016,9 +943,7 @@ destination_tfmode_operand (op, mode)
 /* Similarly.  */
 
 int
-tfreg_or_fp01_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+tfreg_or_fp01_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == SUBREG)
     return 0;
@@ -1028,9 +953,7 @@ tfreg_or_fp01_operand (op, mode)
 /* Return 1 if OP is valid as a base register in a reg + offset address.  */
 
 int
-basereg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+basereg_operand (rtx op, enum machine_mode mode)
 {
   /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
      checks from pa.c basereg_operand as well?  Seems to be OK without them
@@ -1040,11 +963,130 @@ basereg_operand (op, mode)
 	  REG_POINTER ((GET_CODE (op) == SUBREG) ? SUBREG_REG (op) : op));
 }
 
+typedef enum
+  {
+    ADDR_AREA_NORMAL,	/* normal address area */
+    ADDR_AREA_SMALL	/* addressable by "addl" (-2MB < addr < 2MB) */
+  }
+ia64_addr_area;
+
+static GTY(()) tree small_ident1;
+static GTY(()) tree small_ident2;
+
+static void
+init_idents (void)
+{
+  if (small_ident1 == 0)
+    {
+      small_ident1 = get_identifier ("small");
+      small_ident2 = get_identifier ("__small__");
+    }
+}
+
+/* Retrieve the address area that has been chosen for the given decl.  */
+
+static ia64_addr_area
+ia64_get_addr_area (tree decl)
+{
+  tree model_attr;
+
+  model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
+  if (model_attr)
+    {
+      tree id;
+
+      init_idents ();
+      id = TREE_VALUE (TREE_VALUE (model_attr));
+      if (id == small_ident1 || id == small_ident2)
+	return ADDR_AREA_SMALL;
+    }
+  return ADDR_AREA_NORMAL;
+}
+
+static tree
+ia64_handle_model_attribute (tree *node, tree name, tree args, int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
+{
+  ia64_addr_area addr_area = ADDR_AREA_NORMAL;
+  ia64_addr_area area;
+  tree arg, decl = *node;
+
+  init_idents ();
+  arg = TREE_VALUE (args);
+  if (arg == small_ident1 || arg == small_ident2)
+    {
+      addr_area = ADDR_AREA_SMALL;
+    }
+  else
+    {
+      warning ("invalid argument of `%s' attribute",
+	       IDENTIFIER_POINTER (name));
+      *no_add_attrs = true;
+    }
+
+  switch (TREE_CODE (decl))
+    {
+    case VAR_DECL:
+      if ((DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl))
+	   == FUNCTION_DECL)
+	  && !TREE_STATIC (decl))
+	{
+	  error ("%Jan address area attribute cannot be specified for "
+		 "local variables", decl, decl);
+	  *no_add_attrs = true;
+	}
+      area = ia64_get_addr_area (decl);
+      if (area != ADDR_AREA_NORMAL && addr_area != area)
+	{
+	  error ("%Jaddress area of '%s' conflicts with previous "
+		 "declaration", decl, decl);
+	  *no_add_attrs = true;
+	}
+      break;
+
+    case FUNCTION_DECL:
+      error ("%Jaddress area attribute cannot be specified for functions",
+	     decl, decl);
+      *no_add_attrs = true;
+      break;
+
+    default:
+      warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
+      *no_add_attrs = true;
+      break;
+    }
+
+  return NULL_TREE;
+}
+
+static void
+ia64_encode_addr_area (tree decl, rtx symbol)
+{
+  int flags;
+
+  flags = SYMBOL_REF_FLAGS (symbol);
+  switch (ia64_get_addr_area (decl))
+    {
+    case ADDR_AREA_NORMAL: break;
+    case ADDR_AREA_SMALL: flags |= SYMBOL_FLAG_SMALL_ADDR; break;
+    default: abort ();
+    }
+  SYMBOL_REF_FLAGS (symbol) = flags;
+}
+
+static void
+ia64_encode_section_info (tree decl, rtx rtl, int first)
+{
+  default_encode_section_info (decl, rtl, first);
+
+  if (TREE_CODE (decl) == VAR_DECL
+      && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
+    ia64_encode_addr_area (decl, XEXP (rtl, 0));
+}
+
 /* Return 1 if the operands of a move are ok.  */
 
 int
-ia64_move_ok (dst, src)
-     rtx dst, src;
+ia64_move_ok (rtx dst, rtx src)
 {
   /* If we're under init_recog_no_volatile, we'll not be able to use
      memory_operand.  So check the code directly and don't worry about
@@ -1064,17 +1106,9 @@ ia64_move_ok (dst, src)
     return GET_CODE (src) == CONST_DOUBLE && CONST_DOUBLE_OK_FOR_G (src);
 }
 
-/* Return 0 if we are doing C++ code.  This optimization fails with
-   C++ because of GNAT c++/6685.  */
-
 int
-addp4_optimize_ok (op1, op2)
-     rtx op1, op2;
+addp4_optimize_ok (rtx op1, rtx op2)
 {
-
-  if (!strcmp (lang_hooks.name, "GNU C++"))
-    return 0;
-
   return (basereg_operand (op1, GET_MODE(op1)) !=
 	  basereg_operand (op2, GET_MODE(op2)));
 }
@@ -1083,8 +1117,7 @@ addp4_optimize_ok (op1, op2)
    Return the length of the field, or <= 0 on failure.  */
 
 int
-ia64_depz_field_mask (rop, rshift)
-     rtx rop, rshift;
+ia64_depz_field_mask (rtx rop, rtx rshift)
 {
   unsigned HOST_WIDE_INT op = INTVAL (rop);
   unsigned HOST_WIDE_INT shift = INTVAL (rshift);
@@ -1099,8 +1132,7 @@ ia64_depz_field_mask (rop, rshift)
 /* Expand a symbolic constant load.  */
 
 void
-ia64_expand_load_address (dest, src)
-      rtx dest, src;
+ia64_expand_load_address (rtx dest, rtx src)
 {
   if (tls_symbolic_operand (src, VOIDmode))
     abort ();
@@ -1114,7 +1146,12 @@ ia64_expand_load_address (dest, src)
   if (GET_MODE (dest) != Pmode)
     dest = gen_rtx_REG (Pmode, REGNO (dest));
 
-  if (TARGET_AUTO_PIC)
+  if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (src))
+    {
+      emit_insn (gen_rtx_SET (VOIDmode, dest, src));
+      return;
+    }
+  else if (TARGET_AUTO_PIC)
     {
       emit_insn (gen_load_gprel64 (dest, src));
       return;
@@ -1162,7 +1199,7 @@ ia64_expand_load_address (dest, src)
 
 static GTY(()) rtx gen_tls_tga;
 static rtx
-gen_tls_get_addr ()
+gen_tls_get_addr (void)
 {
   if (!gen_tls_tga)
     gen_tls_tga = init_one_libfunc ("__tls_get_addr");
@@ -1171,7 +1208,7 @@ gen_tls_get_addr ()
 
 static GTY(()) rtx thread_pointer_rtx;
 static rtx
-gen_thread_pointer ()
+gen_thread_pointer (void)
 {
   if (!thread_pointer_rtx)
     {
@@ -1182,11 +1219,10 @@ gen_thread_pointer ()
 }
 
 static rtx
-ia64_expand_tls_address (tls_kind, op0, op1)
-     enum tls_model tls_kind;
-     rtx op0, op1;
+ia64_expand_tls_address (enum tls_model tls_kind, rtx op0, rtx op1)
 {
   rtx tga_op1, tga_op2, tga_ret, tga_eqv, tmp, insns;
+  rtx orig_op0 = op0;
 
   switch (tls_kind)
     {
@@ -1202,7 +1238,7 @@ ia64_expand_tls_address (tls_kind, op0, op1)
       emit_insn (gen_load_ltoff_dtprel (tga_op2, op1));
       tga_op2 = gen_rtx_MEM (Pmode, tga_op2);
       RTX_UNCHANGING_P (tga_op2) = 1;
-	      
+
       tga_ret = emit_library_call_value (gen_tls_get_addr (), NULL_RTX,
 					 LCT_CONST, Pmode, 2, tga_op1,
 					 Pmode, tga_op2, Pmode);
@@ -1210,8 +1246,10 @@ ia64_expand_tls_address (tls_kind, op0, op1)
       insns = get_insns ();
       end_sequence ();
 
+      if (GET_MODE (op0) != Pmode)
+	op0 = tga_ret;
       emit_libcall_block (insns, op0, tga_ret, op1);
-      return NULL_RTX;
+      break;
 
     case TLS_MODEL_LOCAL_DYNAMIC:
       /* ??? This isn't the completely proper way to do local-dynamic
@@ -1239,19 +1277,16 @@ ia64_expand_tls_address (tls_kind, op0, op1)
       tmp = gen_reg_rtx (Pmode);
       emit_libcall_block (insns, tmp, tga_ret, tga_eqv);
 
-      if (register_operand (op0, Pmode))
-	tga_ret = op0;
-      else
-	tga_ret = gen_reg_rtx (Pmode);
+      if (!register_operand (op0, Pmode))
+	op0 = gen_reg_rtx (Pmode);
       if (TARGET_TLS64)
 	{
-	  emit_insn (gen_load_dtprel (tga_ret, op1));
-	  emit_insn (gen_adddi3 (tga_ret, tmp, tga_ret));
+	  emit_insn (gen_load_dtprel (op0, op1));
+	  emit_insn (gen_adddi3 (op0, tmp, op0));
 	}
       else
-	emit_insn (gen_add_dtprel (tga_ret, tmp, op1));
-
-      return (tga_ret == op0 ? NULL_RTX : tga_ret);
+	emit_insn (gen_add_dtprel (op0, tmp, op1));
+      break;
 
     case TLS_MODEL_INITIAL_EXEC:
       tmp = gen_reg_rtx (Pmode);
@@ -1260,37 +1295,36 @@ ia64_expand_tls_address (tls_kind, op0, op1)
       RTX_UNCHANGING_P (tmp) = 1;
       tmp = force_reg (Pmode, tmp);
 
-      if (register_operand (op0, Pmode))
-	op1 = op0;
-      else
-	op1 = gen_reg_rtx (Pmode);
-      emit_insn (gen_adddi3 (op1, tmp, gen_thread_pointer ()));
-
-      return (op1 == op0 ? NULL_RTX : op1);
+      if (!register_operand (op0, Pmode))
+	op0 = gen_reg_rtx (Pmode);
+      emit_insn (gen_adddi3 (op0, tmp, gen_thread_pointer ()));
+      break;
 
     case TLS_MODEL_LOCAL_EXEC:
-      if (register_operand (op0, Pmode))
-	tmp = op0;
-      else
-	tmp = gen_reg_rtx (Pmode);
+      if (!register_operand (op0, Pmode))
+	op0 = gen_reg_rtx (Pmode);
       if (TARGET_TLS64)
 	{
-	  emit_insn (gen_load_tprel (tmp, op1));
-	  emit_insn (gen_adddi3 (tmp, gen_thread_pointer (), tmp));
+	  emit_insn (gen_load_tprel (op0, op1));
+	  emit_insn (gen_adddi3 (op0, gen_thread_pointer (), op0));
 	}
       else
-	emit_insn (gen_add_tprel (tmp, gen_thread_pointer (), op1));
-
-      return (tmp == op0 ? NULL_RTX : tmp);
+	emit_insn (gen_add_tprel (op0, gen_thread_pointer (), op1));
+      break;
 
     default:
       abort ();
     }
+
+  if (orig_op0 == op0)
+    return NULL_RTX;
+  if (GET_MODE (orig_op0) == Pmode)
+    return op0;
+  return gen_lowpart (GET_MODE (orig_op0), op0);
 }
 
 rtx
-ia64_expand_move (op0, op1)
-     rtx op0, op1;
+ia64_expand_move (rtx op0, rtx op1)
 {
   enum machine_mode mode = GET_MODE (op0);
 
@@ -1316,8 +1350,7 @@ ia64_expand_move (op0, op1)
 /* Split a move from OP1 to OP0 conditional on COND.  */
 
 void
-ia64_emit_cond_move (op0, op1, cond)
-     rtx op0, op1, cond;
+ia64_emit_cond_move (rtx op0, rtx op1, rtx cond)
 {
   rtx insn, first = get_last_insn ();
 
@@ -1332,9 +1365,7 @@ ia64_emit_cond_move (op0, op1, cond)
 /* Split a post-reload TImode reference into two DImode components.  */
 
 rtx
-ia64_split_timode (out, in, scratch)
-     rtx out[2];
-     rtx in, scratch;
+ia64_split_timode (rtx out[2], rtx in, rtx scratch)
 {
   switch (GET_CODE (in))
     {
@@ -1401,14 +1432,12 @@ ia64_split_timode (out, in, scratch)
    SECONDARY_RELOAD_CLASS, but not both.
 
    We got into problems in the first place by allowing a construct like
-   (subreg:TF (reg:TI)), which we got from a union containing a long double.  
+   (subreg:TF (reg:TI)), which we got from a union containing a long double.
    This solution attempts to prevent this situation from occurring.  When
    we see something like the above, we spill the inner register to memory.  */
 
 rtx
-spill_tfmode_operand (in, force)
-     rtx in;
-     int force;
+spill_tfmode_operand (rtx in, int force)
 {
   if (GET_CODE (in) == SUBREG
       && GET_MODE (SUBREG_REG (in)) == TImode
@@ -1433,9 +1462,7 @@ spill_tfmode_operand (in, force)
    that holds the compare result in the proper mode.  */
 
 rtx
-ia64_expand_compare (code, mode)
-     enum rtx_code code;
-     enum machine_mode mode;
+ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
 {
   rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
   rtx cmp;
@@ -1463,11 +1490,8 @@ ia64_expand_compare (code, mode)
 /* Emit the appropriate sequence for a call.  */
 
 void
-ia64_expand_call (retval, addr, nextarg, sibcall_p)
-     rtx retval;
-     rtx addr;
-     rtx nextarg ATTRIBUTE_UNUSED;
-     int sibcall_p;
+ia64_expand_call (rtx retval, rtx addr, rtx nextarg ATTRIBUTE_UNUSED,
+		  int sibcall_p)
 {
   rtx insn, b0;
 
@@ -1503,7 +1527,7 @@ ia64_expand_call (retval, addr, nextarg, sibcall_p)
 }
 
 void
-ia64_reload_gp ()
+ia64_reload_gp (void)
 {
   rtx tmp;
 
@@ -1543,10 +1567,8 @@ ia64_reload_gp ()
 }
 
 void
-ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
-		 noreturn_p, sibcall_p)
-     rtx retval, addr, retaddr, scratch_r, scratch_b;
-     int noreturn_p, sibcall_p;
+ia64_split_call (rtx retval, rtx addr, rtx retaddr, rtx scratch_r,
+		 rtx scratch_b, int noreturn_p, int sibcall_p)
 {
   rtx insn;
   bool is_desc = false;
@@ -1560,7 +1582,7 @@ ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
 
       /* ??? We are currently constrained to *not* use peep2, because
 	 we can legitimately change the global lifetime of the GP
-	 (in the form of killing where previously live).  This is 
+	 (in the form of killing where previously live).  This is
 	 because a call through a descriptor doesn't use the previous
 	 value of the GP, while a direct call does, and we do not
 	 commit to either form until the split here.
@@ -1609,14 +1631,14 @@ ia64_split_call (retval, addr, retaddr, scratch_r, scratch_b,
 /* Begin the assembly file.  */
 
 static void
-ia64_file_start ()
+ia64_file_start (void)
 {
   default_file_start ();
   emit_safe_across_calls ();
 }
 
 void
-emit_safe_across_calls ()
+emit_safe_across_calls (void)
 {
   unsigned int rs, re;
   int out_state;
@@ -1654,8 +1676,7 @@ emit_safe_across_calls ()
    TRY_LOCALS is true if we should attempt to locate a local regnum.  */
 
 static int
-find_gr_spill (try_locals)
-     int try_locals;
+find_gr_spill (int try_locals)
 {
   int regno;
 
@@ -1704,7 +1725,7 @@ find_gr_spill (try_locals)
 static int last_scratch_gr_reg;
 
 static int
-next_scratch_gr_reg ()
+next_scratch_gr_reg (void)
 {
   int i, regno;
 
@@ -1729,9 +1750,7 @@ next_scratch_gr_reg ()
    diddle_return_value.  Mark REG in current_frame_info.gr_used_mask.  */
 
 static void
-mark_reg_gr_used_mask (reg, data)
-     rtx reg;
-     void *data ATTRIBUTE_UNUSED;
+mark_reg_gr_used_mask (rtx reg, void *data ATTRIBUTE_UNUSED)
 {
   unsigned int regno = REGNO (reg);
   if (regno < 32)
@@ -1747,8 +1766,7 @@ mark_reg_gr_used_mask (reg, data)
    needed for local variables.  */
 
 static void
-ia64_compute_frame_size (size)
-     HOST_WIDE_INT size;
+ia64_compute_frame_size (HOST_WIDE_INT size)
 {
   HOST_WIDE_INT total_size;
   HOST_WIDE_INT spill_size = 0;
@@ -1821,7 +1839,7 @@ ia64_compute_frame_size (size)
   current_frame_info.n_rotate_regs = 0;
 
   /* Discover which registers need spilling, and how much room that
-     will take.  Begin with floating point and general registers, 
+     will take.  Begin with floating point and general registers,
      which will always wind up on the stack.  */
 
   for (regno = FR_REG (2); regno <= FR_REG (127); regno++)
@@ -1852,7 +1870,7 @@ ia64_compute_frame_size (size)
 
   /* Now come all special registers that might get saved in other
      general registers.  */
-  
+
   if (frame_pointer_needed)
     {
       current_frame_info.reg_fp = find_gr_spill (1);
@@ -2014,8 +2032,7 @@ ia64_compute_frame_size (size)
 /* Compute the initial difference between the specified pair of registers.  */
 
 HOST_WIDE_INT
-ia64_initial_elimination_offset (from, to)
-     int from, to;
+ia64_initial_elimination_offset (int from, int to)
 {
   HOST_WIDE_INT offset;
 
@@ -2054,10 +2071,6 @@ ia64_initial_elimination_offset (from, to)
 	abort ();
       break;
 
-    case RETURN_ADDRESS_POINTER_REGNUM:
-      offset = 0;
-      break;
-
     default:
       abort ();
     }
@@ -2091,10 +2104,7 @@ struct spill_fill_data
 static struct spill_fill_data spill_fill_data;
 
 static void
-setup_spill_pointers (n_spills, init_reg, cfa_off)
-     int n_spills;
-     rtx init_reg;
-     HOST_WIDE_INT cfa_off;
+setup_spill_pointers (int n_spills, rtx init_reg, HOST_WIDE_INT cfa_off)
 {
   int i;
 
@@ -2120,15 +2130,13 @@ setup_spill_pointers (n_spills, init_reg, cfa_off)
 }
 
 static void
-finish_spill_pointers ()
+finish_spill_pointers (void)
 {
   current_frame_info.gr_used_mask = spill_fill_data.save_gr_used_mask;
 }
 
 static rtx
-spill_restore_mem (reg, cfa_off)
-     rtx reg;
-     HOST_WIDE_INT cfa_off;
+spill_restore_mem (rtx reg, HOST_WIDE_INT cfa_off)
 {
   int iter = spill_fill_data.next_iter;
   HOST_WIDE_INT disp = spill_fill_data.prev_off[iter] - cfa_off;
@@ -2241,10 +2249,8 @@ spill_restore_mem (reg, cfa_off)
 }
 
 static void
-do_spill (move_fn, reg, cfa_off, frame_reg)
-     rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
-     rtx reg, frame_reg;
-     HOST_WIDE_INT cfa_off;
+do_spill (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off,
+	  rtx frame_reg)
 {
   int iter = spill_fill_data.next_iter;
   rtx mem, insn;
@@ -2260,7 +2266,7 @@ do_spill (move_fn, reg, cfa_off, frame_reg)
 
       RTX_FRAME_RELATED_P (insn) = 1;
 
-      /* Don't even pretend that the unwind code can intuit its way 
+      /* Don't even pretend that the unwind code can intuit its way
 	 through a pair of interleaved post_modify iterators.  Just
 	 provide the correct answer.  */
 
@@ -2286,10 +2292,7 @@ do_spill (move_fn, reg, cfa_off, frame_reg)
 }
 
 static void
-do_restore (move_fn, reg, cfa_off)
-     rtx (*move_fn) PARAMS ((rtx, rtx, rtx));
-     rtx reg;
-     HOST_WIDE_INT cfa_off;
+do_restore (rtx (*move_fn) (rtx, rtx, rtx), rtx reg, HOST_WIDE_INT cfa_off)
 {
   int iter = spill_fill_data.next_iter;
   rtx insn;
@@ -2304,25 +2307,19 @@ do_restore (move_fn, reg, cfa_off)
    use a consistent function interface.  */
 
 static rtx
-gen_movdi_x (dest, src, offset)
-     rtx dest, src;
-     rtx offset ATTRIBUTE_UNUSED;
+gen_movdi_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
 {
   return gen_movdi (dest, src);
 }
 
 static rtx
-gen_fr_spill_x (dest, src, offset)
-     rtx dest, src;
-     rtx offset ATTRIBUTE_UNUSED;
+gen_fr_spill_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
 {
   return gen_fr_spill (dest, src);
 }
 
 static rtx
-gen_fr_restore_x (dest, src, offset)
-     rtx dest, src;
-     rtx offset ATTRIBUTE_UNUSED;
+gen_fr_restore_x (rtx dest, rtx src, rtx offset ATTRIBUTE_UNUSED)
 {
   return gen_fr_restore (dest, src);
 }
@@ -2350,7 +2347,7 @@ gen_fr_restore_x (dest, src, offset)
    adds instruction.  */
 
 void
-ia64_expand_prologue ()
+ia64_expand_prologue (void)
 {
   rtx insn, ar_pfs_save_reg, ar_unat_save_reg;
   int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;
@@ -2408,17 +2405,6 @@ ia64_expand_prologue ()
       reg_names[current_frame_info.reg_fp] = tmp;
     }
 
-  /* Fix up the return address placeholder.  */
-  /* ??? We can fail if __builtin_return_address is used, and we didn't
-     allocate a register in which to save b0.  I can't think of a way to
-     eliminate RETURN_ADDRESS_POINTER_REGNUM to a local register and
-     then be sure that I got the right one.  Further, reload doesn't seem
-     to care if an eliminable register isn't used, and "eliminates" it
-     anyway.  */
-  if (regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM]
-      && current_frame_info.reg_save_b0 != 0)
-    XINT (return_address_pointer_rtx, 0) = current_frame_info.reg_save_b0;
-
   /* We don't need an alloc instruction if we've used no outputs or locals.  */
   if (current_frame_info.n_local_regs == 0
       && current_frame_info.n_output_regs == 0
@@ -2440,7 +2426,7 @@ ia64_expand_prologue ()
 	regno = next_scratch_gr_reg ();
       ar_pfs_save_reg = gen_rtx_REG (DImode, regno);
 
-      insn = emit_insn (gen_alloc (ar_pfs_save_reg, 
+      insn = emit_insn (gen_alloc (ar_pfs_save_reg,
 				   GEN_INT (current_frame_info.n_input_regs),
 				   GEN_INT (current_frame_info.n_local_regs),
 				   GEN_INT (current_frame_info.n_output_regs),
@@ -2470,7 +2456,7 @@ ia64_expand_prologue ()
       else
 	{
 	  regno = next_scratch_gr_reg ();
- 	  offset = gen_rtx_REG (DImode, regno);
+	  offset = gen_rtx_REG (DImode, regno);
 	  emit_move_insn (offset, frame_size_rtx);
 	}
 
@@ -2707,8 +2693,7 @@ ia64_expand_prologue ()
    insn to prevent such scheduling.  */
 
 void
-ia64_expand_epilogue (sibcall_p)
-     int sibcall_p;
+ia64_expand_epilogue (int sibcall_p)
 {
   rtx insn, reg, alt_reg, ar_unat_save_reg;
   int regno, alt_regno, cfa_off;
@@ -2722,7 +2707,7 @@ ia64_expand_epilogue (sibcall_p)
     setup_spill_pointers (current_frame_info.n_spilled,
 			  hard_frame_pointer_rtx, 0);
   else
-    setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx, 
+    setup_spill_pointers (current_frame_info.n_spilled, stack_pointer_rtx,
 			  current_frame_info.total_size);
 
   if (current_frame_info.total_size != 0)
@@ -2774,7 +2759,7 @@ ia64_expand_epilogue (sibcall_p)
     }
   else
     ar_unat_save_reg = NULL_RTX;
-      
+
   if (current_frame_info.reg_save_ar_pfs != 0)
     {
       alt_reg = gen_rtx_REG (DImode, current_frame_info.reg_save_ar_pfs);
@@ -2824,7 +2809,7 @@ ia64_expand_epilogue (sibcall_p)
 	do_restore (gen_gr_restore, reg, cfa_off);
 	cfa_off -= 8;
       }
-  
+
   /* Restore the branch registers.  Handle B0 specially, as it may
      have gotten stored in some GR register.  */
   if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
@@ -2841,7 +2826,7 @@ ia64_expand_epilogue (sibcall_p)
       reg = gen_rtx_REG (DImode, BR_REG (0));
       emit_move_insn (reg, alt_reg);
     }
-    
+
   for (regno = BR_REG (1); regno <= BR_REG (7); ++regno)
     if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
       {
@@ -2925,15 +2910,15 @@ ia64_expand_epilogue (sibcall_p)
 
   if (cfun->machine->ia64_eh_epilogue_bsp)
     emit_insn (gen_set_bsp (cfun->machine->ia64_eh_epilogue_bsp));
- 
+
   if (! sibcall_p)
     emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode, BR_REG (0))));
   else
     {
       int fp = GR_REG (2);
       /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
-	 first available call clobbered register.  If there was a frame_pointer 
-	 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM, 
+	 first available call clobbered register.  If there was a frame_pointer
+	 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
 	 so we have to make sure we're using the string "r2" when emitting
 	 the register name for the assembler.  */
       if (current_frame_info.reg_fp && current_frame_info.reg_fp == GR_REG (2))
@@ -2958,7 +2943,7 @@ ia64_expand_epilogue (sibcall_p)
    function.  */
 
 int
-ia64_direct_return ()
+ia64_direct_return (void)
 {
   if (reload_completed && ! frame_pointer_needed)
     {
@@ -2975,10 +2960,71 @@ ia64_direct_return ()
   return 0;
 }
 
+/* Return the magic cookie that we use to hold the return address
+   during early compilation.  */
+
+rtx
+ia64_return_addr_rtx (HOST_WIDE_INT count, rtx frame ATTRIBUTE_UNUSED)
+{
+  if (count != 0)
+    return NULL;
+  return gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_RET_ADDR);
+}
+
+/* Split this value after reload, now that we know where the return
+   address is saved.  */
+
+void
+ia64_split_return_addr_rtx (rtx dest)
+{
+  rtx src;
+
+  if (TEST_HARD_REG_BIT (current_frame_info.mask, BR_REG (0)))
+    {
+      if (current_frame_info.reg_save_b0 != 0)
+	src = gen_rtx_REG (DImode, current_frame_info.reg_save_b0);
+      else
+	{
+	  HOST_WIDE_INT off;
+	  unsigned int regno;
+
+	  /* Compute offset from CFA for BR0.  */
+	  /* ??? Must be kept in sync with ia64_expand_prologue.  */
+	  off = (current_frame_info.spill_cfa_off
+		 + current_frame_info.spill_size);
+	  for (regno = GR_REG (1); regno <= GR_REG (31); ++regno)
+	    if (TEST_HARD_REG_BIT (current_frame_info.mask, regno))
+	      off -= 8;
+
+	  /* Convert CFA offset to a register based offset.  */
+	  if (frame_pointer_needed)
+	    src = hard_frame_pointer_rtx;
+	  else
+	    {
+	      src = stack_pointer_rtx;
+	      off += current_frame_info.total_size;
+	    }
+
+	  /* Load address into scratch register.  */
+	  if (CONST_OK_FOR_I (off))
+	    emit_insn (gen_adddi3 (dest, src, GEN_INT (off)));
+	  else
+	    {
+	      emit_move_insn (dest, GEN_INT (off));
+	      emit_insn (gen_adddi3 (dest, src, dest));
+	    }
+
+	  src = gen_rtx_MEM (Pmode, dest);
+	}
+    }
+  else
+    src = gen_rtx_REG (DImode, BR_REG (0));
+
+  emit_move_insn (dest, src);
+}
+
 int
-ia64_hard_regno_rename_ok (from, to)
-     int from;
-     int to;
+ia64_hard_regno_rename_ok (int from, int to)
 {
   /* Don't clobber any of the registers we reserved for the prologue.  */
   if (to == current_frame_info.reg_fp
@@ -3012,10 +3058,7 @@ ia64_hard_regno_rename_ok (from, to)
    aligned objects and detect the cases when @fptr is needed.  */
 
 static bool
-ia64_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if (size == (TARGET_ILP32 ? 4 : 8)
       && aligned_p
@@ -3037,9 +3080,7 @@ ia64_assemble_integer (x, size, aligned_p)
 /* Emit the function prologue.  */
 
 static void
-ia64_output_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+ia64_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   int mask, grsave, grsave_prev;
 
@@ -3106,8 +3147,7 @@ ia64_output_function_prologue (file, size)
 /* Emit the .body directive at the scheduled end of the prologue.  */
 
 static void
-ia64_output_function_end_prologue (file)
-     FILE *file;
+ia64_output_function_end_prologue (FILE *file)
 {
   if (!flag_unwind_tables && (!flag_exceptions || USING_SJLJ_EXCEPTIONS))
     return;
@@ -3118,15 +3158,11 @@ ia64_output_function_end_prologue (file)
 /* Emit the function epilogue.  */
 
 static void
-ia64_output_function_epilogue (file, size)
-     FILE *file ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
+			       HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   int i;
 
-  /* Reset from the function's potential modifications.  */
-  XINT (return_address_pointer_rtx, 0) = RETURN_ADDRESS_POINTER_REGNUM;
-
   if (current_frame_info.reg_fp)
     {
       const char *tmp = reg_names[HARD_FRAME_POINTER_REGNUM];
@@ -3148,8 +3184,7 @@ ia64_output_function_epilogue (file, size)
 }
 
 int
-ia64_dbx_register_number (regno)
-     int regno;
+ia64_dbx_register_number (int regno)
 {
   /* In ia64_expand_prologue we quite literally renamed the frame pointer
      from its home at loc79 to something inside the register frame.  We
@@ -3174,8 +3209,7 @@ ia64_dbx_register_number (regno)
 }
 
 void
-ia64_initialize_trampoline (addr, fnaddr, static_chain)
-     rtx addr, fnaddr, static_chain;
+ia64_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
 {
   rtx addr_reg, eight = GEN_INT (8);
 
@@ -3207,12 +3241,9 @@ ia64_initialize_trampoline (addr, fnaddr, static_chain)
    We generate the actual spill instructions during prologue generation.  */
 
 void
-ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
-     CUMULATIVE_ARGS cum;
-     int             int_mode;
-     tree            type;
-     int *           pretend_size;
-     int	     second_time ATTRIBUTE_UNUSED;
+ia64_setup_incoming_varargs (CUMULATIVE_ARGS cum, int int_mode, tree type,
+			     int * pretend_size,
+			     int second_time ATTRIBUTE_UNUSED)
 {
   /* Skip the current argument.  */
   ia64_function_arg_advance (&cum, int_mode, type, 1);
@@ -3234,9 +3265,7 @@ ia64_setup_incoming_varargs (cum, int_mode, type, pretend_size, second_time)
    SFmode).  128-bit quad-precision floats are excluded.  */
 
 static enum machine_mode
-hfa_element_mode (type, nested)
-     tree type;
-     int nested;
+hfa_element_mode (tree type, int nested)
 {
   enum machine_mode element_mode = VOIDmode;
   enum machine_mode mode;
@@ -3317,12 +3346,8 @@ hfa_element_mode (type, nested)
    registers.  */
 
 rtx
-ia64_function_arg (cum, mode, type, named, incoming)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     int incoming;
+ia64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
+		   int named, int incoming)
 {
   int basereg = (incoming ? GR_ARG_FIRST : AR_ARG_FIRST);
   int words = (((mode == BLKmode ? int_size_in_bytes (type)
@@ -3493,11 +3518,8 @@ ia64_function_arg (cum, mode, type, named, incoming)
    in memory.  */
 
 int
-ia64_function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+ia64_function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+				 tree type, int named ATTRIBUTE_UNUSED)
 {
   int words = (((mode == BLKmode ? int_size_in_bytes (type)
 		 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
@@ -3530,11 +3552,8 @@ ia64_function_arg_partial_nregs (cum, mode, type, named)
    ia64_function_arg.  */
 
 void
-ia64_function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
+ia64_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+			   tree type, int named)
 {
   int words = (((mode == BLKmode ? int_size_in_bytes (type)
 		 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
@@ -3614,7 +3633,7 @@ ia64_function_arg_advance (cum, mode, type, named)
   /* If there is no prototype, then FP values go in both FR and GR
      registers.  */
   else
-    { 
+    {
       /* ??? Complex types should not reach here.  */
       cum->fp_regs += (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT ? 2 : 1);
       cum->int_regs = cum->words;
@@ -3625,11 +3644,9 @@ ia64_function_arg_advance (cum, mode, type, named)
 /* ??? At present this is a GCC extension to the IA-64 ABI.  */
 
 int
-ia64_function_arg_pass_by_reference (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+				     enum machine_mode mode ATTRIBUTE_UNUSED,
+				     tree type, int named ATTRIBUTE_UNUSED)
 {
   return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST;
 }
@@ -3638,26 +3655,18 @@ ia64_function_arg_pass_by_reference (cum, mode, type, named)
    call expression EXP.  DECL will be the called function, or NULL if
    this is an indirect call.  */
 static bool
-ia64_function_ok_for_sibcall (decl, exp)
-     tree decl;
-     tree exp ATTRIBUTE_UNUSED;
+ia64_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
-  /* Direct calls are always ok.  */
-  if (decl)
-    return true;
-
-  /* If TARGET_CONST_GP is in effect, then our caller expects us to
-     return with our current GP.  This means that we'll always have
-     a GP reload after an indirect call.  */
-  return !ia64_epilogue_uses (R_GR (1));
+  /* We must always return with our current GP.  This means we can
+     only sibcall to functions defined in the current module.  */
+  return decl && (*targetm.binds_local_p) (decl);
 }
 
 
 /* Implement va_arg.  */
 
 rtx
-ia64_va_arg (valist, type)
-     tree valist, type;
+ia64_va_arg (tree valist, tree type)
 {
   tree t;
 
@@ -3688,8 +3697,7 @@ ia64_va_arg (valist, type)
    in a register.  */
 
 int
-ia64_return_in_memory (valtype)
-     tree valtype;
+ia64_return_in_memory (tree valtype)
 {
   enum machine_mode mode;
   enum machine_mode hfa_mode;
@@ -3725,9 +3733,7 @@ ia64_return_in_memory (valtype)
 /* Return rtx for register that holds the function return value.  */
 
 rtx
-ia64_function_value (valtype, func)
-     tree valtype;
-     tree func ATTRIBUTE_UNUSED;
+ia64_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
 {
   enum machine_mode mode;
   enum machine_mode hfa_mode;
@@ -3794,10 +3800,7 @@ ia64_function_value (valtype, func)
    We need to emit DTP-relative relocations.  */
 
 void
-ia64_output_dwarf_dtprel (file, size, x)
-     FILE *file;
-     int size;
-     rtx x;
+ia64_output_dwarf_dtprel (FILE *file, int size, rtx x)
 {
   if (size != 8)
     abort ();
@@ -3812,9 +3815,8 @@ ia64_output_dwarf_dtprel (file, size, x)
    also call this from ia64_print_operand for memory addresses.  */
 
 void
-ia64_print_operand_address (stream, address)
-     FILE * stream ATTRIBUTE_UNUSED;
-     rtx    address ATTRIBUTE_UNUSED;
+ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED,
+			    rtx address ATTRIBUTE_UNUSED)
 {
 }
 
@@ -3839,10 +3841,7 @@ ia64_print_operand_address (stream, address)
    r	Print register name, or constant 0 as r0.  HP compatibility for
 	Linux kernel.  */
 void
-ia64_print_operand (file, x, code)
-     FILE * file;
-     rtx    x;
-     int    code;
+ia64_print_operand (FILE * file, rtx x, int code)
 {
   const char *str;
 
@@ -4001,7 +4000,7 @@ ia64_print_operand (file, x, code)
     case '+':
       {
 	const char *which;
-	
+
 	/* For conditional branches, returns or calls, substitute
 	   sptk, dptk, dpnt, or spnt for %s.  */
 	x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
@@ -4080,10 +4079,7 @@ ia64_print_operand (file, x, code)
 /* ??? This is incomplete.  */
 
 static bool
-ia64_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code;
-     int *total;
+ia64_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   switch (code)
     {
@@ -4157,9 +4153,8 @@ ia64_rtx_costs (x, code, outer_code, total)
    one in class TO, using MODE.  */
 
 int
-ia64_register_move_cost (mode, from, to)
-     enum machine_mode mode;
-     enum reg_class from, to;
+ia64_register_move_cost (enum machine_mode mode, enum reg_class from,
+			 enum reg_class to)
 {
   /* ADDL_REGS is the same as GR_REGS for movement purposes.  */
   if (to == ADDL_REGS)
@@ -4231,10 +4226,8 @@ ia64_register_move_cost (mode, from, to)
    is required.  */
 
 enum reg_class
-ia64_secondary_reload_class (class, mode, x)
-     enum reg_class class;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx x;
+ia64_secondary_reload_class (enum reg_class class,
+			     enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
 {
   int regno = -1;
 
@@ -4271,7 +4264,7 @@ ia64_secondary_reload_class (class, mode, x)
       /* Need to go through general registers to get to other class regs.  */
       if (regno >= 0 && ! (FR_REGNO_P (regno) || GENERAL_REGNO_P (regno)))
 	return GR_REGS;
- 
+
       /* This can happen when a paradoxical subreg is an operand to the
 	 muldi3 pattern.  */
       /* ??? This shouldn't be necessary after instruction scheduling is
@@ -4331,10 +4324,7 @@ ia64_secondary_reload_class (class, mode, x)
    the Intel assembler does not support undefined externals.  */
 
 void
-ia64_asm_output_external (file, decl, name)
-     FILE *file;
-     tree decl;
-     const char *name;
+ia64_asm_output_external (FILE *file, tree decl, const char *name)
 {
   int save_referenced;
 
@@ -4376,8 +4366,7 @@ ia64_asm_output_external (file, decl, name)
 /* Parse the -mfixed-range= option string.  */
 
 static void
-fix_range (const_str)
-     const char *const_str;
+fix_range (const char *const_str)
 {
   int i, first, last;
   char *str, *dash, *comma;
@@ -4440,7 +4429,7 @@ fix_range (const_str)
 }
 
 static struct machine_function *
-ia64_init_machine_status ()
+ia64_init_machine_status (void)
 {
   return ggc_alloc_cleared (sizeof (struct machine_function));
 }
@@ -4448,7 +4437,7 @@ ia64_init_machine_status ()
 /* Handle TARGET_OPTIONS switches.  */
 
 void
-ia64_override_options ()
+ia64_override_options (void)
 {
   static struct pta
     {
@@ -4520,12 +4509,11 @@ ia64_override_options ()
     real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format;
 }
 
-static enum attr_itanium_class ia64_safe_itanium_class PARAMS((rtx));
-static enum attr_type ia64_safe_type PARAMS((rtx));
+static enum attr_itanium_class ia64_safe_itanium_class (rtx);
+static enum attr_type ia64_safe_type (rtx);
 
 static enum attr_itanium_class
-ia64_safe_itanium_class (insn)
-     rtx insn;
+ia64_safe_itanium_class (rtx insn)
 {
   if (recog_memoized (insn) >= 0)
     return get_attr_itanium_class (insn);
@@ -4534,8 +4522,7 @@ ia64_safe_itanium_class (insn)
 }
 
 static enum attr_type
-ia64_safe_type (insn)
-     rtx insn;
+ia64_safe_type (rtx insn)
 {
   if (recog_memoized (insn) >= 0)
     return get_attr_type (insn);
@@ -4613,26 +4600,21 @@ struct reg_flags
   unsigned int is_sibcall : 1;	/* Is this a sibling or normal call?  */
 };
 
-static void rws_update PARAMS ((struct reg_write_state *, int,
-				struct reg_flags, int));
-static int rws_access_regno PARAMS ((int, struct reg_flags, int));
-static int rws_access_reg PARAMS ((rtx, struct reg_flags, int));
-static void update_set_flags PARAMS ((rtx, struct reg_flags *, int *, rtx *));
-static int set_src_needs_barrier PARAMS ((rtx, struct reg_flags, int, rtx));
-static int rtx_needs_barrier PARAMS ((rtx, struct reg_flags, int));
-static void init_insn_group_barriers PARAMS ((void));
-static int group_barrier_needed_p PARAMS ((rtx));
-static int safe_group_barrier_needed_p PARAMS ((rtx));
+static void rws_update (struct reg_write_state *, int, struct reg_flags, int);
+static int rws_access_regno (int, struct reg_flags, int);
+static int rws_access_reg (rtx, struct reg_flags, int);
+static void update_set_flags (rtx, struct reg_flags *, int *, rtx *);
+static int set_src_needs_barrier (rtx, struct reg_flags, int, rtx);
+static int rtx_needs_barrier (rtx, struct reg_flags, int);
+static void init_insn_group_barriers (void);
+static int group_barrier_needed_p (rtx);
+static int safe_group_barrier_needed_p (rtx);
 
 /* Update *RWS for REGNO, which is being written by the current instruction,
    with predicate PRED, and associated register flags in FLAGS.  */
 
 static void
-rws_update (rws, regno, flags, pred)
-     struct reg_write_state *rws;
-     int regno;
-     struct reg_flags flags;
-     int pred;
+rws_update (struct reg_write_state *rws, int regno, struct reg_flags flags, int pred)
 {
   if (pred)
     rws[regno].write_count++;
@@ -4650,10 +4632,7 @@ rws_update (rws, regno, flags, pred)
    a dependency with an earlier instruction in the same group.  */
 
 static int
-rws_access_regno (regno, flags, pred)
-     int regno;
-     struct reg_flags flags;
-     int pred;
+rws_access_regno (int regno, struct reg_flags flags, int pred)
 {
   int need_barrier = 0;
 
@@ -4688,7 +4667,7 @@ rws_access_regno (regno, flags, pred)
 	  /* ??? This assumes that P and P+1 are always complementary
 	     predicates for P even.  */
 	  if (flags.is_and && rws_sum[regno].written_by_and)
-	    ; 
+	    ;
 	  else if (flags.is_or && rws_sum[regno].written_by_or)
 	    ;
 	  else if ((rws_sum[regno].first_pred ^ 1) != pred)
@@ -4771,10 +4750,7 @@ rws_access_regno (regno, flags, pred)
 }
 
 static int
-rws_access_reg (reg, flags, pred)
-     rtx reg;
-     struct reg_flags flags;
-     int pred;
+rws_access_reg (rtx reg, struct reg_flags flags, int pred)
 {
   int regno = REGNO (reg);
   int n = HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg));
@@ -4794,11 +4770,7 @@ rws_access_reg (reg, flags, pred)
    the condition, stored in *PFLAGS, *PPRED and *PCOND.  */
 
 static void
-update_set_flags (x, pflags, ppred, pcond)
-     rtx x;
-     struct reg_flags *pflags;
-     int *ppred;
-     rtx *pcond;
+update_set_flags (rtx x, struct reg_flags *pflags, int *ppred, rtx *pcond)
 {
   rtx src = SET_SRC (x);
 
@@ -4812,7 +4784,7 @@ update_set_flags (x, pflags, ppred, pcond)
     case IF_THEN_ELSE:
       if (SET_DEST (x) == pc_rtx)
 	/* X is a conditional branch.  */
-	return;	
+	return;
       else
 	{
 	  int is_complemented = 0;
@@ -4875,13 +4847,9 @@ update_set_flags (x, pflags, ppred, pcond)
    source of a given SET rtx found in X needs a barrier.  FLAGS and PRED
    are as in rtx_needs_barrier.  COND is an rtx that holds the condition
    for this insn.  */
-   
+
 static int
-set_src_needs_barrier (x, flags, pred, cond)
-     rtx x;
-     struct reg_flags flags;
-     int pred;
-     rtx cond;
+set_src_needs_barrier (rtx x, struct reg_flags flags, int pred, rtx cond)
 {
   int need_barrier = 0;
   rtx dst;
@@ -4921,10 +4889,7 @@ set_src_needs_barrier (x, flags, pred, cond)
    in the same group.  */
 
 static int
-rtx_needs_barrier (x, flags, pred)
-     rtx x;
-     struct reg_flags flags;
-     int pred;
+rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
 {
   int i, j;
   int is_complemented = 0;
@@ -4940,7 +4905,7 @@ rtx_needs_barrier (x, flags, pred)
 
   switch (GET_CODE (x))
     {
-    case SET:      
+    case SET:
       update_set_flags (x, &new_flags, &pred, &cond);
       need_barrier = set_src_needs_barrier (x, new_flags, pred, cond);
       if (GET_CODE (SET_SRC (x)) != CALL)
@@ -5143,7 +5108,7 @@ rtx_needs_barrier (x, flags, pred)
 					      new_flags, pred);
 	    break;
 	  }
-	  
+
 	case UNSPEC_FR_SPILL:
 	case UNSPEC_FR_RESTORE:
 	case UNSPEC_GETF_EXP:
@@ -5245,7 +5210,7 @@ rtx_needs_barrier (x, flags, pred)
    sequence of insns.  */
 
 static void
-init_insn_group_barriers ()
+init_insn_group_barriers (void)
 {
   memset (rws_sum, 0, sizeof (rws_sum));
   first_instruction = 1;
@@ -5256,8 +5221,7 @@ init_insn_group_barriers ()
    Return nonzero if so.  */
 
 static int
-group_barrier_needed_p (insn)
-     rtx insn;
+group_barrier_needed_p (rtx insn)
 {
   rtx pat;
   int need_barrier = 0;
@@ -5368,8 +5332,7 @@ group_barrier_needed_p (insn)
 /* Like group_barrier_needed_p, but do not clobber the current state.  */
 
 static int
-safe_group_barrier_needed_p (insn)
-     rtx insn;
+safe_group_barrier_needed_p (rtx insn)
 {
   struct reg_write_state rws_saved[NUM_REGS];
   int saved_first_instruction;
@@ -5394,8 +5357,7 @@ safe_group_barrier_needed_p (insn)
    invisible to the scheduler.  */
 
 static void
-emit_insn_group_barriers (dump)
-     FILE *dump;
+emit_insn_group_barriers (FILE *dump)
 {
   rtx insn;
   rtx last_label = 0;
@@ -5451,8 +5413,7 @@ emit_insn_group_barriers (dump)
    This function has to emit all necessary group barriers.  */
 
 static void
-emit_all_insn_group_barriers (dump)
-     FILE *dump ATTRIBUTE_UNUSED;
+emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
 {
   rtx insn;
 
@@ -5489,9 +5450,9 @@ emit_all_insn_group_barriers (dump)
 }
 
 
-static int errata_find_address_regs PARAMS ((rtx *, void *));
-static void errata_emit_nops PARAMS ((rtx));
-static void fixup_errata PARAMS ((void));
+static int errata_find_address_regs (rtx *, void *);
+static void errata_emit_nops (rtx);
+static void fixup_errata (void);
 
 /* This structure is used to track some details about the previous insns
    groups so we can determine if it may be necessary to insert NOPs to
@@ -5509,9 +5470,7 @@ static int group_idx;
    conditionally set in the previous group is used as an address register.
    It ensures that for_each_rtx returns 1 in that case.  */
 static int
-errata_find_address_regs (xp, data)
-     rtx *xp;
-     void *data ATTRIBUTE_UNUSED;
+errata_find_address_regs (rtx *xp, void *data ATTRIBUTE_UNUSED)
 {
   rtx x = *xp;
   if (GET_CODE (x) != MEM)
@@ -5534,8 +5493,7 @@ errata_find_address_regs (xp, data)
    last_group and emits additional NOPs if necessary to work around
    an Itanium A/B step erratum.  */
 static void
-errata_emit_nops (insn)
-     rtx insn;
+errata_emit_nops (rtx insn)
 {
   struct group *this_group = last_group + group_idx;
   struct group *prev_group = last_group + (group_idx ^ 1);
@@ -5608,7 +5566,7 @@ errata_emit_nops (insn)
 /* Emit extra nops if they are required to work around hardware errata.  */
 
 static void
-fixup_errata ()
+fixup_errata (void)
 {
   rtx insn;
 
@@ -5717,14 +5675,13 @@ static int *clocks;
 
 static int *add_cycles;
 
-static rtx ia64_single_set PARAMS ((rtx));
-static void ia64_emit_insn_before PARAMS ((rtx, rtx));
+static rtx ia64_single_set (rtx);
+static void ia64_emit_insn_before (rtx, rtx);
 
 /* Map a bundle number to its pseudo-op.  */
 
 const char *
-get_bundle_name (b)
-     int b;
+get_bundle_name (int b)
 {
   return bundle_name[b];
 }
@@ -5733,7 +5690,7 @@ get_bundle_name (b)
 /* Return the maximum number of instructions a cpu can issue.  */
 
 static int
-ia64_issue_rate ()
+ia64_issue_rate (void)
 {
   return 6;
 }
@@ -5741,8 +5698,7 @@ ia64_issue_rate ()
 /* Helper function - like single_set, but look inside COND_EXEC.  */
 
 static rtx
-ia64_single_set (insn)
-     rtx insn;
+ia64_single_set (rtx insn)
 {
   rtx x = PATTERN (insn), ret;
   if (GET_CODE (x) == COND_EXEC)
@@ -5772,9 +5728,7 @@ ia64_single_set (insn)
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
 static int
-ia64_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn, link, dep_insn;
-     int cost;
+ia64_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 {
   enum attr_itanium_class dep_class;
   enum attr_itanium_class insn_class;
@@ -5795,8 +5749,7 @@ ia64_adjust_cost (insn, link, dep_insn, cost)
    ??? When cycle display notes are implemented, update this.  */
 
 static void
-ia64_emit_insn_before (insn, before)
-     rtx insn, before;
+ia64_emit_insn_before (rtx insn, rtx before)
 {
   emit_insn_before (insn, before);
 }
@@ -5807,11 +5760,10 @@ ia64_emit_insn_before (insn, before)
    `ia64_produce_address_p' and the DFA descriptions).  */
 
 static void
-ia64_dependencies_evaluation_hook (head, tail)
-     rtx head, tail;
+ia64_dependencies_evaluation_hook (rtx head, rtx tail)
 {
   rtx insn, link, next, next_tail;
-  
+
   next_tail = NEXT_INSN (tail);
   for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
     if (INSN_P (insn))
@@ -5840,14 +5792,13 @@ ia64_dependencies_evaluation_hook (head, tail)
 /* We're beginning a new block.  Initialize data structures as necessary.  */
 
 static void
-ia64_sched_init (dump, sched_verbose, max_ready)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     int max_ready ATTRIBUTE_UNUSED;
+ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED,
+		 int sched_verbose ATTRIBUTE_UNUSED,
+		 int max_ready ATTRIBUTE_UNUSED)
 {
 #ifdef ENABLE_CHECKING
   rtx insn;
-  
+
   if (reload_completed)
     for (insn = NEXT_INSN (current_sched_info->prev_head);
 	 insn != current_sched_info->next_tail;
@@ -5863,14 +5814,9 @@ ia64_sched_init (dump, sched_verbose, max_ready)
    Override the default sort algorithm to better slot instructions.  */
 
 static int
-ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
-			clock_var, reorder_type)
-     FILE *dump;
-     int sched_verbose;
-     rtx *ready;
-     int *pn_ready;
-     int clock_var  ATTRIBUTE_UNUSED;
-     int reorder_type;
+ia64_dfa_sched_reorder (FILE *dump, int sched_verbose, rtx *ready,
+			int *pn_ready, int clock_var ATTRIBUTE_UNUSED,
+			int reorder_type)
 {
   int n_asms;
   int n_ready = *pn_ready;
@@ -5927,7 +5873,7 @@ ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
       for (insnp = ready; insnp < e_ready; insnp++)
 	if (safe_group_barrier_needed_p (*insnp))
 	  nr_need_stop++;
-      
+
       if (reorder_type == 1 && n_ready == nr_need_stop)
 	return 0;
       if (reorder_type == 0)
@@ -5956,12 +5902,8 @@ ia64_dfa_sched_reorder (dump, sched_verbose, ready, pn_ready,
    the default sort algorithm to better slot instructions.  */
 
 static int
-ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
-     FILE *dump;
-     int sched_verbose;
-     rtx *ready;
-     int *pn_ready;
-     int clock_var;
+ia64_sched_reorder (FILE *dump, int sched_verbose, rtx *ready, int *pn_ready,
+		    int clock_var)
 {
   return ia64_dfa_sched_reorder (dump, sched_verbose, ready,
 				 pn_ready, clock_var, 0);
@@ -5971,12 +5913,9 @@ ia64_sched_reorder (dump, sched_verbose, ready, pn_ready, clock_var)
    Override the default sort algorithm to better slot instructions.  */
 
 static int
-ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     rtx *ready;
-     int *pn_ready;
-     int clock_var;
+ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
+		     int sched_verbose ATTRIBUTE_UNUSED, rtx *ready,
+		     int *pn_ready, int clock_var)
 {
   if (ia64_tune == PROCESSOR_ITANIUM && reload_completed && last_scheduled_insn)
     clocks [INSN_UID (last_scheduled_insn)] = clock_var;
@@ -5988,11 +5927,10 @@ ia64_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
    ready queue that can be issued this cycle.  */
 
 static int
-ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     rtx insn ATTRIBUTE_UNUSED;
-     int can_issue_more ATTRIBUTE_UNUSED;
+ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
+		     int sched_verbose ATTRIBUTE_UNUSED,
+		     rtx insn ATTRIBUTE_UNUSED,
+		     int can_issue_more ATTRIBUTE_UNUSED)
 {
   last_scheduled_insn = insn;
   memcpy (prev_cycle_state, curr_state, dfa_state_size);
@@ -6012,8 +5950,7 @@ ia64_variable_issue (dump, sched_verbose, insn, can_issue_more)
    can be chosen.  */
 
 static int
-ia64_first_cycle_multipass_dfa_lookahead_guard (insn)
-     rtx insn;
+ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn)
 {
   if (insn == NULL_RTX || !INSN_P (insn))
     abort ();
@@ -6032,12 +5969,8 @@ static rtx dfa_pre_cycle_insn;
    the ready queue on the next clock start.  */
 
 static int
-ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
-     FILE *dump;
-     int verbose;
-     rtx insn;
-     int last_clock, clock;
-     int *sort_p;
+ia64_dfa_new_cycle (FILE *dump, int verbose, rtx insn, int last_clock,
+		    int clock, int *sort_p)
 {
   int setup_clocks_p = FALSE;
 
@@ -6076,18 +6009,18 @@ ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
   if (setup_clocks_p && ia64_tune == PROCESSOR_ITANIUM)
     {
       enum attr_itanium_class c = ia64_safe_itanium_class (insn);
-      
+
       if (c != ITANIUM_CLASS_MMMUL && c != ITANIUM_CLASS_MMSHF)
 	{
 	  rtx link;
 	  int d = -1;
-	  
+
 	  for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
 	    if (REG_NOTE_KIND (link) == 0)
 	      {
 		enum attr_itanium_class dep_class;
 		rtx dep_insn = XEXP (link, 0);
-		
+
 		dep_class = ia64_safe_itanium_class (dep_insn);
 		if ((dep_class == ITANIUM_CLASS_MMMUL
 		     || dep_class == ITANIUM_CLASS_MMSHF)
@@ -6153,7 +6086,7 @@ static struct bundle_state *free_bundle_state_chain;
 /* The following function returns a free bundle state.  */
 
 static struct bundle_state *
-get_free_bundle_state ()
+get_free_bundle_state (void)
 {
   struct bundle_state *result;
 
@@ -6171,14 +6104,13 @@ get_free_bundle_state ()
     }
   result->unique_num = bundle_states_num++;
   return result;
-  
+
 }
 
 /* The following function frees given bundle state.  */
 
 static void
-free_bundle_state (state)
-     struct bundle_state *state;
+free_bundle_state (struct bundle_state *state)
 {
   state->next = free_bundle_state_chain;
   free_bundle_state_chain = state;
@@ -6187,7 +6119,7 @@ free_bundle_state (state)
 /* Start work with abstract data `bundle states'.  */
 
 static void
-initiate_bundle_states ()
+initiate_bundle_states (void)
 {
   bundle_states_num = 0;
   free_bundle_state_chain = NULL;
@@ -6197,7 +6129,7 @@ initiate_bundle_states ()
 /* Finish work with abstract data `bundle states'.  */
 
 static void
-finish_bundle_states ()
+finish_bundle_states (void)
 {
   struct bundle_state *curr_state, *next_state;
 
@@ -6219,8 +6151,7 @@ static htab_t bundle_state_table;
 /* The function returns hash of BUNDLE_STATE.  */
 
 static unsigned
-bundle_state_hash (bundle_state)
-     const void *bundle_state;
+bundle_state_hash (const void *bundle_state)
 {
   const struct bundle_state *state = (struct bundle_state *) bundle_state;
   unsigned result, i;
@@ -6234,9 +6165,7 @@ bundle_state_hash (bundle_state)
 /* The function returns nonzero if the bundle state keys are equal.  */
 
 static int
-bundle_state_eq_p (bundle_state_1, bundle_state_2)
-     const void *bundle_state_1;
-     const void *bundle_state_2;
+bundle_state_eq_p (const void *bundle_state_1, const void *bundle_state_2)
 {
   const struct bundle_state * state1 = (struct bundle_state *) bundle_state_1;
   const struct bundle_state * state2 = (struct bundle_state *) bundle_state_2;
@@ -6251,8 +6180,7 @@ bundle_state_eq_p (bundle_state_1, bundle_state_2)
    table.  The table contains the best bundle state with given key.  */
 
 static int
-insert_bundle_state (bundle_state)
-     struct bundle_state *bundle_state;
+insert_bundle_state (struct bundle_state *bundle_state)
 {
   void **entry_ptr;
 
@@ -6274,7 +6202,7 @@ insert_bundle_state (bundle_state)
 		       && ((struct bundle_state *)
 			   *entry_ptr)->branch_deviation
 		       > bundle_state->branch_deviation))))
-		   
+
     {
       struct bundle_state temp;
 
@@ -6289,7 +6217,7 @@ insert_bundle_state (bundle_state)
 /* Start work with the hash table.  */
 
 static void
-initiate_bundle_state_table ()
+initiate_bundle_state_table (void)
 {
   bundle_state_table = htab_create (50, bundle_state_hash, bundle_state_eq_p,
 				    (htab_del) 0);
@@ -6298,7 +6226,7 @@ initiate_bundle_state_table ()
 /* Finish work with the hash table.  */
 
 static void
-finish_bundle_state_table ()
+finish_bundle_state_table (void)
 {
   htab_delete (bundle_state_table);
 }
@@ -6315,9 +6243,7 @@ static rtx ia64_nop;
    function returns FALSE and frees the current state.  */
 
 static int
-try_issue_nops (curr_state, nops_num)
-     struct bundle_state *curr_state;
-     int nops_num;
+try_issue_nops (struct bundle_state *curr_state, int nops_num)
 {
   int i;
 
@@ -6335,9 +6261,7 @@ try_issue_nops (curr_state, nops_num)
    function returns FALSE and frees the current state.  */
 
 static int
-try_issue_insn (curr_state, insn)
-     struct bundle_state *curr_state;
-     rtx insn;
+try_issue_insn (struct bundle_state *curr_state, rtx insn)
 {
   if (insn && state_transition (curr_state->dfa_state, insn) >= 0)
     {
@@ -6355,12 +6279,8 @@ try_issue_insn (curr_state, insn)
    insert into the hash table and into `index_to_bundle_states'.  */
 
 static void
-issue_nops_and_insn (originator, before_nops_num, insn, try_bundle_end_p,
-		     only_bundle_end_p)
-     struct bundle_state *originator;
-     int before_nops_num;
-     rtx insn;
-     int try_bundle_end_p, only_bundle_end_p;
+issue_nops_and_insn (struct bundle_state *originator, int before_nops_num,
+		     rtx insn, int try_bundle_end_p, int only_bundle_end_p)
 {
   struct bundle_state *curr_state;
 
@@ -6466,8 +6386,7 @@ issue_nops_and_insn (originator, before_nops_num, insn, try_bundle_end_p,
    for given STATE.  */
 
 static int
-get_max_pos (state)
-     state_t state;
+get_max_pos (state_t state)
 {
   if (cpu_unit_reservation_p (state, pos_6))
     return 6;
@@ -6490,9 +6409,7 @@ get_max_pos (state)
    position equal to 3 or 6.  */
 
 static int
-get_template (state, pos)
-     state_t state;
-     int pos;
+get_template (state_t state, int pos)
 {
   switch (pos)
     {
@@ -6551,8 +6468,7 @@ get_template (state, pos)
    followed by INSN and before TAIL.  */
 
 static rtx
-get_next_important_insn (insn, tail)
-     rtx insn, tail;
+get_next_important_insn (rtx insn, rtx tail)
 {
   for (; insn && insn != tail; insn = NEXT_INSN (insn))
     if (INSN_P (insn)
@@ -6572,10 +6488,7 @@ get_next_important_insn (insn, tail)
    scheduling.  */
 
 static void
-bundling (dump, verbose, prev_head_insn, tail)
-     FILE *dump;
-     int verbose;
-     rtx prev_head_insn, tail;
+bundling (FILE *dump, int verbose, rtx prev_head_insn, rtx tail)
 {
   struct bundle_state *curr_state, *next_state, *best_state;
   rtx insn, next_insn;
@@ -6690,7 +6603,7 @@ bundling (dump, verbose, prev_head_insn, tail)
 	      unsigned short two_automaton_state;
 	      unsigned short twob_automaton_state;
 	    };
-	    
+
 	    fprintf
 	      (dump,
 	       "//    Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
@@ -6743,7 +6656,7 @@ bundling (dump, verbose, prev_head_insn, tail)
 	    unsigned short two_automaton_state;
 	    unsigned short twob_automaton_state;
 	  };
-	  
+
 	  fprintf
 	    (dump,
 	     "//    Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
@@ -6856,7 +6769,7 @@ bundling (dump, verbose, prev_head_insn, tail)
 	    rtx last;
 	    int i, j, n;
 	    int pred_stop_p;
-	    
+
 	    last = prev_active_insn (insn);
 	    pred_stop_p = recog_memoized (last) == CODE_FOR_insn_group_barrier;
 	    if (pred_stop_p)
@@ -6920,9 +6833,7 @@ bundling (dump, verbose, prev_head_insn, tail)
    EBB.  After reload, it inserts stop bits and does insn bundling.  */
 
 static void
-ia64_sched_finish (dump, sched_verbose)
-     FILE *dump;
-     int sched_verbose;
+ia64_sched_finish (FILE *dump, int sched_verbose)
 {
   if (sched_verbose)
     fprintf (dump, "// Finishing schedule.\n");
@@ -6937,7 +6848,7 @@ ia64_sched_finish (dump, sched_verbose)
 	fprintf (dump, "//    finishing %d-%d\n",
 		 INSN_UID (NEXT_INSN (current_sched_info->prev_head)),
 		 INSN_UID (PREV_INSN (current_sched_info->next_tail)));
-      
+
       return;
     }
 }
@@ -6945,8 +6856,7 @@ ia64_sched_finish (dump, sched_verbose)
 /* The following function inserts stop bits in scheduled BB or EBB.  */
 
 static void
-final_emit_insn_group_barriers (dump)
-     FILE *dump ATTRIBUTE_UNUSED;
+final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED)
 {
   rtx insn;
   int need_barrier_p = 0;
@@ -6987,7 +6897,7 @@ final_emit_insn_group_barriers (dump)
 	      if (TARGET_EARLY_STOP_BITS)
 		{
 		  rtx last;
-		  
+
 		  for (last = insn;
 		       last != current_sched_info->prev_head;
 		       last = PREV_INSN (last))
@@ -7032,7 +6942,7 @@ final_emit_insn_group_barriers (dump)
    insn scheduler.  */
 
 static int
-ia64_use_dfa_pipeline_interface ()
+ia64_use_dfa_pipeline_interface (void)
 {
   return 1;
 }
@@ -7041,7 +6951,7 @@ ia64_use_dfa_pipeline_interface ()
    insn scheduler.  */
 
 static int
-ia64_first_cycle_multipass_dfa_lookahead ()
+ia64_first_cycle_multipass_dfa_lookahead (void)
 {
   return (reload_completed ? 6 : 4);
 }
@@ -7049,7 +6959,7 @@ ia64_first_cycle_multipass_dfa_lookahead ()
 /* The following function initiates variable `dfa_pre_cycle_insn'.  */
 
 static void
-ia64_init_dfa_pre_cycle_insn ()
+ia64_init_dfa_pre_cycle_insn (void)
 {
   if (temp_dfa_state == NULL)
     {
@@ -7069,7 +6979,7 @@ ia64_init_dfa_pre_cycle_insn ()
    used by the DFA insn scheduler.  */
 
 static rtx
-ia64_dfa_pre_cycle_insn ()
+ia64_dfa_pre_cycle_insn (void)
 {
   return dfa_pre_cycle_insn;
 }
@@ -7078,9 +6988,7 @@ ia64_dfa_pre_cycle_insn ()
    ld) produces address for CONSUMER (of type st or stf). */
 
 int
-ia64_st_address_bypass_p (producer, consumer)
-     rtx producer;
-     rtx consumer;
+ia64_st_address_bypass_p (rtx producer, rtx consumer)
 {
   rtx dest, reg, mem;
 
@@ -7103,9 +7011,7 @@ ia64_st_address_bypass_p (producer, consumer)
    ld) produces address for CONSUMER (of type ld or fld). */
 
 int
-ia64_ld_address_bypass_p (producer, consumer)
-     rtx producer;
-     rtx consumer;
+ia64_ld_address_bypass_p (rtx producer, rtx consumer)
 {
   rtx dest, src, reg, mem;
 
@@ -7137,8 +7043,7 @@ ia64_ld_address_bypass_p (producer, consumer)
    decreases its latency time. */
 
 int
-ia64_produce_address_p (insn)
-     rtx insn;
+ia64_produce_address_p (rtx insn)
 {
   return insn->call;
 }
@@ -7150,7 +7055,7 @@ ia64_produce_address_p (insn)
    straight-line code.  */
 
 static void
-emit_predicate_relation_info ()
+emit_predicate_relation_info (void)
 {
   basic_block bb;
 
@@ -7184,7 +7089,7 @@ emit_predicate_relation_info ()
   FOR_EACH_BB_REVERSE (bb)
     {
       rtx insn = bb->head;
-      
+
       while (1)
 	{
 	  if (GET_CODE (insn) == CALL_INSN
@@ -7198,7 +7103,7 @@ emit_predicate_relation_info ()
 	      if (bb->end == insn)
 		bb->end = a;
 	    }
-	  
+
 	  if (insn == bb->end)
 	    break;
 	  insn = NEXT_INSN (insn);
@@ -7209,7 +7114,7 @@ emit_predicate_relation_info ()
 /* Perform machine dependent operations on the rtl chain INSNS.  */
 
 static void
-ia64_reorg ()
+ia64_reorg (void)
 {
   /* We are freeing block_for_insn in the toplev to keep compatibility
      with old MDEP_REORGS that are not CFG based.  Recompute it now.  */
@@ -7233,14 +7138,11 @@ ia64_reorg ()
       PREV_INSN (ia64_nop) = NEXT_INSN (ia64_nop) = NULL_RTX;
       recog_memoized (ia64_nop);
       clocks_length = get_max_uid () + 1;
-      stops_p = (char *) xmalloc (clocks_length);
-      memset (stops_p, 0, clocks_length);
+      stops_p = xcalloc (1, clocks_length);
       if (ia64_tune == PROCESSOR_ITANIUM)
 	{
-	  clocks = (int *) xmalloc (clocks_length * sizeof (int));
-	  memset (clocks, 0, clocks_length * sizeof (int));
-	  add_cycles = (int *) xmalloc (clocks_length * sizeof (int));
-	  memset (add_cycles, 0, clocks_length * sizeof (int));
+	  clocks = xcalloc (clocks_length, sizeof (int));
+	  add_cycles = xcalloc (clocks_length, sizeof (int));
 	}
       if (ia64_tune == PROCESSOR_ITANIUM2)
 	{
@@ -7350,18 +7252,16 @@ ia64_reorg ()
 /* Return true if REGNO is used by the epilogue.  */
 
 int
-ia64_epilogue_uses (regno)
-     int regno;
+ia64_epilogue_uses (int regno)
 {
   switch (regno)
     {
     case R_GR (1):
-      /* When a function makes a call through a function descriptor, we
-         will write a (potentially) new value to "gp".  After returning
-         from such a call, we need to make sure the function restores the
-         original gp-value, even if the function itself does not use the
-         gp anymore.  */
-      return (TARGET_CONST_GP && !(TARGET_AUTO_PIC || TARGET_NO_PIC));
+      /* With a call to a function in another module, we will write a new
+	 value to "gp".  After returning from such a call, we need to make
+	 sure the function restores the original gp-value, even if the
+	 function itself does not use the gp anymore.  */
+      return !(TARGET_AUTO_PIC || TARGET_NO_PIC);
 
     case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
     case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
@@ -7391,8 +7291,7 @@ ia64_epilogue_uses (regno)
 /* Return true if REGNO is used by the frame unwinder.  */
 
 int
-ia64_eh_uses (regno)
-     int regno;
+ia64_eh_uses (int regno)
 {
   if (! reload_completed)
     return 0;
@@ -7424,8 +7323,7 @@ ia64_eh_uses (regno)
    types which can't go in sdata/sbss.  */
 
 static bool
-ia64_in_small_data_p (exp)
-     tree exp;
+ia64_in_small_data_p (tree exp)
 {
   if (TARGET_NO_SDATA)
     return false;
@@ -7467,7 +7365,7 @@ static bool need_copy_state;
 /* The function emits unwind directives for the start of an epilogue.  */
 
 static void
-process_epilogue ()
+process_epilogue (void)
 {
   /* If this isn't the last block of the function, then we need to label the
      current state, and copy it back in at the start of the next block.  */
@@ -7485,9 +7383,7 @@ process_epilogue ()
    which result in emitting an assembly directive required for unwinding.  */
 
 static int
-process_set (asm_out_file, pat)
-     FILE *asm_out_file;
-     rtx pat;
+process_set (FILE *asm_out_file, rtx pat)
 {
   rtx src = SET_SRC (pat);
   rtx dest = SET_DEST (pat);
@@ -7697,9 +7593,7 @@ process_set (asm_out_file, pat)
 /* This function looks at a single insn and emits any directives
    required to unwind this insn.  */
 void
-process_for_unwind_directive (asm_out_file, insn)
-     FILE *asm_out_file;
-     rtx insn;
+process_for_unwind_directive (FILE *asm_out_file, rtx insn)
 {
   if (flag_unwind_tables
       || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))
@@ -7756,7 +7650,7 @@ process_for_unwind_directive (asm_out_file, insn)
 
 
 void
-ia64_init_builtins ()
+ia64_init_builtins (void)
 {
   tree psi_type_node = build_pointer_type (integer_type_node);
   tree pdi_type_node = build_pointer_type (long_integer_type_node);
@@ -7800,6 +7694,42 @@ ia64_init_builtins ()
   tree void_ftype_pdi
     = build_function_type_list (void_type_node, pdi_type_node, NULL_TREE);
 
+  tree fpreg_type;
+  tree float80_type;
+
+  /* The __fpreg type.  */
+  fpreg_type = make_node (REAL_TYPE);
+  /* ??? Once the IA64 back end supports both 80-bit and 128-bit
+     floating types, this type should have XFmode, not TFmode.
+     TYPE_PRECISION should be 80 bits, not 128.  And, the back end
+     should know to load/save __fpreg variables using the ldf.fill and
+     stf.spill instructions.  */
+  TYPE_PRECISION (fpreg_type) = 128;
+  layout_type (fpreg_type);
+  (*lang_hooks.types.register_builtin_type) (fpreg_type, "__fpreg");
+
+  /* The __float80 type.  */
+  float80_type = make_node (REAL_TYPE);
+  /* ??? Once the IA64 back end supports both 80-bit and 128-bit
+     floating types, this type should have XFmode, not TFmode.
+     TYPE_PRECISION should be 80 bits, not 128.  */
+  TYPE_PRECISION (float80_type) = 128;
+  layout_type (float80_type);
+  (*lang_hooks.types.register_builtin_type) (float80_type, "__float80");
+
+  /* The __float128 type.  */
+  if (INTEL_EXTENDED_IEEE_FORMAT)
+    {
+      tree float128_type = make_node (REAL_TYPE);
+      TYPE_PRECISION (float128_type) = 128;
+      layout_type (float128_type);
+      (*lang_hooks.types.register_builtin_type) (float128_type, "__float128");
+    }
+  else
+    /* This is a synonym for "long double".  */
+    (*lang_hooks.types.register_builtin_type) (long_double_type_node,
+					       "__float128");
+
 #define def_builtin(name, type, code) \
   builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
 
@@ -7828,8 +7758,8 @@ ia64_init_builtins ()
 	       build_function_type (ptr_type_node, void_list_node),
 	       IA64_BUILTIN_BSP);
 
-  def_builtin ("__builtin_ia64_flushrs", 
-	       build_function_type (void_type_node, void_list_node), 
+  def_builtin ("__builtin_ia64_flushrs",
+	       build_function_type (void_type_node, void_list_node),
 	       IA64_BUILTIN_FLUSHRS);
 
   def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si,
@@ -7900,11 +7830,8 @@ ia64_init_builtins ()
 */
 
 static rtx
-ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
-     optab binoptab;
-     enum machine_mode mode;
-     tree arglist;
-     rtx target;
+ia64_expand_fetch_and_op (optab binoptab, enum machine_mode mode,
+			  tree arglist, rtx target)
 {
   rtx ret, label, tmp, ccv, insn, mem, value;
   tree arg0, arg1;
@@ -7981,11 +7908,8 @@ ia64_expand_fetch_and_op (binoptab, mode, arglist, target)
 */
 
 static rtx
-ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
-     optab binoptab;
-     enum machine_mode mode;
-     tree arglist;
-     rtx target;
+ia64_expand_op_and_fetch (optab binoptab, enum machine_mode mode,
+			  tree arglist, rtx target)
 {
   rtx old, label, tmp, ret, ccv, insn, mem, value;
   tree arg0, arg1;
@@ -8049,12 +7973,8 @@ ia64_expand_op_and_fetch (binoptab, mode, arglist, target)
 */
 
 static rtx
-ia64_expand_compare_and_swap (rmode, mode, boolp, arglist, target)
-     enum machine_mode rmode;
-     enum machine_mode mode;
-     int boolp;
-     tree arglist;
-     rtx target;
+ia64_expand_compare_and_swap (enum machine_mode rmode, enum machine_mode mode,
+			      int boolp, tree arglist, rtx target)
 {
   tree arg0, arg1, arg2;
   rtx mem, old, new, ccv, tmp, insn;
@@ -8108,10 +8028,8 @@ ia64_expand_compare_and_swap (rmode, mode, boolp, arglist, target)
 /* Expand lock_test_and_set.  I.e. `xchgsz ret = [ptr], new'.  */
 
 static rtx
-ia64_expand_lock_test_and_set (mode, arglist, target)
-     enum machine_mode mode;
-     tree arglist;
-     rtx target;
+ia64_expand_lock_test_and_set (enum machine_mode mode, tree arglist,
+			       rtx target)
 {
   tree arg0, arg1;
   rtx mem, new, ret, insn;
@@ -8143,10 +8061,8 @@ ia64_expand_lock_test_and_set (mode, arglist, target)
 /* Expand lock_release.  I.e. `stsz.rel [ptr] = r0'.  */
 
 static rtx
-ia64_expand_lock_release (mode, arglist, target)
-     enum machine_mode mode;
-     tree arglist;
-     rtx target ATTRIBUTE_UNUSED;
+ia64_expand_lock_release (enum machine_mode mode, tree arglist,
+			  rtx target ATTRIBUTE_UNUSED)
 {
   tree arg0;
   rtx mem;
@@ -8163,12 +8079,9 @@ ia64_expand_lock_release (mode, arglist, target)
 }
 
 rtx
-ia64_expand_builtin (exp, target, subtarget, mode, ignore)
-     tree exp;
-     rtx target;
-     rtx subtarget ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     int ignore ATTRIBUTE_UNUSED;
+ia64_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
+		     enum machine_mode mode ATTRIBUTE_UNUSED,
+		     int ignore ATTRIBUTE_UNUSED)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
@@ -8327,9 +8240,7 @@ ia64_expand_builtin (exp, target, subtarget, mode, ignore)
    most significant bits of the stack slot.  */
 
 enum direction
-ia64_hpux_function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
+ia64_hpux_function_arg_padding (enum machine_mode mode, tree type)
 {
    /* Exception to normal case for structures/unions/etc.  */
 
@@ -8337,14 +8248,8 @@ ia64_hpux_function_arg_padding (mode, type)
        && int_size_in_bytes (type) < UNITS_PER_WORD)
      return upward;
 
-   /* This is the standard FUNCTION_ARG_PADDING with !BYTES_BIG_ENDIAN
-      hardwired to be true.  */
-
-   return((mode == BLKmode
-       ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-          && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
-       : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
-      ? downward : upward);
+   /* Fall back to the default.  */
+   return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
 }
 
 /* Linked list of all external functions that are to be emitted by GCC.
@@ -8358,8 +8263,7 @@ struct extern_func_list
 } *extern_func_head = 0;
 
 static void
-ia64_hpux_add_extern_decl (name)
-        const char *name;
+ia64_hpux_add_extern_decl (const char *name)
 {
   struct extern_func_list *p;
 
@@ -8373,7 +8277,7 @@ ia64_hpux_add_extern_decl (name)
 /* Print out the list of used global functions.  */
 
 static void
-ia64_hpux_file_end ()
+ia64_hpux_file_end (void)
 {
   while (extern_func_head)
     {
@@ -8405,10 +8309,8 @@ ia64_hpux_file_end ()
    special we do here is to honor small data.  */
 
 static void
-ia64_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align;
+ia64_select_rtx_section (enum machine_mode mode, rtx x,
+			 unsigned HOST_WIDE_INT align)
 {
   if (GET_MODE_SIZE (mode) > 0
       && GET_MODE_SIZE (mode) <= ia64_section_threshold)
@@ -8421,27 +8323,20 @@ ia64_select_rtx_section (mode, x, align)
    Pretend flag_pic is always set.  */
 
 static void
-ia64_rwreloc_select_section (exp, reloc, align)
-     tree exp;
-     int reloc;
-     unsigned HOST_WIDE_INT align;
+ia64_rwreloc_select_section (tree exp, int reloc, unsigned HOST_WIDE_INT align)
 {
   default_elf_select_section_1 (exp, reloc, align, true);
 }
 
 static void
-ia64_rwreloc_unique_section (decl, reloc)
-     tree decl;
-     int reloc;
+ia64_rwreloc_unique_section (tree decl, int reloc)
 {
   default_unique_section_1 (decl, reloc, true);
 }
 
 static void
-ia64_rwreloc_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align;
+ia64_rwreloc_select_rtx_section (enum machine_mode mode, rtx x,
+				 unsigned HOST_WIDE_INT align)
 {
   int save_pic = flag_pic;
   flag_pic = 1;
@@ -8450,10 +8345,7 @@ ia64_rwreloc_select_rtx_section (mode, x, align)
 }
 
 static unsigned int
-ia64_rwreloc_section_type_flags (decl, name, reloc)
-     tree decl;
-     const char *name;
-     int reloc;
+ia64_rwreloc_section_type_flags (tree decl, const char *name, int reloc)
 {
   return default_section_type_flags_1 (decl, name, reloc, true);
 }
@@ -8466,12 +8358,9 @@ ia64_rwreloc_section_type_flags (decl, name, reloc)
    *(*this + vcall_offset) should be added to THIS.  */
 
 static void
-ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset;
-     tree function;
+ia64_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+		      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+		      tree function)
 {
   rtx this, insn, funexp;
 
@@ -8494,6 +8383,18 @@ ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
   emit_note (NOTE_INSN_PROLOGUE_END);
 
   this = gen_rtx_REG (Pmode, IN_REG (0));
+  if (TARGET_ILP32)
+    {
+      rtx tmp = gen_rtx_REG (ptr_mode, IN_REG (0));
+      REG_POINTER (tmp) = 1;
+      if (delta && CONST_OK_FOR_I (delta))
+	{
+	  emit_insn (gen_ptr_extend_plus_imm (this, tmp, GEN_INT (delta)));
+	  delta = 0;
+	}
+      else
+	emit_insn (gen_ptr_extend (this, tmp));
+    }
 
   /* Apply the constant offset, if required.  */
   if (delta)
@@ -8515,17 +8416,39 @@ ia64_output_mi_thunk (file, thunk, delta, vcall_offset, function)
       rtx vcall_offset_rtx = GEN_INT (vcall_offset);
       rtx tmp = gen_rtx_REG (Pmode, 2);
 
-      emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
+      if (TARGET_ILP32)
+	{
+	  rtx t = gen_rtx_REG (ptr_mode, 2);
+	  REG_POINTER (t) = 1;
+	  emit_move_insn (t, gen_rtx_MEM (ptr_mode, this));
+	  if (CONST_OK_FOR_I (vcall_offset))
+	    {
+	      emit_insn (gen_ptr_extend_plus_imm (tmp, t, 
+						  vcall_offset_rtx));
+	      vcall_offset = 0;
+	    }
+	  else
+	    emit_insn (gen_ptr_extend (tmp, t));
+	}
+      else
+	emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
 
-      if (!CONST_OK_FOR_J (vcall_offset))
+      if (vcall_offset)
 	{
-	  rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
-	  emit_move_insn (tmp2, vcall_offset_rtx);
-	  vcall_offset_rtx = tmp2;
+	  if (!CONST_OK_FOR_J (vcall_offset))
+	    {
+	      rtx tmp2 = gen_rtx_REG (Pmode, next_scratch_gr_reg ());
+	      emit_move_insn (tmp2, vcall_offset_rtx);
+	      vcall_offset_rtx = tmp2;
+	    }
+	  emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
 	}
-      emit_insn (gen_adddi3 (tmp, tmp, vcall_offset_rtx));
 
-      emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
+      if (TARGET_ILP32)
+	emit_move_insn (gen_rtx_REG (ptr_mode, 2), 
+			gen_rtx_MEM (ptr_mode, tmp));
+      else
+	emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
 
       emit_insn (gen_adddi3 (this, this, tmp));
     }
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index e7e1d29d613..a8bc569a7f0 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -455,7 +455,7 @@ while (0)
    64 predicate registers, 8 branch registers, one frame pointer,
    and several "application" registers.  */
 
-#define FIRST_PSEUDO_REGISTER 335
+#define FIRST_PSEUDO_REGISTER 334
 
 /* Ranges for the various kinds of registers.  */
 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3)
@@ -464,9 +464,7 @@ while (0)
 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319)
 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327)
 #define GENERAL_REGNO_P(REGNO) \
-  (GR_REGNO_P (REGNO)							\
-   || (REGNO) == FRAME_POINTER_REGNUM					\
-   || (REGNO) == RETURN_ADDRESS_POINTER_REGNUM)
+  (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM)
 
 #define GR_REG(REGNO) ((REGNO) + 0)
 #define FR_REG(REGNO) ((REGNO) + 128)
@@ -476,11 +474,11 @@ while (0)
 #define IN_REG(REGNO) ((REGNO) + 112)
 #define LOC_REG(REGNO) ((REGNO) + 32)
 
-#define AR_CCV_REGNUM	330
-#define AR_UNAT_REGNUM  331
-#define AR_PFS_REGNUM	332
-#define AR_LC_REGNUM	333
-#define AR_EC_REGNUM	334
+#define AR_CCV_REGNUM	329
+#define AR_UNAT_REGNUM  330
+#define AR_PFS_REGNUM	331
+#define AR_LC_REGNUM	332
+#define AR_EC_REGNUM	333
 
 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7))
 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79))
@@ -543,8 +541,8 @@ while (0)
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
   /* Branch registers.  */				\
   0, 0, 0, 0, 0, 0, 0, 0,				\
-  /*FP RA CCV UNAT PFS LC EC */				\
-     1, 1,  1,   1,  1, 0, 1				\
+  /*FP CCV UNAT PFS LC EC */				\
+     1,  1,   1,  1, 0, 1				\
  }
 
 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered
@@ -578,8 +576,8 @@ while (0)
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
   /* Branch registers.  */				\
   1, 0, 0, 0, 0, 0, 1, 1,				\
-  /*FP RA CCV UNAT PFS LC EC */				\
-     1, 1,  1,   1,  1, 0, 1				\
+  /*FP CCV UNAT PFS LC EC */				\
+     1,  1,   1,  1, 0, 1				\
 }
 
 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
@@ -616,8 +614,8 @@ while (0)
   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,	\
   /* Branch registers.  */				\
   1, 0, 0, 0, 0, 0, 1, 1,				\
-  /*FP RA CCV UNAT PFS LC EC */				\
-     0, 0,  1,   0,  1, 0, 0				\
+  /*FP CCV UNAT PFS LC EC */				\
+     0,  1,   0,  1, 0, 0				\
 }
 
 
@@ -763,7 +761,7 @@ while (0)
   /* Special branch registers.  */					   \
   R_BR (0),								   \
   /* Other fixed registers.  */						   \
-  FRAME_POINTER_REGNUM, RETURN_ADDRESS_POINTER_REGNUM,			   \
+  FRAME_POINTER_REGNUM, 						   \
   AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM,		   \
   AR_EC_REGNUM		  						   \
 }
@@ -892,11 +890,11 @@ enum reg_class
   /* AR_M_REGS.  */					\
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
     0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
-    0x00000000, 0x00000000, 0x0C00 },			\
+    0x00000000, 0x00000000, 0x0600 },			\
   /* AR_I_REGS.  */					\
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
     0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
-    0x00000000, 0x00000000, 0x7000 },			\
+    0x00000000, 0x00000000, 0x3800 },			\
   /* ADDL_REGS.  */					\
   { 0x0000000F, 0x00000000, 0x00000000, 0x00000000,	\
     0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
@@ -904,7 +902,7 @@ enum reg_class
   /* GR_REGS.  */					\
   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
     0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
-    0x00000000, 0x00000000, 0x0300 },			\
+    0x00000000, 0x00000000, 0x0100 },			\
   /* FR_REGS.  */					\
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
@@ -912,15 +910,15 @@ enum reg_class
   /* GR_AND_BR_REGS.  */				\
   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
     0x00000000, 0x00000000, 0x00000000, 0x00000000,	\
-    0x00000000, 0x00000000, 0x03FF },			\
+    0x00000000, 0x00000000, 0x01FF },			\
   /* GR_AND_FR_REGS.  */				\
   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
-    0x00000000, 0x00000000, 0x0300 },			\
+    0x00000000, 0x00000000, 0x0100 },			\
   /* ALL_REGS.  */					\
   { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
     0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,	\
-    0xFFFFFFFF, 0xFFFFFFFF, 0x7FFF },			\
+    0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF },			\
 }
 
 /* A C expression whose value is a register class containing hard register
@@ -1098,11 +1096,15 @@ enum reg_class
   (GET_CODE (VALUE) == MEM					\
    && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a'	\
    && (reload_in_progress || memory_operand ((VALUE), VOIDmode)))
+/* Symbol ref to small-address-area: */
+#define CONSTRAINT_OK_FOR_T(VALUE)						\
+	(GET_CODE (VALUE) == SYMBOL_REF && SYMBOL_REF_SMALL_ADDR_P (VALUE))
 
 #define EXTRA_CONSTRAINT(VALUE, C) \
   ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE)	\
    : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE)	\
    : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE)	\
+   : (C) == 'T' ? CONSTRAINT_OK_FOR_T (VALUE)	\
    : 0)
 
 /* Basic Stack Layout */
@@ -1138,7 +1140,7 @@ enum reg_class
    DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush).  */
 
 #define RETURN_ADDR_RTX(COUNT, FRAME) \
-  ((COUNT) == 0 ? return_address_pointer_rtx : const0_rtx)
+  ia64_return_addr_rtx (COUNT, FRAME)
 
 /* A C expression whose value is RTL representing the location of the incoming
    return address at the beginning of any function, before the prologue.  This
@@ -1199,13 +1201,6 @@ enum reg_class
       REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64;	\
   } while (0)
 
-/* The register number for the return address register.  For IA-64, this
-   is not actually a pointer as the name suggests, but that's a name that
-   gen_rtx_REG already takes care to keep unique.  We modify
-   return_address_pointer_rtx in ia64_expand_prologue to reference the
-   final output regnum.  */
-#define RETURN_ADDRESS_POINTER_REGNUM 329
-
 /* Register numbers used for passing a function's static chain pointer.  */
 /* ??? The ABI sez the static chain should be passed as a normal parameter.  */
 #define STATIC_CHAIN_REGNUM 15
@@ -1229,7 +1224,6 @@ enum reg_class
   {ARG_POINTER_REGNUM,	 HARD_FRAME_POINTER_REGNUM},			\
   {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},				\
   {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},			\
-  {RETURN_ADDRESS_POINTER_REGNUM, BR_REG (0)},				\
 }
 
 /* A C expression that returns nonzero if the compiler is allowed to try to
@@ -1875,8 +1869,8 @@ do {									\
   "p60", "p61", "p62", "p63",						\
   /* Branch registers.  */						\
   "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7",			\
-  /* Frame pointer.  Return address.  */				\
-  "sfp", "retaddr", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec",	\
+  /* Frame pointer.  Application registers.  */				\
+  "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec",	\
 }
 
 /* If defined, a C initializer for an array of structures containing a name and
@@ -2172,6 +2166,12 @@ do {									\
 
 /* Miscellaneous Parameters.  */
 
+/* Flag to mark data that is in the small address area (addressable
+   via "addl", that is, within a 2MByte offset of 0.  */
+#define SYMBOL_FLAG_SMALL_ADDR		(SYMBOL_FLAG_MACH_DEP << 0)
+#define SYMBOL_REF_SMALL_ADDR_P(X)	\
+	((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_SMALL_ADDR) != 0)
+
 /* Define this if you have defined special-purpose predicates in the file
    `MACHINE.c'.  For each predicate, list all rtl codes that can be in
    expressions matched by the predicate.  */
@@ -2180,6 +2180,7 @@ do {									\
 { "call_operand", {SUBREG, REG, SYMBOL_REF}},				\
 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}},		\
 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}},			\
+{ "small_addr_symbolic_operand", {SYMBOL_REF}},				\
 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}},			\
 { "function_operand", {SYMBOL_REF}},					\
 { "setjmp_operand", {SYMBOL_REF}},					\
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index d53234ea7fc..9ead0866798 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -73,6 +73,7 @@
    (UNSPEC_BUNDLE_SELECTOR	23)
    (UNSPEC_ADDP4		24)
    (UNSPEC_PROLOGUE_USE		25)
+   (UNSPEC_RET_ADDR		26)
   ])
 
 (define_constants
@@ -325,7 +326,7 @@
   [(set (match_operand:DI 0 "destination_operand"
 		    "=r,r,r,r, m, r,*f,*f,*f, Q, r,*b, r,*e, r,*d, r,*c")
 	(match_operand:DI 1 "move_operand"
-		    "rO,J,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
+		    "rO,JT,i,m,rO,*f,rO,*f, Q,*f,*b,rO,*e,rK,*d,rK,*c,rO"))]
   "ia64_move_ok (operands[0], operands[1])"
 {
   static const char * const alt[] = {
@@ -410,6 +411,25 @@
   operands[3] = pic_offset_table_rtx;
 })
 
+;; This is used as a placeholder for the return address during early
+;; compilation.  We won't know where we've placed this until during
+;; reload, at which point it can wind up in b0, a general register,
+;; or memory.  The only safe destination under these conditions is a
+;; general register.
+
+(define_insn_and_split "*movdi_ret_addr"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(const_int 0)] UNSPEC_RET_ADDR))]
+  ""
+  "#"
+  "reload_completed"
+  [(const_int 0)]
+{
+  ia64_split_return_addr_rtx (operands[0]);
+  DONE;
+}
+  [(set_attr "itanium_class" "ialu")])
+
 (define_insn "*load_symptr_high"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(plus:DI (high:DI (match_operand 1 "got_symbolic_operand" "s"))
@@ -5217,16 +5237,16 @@
 {
   static const char * const alt[2][4] = {
     {
-      "lfetch.nta [%0]",
-      "lfetch.nt1 [%0]",
-      "lfetch.nt2 [%0]",
-      "lfetch [%0]"
+      "%,lfetch.nta [%0]",
+      "%,lfetch.nt1 [%0]",
+      "%,lfetch.nt2 [%0]",
+      "%,lfetch [%0]"
     },
     {
-      "lfetch.excl.nta [%0]",
-      "lfetch.excl.nt1 [%0]",
-      "lfetch.excl.nt2 [%0]",
-      "lfetch.excl [%0]"
+      "%,lfetch.excl.nta [%0]",
+      "%,lfetch.excl.nt1 [%0]",
+      "%,lfetch.excl.nt2 [%0]",
+      "%,lfetch.excl [%0]"
     }
   };
   int i = (INTVAL (operands[1]));
@@ -5452,7 +5472,7 @@
 ;;
 ;; Optimizations for ptr_extend
 
-(define_insn "*ptr_extend_plus_1"
+(define_insn "ptr_extend_plus_imm"
   [(set (match_operand:DI 0 "gr_register_operand" "=r")
         (unspec:DI
          [(plus:SI (match_operand:SI 1 "basereg_operand" "r")
diff --git a/gcc/config/ia64/libgcc-ia64.ver b/gcc/config/ia64/libgcc-ia64.ver
index 2ffb6936864..cd769907df0 100644
--- a/gcc/config/ia64/libgcc-ia64.ver
+++ b/gcc/config/ia64/libgcc-ia64.ver
@@ -7,3 +7,6 @@ GCC_3.0 {
   __ia64_trampoline
   __ia64_backtrace
 }
+GCC_3.3.2 {
+  _Unwind_GetBSP
+}
diff --git a/gcc/config/ia64/unwind-ia64.c b/gcc/config/ia64/unwind-ia64.c
index 9b6023da58a..41f59d10b9d 100644
--- a/gcc/config/ia64/unwind-ia64.c
+++ b/gcc/config/ia64/unwind-ia64.c
@@ -1667,6 +1667,14 @@ _Unwind_GetCFA (struct _Unwind_Context *context)
   return (_Unwind_Ptr) context->psp;
 }
 
+/* Get the value of the Backing Store Pointer as saved in CONTEXT.  */
+
+_Unwind_Word
+_Unwind_GetBSP (struct _Unwind_Context *context)
+{
+  return (_Unwind_Ptr) context->bsp;
+}
+
 
 static _Unwind_Reason_Code
 uw_frame_state_for (struct _Unwind_Context *context, _Unwind_FrameState *fs)
diff --git a/gcc/config/linux.h b/gcc/config/linux.h
index 75b403057e2..2c85148c685 100644
--- a/gcc/config/linux.h
+++ b/gcc/config/linux.h
@@ -1,5 +1,6 @@
 /* Definitions for Linux-based GNU systems with ELF format
-   Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+   Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003
+   Free Software Foundation, Inc.
    Contributed by Eric Youngdale.
    Modified for stabs-in-ELF by H.J. Lu (hjl@lucon.org).
 
@@ -103,6 +104,8 @@ Boston, MA 02111-1307, USA.  */
 /* Define this so we can compile MS code for use with WINE.  */
 #define HANDLE_PRAGMA_PACK_PUSH_POP
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
 
 /* Determine whether the the entire c99 runtime
    is present in the runtime library.  */
diff --git a/gcc/config/lynx.h b/gcc/config/lynx.h
index 267f499e221..a2366d106da 100644
--- a/gcc/config/lynx.h
+++ b/gcc/config/lynx.h
@@ -1,5 +1,5 @@
 /* Target independent definitions for LynxOS using gas and gnu ld.
-   Copyright (C) 1993, 1994, 1995, 1996, 1999, 2000, 2002
+   Copyright (C) 1993, 1994, 1995, 1996, 1999, 2000, 2002, 2003
    Free Software Foundation, Inc.
 
 This file is part of GCC.
@@ -19,10 +19,7 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* LynxOS is a multi-platform Unix, similar to SVR3, but not identical.
-   We can get quite a bit from generic svr3, but have to do some overrides.  */
-
-#include "svr3.h"
+/* LynxOS is a multi-platform Unix, similar to SVR3, but not identical.  */
 
 /* Define various macros, depending on the combination of flags.  */
 
diff --git a/gcc/config/m68hc11/m68hc11.c b/gcc/config/m68hc11/m68hc11.c
index 38690ee7319..c97ea89c447 100644
--- a/gcc/config/m68hc11/m68hc11.c
+++ b/gcc/config/m68hc11/m68hc11.c
@@ -1490,7 +1490,7 @@ m68hc11_init_cumulative_args (cum, fntype, libname)
 
   ret_type = TREE_TYPE (fntype);
 
-  if (ret_type && aggregate_value_p (ret_type))
+  if (ret_type && aggregate_value_p (ret_type, fntype))
     {
       cum->words = 1;
       cum->nregs = 1;
@@ -1582,14 +1582,8 @@ m68hc11_function_arg_padding (mode, type)
   if (type != 0 && AGGREGATE_TYPE_P (type))
     return upward;
 
-  /* This is the default definition.  */
-  return (!BYTES_BIG_ENDIAN
-	  ? upward
-	  : ((mode == BLKmode
-	      ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-		 && int_size_in_bytes (type) <
-		 (PARM_BOUNDARY / BITS_PER_UNIT)) : GET_MODE_BITSIZE (mode) <
-	      PARM_BOUNDARY) ? downward : upward));
+  /* Fall back to the default.  */
+  return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
 }
 
 
diff --git a/gcc/config/m68k/coff.h b/gcc/config/m68k/coff.h
index 77be8b9743c..21699a60c78 100644
--- a/gcc/config/m68k/coff.h
+++ b/gcc/config/m68k/coff.h
@@ -22,13 +22,13 @@ Boston, MA 02111-1307, USA.  */
 /* This file is included after m68k.h by CPU COFF specific files.  It
    is not a complete target itself.  */
 
-/* Generate sdb debugging information.  */
+/* Used in m68k.c to include required support code.  */
 
-#define SDB_DEBUGGING_INFO 1
+#define M68K_TARGET_COFF 1
 
-/* Output DBX (stabs) debugging information if using -gstabs.  */
+/* Generate sdb debugging information.  */
 
-#include "dbxcoff.h"
+#define SDB_DEBUGGING_INFO 1
 
 /* COFF symbols don't start with an underscore.  */
 
@@ -57,7 +57,7 @@ Boston, MA 02111-1307, USA.  */
 
 #define ASM_RETURN_CASE_JUMP				\
   do {							\
-    if (TARGET_5200)					\
+    if (TARGET_COLDFIRE)				\
       {							\
 	if (ADDRESS_REG_P (operands[0]))		\
 	  return "jmp %%pc@(2,%0:l)";			\
@@ -74,7 +74,7 @@ Boston, MA 02111-1307, USA.  */
 #define REGISTER_NAMES \
 {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
+ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", "argptr" }
 
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
 
diff --git a/gcc/config/m68k/hp310.h b/gcc/config/m68k/hp310.h
index 4c765b89f55..1abbeaeddc9 100644
--- a/gcc/config/m68k/hp310.h
+++ b/gcc/config/m68k/hp310.h
@@ -1,10 +1,5 @@
 /* Definitions of target machine for GNU compiler.  HP-UX 68010 version.  */
 
-/* See m68k.h.  0 means 68000 without 68881 and no bitfields.  */
-#define	TARGET_DEFAULT 0
-
-#include "m68k/hp320.h"
-
 /* Don't try using XFmode.  */
 #undef LONG_DOUBLE_TYPE_SIZE
 #define LONG_DOUBLE_TYPE_SIZE 64
diff --git a/gcc/config/m68k/hp310g.h b/gcc/config/m68k/hp310g.h
deleted file mode 100644
index d5c543eb3b2..00000000000
--- a/gcc/config/m68k/hp310g.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68010 version.
-   Use this file if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)  */
-
-/* This wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO 1
-
-#define USE_GAS
-
-#include "m68k/hp310.h"
diff --git a/gcc/config/m68k/hp320.h b/gcc/config/m68k/hp320.h
index 17ce3504d9b..edfe3b9b174 100644
--- a/gcc/config/m68k/hp320.h
+++ b/gcc/config/m68k/hp320.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler.  HP-UX 68000/68020 version.
-   Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2002
+   Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2002, 2003
    Free Software Foundation, Inc.
 
 This file is part of GNU CC.
@@ -19,34 +19,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Define USE_GAS if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)
-   Undefine USE_GAS if you want GCC to feed the HP assembler.  */
-
-/* #define USE_GAS */  /* Use hp320g.h if you want this.  */
-
-/* Control assembler-syntax conditionals in m68k.md.  */
-
-#ifndef USE_GAS
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-#define HPUX_ASM
-
-#if !defined (CROSS_COMPILE) && !defined (NO_BUGS)
-/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't translate
-   floating point constants behind some operands.  The workaround is to
-   use hex constants.  Reported by Thomas Nau (nau@medizin.uni-ulm.de).  */
-#define AS_BUG_FLOATING_CONSTANT
-/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't accept
-   labels followed by a text, data, or other section directive.  Reported
-   by Thomas Nau (nau@medizin.uni-ulm.de).  */
-#define AS_BUG_TRAILING_LABEL
-#endif
-
-#endif /* not USE_GAS */
-
 /* gcc.c should find libgcc.a itself rather than expecting linker to.  */
 #define LINK_LIBGCC_SPECIAL
 /* The arguments of -L must be a separate argv element.  */
@@ -57,8 +29,6 @@ Boston, MA 02111-1307, USA.  */
 /* Be compatible with system stddef.h.  */
 #define SIZE_TYPE "unsigned int"
 
-#include "m68k/m68k.h"
-
 #undef INT_OP_GROUP
 #define INT_OP_GROUP INT_OP_NO_DOT
 
@@ -188,7 +158,7 @@ Boston, MA 02111-1307, USA.  */
 #define REGISTER_NAMES \
 {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7",	\
  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp",	\
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7"}
+ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", "argptr"}
 
 #define IMMEDIATE_PREFIX        "&"
 #define REGISTER_PREFIX         "%"
diff --git a/gcc/config/m68k/hp320base.h b/gcc/config/m68k/hp320base.h
new file mode 100644
index 00000000000..ad84d45600d
--- /dev/null
+++ b/gcc/config/m68k/hp320base.h
@@ -0,0 +1,40 @@
+/* Configuration file for an HP 320.
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* Control assembler-syntax conditionals in m68k.md.  */
+
+#ifndef USE_GAS
+#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
+#define SGS			/* Uses SGS assembler */
+#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
+#define HPUX_ASM
+
+#if !defined (CROSS_COMPILE) && !defined (NO_BUGS)
+/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't translate
+   floating point constants behind some operands.  The workaround is to
+   use hex constants.  Reported by Thomas Nau (nau@medizin.uni-ulm.de).  */
+#define AS_BUG_FLOATING_CONSTANT
+/* The assembler on HP 9k3xx machines running HPUX 8.0 doesn't accept
+   labels followed by a text, data, or other section directive.  Reported
+   by Thomas Nau (nau@medizin.uni-ulm.de).  */
+#define AS_BUG_TRAILING_LABEL
+#endif
+
+#endif /* not USE_GAS */
diff --git a/gcc/config/m68k/hp320g.h b/gcc/config/m68k/hp320g.h
deleted file mode 100644
index b20cc3d03cc..00000000000
--- a/gcc/config/m68k/hp320g.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Definitions of target machine for GNU compiler.  HP-UX 68000/68020 version.
-   Use this file if GCC is supposed to work with the GNU assembler,
-   GNU linker and GNU debugger using DBX debugging information.
-   (In other words, much of HPUX has been cast aside.)  */
-
-/* This wants DBX format.  */
-
-#define DBX_DEBUGGING_INFO 1
-
-#define USE_GAS
-
-#include "m68k/hp320.h"
diff --git a/gcc/config/m68k/hpux7.h b/gcc/config/m68k/hpux7.h
deleted file mode 100644
index ae584bde097..00000000000
--- a/gcc/config/m68k/hpux7.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/* tm.h for m68k running HPUX version 7.  */
-
-/* fletcher@cs.utexas.edu says this is needed.  */
-#define NO_DOT_IN_LABEL
-#define NO_BUGS
-
-#include "m68k/hp320.h"
diff --git a/gcc/config/m68k/lb1sf68.asm b/gcc/config/m68k/lb1sf68.asm
index 7bcee2eabe4..d424e9787f1 100644
--- a/gcc/config/m68k/lb1sf68.asm
+++ b/gcc/config/m68k/lb1sf68.asm
@@ -214,7 +214,7 @@ TRUNCDFSF    = 7
 | void __clear_sticky_bits(void);
 SYM (__clear_sticky_bit):		
 	lea	SYM (_fpCCR),a0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	movew	IMM (0),a0@(STICK)
 #else
 	clr.w	a0@(STICK)
@@ -248,7 +248,7 @@ FPTRAP = 15
 $_exception_handler:
 	lea	SYM (_fpCCR),a0
 	movew	d7,a0@(EBITS)	| set __exception_bits
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d7,a0@(STICK)	| and __sticky_bits
 #else
 	movew	a0@(STICK),d4
@@ -259,7 +259,7 @@ $_exception_handler:
 	movew	d5,a0@(LASTO)	| and __last_operation
 
 | Now put the operands in place:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (SINGLE_FLOAT),d6
 #else
 	cmpl	IMM (SINGLE_FLOAT),d6
@@ -274,7 +274,7 @@ $_exception_handler:
 	movel	a6@(12),a0@(OPER2)
 2:
 | And check whether the exception is trap-enabled:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	andw	a0@(TRAPE),d7	| is exception trap-enabled?
 #else
 	clrl	d6
@@ -284,7 +284,7 @@ $_exception_handler:
 	beq	1f		| no, exit
 	pea	SYM (_fpCCR)	| yes, push address of _fpCCR
 	trap	IMM (FPTRAP)	| and trap
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 1:	moveml	sp@+,d2-d7	| restore data registers
 #else
 1:	moveml	sp@,d2-d7
@@ -304,7 +304,7 @@ SYM (__mulsi3):
 	muluw	sp@(10), d0	/* x0*y1 */
 	movew	sp@(6), d1	/* x1 -> d1 */
 	muluw	sp@(8), d1	/* x1*y0 */
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	d1, d0
 #else
 	addl	d1, d0
@@ -323,7 +323,7 @@ SYM (__mulsi3):
 	.proc
 	.globl	SYM (__udivsi3)
 SYM (__udivsi3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	movel	d2, sp@-
 	movel	sp@(12), d1	/* d1 = divisor */
 	movel	sp@(8), d0	/* d0 = dividend */
@@ -368,7 +368,7 @@ L5:	subql	IMM (1), d0	/* adjust quotient */
 L6:	movel	sp@+, d2
 	rts
 
-#else /* __mcf5200__ */
+#else /* __mcoldfire__ */
 
 /* Coldfire implementation of non-restoring division algorithm from
    Hennessy & Patterson, Appendix A. */
@@ -390,7 +390,7 @@ L2:	subql	IMM (1),d4
 	moveml	sp@,d2-d4	| restore data registers
 	unlk	a6		| and return
 	rts
-#endif /* __mcf5200__ */
+#endif /* __mcoldfire__ */
 
 #endif /* L_udivsi3 */
 
@@ -405,7 +405,7 @@ SYM (__divsi3):
 	movel	sp@(12), d1	/* d1 = divisor */
 	jpl	L1
 	negl	d1
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	negb	d2		/* change sign because divisor <0  */
 #else
 	negl	d2		/* change sign because divisor <0  */
@@ -413,7 +413,7 @@ SYM (__divsi3):
 L1:	movel	sp@(8), d0	/* d0 = dividend */
 	jpl	L2
 	negl	d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	negb	d2
 #else
 	negl	d2
@@ -444,7 +444,7 @@ SYM (__umodsi3):
 	jbsr	SYM (__udivsi3)
 	addql	IMM (8), sp
 	movel	sp@(8), d1	/* d1 = divisor */
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	movel	d1, sp@-
 	movel	d0, sp@-
 	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
@@ -470,7 +470,7 @@ SYM (__modsi3):
 	jbsr	SYM (__divsi3)
 	addql	IMM (8), sp
 	movel	sp@(8), d1	/* d1 = divisor */
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	movel	d1, sp@-
 	movel	d0, sp@-
 	jbsr	SYM (__mulsi3)	/* d0 = (a/b)*b */
@@ -611,7 +611,7 @@ SYM (__subdf3):
 
 | double __adddf3(double, double);
 SYM (__adddf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)	| everything will be done in registers
 	moveml	d2-d7,sp@-	| save all data registers and a2 (but d0-d1)
 #else
@@ -635,7 +635,7 @@ SYM (__adddf3):
 
 	andl	IMM (0x80000000),d7 | isolate a's sign bit '
         swap	d6		| and also b's sign bit '
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	andw	IMM (0x8000),d6	|
 	orw	d6,d7		| and combine them into d7, so that a's sign '
 				| bit is in the high word and b's is in the '
@@ -662,7 +662,7 @@ SYM (__adddf3):
 	orl	d7,d0		| and put hidden bit back
 Ladddf$1:
 	swap	d4		| shift right exponent so that it starts
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (5),d4	| in bit 0 and not bit 20
 #else
 	lsrl	IMM (5),d4	| in bit 0 and not bit 20
@@ -678,7 +678,7 @@ Ladddf$1:
 	orl	d7,d2		| and put hidden bit back
 Ladddf$2:
 	swap	d5		| shift right exponent so that it starts
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (5),d5	| in bit 0 and not bit 20
 #else
 	lsrl	IMM (5),d5	| in bit 0 and not bit 20
@@ -693,7 +693,7 @@ Ladddf$2:
 | and d4-d5-d6-d7 for the second. To do this we store (temporarily) the
 | exponents in a2-a3.
 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	a2-a3,sp@-	| save the address registers
 #else
 	movel	a2,sp@-	
@@ -713,7 +713,7 @@ Ladddf$2:
 
 | Here we shift the numbers until the exponents are the same, and put 
 | the largest exponent in a2.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d4,a2		| get exponents back
 	exg	d5,a3		|
 	cmpw	d4,d5		| compare the exponents
@@ -732,7 +732,7 @@ Ladddf$2:
 | Here we have a's exponent larger than b's, so we have to shift b. We do 
 | this by using as counter d2:
 1:	movew	d4,d2		| move largest exponent to d2
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	d5,d2		| and subtract second exponent
 	exg	d4,a2		| get back the longs we saved
 	exg	d5,a3		|
@@ -746,20 +746,20 @@ Ladddf$2:
 	movel	a4,a3
 #endif
 | if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (DBL_MANT_DIG+2),d2
 #else
 	cmpl	IMM (DBL_MANT_DIG+2),d2
 #endif
 	bge	Ladddf$b$small
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (32),d2	| if difference >= 32, shift by longs
 #else
 	cmpl	IMM (32),d2	| if difference >= 32, shift by longs
 #endif
 	bge	5f
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (16),d2	| if difference >= 16, shift by words	
 #else
 	cmpl	IMM (16),d2	| if difference >= 16, shift by words	
@@ -768,7 +768,7 @@ Ladddf$2:
 	bra	3f		| enter dbra loop
 
 4:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d4
 	roxrl	IMM (1),d5
 	roxrl	IMM (1),d6
@@ -789,7 +789,7 @@ Ladddf$2:
 12:	lsrl	IMM (1),d4
 #endif
 3:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d2,4b
 #else
 	subql	IMM (1),d2
@@ -803,7 +803,7 @@ Ladddf$2:
 	movel	d5,d6
 	movel	d4,d5
 	movel	IMM (0),d4
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (32),d2
 #else
 	subl	IMM (32),d2
@@ -818,7 +818,7 @@ Ladddf$2:
 	swap	d5
 	movew	IMM (0),d4
 	swap	d4
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (16),d2
 #else
 	subl	IMM (16),d2
@@ -826,7 +826,7 @@ Ladddf$2:
 	bra	3b
 	
 9:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d4,d5
 	movew	d4,d6
 	subw	d5,d6		| keep d5 (largest exponent) in d4
@@ -845,20 +845,20 @@ Ladddf$2:
 	movel	a4,a3
 #endif
 | if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (DBL_MANT_DIG+2),d6
 #else
 	cmpl	IMM (DBL_MANT_DIG+2),d6
 #endif
 	bge	Ladddf$a$small
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (32),d6	| if difference >= 32, shift by longs
 #else
 	cmpl	IMM (32),d6	| if difference >= 32, shift by longs
 #endif
 	bge	5f
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (16),d6	| if difference >= 16, shift by words	
 #else
 	cmpl	IMM (16),d6	| if difference >= 16, shift by words	
@@ -867,7 +867,7 @@ Ladddf$2:
 	bra	3f		| enter dbra loop
 
 4:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	roxrl	IMM (1),d2
@@ -888,7 +888,7 @@ Ladddf$2:
 12:	lsrl	IMM (1),d0
 #endif
 3:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d6,4b
 #else
 	subql	IMM (1),d6
@@ -902,7 +902,7 @@ Ladddf$2:
 	movel	d1,d2
 	movel	d0,d1
 	movel	IMM (0),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (32),d6
 #else
 	subl	IMM (32),d6
@@ -917,14 +917,14 @@ Ladddf$2:
 	swap	d1
 	movew	IMM (0),d0
 	swap	d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (16),d6
 #else
 	subl	IMM (16),d6
 #endif
 	bra	3b
 Ladddf$3:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d4,a2	
 	exg	d5,a3
 #else
@@ -940,7 +940,7 @@ Ladddf$4:
 | the signs in a4.
 
 | Here we have to decide whether to add or subtract the numbers:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a0		| get the signs 
 	exg	d6,a3		| a3 is free to be used
 #else
@@ -958,7 +958,7 @@ Ladddf$4:
 	eorl	d7,d6		| compare the signs
 	bmi	Lsubdf$0	| if the signs are different we have 
 				| to subtract
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a0		| else we add the numbers
 	exg	d6,a3		|
 #else
@@ -978,7 +978,7 @@ Ladddf$4:
 	movel	a0,d7		| 
 	andl	IMM (0x80000000),d7 | d7 now has the sign
 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3	
 #else
 	movel	sp@+,a4	
@@ -992,7 +992,7 @@ Ladddf$4:
 | one more bit we check this:
 	btst	IMM (DBL_MANT_DIG+1),d0	
 	beq	1f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	roxrl	IMM (1),d2
@@ -1017,12 +1017,12 @@ Ladddf$4:
 1:
 	lea	Ladddf$5,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -1032,20 +1032,20 @@ Ladddf$4:
 	bra	Lround$to$plus
 Ladddf$5:
 | Put back the exponent and check for overflow
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (0x7ff),d4	| is the exponent big?
 #else
 	cmpl	IMM (0x7ff),d4	| is the exponent big?
 #endif
 	bge	1f
 	bclr	IMM (DBL_MANT_DIG-1),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (4),d4	| put exponent back into position
 #else
 	lsll	IMM (4),d4	| put exponent back into position
 #endif
 	swap	d0		| 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d4,d0		|
 #else
 	orl	d4,d0		|
@@ -1058,7 +1058,7 @@ Ladddf$5:
 
 Lsubdf$0:
 | Here we do the subtraction.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a0		| put sign back in a0
 	exg	d6,a3		|
 #else
@@ -1086,7 +1086,7 @@ Lsubdf$0:
 	movel	a2,d4		| return exponent to d4
 	movel	a0,d7
 	andl	IMM (0x80000000),d7 | isolate sign bit
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3	|
 #else
 	movel	sp@+,a4
@@ -1100,7 +1100,7 @@ Lsubdf$0:
 | one more bit we check this:
 	btst	IMM (DBL_MANT_DIG+1),d0	
 	beq	1f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	roxrl	IMM (1),d2
@@ -1125,12 +1125,12 @@ Lsubdf$0:
 1:
 	lea	Lsubdf$1,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -1141,13 +1141,13 @@ Lsubdf$0:
 Lsubdf$1:
 | Put back the exponent and sign (we don't have overflow). '
 	bclr	IMM (DBL_MANT_DIG-1),d0	
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (4),d4	| put exponent back into position
 #else
 	lsll	IMM (4),d4	| put exponent back into position
 #endif
 	swap	d0		| 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d4,d0		|
 #else
 	orl	d4,d0		|
@@ -1159,7 +1159,7 @@ Lsubdf$1:
 | DBL_MANT_DIG+1) we return the other (and now we don't have to '
 | check for finiteness or zero).
 Ladddf$a$small:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3	
 #else
 	movel	sp@+,a4
@@ -1170,7 +1170,7 @@ Ladddf$a$small:
 	movel	a6@(20),d1
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| restore data registers
 #else
 	moveml	sp@,d2-d7
@@ -1181,7 +1181,7 @@ Ladddf$a$small:
 	rts
 
 Ladddf$b$small:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3	
 #else
 	movel	sp@+,a4	
@@ -1192,7 +1192,7 @@ Ladddf$b$small:
 	movel	a6@(12),d1
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| restore data registers
 #else
 	moveml	sp@,d2-d7
@@ -1238,7 +1238,7 @@ Ladddf$a:
 	bra	Ld$infty		|
 	
 Ladddf$ret$1:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3	| restore regs and exit
 #else
 	movel	sp@+,a4
@@ -1251,7 +1251,7 @@ Ladddf$ret:
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
 	orl	d7,d0		| put sign bit back
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -1263,7 +1263,7 @@ Ladddf$ret:
 
 Ladddf$ret$den:
 | Return a denormalized number.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0	| shift right once more
 	roxrl	IMM (1),d1	|
 #else
@@ -1329,7 +1329,7 @@ Ladddf$nf:
 
 | double __muldf3(double, double);
 SYM (__muldf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -1370,7 +1370,7 @@ SYM (__muldf3):
 	andl	d6,d0			| isolate fraction
 	orl	IMM (0x00100000),d0	| and put hidden bit back
 	swap	d4			| I like exponents in the first byte
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (4),d4		| 
 #else
 	lsrl	IMM (4),d4		| 
@@ -1381,13 +1381,13 @@ Lmuldf$1:
 	andl	d6,d2			|
 	orl	IMM (0x00100000),d2	| and put hidden bit back
 	swap	d5			|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (4),d5		|
 #else
 	lsrl	IMM (4),d5		|
 #endif
 Lmuldf$2:				|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	d5,d4			| add exponents
 	subw	IMM (D_BIAS+1),d4	| and subtract bias (plus one)
 #else
@@ -1405,7 +1405,7 @@ Lmuldf$2:				|
 | enough to keep everything in them. So we use the address registers to keep
 | some intermediate data.
 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	a2-a3,sp@-	| save a2 and a3 for temporary use
 #else
 	movel	a2,sp@-
@@ -1416,7 +1416,7 @@ Lmuldf$2:				|
 	movel	d4,a3		| and a3 will preserve the exponent
 
 | First, shift d2-d3 so bit 20 becomes bit 31:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	rorl	IMM (5),d2	| rotate d2 5 places right
 	swap	d2		| and swap it
 	rorl	IMM (5),d3	| do the same thing with d3
@@ -1447,7 +1447,7 @@ Lmuldf$2:				|
 
 | We use a1 as counter:	
 	movel	IMM (DBL_MANT_DIG-1),a1		
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a1
 #else
 	movel	d7,a4
@@ -1456,7 +1456,7 @@ Lmuldf$2:				|
 #endif
 
 1:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a1		| put counter back in a1
 #else
 	movel	d7,a4
@@ -1470,7 +1470,7 @@ Lmuldf$2:				|
 	addl	d7,d7		|
 	addxl	d6,d6		|
 	bcc	2f		| if bit clear skip the following
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a2		|
 #else
 	movel	d7,a4
@@ -1481,7 +1481,7 @@ Lmuldf$2:				|
 	addxl	d4,d2		|
 	addxl	d7,d1		|
 	addxl	d7,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a2		| 
 #else
 	movel	d7,a4
@@ -1489,7 +1489,7 @@ Lmuldf$2:				|
 	movel	a4,a2
 #endif
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d7,a1		| put counter in d7
 	dbf	d7,1b		| decrement and branch
 #else
@@ -1501,7 +1501,7 @@ Lmuldf$2:				|
 #endif
 
 	movel	a3,d4		| restore exponent
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,a2-a3
 #else
 	movel	sp@+,a4
@@ -1520,7 +1520,7 @@ Lmuldf$2:				|
 	swap	d3
 	movew	d3,d2
 	movew	IMM (0),d3
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	roxrl	IMM (1),d2
@@ -1556,7 +1556,7 @@ Lmuldf$2:				|
 
 	btst	IMM (DBL_MANT_DIG+1-32),d0
 	beq	Lround$exit
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	addw	IMM (1),d4
@@ -1592,7 +1592,7 @@ Lmuldf$a$nf:
 | NaN, in which case we return NaN.
 Lmuldf$b$0:
 	movew	IMM (MULTIPLY),d5
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d2,d0		| put b (==0) into d0-d1
 	exg	d3,d1		| and a (with sign bit cleared) into d2-d3
 #else
@@ -1612,7 +1612,7 @@ Lmuldf$a$0:
 	bge	Ld$inop		| in case NaN or +/-INFINITY return NaN
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -1631,7 +1631,7 @@ Lmuldf$a$den:
 	andl	d6,d0
 1:	addl	d1,d1           | shift a left until bit 20 is set
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d4	| and adjust exponent
 #else
 	subl	IMM (1),d4	| and adjust exponent
@@ -1645,7 +1645,7 @@ Lmuldf$b$den:
 	andl	d6,d2
 1:	addl	d3,d3		| shift b left until bit 20 is set
 	addxl	d2,d2		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d5	| and adjust exponent
 #else
 	subql	IMM (1),d5	| and adjust exponent
@@ -1661,7 +1661,7 @@ Lmuldf$b$den:
 
 | double __divdf3(double, double);
 SYM (__divdf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -1706,7 +1706,7 @@ SYM (__divdf3):
 	andl	d6,d0		| and isolate fraction
 	orl	IMM (0x00100000),d0 | and put hidden bit back
 	swap	d4		| I like exponents in the first byte
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (4),d4	| 
 #else
 	lsrl	IMM (4),d4	| 
@@ -1717,13 +1717,13 @@ Ldivdf$1:			|
 	andl	d6,d2		|
 	orl	IMM (0x00100000),d2
 	swap	d5		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (4),d5	|
 #else
 	lsrl	IMM (4),d5	|
 #endif
 Ldivdf$2:			|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	d5,d4		| subtract exponents
 	addw	IMM (D_BIAS),d4	| and add bias
 #else
@@ -1760,7 +1760,7 @@ Ldivdf$2:			|
 	bset	d5,d6		| set the corresponding bit in d6
 3:	addl	d1,d1		| shift a by 1
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d5,1b		| and branch back
 #else
 	subql	IMM (1), d5
@@ -1782,7 +1782,7 @@ Ldivdf$2:			|
 	bset	d5,d7		| set the corresponding bit in d7
 3:	addl	d1,d1		| shift a by 1
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d5,1b		| and branch back
 #else
 	subql	IMM (1), d5
@@ -1800,7 +1800,7 @@ Ldivdf$2:			|
 	beq	3f		| if d0==d2 check d1 and d3
 2:	addl	d1,d1		| shift a by 1
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d5,1b		| and branch back
 #else
 	subql	IMM (1), d5
@@ -1816,7 +1816,7 @@ Ldivdf$2:			|
 | to it; if you don't do this the algorithm loses in some cases). '
 	movel	IMM (0),d2
 	movel	d2,d3
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (DBL_MANT_DIG),d5
 	addw	IMM (63),d5
 	cmpw	IMM (31),d5
@@ -1828,7 +1828,7 @@ Ldivdf$2:			|
 	bhi	2f
 1:	bset	d5,d3
 	bra	5f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (32),d5
 #else
 	subl	IMM (32),d5
@@ -1847,7 +1847,7 @@ Ldivdf$2:			|
 | not set:
 	btst	IMM (DBL_MANT_DIG-32+1),d0
 	beq	1f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	roxrl	IMM (1),d2
@@ -1897,7 +1897,7 @@ Ldivdf$a$0:
 	movel	d0,d1		| 
 	lea	SYM (_fpCCR),a0	| clear exception flags
 	movew	IMM (0),a0@	|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| 
 #else
 	moveml	sp@,d2-d7	| 
@@ -1945,7 +1945,7 @@ Ldivdf$a$den:
 	andl	d6,d0
 1:	addl	d1,d1		| shift a left until bit 20 is set
 	addxl	d0,d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d4	| and adjust exponent
 #else
 	subl	IMM (1),d4	| and adjust exponent
@@ -1959,7 +1959,7 @@ Ldivdf$b$den:
 	andl	d6,d2
 1:	addl	d3,d3		| shift b left until bit 20 is set
 	addxl	d2,d2
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d5	| and adjust exponent
 #else
 	subql	IMM (1),d5	| and adjust exponent
@@ -1974,7 +1974,7 @@ Lround$exit:
 | so that 2^21 <= d0 < 2^22, and the exponent is in the lower byte of d4.
 
 | First check for underlow in the exponent:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (-DBL_MANT_DIG-1),d4		
 #else
 	cmpl	IMM (-DBL_MANT_DIG-1),d4		
@@ -1987,14 +1987,14 @@ Lround$exit:
 	movel	d7,a0		|
 	movel	IMM (0),d6	| use d6-d7 to collect bits flushed right
 	movel	d6,d7		| use d6-d7 to collect bits flushed right
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (1),d4	| if the exponent is less than 1 we 
 #else
 	cmpl	IMM (1),d4	| if the exponent is less than 1 we 
 #endif
 	bge	2f		| have to shift right (denormalize)
 1:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	IMM (1),d4	| adjust the exponent
 	lsrl	IMM (1),d0	| shift right once 
 	roxrl	IMM (1),d1	|
@@ -2037,12 +2037,12 @@ Lround$exit:
 | Now call the rounding routine (which takes care of denormalized numbers):
 	lea	Lround$0,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -2058,7 +2058,7 @@ Lround$0:
 | check again for underflow!). We have to check for overflow or for a 
 | denormalized number (which also signals underflow).
 | Check for overflow (i.e., exponent >= 0x7ff).
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (0x07ff),d4
 #else
 	cmpl	IMM (0x07ff),d4
@@ -2069,14 +2069,14 @@ Lround$0:
 	beq	Ld$den
 1:
 | Put back the exponents and sign and return.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (4),d4	| exponent back to fourth byte
 #else
 	lsll	IMM (4),d4	| exponent back to fourth byte
 #endif
 	bclr	IMM (DBL_MANT_DIG-32-1),d0
 	swap	d0		| and put back exponent
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d4,d0		| 
 #else
 	orl	d4,d0		| 
@@ -2086,7 +2086,7 @@ Lround$0:
 
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -2102,7 +2102,7 @@ Lround$0:
 
 | double __negdf2(double, double);
 SYM (__negdf2):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -2128,7 +2128,7 @@ SYM (__negdf2):
 	bra	Ld$infty		
 1:	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -2150,7 +2150,7 @@ EQUAL   =  0
 
 | int __cmpdf2(double, double);
 SYM (__cmpdf2):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@- 	| save registers
 #else
@@ -2194,7 +2194,7 @@ Lcmpdf$1:
 	tstl	d6
 	bpl	1f
 | If both are negative exchange them
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d0,d2
 	exg	d1,d3
 #else
@@ -2217,7 +2217,7 @@ Lcmpdf$1:
 	bne	Lcmpdf$a$gt$b	| |b| < |a|
 | If we got here a == b.
 	movel	IMM (EQUAL),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -2228,7 +2228,7 @@ Lcmpdf$1:
 	rts
 Lcmpdf$a$gt$b:
 	movel	IMM (GREATER),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -2239,7 +2239,7 @@ Lcmpdf$a$gt$b:
 	rts
 Lcmpdf$b$gt$a:
 	movel	IMM (LESS),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -2287,7 +2287,7 @@ Lround$to$nearest:
 | Normalize shifting left until bit #DBL_MANT_DIG-32 is set or the exponent 
 | is one (remember that a denormalized number corresponds to an 
 | exponent of -D_BIAS+1).
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (1),d4	| remember that the exponent is at least one
 #else
 	cmpl	IMM (1),d4	| remember that the exponent is at least one
@@ -2297,7 +2297,7 @@ Lround$to$nearest:
 	addxl	d2,d2		|
 	addxl	d1,d1		|
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d4,1b		|
 #else
 	subql	IMM (1), d4
@@ -2325,7 +2325,7 @@ Lround$to$nearest:
 	addxl	d2,d0
 | Shift right once (because we used bit #DBL_MANT_DIG-32!).
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1		
 #else
@@ -2340,7 +2340,7 @@ Lround$to$nearest:
 | 'fraction overflow' ...).
 	btst	IMM (DBL_MANT_DIG-32),d0	
 	beq	1f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	addw	IMM (1),d4
@@ -2491,7 +2491,7 @@ SYM (__subsf3):
 
 | float __addsf3(float, float);
 SYM (__addsf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)	| everything will be done in registers
 	moveml	d2-d7,sp@-	| save all data registers but d0-d1
 #else
@@ -2551,7 +2551,7 @@ Laddsf$2:
 | same, and put the largest exponent in d6. Note that we are using two
 | registers for each number (see the discussion by D. Knuth in "Seminumerical 
 | Algorithms").
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	d6,d7		| compare exponents
 #else
 	cmpl	d6,d7		| compare exponents
@@ -2561,32 +2561,32 @@ Laddsf$2:
 1:
 	subl	d6,d7		| keep the largest exponent
 	negl	d7
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (8),d7	| put difference in lower byte
 #else
 	lsrl	IMM (8),d7	| put difference in lower byte
 #endif
 | if difference is too large we don't shift (actually, we can just exit) '
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (FLT_MANT_DIG+2),d7		
 #else
 	cmpl	IMM (FLT_MANT_DIG+2),d7		
 #endif
 	bge	Laddsf$b$small
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (16),d7	| if difference >= 16 swap
 #else
 	cmpl	IMM (16),d7	| if difference >= 16 swap
 #endif
 	bge	4f
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d7
 #else
 	subql	IMM (1), d7
 #endif
 3:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d2	| shift right second operand
 	roxrl	IMM (1),d3
 	dbra	d7,3b
@@ -2605,7 +2605,7 @@ Laddsf$2:
 	swap	d3
 	movew	d3,d2
 	swap	d2
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (16),d7
 #else
 	subl	IMM (16),d7
@@ -2613,7 +2613,7 @@ Laddsf$2:
 	bne	2b		| if still more bits, go back to normal case
 	bra	Laddsf$3
 5:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d6,d7		| exchange the exponents
 #else
 	eorl	d6,d7
@@ -2622,32 +2622,32 @@ Laddsf$2:
 #endif
 	subl	d6,d7		| keep the largest exponent
 	negl	d7		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (8),d7	| put difference in lower byte
 #else
 	lsrl	IMM (8),d7	| put difference in lower byte
 #endif
 | if difference is too large we don't shift (and exit!) '
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (FLT_MANT_DIG+2),d7		
 #else
 	cmpl	IMM (FLT_MANT_DIG+2),d7		
 #endif
 	bge	Laddsf$a$small
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (16),d7	| if difference >= 16 swap
 #else
 	cmpl	IMM (16),d7	| if difference >= 16 swap
 #endif
 	bge	8f
 6:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d7
 #else
 	subl	IMM (1),d7
 #endif
 7:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0	| shift right first operand
 	roxrl	IMM (1),d1
 	dbra	d7,7b
@@ -2666,7 +2666,7 @@ Laddsf$2:
 	swap	d1
 	movew	d1,d0
 	swap	d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (16),d7
 #else
 	subl	IMM (16),d7
@@ -2679,7 +2679,7 @@ Laddsf$2:
 
 Laddsf$3:
 | Here we have to decide whether to add or subtract the numbers
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d6,a0		| get signs back
 	exg	d7,a1		| and save the exponents
 #else
@@ -2696,7 +2696,7 @@ Laddsf$3:
 				| numbers
 
 | Here we have both positive or both negative
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d6,a0		| now we have the exponent in d6
 #else
 	movel	d6,d4
@@ -2713,7 +2713,7 @@ Laddsf$3:
 | Put the exponent, in the first byte, in d2, to use the "standard" rounding
 | routines:
 	movel	d6,d2
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (8),d2
 #else
 	lsrl	IMM (8),d2
@@ -2725,7 +2725,7 @@ Laddsf$3:
 | one more bit we check this:
 	btst	IMM (FLT_MANT_DIG+1),d0	
 	beq	1f
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 #else
@@ -2739,12 +2739,12 @@ Laddsf$3:
 1:
 	lea	Laddsf$4,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -2754,14 +2754,14 @@ Laddsf$3:
 	bra	Lround$to$plus
 Laddsf$4:
 | Put back the exponent, but check for overflow.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (0xff),d2
 #else
 	cmpl	IMM (0xff),d2
 #endif
 	bhi	1f
 	bclr	IMM (FLT_MANT_DIG-1),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (7),d2
 #else
 	lsll	IMM (7),d2
@@ -2787,7 +2787,7 @@ Lsubsf$0:
 	negl	d1
 	negxl	d0
 1:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d2,a0		| now we have the exponent in d2
 	lsrw	IMM (8),d2	| put it in the first byte
 #else
@@ -2804,12 +2804,12 @@ Lsubsf$0:
 | the rounding routines themselves.
 	lea	Lsubsf$1,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -2820,7 +2820,7 @@ Lsubsf$0:
 Lsubsf$1:
 | Put back the exponent (we can't have overflow!). '
 	bclr	IMM (FLT_MANT_DIG-1),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (7),d2
 #else
 	lsll	IMM (7),d2
@@ -2836,7 +2836,7 @@ Laddsf$a$small:
 	movel	a6@(12),d0
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| restore data registers
 #else
 	moveml	sp@,d2-d7
@@ -2850,7 +2850,7 @@ Laddsf$b$small:
 	movel	a6@(8),d0
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| restore data registers
 #else
 	moveml	sp@,d2-d7
@@ -2908,7 +2908,7 @@ Laddsf$ret:
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
 	orl	d7,d0		| put sign bit
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| restore data registers
 #else
 	moveml	sp@,d2-d7
@@ -2975,7 +2975,7 @@ Laddsf$nf:
 
 | float __mulsf3(float, float);
 SYM (__mulsf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -3010,7 +3010,7 @@ SYM (__mulsf3):
 	andl	d5,d0		| and isolate fraction
 	orl	d4,d0		| and put hidden bit back
 	swap	d2		| I like exponents in the first byte
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (7),d2	| 
 #else
 	lsrl	IMM (7),d2	| 
@@ -3021,13 +3021,13 @@ Lmulsf$1:			| number
 	andl	d5,d1		|
 	orl	d4,d1		|
 	swap	d3		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (7),d3	|
 #else
 	lsrl	IMM (7),d3	|
 #endif
 Lmulsf$2:			|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	d3,d2		| add exponents
 	subw	IMM (F_BIAS+1),d2 | and subtract bias (plus one)
 #else
@@ -3060,7 +3060,7 @@ Lmulsf$2:			|
 	addl	d5,d1		| add a
 	addxl	d4,d0
 2:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbf	d3,1b		| loop back
 #else
 	subql	IMM (1),d3
@@ -3070,7 +3070,7 @@ Lmulsf$2:			|
 | Now we have the product in d0-d1, with bit (FLT_MANT_DIG - 1) + FLT_MANT_DIG
 | (mod 32) of d0 set. The first thing to do now is to normalize it so bit 
 | FLT_MANT_DIG is set (to do the rounding).
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	rorl	IMM (6),d1
 	swap	d1
 	movew	d1,d3
@@ -3089,7 +3089,7 @@ Lmulsf$2:			|
 	lsll	IMM (8),d0
 	addl	d0,d0
 	addl	d0,d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d3,d0
 #else
 	orl	d3,d0
@@ -3099,7 +3099,7 @@ Lmulsf$2:			|
 	
 	btst	IMM (FLT_MANT_DIG+1),d0
 	beq	Lround$exit
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrl	IMM (1),d0
 	roxrl	IMM (1),d1
 	addw	IMM (1),d2
@@ -3143,7 +3143,7 @@ Lmulsf$a$0:
 	bge	Lf$inop		| if b is +/-INFINITY or NaN return NaN
 	lea	SYM (_fpCCR),a0	| else return zero
 	movew	IMM (0),a0@	| 
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7	| 
 #else
 	moveml	sp@,d2-d7
@@ -3161,7 +3161,7 @@ Lmulsf$a$den:
 	movel	IMM (1),d2
 	andl	d5,d0
 1:	addl	d0,d0		| shift a left (until bit 23 is set)
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d2	| and adjust exponent
 #else
 	subql	IMM (1),d2	| and adjust exponent
@@ -3174,7 +3174,7 @@ Lmulsf$b$den:
 	movel	IMM (1),d3
 	andl	d5,d1
 1:	addl	d1,d1		| shift b left until bit 23 is set
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d3	| and adjust exponent
 #else
 	subl	IMM (1),d3	| and adjust exponent
@@ -3189,7 +3189,7 @@ Lmulsf$b$den:
 
 | float __divsf3(float, float);
 SYM (__divsf3):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -3226,7 +3226,7 @@ SYM (__divsf3):
 	andl	d5,d0		| and isolate fraction
 	orl	d4,d0		| and put hidden bit back
 	swap	d2		| I like exponents in the first byte
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (7),d2	| 
 #else
 	lsrl	IMM (7),d2	| 
@@ -3237,13 +3237,13 @@ Ldivsf$1:			|
 	andl	d5,d1		|
 	orl	d4,d1		|
 	swap	d3		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lsrw	IMM (7),d3	|
 #else
 	lsrl	IMM (7),d3	|
 #endif
 Ldivsf$2:			|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	d3,d2		| subtract exponents
  	addw	IMM (F_BIAS),d2	| and add bias
 #else
@@ -3270,7 +3270,7 @@ Ldivsf$2:			|
 	subl	d1,d0		| if a >= b  a <-- a-b
 	beq	3f		| if a is zero, exit
 2:	addl	d0,d0		| multiply a by 2
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d3,1b
 #else
 	subql	IMM (1),d3
@@ -3282,7 +3282,7 @@ Ldivsf$2:			|
 1:	cmpl	d0,d1
 	ble	2f
 	addl	d0,d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d3,1b
 #else
 	subql	IMM(1),d3
@@ -3291,7 +3291,7 @@ Ldivsf$2:			|
 	movel	IMM (0),d1
 	bra	3f
 2:	movel	IMM (0),d1
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (FLT_MANT_DIG),d3
 	addw	IMM (31),d3
 #else
@@ -3309,7 +3309,7 @@ Ldivsf$2:			|
 	btst	IMM (FLT_MANT_DIG+1),d0		
 	beq	1f              | if it is not set, then bit 24 is set
 	lsrl	IMM (1),d0	|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	IMM (1),d2	|
 #else
 	addl	IMM (1),d2	|
@@ -3343,7 +3343,7 @@ Ldivsf$a$0:
 	movel	IMM (0),d0		| else return zero
 	lea	SYM (_fpCCR),a0		|
 	movew	IMM (0),a0@		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7		| 
 #else
 	moveml	sp@,d2-d7		| 
@@ -3375,7 +3375,7 @@ Ldivsf$a$den:
 	movel	IMM (1),d2
 	andl	d5,d0
 1:	addl	d0,d0		| shift a left until bit FLT_MANT_DIG-1 is set
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d2	| and adjust exponent
 #else
 	subl	IMM (1),d2	| and adjust exponent
@@ -3388,7 +3388,7 @@ Ldivsf$b$den:
 	movel	IMM (1),d3
 	andl	d5,d1
 1:	addl	d1,d1		| shift b left until bit FLT_MANT_DIG is set
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	subw	IMM (1),d3	| and adjust exponent
 #else
 	subl	IMM (1),d3	| and adjust exponent
@@ -3401,7 +3401,7 @@ Lround$exit:
 | This is a common exit point for __mulsf3 and __divsf3. 
 
 | First check for underlow in the exponent:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (-FLT_MANT_DIG-1),d2		
 #else
 	cmpl	IMM (-FLT_MANT_DIG-1),d2		
@@ -3412,14 +3412,14 @@ Lround$exit:
 | exponent until it becomes 1 or the fraction is zero (in the latter case 
 | we signal underflow and return zero).
 	movel	IMM (0),d6	| d6 is used temporarily
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (1),d2	| if the exponent is less than 1 we 
 #else
 	cmpl	IMM (1),d2	| if the exponent is less than 1 we 
 #endif
 	bge	2f		| have to shift right (denormalize)
 1:
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	IMM (1),d2	| adjust the exponent
 	lsrl	IMM (1),d0	| shift right once 
 	roxrl	IMM (1),d1	|
@@ -3446,12 +3446,12 @@ Lround$exit:
 | Now call the rounding routine (which takes care of denormalized numbers):
 	lea	Lround$0,a0	| to return from rounding routine
 	lea	SYM (_fpCCR),a1	| check the rounding mode
-#ifdef __mcf5200__
+#ifdef __mcoldfire__
 	clrl	d6
 #endif
 	movew	a1@(6),d6	| rounding mode in d6
 	beq	Lround$to$nearest
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (ROUND_TO_PLUS),d6
 #else
 	cmpl	IMM (ROUND_TO_PLUS),d6
@@ -3467,7 +3467,7 @@ Lround$0:
 | check again for underflow!). We have to check for overflow or for a 
 | denormalized number (which also signals underflow).
 | Check for overflow (i.e., exponent >= 255).
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (0x00ff),d2
 #else
 	cmpl	IMM (0x00ff),d2
@@ -3478,14 +3478,14 @@ Lround$0:
 	beq	Lf$den
 1:
 | Put back the exponents and sign and return.
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	lslw	IMM (7),d2	| exponent back to fourth byte
 #else
 	lsll	IMM (7),d2	| exponent back to fourth byte
 #endif
 	bclr	IMM (FLT_MANT_DIG-1),d0
 	swap	d0		| and put back exponent
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	orw	d2,d0		| 
 #else
 	orl	d2,d0
@@ -3495,7 +3495,7 @@ Lround$0:
 
 	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -3514,7 +3514,7 @@ Lround$0:
 
 | float __negsf2(float);
 SYM (__negsf2):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@-
 #else
@@ -3536,7 +3536,7 @@ SYM (__negsf2):
 	bra	Lf$infty		
 1:	lea	SYM (_fpCCR),a0
 	movew	IMM (0),a0@
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7
 #else
 	moveml	sp@,d2-d7
@@ -3558,7 +3558,7 @@ EQUAL   =  0
 
 | int __cmpsf2(float, float);
 SYM (__cmpsf2):
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	link	a6,IMM (0)
 	moveml	d2-d7,sp@- 	| save registers
 #else
@@ -3595,7 +3595,7 @@ Lcmpsf$2:
 	tstl	d6
 	bpl	1f
 | If both are negative exchange them
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	exg	d0,d1
 #else
 	movel	d0,d7
@@ -3610,7 +3610,7 @@ Lcmpsf$2:
 	bne	Lcmpsf$a$gt$b	| |b| < |a|
 | If we got here a == b.
 	movel	IMM (EQUAL),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -3619,7 +3619,7 @@ Lcmpsf$2:
 	rts
 Lcmpsf$a$gt$b:
 	movel	IMM (GREATER),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -3630,7 +3630,7 @@ Lcmpsf$a$gt$b:
 	rts
 Lcmpsf$b$gt$a:
 	movel	IMM (LESS),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	moveml	sp@+,d2-d7 	| put back the registers
 #else
 	moveml	sp@,d2-d7
@@ -3668,7 +3668,7 @@ Lround$to$nearest:
 | Normalize shifting left until bit #FLT_MANT_DIG is set or the exponent 
 | is one (remember that a denormalized number corresponds to an 
 | exponent of -F_BIAS+1).
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	cmpw	IMM (1),d2	| remember that the exponent is at least one
 #else
 	cmpl	IMM (1),d2	| remember that the exponent is at least one
@@ -3676,7 +3676,7 @@ Lround$to$nearest:
  	beq	2f		| an exponent of one means denormalized
 	addl	d1,d1		| else shift and adjust the exponent
 	addxl	d0,d0		|
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	dbra	d2,1b		|
 #else
 	subql	IMM (1),d2
@@ -3705,7 +3705,7 @@ Lround$to$nearest:
 	btst	IMM (FLT_MANT_DIG),d0	
 	beq	1f
 	lsrl	IMM (1),d0
-#ifndef __mcf5200__
+#ifndef __mcoldfire__
 	addw	IMM (1),d2
 #else
 	addql	IMM (1),d2
diff --git a/gcc/config/m68k/linux.h b/gcc/config/m68k/linux.h
index efedd4f2d1e..8178d527459 100644
--- a/gcc/config/m68k/linux.h
+++ b/gcc/config/m68k/linux.h
@@ -19,21 +19,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#define LINUX_DEFAULT_ELF
-#define MOTOROLA		/* Use Motorola syntax */
-#define USE_GAS			/* But GAS wants jbsr instead of jsr */
-
-/* TODO: convert includes to ${tm_file} list in config.gcc.  */
-#include <m68k/m68k.h>
-
-/* Make sure CC1 is undefined.  */
-#undef CC1_SPEC
-
-#include "dbxelf.h"
-#include "elfos.h"
-#include "svr4.h"
-#include <linux.h>		/* some common stuff */
-
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (68k GNU/Linux with ELF)");
 
@@ -83,7 +68,7 @@ Boston, MA 02111-1307, USA.  */
 #define REGISTER_NAMES \
 {"%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", \
  "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%sp", \
- "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7" }
+ "%fp0", "%fp1", "%fp2", "%fp3", "%fp4", "%fp5", "%fp6", "%fp7", "argptr" }
 
 #undef SIZE_TYPE
 #define SIZE_TYPE "unsigned int"
@@ -171,7 +156,7 @@ Boston, MA 02111-1307, USA.  */
 #undef ASM_OUTPUT_CASE_LABEL
 #define ASM_RETURN_CASE_JUMP				\
   do {							\
-    if (TARGET_5200)					\
+    if (TARGET_COLDFIRE)				\
       {							\
 	if (ADDRESS_REG_P (operands[0]))		\
 	  return "jmp %%pc@(2,%0:l)";			\
diff --git a/gcc/config/m68k/m68k-aout.h b/gcc/config/m68k/m68k-aout.h
index 095ec874795..cf553fbf220 100644
--- a/gcc/config/m68k/m68k-aout.h
+++ b/gcc/config/m68k/m68k-aout.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler.  "naked" 68020,
    a.out object files and debugging, version.
-   Copyright (C) 1994, 1996 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1996, 2003 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -19,11 +19,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* This comment is here to see if it will keep Sun's cpp from dying.  */
-
-#include "m68k/m68k-none.h"
-#include "m68k/m68kemb.h"
-
 #define DBX_DEBUGGING_INFO 1
 #undef SDB_DEBUGGING_INFO
 
diff --git a/gcc/config/m68k/m68k-coff.h b/gcc/config/m68k/m68k-coff.h
deleted file mode 100644
index ad08a48579b..00000000000
--- a/gcc/config/m68k/m68k-coff.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Definitions of target machine for GNU compiler.  "naked" 68020,
-   COFF object files and debugging, version.
-   Copyright (C) 1994 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define MOTOROLA	/* Use Motorola syntax rather than MIT.  */
-#ifndef  USE_GAS  /* forces jsbr instead of jsr.  */
-#define  USE_GAS
-#endif
-
-#include "m68k/m68k-none.h"
-#include "m68k/m68kemb.h"
-#include "m68k/coff.h"
-
-/* end of m68k-coff.h */
diff --git a/gcc/config/m68k/m68k-none.h b/gcc/config/m68k/m68k-none.h
index 0c9514b89ca..040122f01d2 100644
--- a/gcc/config/m68k/m68k-none.h
+++ b/gcc/config/m68k/m68k-none.h
@@ -18,25 +18,21 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#include "m68k/m68k.h"
-
 /* Default to m68k (m68020).  */
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT M68K_CPU_m68k
 #endif
 
 /* These are values set by the configure script in TARGET_CPU_DEFAULT.
-   They are ((desired value for TARGET_DEFAULT) << 4) + sequential integer.
-   See m68k.h for the values (it should really define MASK_FOO so we can
-   use them).  */
-#define M68K_CPU_m68k	((7 << 4) + 0)
-#define M68K_CPU_m68000 ((0 << 4) + 1)
-#define M68K_CPU_m68010 ((0 << 4) + 1) /* make same as m68000 */
-#define M68K_CPU_m68020 ((7 << 4) + 2)
-#define M68K_CPU_m68030 ((7 << 4) + 3)
-#define M68K_CPU_m68040 ((01007 << 4) + 4)
-#define M68K_CPU_m68302 ((0 << 4) + 5)
-#define M68K_CPU_m68332 ((1 << 4) + 6)
+   They are (sequential integer + (desired value for TARGET_DEFAULT) << 4).  */
+#define M68K_CPU_m68k	(0 + ((MASK_68020|MASK_68881|MASK_BITFIELD)<<4))
+#define M68K_CPU_m68000 (1 + (0 << 4))
+#define M68K_CPU_m68010 (1 + (0 << 4)) /* make same as m68000 */
+#define M68K_CPU_m68020 (2 + ((MASK_68020|MASK_68881|MASK_BITFIELD) << 4))
+#define M68K_CPU_m68030 (3 + ((MASK_68030|MASK_68020|MASK_68881|MASK_BITFIELD) << 4))
+#define M68K_CPU_m68040 (4 + ((MASK_68040_ONLY|MASK_68020|MASK_68881|MASK_BITFIELD) << 4))
+#define M68K_CPU_m68302 (5 + (0 << 4))
+#define M68K_CPU_m68332 (6 + (MASK_68020 << 4))
 
 /* This is tested for below, so if target wants to override this, it
    just set this first in cover file.  */
@@ -50,32 +46,26 @@ Boston, MA 02111-1307, USA.  */
    this file.  However, it's not used anywhere here because it doesn't
    seem to be necessary.  */
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68k || TARGET_CPU_DEFAULT == M68K_CPU_m68020
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68020 } -D__mc68020 -D__mc68020__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68020"
 #define CC1_CPU_DEFAULT_SPEC "-m68020"
 #else
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68000
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68000 } -D__mc68000 -D__mc68000__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68000"
 #define CC1_CPU_DEFAULT_SPEC "-m68000"
 #else
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68030
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68030 } -D__mc68030 -D__mc68030__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68030"
 #define CC1_CPU_DEFAULT_SPEC "-m68030"
 #else
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68040
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68040 } -D__mc68040 -D__mc68040__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68040"
 #define CC1_CPU_DEFAULT_SPEC "-m68040"
 #else
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68302
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68302 } -D__mc68302 -D__mc68302__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68302"
 #define CC1_CPU_DEFAULT_SPEC "-m68302"
 #else
 #if TARGET_CPU_DEFAULT == M68K_CPU_m68332
-#define CPP_CPU_DEFAULT_SPEC "%{!ansi:-Dmc68332 -Dmcpu32 } -D__mc68332 -D__mc68332__ -D__mcpu32 -D__mcpu32__"
 #define ASM_CPU_DEFAULT_SPEC "-mc68332"
 #define CC1_CPU_DEFAULT_SPEC "-m68332"
 #else
@@ -86,52 +76,12 @@ Unrecognized value in TARGET_CPU_DEFAULT.
 #endif
 #endif
 #endif
-
-/* Define __HAVE_68881__ or nothing (soft float), appropriately.  */
-#undef CPP_FPU_SPEC
-#if TARGET_DEFAULT & MASK_68881
-#define CPP_FPU_SPEC "\
-%{!mc68000:%{!m68000:%{!m68302:%{!mcpu32:%{!m68332:%{!m5200:%{!msoft-float:%{!mno-68881:-D__HAVE_68881__ }}}}}}}} \
-%{m68881:-D__HAVE_68881__ }"
-#else
-#define CPP_FPU_SPEC "\
-%{m68881:-D__HAVE_68881__ }"
-#endif
-
-/* Names to predefine in the preprocessor for this target machine.
-   Other definitions depend on what the default cpu is and switches
-   given to the compiler:
-
-   -m68000, -mc68000: define nothing else
-   -m68010: define mc68010
-   -m68020, -mc68020: define mc68020
-   -m68030: define mc68030
-   -m68040: define mc68040
-   -m68060: define mc68060
-   -m68020-40: define mc68020 mc68030 mc68040
-   -m68020-60: define mc68020 mc68030 mc68040 mc68060
-   -m68302: define mc68302 
-   -m68332: define mc68332 mcpu32
-   -mcpu32: define mcpu32
-   -m5200: define mcf5200
-   default: define as above appropriately
-
-   GCC won't automatically add __'d versions, we have to mention them
-   explicitly.  */
-
-#undef CPP_SPEC
-#define CPP_SPEC "\
-%(cpp_fpu)%{!ansi:%{m68302:-Dmc68302 }%{m68010:-Dmc68010 }%{m68020:-Dmc68020 }%{mc68020:-Dmc68020 }%{m68030:-Dmc68030 }%{m68040:-Dmc68040 }%{m68020-40:-Dmc68020 -Dmc68030 -Dmc68040 }%{m68020-60:-Dmc68020 -Dmc68030 -Dmc68040 -Dmc68060 }%{m68060:-Dmc68060 }%{mcpu32:-Dmcpu32 } %{m68332:-Dmc68332 -Dmcpu32 }%{m5200:-Dmcf5200 }} \
-%{m68302:-D__mc68302__ -D__mc68302 }%{m68010:-D__mc68010__ -D__mc68010 }%{m68020:-D__mc68020__ -D__mc68020 }%{mc68020:-D__mc68020__ -D__mc68020 }%{m68030:-D__mc68030__ -D__mc68030 }%{m68040:-D__mc68040__ -D__mc68040 }%{m68020-40:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 }%{m68020-60:-D__mc68020__ -D__mc68030__ -D__mc68040__ -D__mc68020 -D__mc68030 -D__mc68040 -D__mc68060__ -D__mc68060 }%{m68060:-D__mc68060__ -D__mc68060 }%{mcpu32:-D__mcpu32__ -D__mcpu32 }%{m68332:-D__mc68332__ -D__mc68332 -D__mcpu32__ -D__mcpu32 }%{m5200:-D__mcf5200__ -D__mcf5200 } \
-%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32: %{!m68332:%{!m5200:%(cpp_cpu_default)}}}}}}}}}}}}}} \
-%(cpp_subtarget) \
-"
 
 /* Pass flags to gas indicating which type of processor we have.  */
 
 #undef ASM_SPEC
 #define ASM_SPEC "\
-%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%(asm_cpu_default)}}}}}}}}}}}}}} \
+%{m68851}%{mno-68851}%{m68881}%{mno-68881}%{msoft-float:-mno-68881} %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}%{m68040}%{m68020-40:-mc68040} %{m68020-60:-mc68040} %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:%{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:%{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%(asm_cpu_default)}}}}}}}}}}}}}}}}}} \
 "
 
 /* cc1/cc1plus always receives all the -m flags. If the specs strings above 
@@ -152,11 +102,8 @@ Unrecognized value in TARGET_CPU_DEFAULT.
    Do not define this macro if it does not need to do anything.  */
 
 #define EXTRA_SPECS					\
-  { "cpp_cpu_default",	CPP_CPU_DEFAULT_SPEC },		\
-  { "cpp_fpu",		CPP_FPU_SPEC },			\
-  { "cpp_subtarget",	CPP_SUBTARGET_SPEC },		\
   { "asm_cpu_default",	ASM_CPU_DEFAULT_SPEC },		\
-/*{ "cc1_cpu_default",	CC1_CPU_DEFAULT__SPEC },*/	\
+  { "cc1_cpu_default",	CC1_CPU_DEFAULT_SPEC },		\
   SUBTARGET_EXTRA_SPECS
 
 #define CPP_SUBTARGET_SPEC ""
diff --git a/gcc/config/m68k/m68k-protos.h b/gcc/config/m68k/m68k-protos.h
index e0ffee80eb7..955cbf576f0 100644
--- a/gcc/config/m68k/m68k-protos.h
+++ b/gcc/config/m68k/m68k-protos.h
@@ -21,49 +21,49 @@ Boston, MA 02111-1307, USA.  */
 /* Define functions defined in aux-output.c and used in templates.  */
 
 #ifdef RTX_CODE
-extern const char *output_move_const_into_data_reg PARAMS ((rtx *));
-extern const char *output_move_simode_const PARAMS ((rtx *));
-extern const char *output_move_simode PARAMS ((rtx *));
-extern const char *output_move_himode PARAMS ((rtx *));
-extern const char *output_move_qimode PARAMS ((rtx *));
-extern const char *output_move_stricthi PARAMS ((rtx *));
-extern const char *output_move_strictqi PARAMS ((rtx *));
-extern const char *output_move_double PARAMS ((rtx *));
-extern const char *output_move_const_single PARAMS ((rtx *));
-extern const char *output_move_const_double PARAMS ((rtx *));
-extern const char *output_btst PARAMS ((rtx *, rtx, rtx, rtx, int));
-extern const char *output_scc_di PARAMS ((rtx, rtx, rtx, rtx));
-extern const char *output_addsi3 PARAMS ((rtx *));
-extern const char *output_andsi3 PARAMS ((rtx *));
-extern const char *output_iorsi3 PARAMS ((rtx *));
-extern const char *output_xorsi3 PARAMS ((rtx *));
-extern void output_dbcc_and_branch PARAMS ((rtx *));
-extern int const_uint32_operand PARAMS ((rtx, enum machine_mode));
-extern int const_sint32_operand PARAMS ((rtx, enum machine_mode));
-extern int floating_exact_log2 PARAMS ((rtx));
-extern int not_sp_operand PARAMS ((rtx, enum machine_mode));
-extern int valid_dbcc_comparison_p PARAMS ((rtx, enum machine_mode));
-extern int extend_operator PARAMS ((rtx, enum machine_mode));
-extern int strict_low_part_peephole_ok PARAMS ((enum machine_mode, rtx, rtx));
+extern HOST_WIDE_INT m68k_initial_elimination_offset (int from, int to);
+extern const char *output_move_const_into_data_reg (rtx *);
+extern const char *output_move_simode_const (rtx *);
+extern const char *output_move_simode (rtx *);
+extern const char *output_move_himode (rtx *);
+extern const char *output_move_qimode (rtx *);
+extern const char *output_move_stricthi (rtx *);
+extern const char *output_move_strictqi (rtx *);
+extern const char *output_move_double (rtx *);
+extern const char *output_move_const_single (rtx *);
+extern const char *output_move_const_double (rtx *);
+extern const char *output_btst (rtx *, rtx, rtx, rtx, int);
+extern const char *output_scc_di (rtx, rtx, rtx, rtx);
+extern const char *output_addsi3 (rtx *);
+extern const char *output_andsi3 (rtx *);
+extern const char *output_iorsi3 (rtx *);
+extern const char *output_xorsi3 (rtx *);
+extern void output_dbcc_and_branch (rtx *);
+extern int const_uint32_operand (rtx, enum machine_mode);
+extern int const_sint32_operand (rtx, enum machine_mode);
+extern int floating_exact_log2 (rtx);
+extern int not_sp_operand (rtx, enum machine_mode);
+extern int valid_dbcc_comparison_p (rtx, enum machine_mode);
+extern int extend_operator (rtx, enum machine_mode);
+extern bool strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn, rtx target);
 
 /* Functions from m68k.c used in macros.  */
-extern int symbolic_operand PARAMS ((rtx, enum machine_mode));
-extern int standard_68881_constant_p PARAMS ((rtx));
-extern int standard_sun_fpa_constant_p PARAMS ((rtx));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void notice_update_cc PARAMS ((rtx, rtx));
+extern bool symbolic_operand (rtx, enum machine_mode);
+extern int standard_68881_constant_p (rtx);
+extern void print_operand_address (FILE *, rtx);
+extern void print_operand (FILE *, rtx, int);
+extern void notice_update_cc (rtx, rtx);
 #if 0
-extern void finalize_pic PARAMS ((rtx, enum machine_mode));
+extern void finalize_pic (rtx, enum machine_mode));
 #endif
-extern int general_src_operand PARAMS ((rtx, enum machine_mode));
-extern int nonimmediate_src_operand PARAMS ((rtx, enum machine_mode));
-extern int memory_src_operand PARAMS ((rtx, enum machine_mode));
-extern int pcrel_address PARAMS ((rtx, enum machine_mode));
-extern rtx legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx));
+extern int general_src_operand (rtx, enum machine_mode);
+extern int nonimmediate_src_operand (rtx, enum machine_mode);
+extern int memory_src_operand (rtx, enum machine_mode);
+extern int pcrel_address (rtx, enum machine_mode);
+extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
 #endif /* RTX_CODE */
 
-extern int flags_in_68881 PARAMS ((void));
-extern int use_return_insn PARAMS ((void));
-extern void override_options PARAMS ((void));
-extern void init_68881_table PARAMS ((void));
+extern int flags_in_68881 (void);
+extern int use_return_insn (void);
+extern void override_options (void);
+extern void init_68881_table (void);
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index c9f879ab73c..1c3d8cc6a6e 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -49,23 +49,22 @@ Boston, MA 02111-1307, USA.  */
    if SGS_SWITCH_TABLE.  */
 int switch_table_difference_label_flag;
 
-static rtx find_addr_reg PARAMS ((rtx));
-static const char *singlemove_string PARAMS ((rtx *));
-static void m68k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void m68k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void m68k_coff_asm_named_section PARAMS ((const char *, unsigned int));
-#ifdef CTOR_LIST_BEGIN
-static void m68k_svr3_asm_out_constructor PARAMS ((rtx, int));
-#endif
+static rtx find_addr_reg (rtx);
+static const char *singlemove_string (rtx *);
+static void m68k_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void m68k_output_function_epilogue (FILE *, HOST_WIDE_INT);
+#ifdef M68K_TARGET_COFF
+static void m68k_coff_asm_named_section (const char *, unsigned int);
+#endif /* M68K_TARGET_COFF */
 #ifdef HPUX_ASM
-static void m68k_hp320_internal_label PARAMS ((FILE *, const char *, unsigned long));
-static void m68k_hp320_file_start PARAMS ((void));
-#endif
-static void m68k_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					  HOST_WIDE_INT, tree));
-static int m68k_save_reg PARAMS ((unsigned int));
-static int const_int_cost PARAMS ((rtx));
-static bool m68k_rtx_costs PARAMS ((rtx, int, int, int *));
+static void m68k_hp320_internal_label (FILE *, const char *, unsigned long);
+static void m68k_hp320_file_start (void);
+#endif
+static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+					  HOST_WIDE_INT, tree);
+static int m68k_save_reg (unsigned int);
+static int const_int_cost (rtx);
+static bool m68k_rtx_costs (rtx, int, int, int *);
 
 
 /* Alignment to use for loops and jumps */
@@ -150,7 +149,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
    `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */
 
 void
-override_options ()
+override_options (void)
 {
   int def_align;
   int i;
@@ -216,10 +215,87 @@ override_options ()
   real_format_for_mode[XFmode - QFmode] = &ieee_extended_motorola_format;
 }
 
+/* Structure describing stack frame layout. */
+struct m68k_frame {
+  HOST_WIDE_INT offset;
+  HOST_WIDE_INT size;
+  /* data and address register */
+  int reg_no;
+  unsigned int reg_mask;
+  unsigned int reg_rev_mask;
+  /* fpu registers */
+  int fpu_no;
+  unsigned int fpu_mask;
+  unsigned int fpu_rev_mask;
+  /* fpa registers */
+  int fpa_no;
+  /* offsets relative to ARG_POINTER.  */
+  HOST_WIDE_INT frame_pointer_offset;
+  HOST_WIDE_INT stack_pointer_offset;
+};
+
+static void
+m68k_compute_frame_layout (struct m68k_frame *frame)
+{
+  int regno, saved;
+  unsigned int mask, rmask;
+
+  frame->size = (get_frame_size () + 3) & -4;
+
+  mask = rmask = saved = 0;
+  for (regno = 0; regno < 16; regno++)
+    if (m68k_save_reg (regno))
+      {
+	mask |= 1 << regno;
+	rmask |= 1 << (15 - regno);
+	saved++;
+      }
+  frame->offset = saved * 4;
+  frame->reg_no = saved;
+  frame->reg_mask = mask;
+  frame->reg_rev_mask = rmask;
+
+  if (TARGET_68881 /* || TARGET_CFV4E */)
+    {
+      mask = rmask = saved = 0;
+      for (regno = 16; regno < 24; regno++)
+	if (regs_ever_live[regno] && ! call_used_regs[regno])
+	  {
+	    mask |= 1 << (23 - regno);
+	    rmask |= 1 << (regno - 16);
+	    saved++;
+	  }
+      frame->offset += saved * 12 /* (TARGET_CFV4E ? 8 : 12) */;
+      frame->fpu_no = saved;
+      frame->fpu_mask = mask;
+      frame->fpu_rev_mask = rmask;
+    }
+}
+
+HOST_WIDE_INT
+m68k_initial_elimination_offset (int from, int to)
+{
+  struct m68k_frame frame;
+
+  /* FIXME: The correct offset to compute here would appear to be
+       (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
+     but for some obscure reason, this must be 0 to get correct code.  */
+  if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
+    return 0;
+
+  m68k_compute_frame_layout (&frame);
+
+  if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    return frame.offset + frame.size + (frame_pointer_needed ? -UNITS_PER_WORD * 2 : -UNITS_PER_WORD);
+  else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
+    return frame.offset + frame.size;
+
+  abort();
+}
+
 /* Return 1 if we need to save REGNO.  */
 static int
-m68k_save_reg (regno)
-     unsigned int regno;
+m68k_save_reg (unsigned int regno)
 {
   if (flag_pic && current_function_uses_pic_offset_table
       && regno == PIC_OFFSET_TABLE_REGNUM)
@@ -257,16 +333,14 @@ m68k_save_reg (regno)
    of the order for movem!  */
 
 static void
-m68k_output_function_prologue (stream, size)
-     FILE *stream;
-     HOST_WIDE_INT size;
+m68k_output_function_prologue (FILE *stream, HOST_WIDE_INT size)
 {
   register int regno;
   register int mask = 0;
   int num_saved_regs = 0;
   HOST_WIDE_INT fsize = (size + 3) & -4;
+  HOST_WIDE_INT fsize_with_regs;
   HOST_WIDE_INT cfa_offset = INCOMING_FRAME_SP_OFFSET;
-  HOST_WIDE_INT cfa_store_offset = cfa_offset;
   
   /* If the stack limit is a symbol, we can check it here,
      before actually allocating the space.  */
@@ -282,6 +356,21 @@ m68k_output_function_prologue (stream, size)
 #endif
     }
 
+  if (TARGET_COLDFIRE)
+    {
+      /* on Coldfire add register save into initial stack frame setup, if possible */
+      for (regno = 0; regno < 16; regno++)
+        if (m68k_save_reg (regno))
+          num_saved_regs++;
+
+      if (num_saved_regs <= 2)
+        num_saved_regs = 0;
+    }
+  else
+      num_saved_regs = 0;
+
+  fsize_with_regs = fsize + num_saved_regs * 4;
+  
   if (frame_pointer_needed)
     {
       if (fsize == 0 && TARGET_68040)
@@ -299,75 +388,73 @@ m68k_output_function_prologue (stream, size)
 		   reg_names[FRAME_POINTER_REGNUM]);
 #endif
 	}
-      else if (fsize < 0x8000)
+      else if (fsize_with_regs < 0x8000)
 	{
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlink.w %s,%I%wd\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+	      asm_fprintf (stream, "\tlink.w %s,%I%wd\n",
+		reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #else
-	  asm_fprintf (stream, "\tlink %s,%I%wd\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+	      asm_fprintf (stream, "\tlink %s,%I%wd\n",
+		reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #endif
 	}
       else if (TARGET_68020)
 	{
 #ifdef MOTOROLA
 	  asm_fprintf (stream, "\tlink.l %s,%I%wd\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+		       reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #else
 	  asm_fprintf (stream, "\tlink %s,%I%wd\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+		       reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #endif
 	}
       else
 	{
-      /* Adding negative number is faster on the 68040.  */
+          /* Adding negative number is faster on the 68040.  */
 #ifdef MOTOROLA
 	  asm_fprintf (stream, "\tlink.w %s,%I0\n\tadd.l %I%wd,%Rsp\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+		       reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #else
 	  asm_fprintf (stream, "\tlink %s,%I0\n\taddl %I%wd,%Rsp\n",
-		       reg_names[FRAME_POINTER_REGNUM], -fsize);
+		       reg_names[FRAME_POINTER_REGNUM], -fsize_with_regs);
 #endif
 	}
       if (dwarf2out_do_frame ())
 	{
 	  char *l;
           l = (char *) dwarf2out_cfi_label ();   
-	  cfa_store_offset += 4;
-	  cfa_offset = cfa_store_offset;
-	  dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_store_offset);
+	  cfa_offset += 4;
+	  dwarf2out_reg_save (l, FRAME_POINTER_REGNUM, -cfa_offset);
 	  dwarf2out_def_cfa (l, FRAME_POINTER_REGNUM, cfa_offset);
-	  cfa_store_offset += fsize;
+	  cfa_offset += fsize;
 	}
     }
-  else if (fsize)
+  else if (fsize_with_regs) /* !frame_pointer_needed */
     {
-      if (fsize + 4 < 0x8000)
+      if (fsize_with_regs < 0x8000)
 	{
-#ifndef NO_ADDSUB_Q
-	  if (fsize + 4 <= 8)
+	  if (fsize_with_regs <= 8)
 	    {
-	      if (!TARGET_5200)
+	      if (!TARGET_COLDFIRE)
 		{
 		  /* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-		  asm_fprintf (stream, "\tsubq.w %I%wd,%Rsp\n", fsize + 4);
+		  asm_fprintf (stream, "\tsubq.w %I%wd,%Rsp\n", fsize_with_regs);
 #else
-		  asm_fprintf (stream, "\tsubqw %I%wd,%Rsp\n", fsize + 4);
+		  asm_fprintf (stream, "\tsubqw %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 		}
 	      else
 		{
 		  /* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-		  asm_fprintf (stream, "\tsubq.l %I%wd,%Rsp\n", fsize + 4);
+		  asm_fprintf (stream, "\tsubq.l %I%wd,%Rsp\n", fsize_with_regs);
 #else
-		  asm_fprintf (stream, "\tsubql %I%wd,%Rsp\n", fsize + 4);
+		  asm_fprintf (stream, "\tsubql %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 		}
 	    }
-	  else if (fsize + 4 <= 16 && TARGET_CPU32)
+	  else if (fsize_with_regs <= 16 && TARGET_CPU32)
 	    {
 	      /* On the CPU32 it is faster to use two subqw instructions to
 		 subtract a small integer (8 < N <= 16) to a register.  */
@@ -375,49 +462,48 @@ m68k_output_function_prologue (stream, size)
 #ifdef MOTOROLA
 	      asm_fprintf (stream,
 			   "\tsubq.w %I8,%Rsp\n\tsubq.w %I%wd,%Rsp\n",
-			   fsize + 4 - 8);
+			   fsize_with_regs - 8);
 #else
 	      asm_fprintf (stream, "\tsubqw %I8,%Rsp\n\tsubqw %I%wd,%Rsp\n",
-			   fsize + 4 - 8);
+			   fsize_with_regs - 8);
 #endif
 	    }
-	  else 
-#endif /* not NO_ADDSUB_Q */
-	  if (TARGET_68040)
+	  else if (TARGET_68040)
 	    {
 	      /* Adding negative number is faster on the 68040.  */
 	      /* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", - (fsize + 4));
+	      asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", -fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", - (fsize + 4));
+	      asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", -fsize_with_regs);
 #endif
 	    }
 	  else
 	    {
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", - (fsize + 4));
+	      asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", -fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", - (fsize + 4));
+	      asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", -fsize_with_regs);
 #endif
 	    }
 	}
-      else
+      else /* fsize_with_regs >= 0x8000 */
 	{
-	/* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", - (fsize + 4));
+	  asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", -fsize_with_regs);
 #else
-	  asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", - (fsize + 4));
+	  asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", -fsize_with_regs);
 #endif
 	}
       if (dwarf2out_do_frame ())
 	{
-	  cfa_store_offset += fsize + 4;
-	  cfa_offset = cfa_store_offset;
+	  cfa_offset += fsize + 4;
 	  dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, cfa_offset);
 	}
-    }
+    } /* !frame_pointer_needed */
+
+  num_saved_regs = 0;
+
   if (TARGET_68881)
     {
       for (regno = 16; regno < 24; regno++)
@@ -438,16 +524,13 @@ m68k_output_function_prologue (stream, size)
 	      char *l = (char *) dwarf2out_cfi_label ();
 	      int n_regs;
 
-	      cfa_store_offset += num_saved_regs * 12;
+	      cfa_offset += num_saved_regs * 12;
 	      if (! frame_pointer_needed)
-		{
-		  cfa_offset = cfa_store_offset;
-		  dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
-		}
+		dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
 	      for (regno = 16, n_regs = 0; regno < 24; regno++)
 		if (mask & (1 << (regno - 16)))
 		  dwarf2out_reg_save (l, regno,
-				      -cfa_store_offset + n_regs++ * 12);
+				      -cfa_offset + n_regs++ * 12);
 	    }
 	}
       mask = 0;
@@ -502,29 +585,24 @@ m68k_output_function_prologue (stream, size)
 	      {
 		char *l = (char *) dwarf2out_cfi_label ();
 
-		cfa_store_offset += 4;
+		cfa_offset += 4;
  		if (! frame_pointer_needed)
- 		  {
- 		    cfa_offset = cfa_store_offset;
- 		    dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
- 		  }
- 		dwarf2out_reg_save (l, 15 - i, -cfa_store_offset);
+ 		  dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
+ 		dwarf2out_reg_save (l, 15 - i, -cfa_offset);
 	      }
 	  }
     }
   else if (mask)
     {
-      if (TARGET_5200)
+      if (TARGET_COLDFIRE)
 	{
 	  /* The coldfire does not support the predecrement form of the 
 	     movml instruction, so we must adjust the stack pointer and
 	     then use the plain address register indirect mode.  We also
 	     have to invert the register save mask to use the new mode.
 
-	     FIXME: if num_saved_regs was calculated earlier, we could
-	     combine the stack pointer adjustment with any adjustment
-	     done when the initial stack frame is created.  This would
-	     save an instruction */
+	     The required register save space was combined earlier with
+	     the fsize amount.  Don't add it again.  */
 	     
 	  int newmask = 0;
 	  int i;
@@ -534,10 +612,8 @@ m68k_output_function_prologue (stream, size)
 		newmask |= (1 << (15-i));
 
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs*4);
 	  asm_fprintf (stream, "\tmovm.l %I0x%x,(%Rsp)\n", newmask);
 #else
-	  asm_fprintf (stream, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs*4);
 	  asm_fprintf (stream, "\tmoveml %I0x%x,%Rsp@\n", newmask);
 #endif
 	}
@@ -554,16 +630,13 @@ m68k_output_function_prologue (stream, size)
 	  char *l = (char *) dwarf2out_cfi_label ();
 	  int n_regs;
 
-	  cfa_store_offset += num_saved_regs * 4;
+	  cfa_offset += num_saved_regs * 4;
 	  if (! frame_pointer_needed)
-	    {
-	      cfa_offset = cfa_store_offset;
-	      dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
-	    }
+	    dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, cfa_offset);
 	  for (regno = 0, n_regs = 0; regno < 16; regno++)
 	    if (mask & (1 << (15 - regno)))
 	      dwarf2out_reg_save (l, regno,
-				  -cfa_store_offset + n_regs++ * 4);
+				  -cfa_offset + n_regs++ * 4);
 	}
     }
   if (flag_pic && current_function_uses_pic_offset_table)
@@ -572,7 +645,7 @@ m68k_output_function_prologue (stream, size)
       asm_fprintf (stream, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
 		   reg_names[PIC_OFFSET_TABLE_REGNUM]);
 #else
-      asm_fprintf (stream, "\tmovel %I__GLOBAL_OFFSET_TABLE_, %s\n",
+      asm_fprintf (stream, "\tmovel %I%U_GLOBAL_OFFSET_TABLE_, %s\n",
 		   reg_names[PIC_OFFSET_TABLE_REGNUM]);
       asm_fprintf (stream, "\tlea %Rpc@(0,%s:l),%s\n",
 		   reg_names[PIC_OFFSET_TABLE_REGNUM],
@@ -607,15 +680,14 @@ use_return_insn ()
    omit stack adjustments before returning.  */
 
 static void
-m68k_output_function_epilogue (stream, size)
-     FILE *stream;
-     HOST_WIDE_INT size;
+m68k_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
 {
   register int regno;
   register int mask, fmask;
   register int nregs;
   HOST_WIDE_INT offset, foffset;
   HOST_WIDE_INT fsize = (size + 3) & -4;
+  HOST_WIDE_INT fsize_with_regs;
   int big = 0;
   rtx insn = get_last_insn ();
   int restore_from_sp = 0;
@@ -658,18 +730,45 @@ m68k_output_function_epilogue (stream, size)
      stack adjustment needed at that point.  */
   restore_from_sp = ! frame_pointer_needed
 	     || (! current_function_calls_alloca && leaf_function_p ());
+
+  /* fsize_with_regs is the size we need to adjust the sp when
+     popping the frame */
+  fsize_with_regs = fsize;
+
+  /* Because the ColdFire doesn't support moveml with
+     complex address modes, we must adjust the stack manually
+     after restoring registers. When the frame pointer isn't used,
+     we can merge movem adjustment into frame unlinking
+     made immediately after it. */
+  if (TARGET_COLDFIRE && restore_from_sp && (nregs > 2))
+    fsize_with_regs += nregs * 4;
+
   if (offset + fsize >= 0x8000
       && ! restore_from_sp
       && (mask || fmask))
     {
+      /* Because the ColdFire doesn't support moveml with
+         complex address modes we make an extra correction here */
+      if (TARGET_COLDFIRE)
+        {
+#ifdef MOTOROLA
+          asm_fprintf (stream, "\t%Omove.l %I%d,%Ra1\n", -fsize - offset);
+#else
+          asm_fprintf (stream, "\tmovel %I%d,%Ra1\n", -fsize - offset);
+#endif
+        }
+      else
+        {
 #ifdef MOTOROLA
-      asm_fprintf (stream, "\t%Omove.l %I%wd,%Ra1\n", -fsize);
+          asm_fprintf (stream, "\t%Omove.l %I%wd,%Ra1\n", -fsize);
 #else
-      asm_fprintf (stream, "\tmovel %I%wd,%Ra1\n", -fsize);
+          asm_fprintf (stream, "\tmovel %I%wd,%Ra1\n", -fsize);
 #endif
+        }
+
       fsize = 0, big = 1;
     }
-  if (TARGET_5200 || nregs <= 2)
+  if (nregs <= 2)
     {
       /* Restore each separately in the same order moveml does.
          Using two movel instructions instead of a single moveml
@@ -713,10 +812,9 @@ m68k_output_function_epilogue (stream, size)
 			     reg_names[FRAME_POINTER_REGNUM],
 			     reg_names[i]);
 #else
-		fprintf (stream,
-			 "\tmovel %s@(-" HOST_WIDE_INT_PRINT_DEC "),%s\n",
-			 reg_names[FRAME_POINTER_REGNUM],
-			 offset + fsize, reg_names[i]);
+		asm_fprintf (stream, "\tmovel %s@(-%wd),%s\n",
+			     reg_names[FRAME_POINTER_REGNUM],
+			     offset + fsize, reg_names[i]);
 #endif
 	      }
             offset = offset - 4;
@@ -724,39 +822,77 @@ m68k_output_function_epilogue (stream, size)
     }
   else if (mask)
     {
-      if (big)
-	{
+      /* The ColdFire requires special handling due to its limited moveml insn */
+      if (TARGET_COLDFIRE)
+        {
+          if (big)
+            {
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
-		       offset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       mask);
+              asm_fprintf (stream, "\tadd.l %s,%Ra1\n", reg_names[FRAME_POINTER_REGNUM]);
+              asm_fprintf (stream, "\tmovm.l (%Ra1),%I0x%x\n", mask);
 #else
-	  asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       offset + fsize, mask);
+              asm_fprintf (stream, "\taddl %s,%Ra1\n", reg_names[FRAME_POINTER_REGNUM]);
+              asm_fprintf (stream, "\tmoveml %Ra1@,%I0x%x\n", mask);
 #endif
-	}
-      else if (restore_from_sp)
-	{
+	     }
+	   else if (restore_from_sp)
+	     {
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l (%Rsp)+,%I0x%x\n", mask);
+	       asm_fprintf (stream, "\tmovm.l (%Rsp),%I0x%x\n", mask);
 #else
-	  asm_fprintf (stream, "\tmoveml %Rsp@+,%I0x%x\n", mask);
+	       asm_fprintf (stream, "\tmoveml %Rsp@,%I0x%x\n", mask);
 #endif
-	}
-      else
+            }
+          else
+            {
+#ifdef MOTOROLA
+              asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
+                           offset + fsize,
+                           reg_names[FRAME_POINTER_REGNUM],
+                           mask);
+#else
+              asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
+                           reg_names[FRAME_POINTER_REGNUM],
+                           offset + fsize, mask);
+#endif
+	    }
+        }
+      else /* !TARGET_COLDFIRE */
 	{
+	  if (big)
+	    {
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
-		       offset + fsize,
-		       reg_names[FRAME_POINTER_REGNUM],
-		       mask);
+	      asm_fprintf (stream, "\tmovm.l -%wd(%s,%Ra1.l),%I0x%x\n",
+			   offset + fsize,
+			   reg_names[FRAME_POINTER_REGNUM],
+			   mask);
 #else
-	  asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
-		       reg_names[FRAME_POINTER_REGNUM],
-		       offset + fsize, mask);
+	      asm_fprintf (stream, "\tmoveml %s@(-%wd,%Ra1:l),%I0x%x\n",
+			   reg_names[FRAME_POINTER_REGNUM],
+			   offset + fsize, mask);
+#endif
+	    }
+	  else if (restore_from_sp)
+	    {
+#ifdef MOTOROLA
+	      asm_fprintf (stream, "\tmovm.l (%Rsp)+,%I0x%x\n", mask);
+#else
+	      asm_fprintf (stream, "\tmoveml %Rsp@+,%I0x%x\n", mask);
+#endif
+	    }
+	  else
+	    {
+#ifdef MOTOROLA
+	      asm_fprintf (stream, "\tmovm.l -%wd(%s),%I0x%x\n",
+			   offset + fsize,
+			   reg_names[FRAME_POINTER_REGNUM],
+			   mask);
+#else
+	      asm_fprintf (stream, "\tmoveml %s@(-%wd),%I0x%x\n",
+			   reg_names[FRAME_POINTER_REGNUM],
+			   offset + fsize, mask);
 #endif
+	    }
 	}
     }
   if (fmask)
@@ -799,60 +935,57 @@ m68k_output_function_epilogue (stream, size)
   if (frame_pointer_needed)
     fprintf (stream, "\tunlk %s\n",
 	     reg_names[FRAME_POINTER_REGNUM]);
-  else if (fsize)
+  else if (fsize_with_regs)
     {
-#ifndef NO_ADDSUB_Q
-      if (fsize + 4 <= 8) 
+      if (fsize_with_regs <= 8)
 	{
-	  if (!TARGET_5200)
+	  if (!TARGET_COLDFIRE)
 	    {
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\taddq.w %I%wd,%Rsp\n", fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\taddqw %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\taddqw %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 	    }
-	  else
+	  else /* TARGET_COLDFIRE */
 	    {
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\taddq.l %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\taddq.l %I%wd,%Rsp\n", fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\taddql %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\taddql %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 	    }
 	}
-      else if (fsize + 4 <= 16 && TARGET_CPU32)
+      else if (fsize_with_regs <= 16 && TARGET_CPU32)
 	{
 	  /* On the CPU32 it is faster to use two addqw instructions to
 	     add a small integer (8 < N <= 16) to a register.  */
 	  /* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
 	  asm_fprintf (stream, "\taddq.w %I8,%Rsp\n\taddq.w %I%wd,%Rsp\n",
-		       fsize + 4 - 8);
+		       fsize_with_regs - 8);
 #else
 	  asm_fprintf (stream, "\taddqw %I8,%Rsp\n\taddqw %I%wd,%Rsp\n",
-		       fsize + 4 - 8);
+		       fsize_with_regs - 8);
 #endif
 	}
-      else
-#endif /* not NO_ADDSUB_Q */
-      if (fsize + 4 < 0x8000)
+      else if (fsize_with_regs < 0x8000)
 	{
 	  if (TARGET_68040)
 	    { 
 	      /* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\tadd.w %I%wd,%Rsp\n", fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\taddw %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 	    }
 	  else
 	    {
 #ifdef MOTOROLA
-	      asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\tlea (%wd,%Rsp),%Rsp\n", fsize_with_regs);
 #else
-	      asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", fsize + 4);
+	      asm_fprintf (stream, "\tlea %Rsp@(%wd),%Rsp\n", fsize_with_regs);
 #endif
 	    }
 	}
@@ -860,9 +993,9 @@ m68k_output_function_epilogue (stream, size)
 	{
 	/* asm_fprintf() cannot handle %.  */
 #ifdef MOTOROLA
-	  asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", fsize + 4);
+	  asm_fprintf (stream, "\tadd.l %I%wd,%Rsp\n", fsize_with_regs);
 #else
-	  asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", fsize + 4);
+	  asm_fprintf (stream, "\taddl %I%wd,%Rsp\n", fsize_with_regs);
 #endif
 	}
     }
@@ -883,14 +1016,12 @@ m68k_output_function_epilogue (stream, size)
 /* Similar to general_operand, but exclude stack_pointer_rtx.  */
 
 int
-not_sp_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+not_sp_operand (rtx op, enum machine_mode mode)
 {
   return op != stack_pointer_rtx && nonimmediate_operand (op, mode);
 }
 
-/* Return TRUE if X is a valid comparison operator for the dbcc 
+/* Return true if X is a valid comparison operator for the dbcc 
    instruction.  
 
    Note it rejects floating point comparison operators.
@@ -899,9 +1030,7 @@ not_sp_operand (op, mode)
    It also rejects some comparisons when CC_NO_OVERFLOW is set.  */
    
 int
-valid_dbcc_comparison_p (x, mode)
-     rtx x;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+valid_dbcc_comparison_p (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (x))
     {
@@ -920,7 +1049,7 @@ valid_dbcc_comparison_p (x, mode)
 
 /* Return nonzero if flags are currently in the 68881 flag register.  */
 int
-flags_in_68881 ()
+flags_in_68881 (void)
 {
   /* We could add support for these in the future */
   return cc_status.flags & CC_IN_68881;
@@ -933,8 +1062,7 @@ flags_in_68881 ()
    kick those out before we get here.  */
 
 void
-output_dbcc_and_branch (operands)
-     rtx *operands;
+output_dbcc_and_branch (rtx *operands)
 {
   switch (GET_CODE (operands[3]))
     {
@@ -1043,11 +1171,7 @@ output_dbcc_and_branch (operands)
 }
 
 const char *
-output_scc_di(op, operand1, operand2, dest)
-     rtx op;
-     rtx operand1;
-     rtx operand2;
-     rtx dest;
+output_scc_di(rtx op, rtx operand1, rtx operand2, rtx dest)
 {
   rtx loperands[7];
   enum rtx_code op_code = GET_CODE (op);
@@ -1098,7 +1222,7 @@ output_scc_di(op, operand1, operand2, dest)
     }
   else
     {
-      if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[0]))
+      if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
 	output_asm_insn ("tst%.l %0", loperands);
       else
 	{
@@ -1115,7 +1239,7 @@ output_scc_di(op, operand1, operand2, dest)
       output_asm_insn ("jne %l4", loperands);
 #endif
 
-      if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (loperands[1]))
+      if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
 	output_asm_insn ("tst%.l %1", loperands);
       else
 	{
@@ -1230,11 +1354,7 @@ output_scc_di(op, operand1, operand2, dest)
 }
 
 const char *
-output_btst (operands, countop, dataop, insn, signpos)
-     rtx *operands;
-     rtx countop, dataop;
-     rtx insn;
-     int signpos;
+output_btst (rtx *operands, rtx countop, rtx dataop, rtx insn, int signpos)
 {
   operands[0] = countop;
   operands[1] = dataop;
@@ -1272,19 +1392,17 @@ output_btst (operands, countop, dataop, insn, signpos)
   return "btst %0,%1";
 }
 
-/* Returns 1 if OP is either a symbol reference or a sum of a symbol
+/* Returns true if OP is either a symbol reference or a sum of a symbol
    reference and a constant.  */
 
-int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+bool
+symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
     case SYMBOL_REF:
     case LABEL_REF:
-      return 1;
+      return true;
 
     case CONST:
       op = XEXP (op, 0);
@@ -1299,16 +1417,14 @@ symbolic_operand (op, mode)
 #endif
 
     default:
-      return 0;
+      return false;
     }
 }
 
 /* Check for sign_extend or zero_extend.  Used for bit-count operands.  */
 
 int
-extend_operator(x, mode)
-     rtx x;
-     enum machine_mode mode;
+extend_operator(rtx x, enum machine_mode mode)
 {
     if (mode != VOIDmode && GET_MODE(x) != mode)
 	return 0;
@@ -1364,9 +1480,8 @@ extend_operator(x, mode)
    handled.  */
 
 rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig, reg;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
+		        rtx reg)
 {
   rtx pic_ref = orig;
 
@@ -1416,13 +1531,12 @@ legitimize_pic_address (orig, mode, reg)
 
 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ } CONST_METHOD;
 
-static CONST_METHOD const_method PARAMS ((rtx));
+static CONST_METHOD const_method (rtx);
 
 #define USE_MOVQ(i)	((unsigned)((i) + 128) <= 255)
 
 static CONST_METHOD
-const_method (constant)
-     rtx constant;
+const_method (rtx constant)
 {
   int i;
   unsigned u;
@@ -1433,7 +1547,7 @@ const_method (constant)
 
   /* The Coldfire doesn't have byte or word operations.  */
   /* FIXME: This may not be useful for the m68060 either */
-  if (!TARGET_5200) 
+  if (!TARGET_COLDFIRE) 
     {
       /* if -256 < N < 256 but N is not in range for a moveq
 	 N^ff will be, so use moveq #N^ff, dreg; not.b dreg.  */
@@ -1455,8 +1569,7 @@ const_method (constant)
 }
 
 static int
-const_int_cost (constant)
-     rtx constant;
+const_int_cost (rtx constant)
 {
   switch (const_method (constant))
     {
@@ -1477,10 +1590,7 @@ const_int_cost (constant)
 }
 
 static bool
-m68k_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code;
-     int *total;
+m68k_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   switch (code)
     {
@@ -1514,9 +1624,10 @@ m68k_rtx_costs (x, code, outer_code, total)
        for add and the time for shift, taking away a little more because
        sometimes move insns are needed.  */
     /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms.  */
-#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : 13)
-#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5)
-#define DIVW_COST (TARGET_68020 ? 27 : 12)
+#define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
+#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
+			TARGET_CFV3 ? 2 : 5)
+#define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
 
     case PLUS:
       /* An lea costs about three times as much as a simple add.  */
@@ -1528,7 +1639,11 @@ m68k_rtx_costs (x, code, outer_code, total)
 	  && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
 	      || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
 	      || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
-	*total = COSTS_N_INSNS (3);	 /* lea an@(dx:l:i),am */
+	{
+	    /* lea an@(dx:l:i),am */
+	    *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
+	    return true;
+	}
       return false;
 
     case ASHIFT:
@@ -1539,7 +1654,7 @@ m68k_rtx_costs (x, code, outer_code, total)
           *total = COSTS_N_INSNS(1);
 	  return true;
 	}
-      if (! TARGET_68020)
+      if (! TARGET_68020 && ! TARGET_COLDFIRE)
         {
 	  if (GET_CODE (XEXP (x, 1)) == CONST_INT)
 	    {
@@ -1564,7 +1679,7 @@ m68k_rtx_costs (x, code, outer_code, total)
 	  && !(INTVAL (XEXP (x, 1)) > 0
 	       && INTVAL (XEXP (x, 1)) <= 8))
 	{
-	  *total = COSTS_N_INSNS (3);	 /* lsr #i,dn */
+	  *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3);	 /* lsr #i,dn */
 	  return true;
 	}
       return false;
@@ -1586,6 +1701,8 @@ m68k_rtx_costs (x, code, outer_code, total)
     case UMOD:
       if (GET_MODE (x) == QImode || GET_MODE (x) == HImode)
         *total = COSTS_N_INSNS (DIVW_COST);	/* div.w */
+      else if (TARGET_CF_HWDIV)
+        *total = COSTS_N_INSNS (18);
       else
 	*total = COSTS_N_INSNS (43);		/* div.l */
       return true;
@@ -1596,8 +1713,7 @@ m68k_rtx_costs (x, code, outer_code, total)
 }
 
 const char *
-output_move_const_into_data_reg (operands)
-     rtx *operands;
+output_move_const_into_data_reg (rtx *operands)
 {
   int i;
 
@@ -1605,41 +1721,21 @@ output_move_const_into_data_reg (operands)
   switch (const_method (operands[1]))
     {
     case MOVQ :
-#if defined (MOTOROLA)
-      return "moveq%.l %1,%0";
-#else
       return "moveq %1,%0";
-#endif
     case NOTB :
       operands[1] = GEN_INT (i ^ 0xff);
-#if defined (MOTOROLA)
-      return "moveq%.l %1,%0\n\tnot%.b %0";
-#else
       return "moveq %1,%0\n\tnot%.b %0";
-#endif	 
     case NOTW :
       operands[1] = GEN_INT (i ^ 0xffff);
-#if defined (MOTOROLA)
-      return "moveq%.l %1,%0\n\tnot%.w %0";
-#else
       return "moveq %1,%0\n\tnot%.w %0";
-#endif	 
     case NEGW :
-#if defined (MOTOROLA)
-      return "moveq%.l %#-128,%0\n\tneg%.w %0";
-#else
       return "moveq %#-128,%0\n\tneg%.w %0";
-#endif	 
     case SWAP :
       {
 	unsigned u = i;
 
 	operands[1] = GEN_INT ((u << 16) | (u >> 16));
-#if defined (MOTOROLA)
-	return "moveq%.l %1,%0\n\tswap %0";
-#else
 	return "moveq %1,%0\n\tswap %0";
-#endif	 
       }
     case MOVL :
 	return "move%.l %1,%0";
@@ -1649,15 +1745,14 @@ output_move_const_into_data_reg (operands)
 }
 
 const char *
-output_move_simode_const (operands)
-     rtx *operands;
+output_move_simode_const (rtx *operands)
 {
   if (operands[1] == const0_rtx
       && (DATA_REG_P (operands[0])
 	  || GET_CODE (operands[0]) == MEM)
       /* clr insns on 68000 read before writing.
 	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
+      && ((TARGET_68020 || TARGET_COLDFIRE)
 	  || !(GET_CODE (operands[0]) == MEM
 	       && MEM_VOLATILE_P (operands[0]))))
     return "clr%.l %0";
@@ -1680,8 +1775,7 @@ output_move_simode_const (operands)
 }
 
 const char *
-output_move_simode (operands)
-     rtx *operands;
+output_move_simode (rtx *operands)
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     return output_move_simode_const (operands);
@@ -1697,8 +1791,7 @@ output_move_simode (operands)
 }
 
 const char *
-output_move_himode (operands)
-     rtx *operands;
+output_move_himode (rtx *operands)
 {
  if (GET_CODE (operands[1]) == CONST_INT)
     {
@@ -1707,7 +1800,7 @@ output_move_himode (operands)
 	      || GET_CODE (operands[0]) == MEM)
 	  /* clr insns on 68000 read before writing.
 	     This isn't so on the 68010, but we have no TARGET_68010.  */
-	  && ((TARGET_68020 || TARGET_5200)
+	  && ((TARGET_68020 || TARGET_COLDFIRE)
 	      || !(GET_CODE (operands[0]) == MEM
 		   && MEM_VOLATILE_P (operands[0]))))
 	return "clr%.w %0";
@@ -1718,11 +1811,7 @@ output_move_himode (operands)
 	       && INTVAL (operands[1]) < 128
 	       && INTVAL (operands[1]) >= -128)
 	{
-#if defined(MOTOROLA)
-	  return "moveq%.l %1,%0";
-#else
 	  return "moveq %1,%0";
-#endif
 	}
       else if (INTVAL (operands[1]) < 0x8000
 	       && INTVAL (operands[1]) >= -0x8000)
@@ -1730,7 +1819,6 @@ output_move_himode (operands)
     }
   else if (CONSTANT_P (operands[1]))
     return "move%.l %1,%0";
-#ifndef SGS_NO_LI
   /* Recognize the insn before a tablejump, one that refers
      to a table of offsets.  Such an insn will need to refer
      to a label on the insn.  So output one.  Use the label-number
@@ -1761,13 +1849,11 @@ output_move_himode (operands)
 #endif /* SGS_SWITCH_TABLES */
 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
     }
-#endif /* SGS_NO_LI */
   return "move%.w %1,%0";
 }
 
 const char *
-output_move_qimode (operands)
-     rtx *operands;
+output_move_qimode (rtx *operands)
 {
   rtx xoperands[4];
 
@@ -1779,7 +1865,7 @@ output_move_qimode (operands)
       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
       && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
       && ! ADDRESS_REG_P (operands[1])
-      && ! TARGET_5200)
+      && ! TARGET_COLDFIRE)
     {
       xoperands[1] = operands[1];
       xoperands[2]
@@ -1790,11 +1876,7 @@ output_move_qimode (operands)
       if (!reg_mentioned_p (stack_pointer_rtx, operands[1]))
 	{
 	  xoperands[3] = stack_pointer_rtx;
-#ifndef NO_ADDSUB_Q
 	  output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
-#else
-	  output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands);
-#endif
 	}
       else
 	output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
@@ -1804,12 +1886,12 @@ output_move_qimode (operands)
   /* clr and st insns on 68000 read before writing.
      This isn't so on the 68010, but we have no TARGET_68010.  */
   if (!ADDRESS_REG_P (operands[0])
-      && ((TARGET_68020 || TARGET_5200)
+      && ((TARGET_68020 || TARGET_COLDFIRE)
 	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     {
       if (operands[1] == const0_rtx)
 	return "clr%.b %0";
-      if ((!TARGET_5200 || DATA_REG_P (operands[0]))
+      if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
 	  && GET_CODE (operands[1]) == CONST_INT
 	  && (INTVAL (operands[1]) & 255) == 255)
 	{
@@ -1822,11 +1904,7 @@ output_move_qimode (operands)
       && INTVAL (operands[1]) < 128
       && INTVAL (operands[1]) >= -128)
     {
-#if defined(MOTOROLA)
-      return "moveq%.l %1,%0";
-#else
       return "moveq %1,%0";
-#endif
     }
   if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
     return "sub%.l %0,%0";
@@ -1840,26 +1918,24 @@ output_move_qimode (operands)
 }
 
 const char *
-output_move_stricthi (operands)
-     rtx *operands;
+output_move_stricthi (rtx *operands)
 {
   if (operands[1] == const0_rtx
       /* clr insns on 68000 read before writing.
 	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
+      && ((TARGET_68020 || TARGET_COLDFIRE)
 	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     return "clr%.w %0";
   return "move%.w %1,%0";
 }
 
 const char *
-output_move_strictqi (operands)
-     rtx *operands;
+output_move_strictqi (rtx *operands)
 {
   if (operands[1] == const0_rtx
       /* clr insns on 68000 read before writing.
          This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
+      && ((TARGET_68020 || TARGET_COLDFIRE)
           || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     return "clr%.b %0";
   return "move%.b %1,%0";
@@ -1869,8 +1945,7 @@ output_move_strictqi (operands)
    for moving operands[1] into operands[0] as a fullword.  */
 
 static const char *
-singlemove_string (operands)
-     rtx *operands;
+singlemove_string (rtx *operands)
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     return output_move_simode_const (operands);
@@ -1882,8 +1957,7 @@ singlemove_string (operands)
    with operands OPERANDS.  */
 
 const char *
-output_move_double (operands)
-     rtx *operands;
+output_move_double (rtx *operands)
 {
   enum
     {
@@ -2236,8 +2310,7 @@ compadr:
    ADDR can be effectively incremented by incrementing REG.  */
 
 static rtx
-find_addr_reg (addr)
-     rtx addr;
+find_addr_reg (rtx addr)
 {
   while (GET_CODE (addr) == PLUS)
     {
@@ -2260,8 +2333,7 @@ find_addr_reg (addr)
 /* Output assembler code to perform a 32 bit 3 operand add.  */
 
 const char *
-output_addsi3 (operands)
-     rtx *operands;
+output_addsi3 (rtx *operands)
 {
   if (! operands_match_p (operands[0], operands[1]))
     {
@@ -2283,8 +2355,7 @@ output_addsi3 (operands)
 	return "lea 0(%1,%2.l),%0";
       else
 	return "lea %c2(%1),%0";
-#else /* not SGS */
-#ifdef MOTOROLA
+#elif defined(MOTOROLA)
       if (GET_CODE (operands[2]) == REG)
 	return "lea (%1,%2.l),%0";
       else
@@ -2295,11 +2366,9 @@ output_addsi3 (operands)
       else
 	return "lea %1@(%c2),%0";
 #endif /* not MOTOROLA */
-#endif /* not SGS */
     }
   if (GET_CODE (operands[2]) == CONST_INT)
     {
-#ifndef NO_ADDSUB_Q
       if (INTVAL (operands[2]) > 0
 	  && INTVAL (operands[2]) <= 8)
 	return "addq%.l %2,%0";
@@ -2327,7 +2396,6 @@ output_addsi3 (operands)
 	      return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
 	    }
 	}
-#endif
       if (ADDRESS_REG_P (operands[0])
 	  && INTVAL (operands[2]) >= -0x8000
 	  && INTVAL (operands[2]) < 0x8000)
@@ -2355,9 +2423,7 @@ output_addsi3 (operands)
    some or all of the saved cc's so they won't be used.  */
 
 void
-notice_update_cc (exp, insn)
-     rtx exp;
-     rtx insn;
+notice_update_cc (rtx exp, rtx insn)
 {
   if (GET_CODE (exp) == SET)
     {
@@ -2452,8 +2518,7 @@ notice_update_cc (exp, insn)
 }
 
 const char *
-output_move_const_double (operands)
-     rtx *operands;
+output_move_const_double (rtx *operands)
 {
   int code = standard_68881_constant_p (operands[1]);
 
@@ -2468,8 +2533,7 @@ output_move_const_double (operands)
 }
 
 const char *
-output_move_const_single (operands)
-     rtx *operands;
+output_move_const_single (rtx *operands)
 {
   int code = standard_68881_constant_p (operands[1]);
 
@@ -2518,7 +2582,7 @@ REAL_VALUE_TYPE values_68881[7];
    strings_68881 to binary.  */
 
 void
-init_68881_table ()
+init_68881_table (void)
 {
   int i;
   REAL_VALUE_TYPE r;
@@ -2536,16 +2600,11 @@ init_68881_table ()
 }
 
 int
-standard_68881_constant_p (x)
-     rtx x;
+standard_68881_constant_p (rtx x)
 {
   REAL_VALUE_TYPE r;
   int i;
 
-#ifdef NO_ASM_FMOVECR
-  return 0;
-#endif
-
   /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
      used at all on those chips.  */
   if (TARGET_68040 || TARGET_68060)
@@ -2579,8 +2638,7 @@ standard_68881_constant_p (x)
    or 0 if X is not a power of 2.  */
 
 int
-floating_exact_log2 (x)
-     rtx x;
+floating_exact_log2 (rtx x)
 {
   REAL_VALUE_TYPE r, r1;
   int exp;
@@ -2645,10 +2703,7 @@ floating_exact_log2 (x)
    */
 
 void
-print_operand (file, op, letter)
-     FILE *file;		/* file to write to */
-     rtx op;			/* operand to print */
-     int letter;		/* %<letter> or 0 */
+print_operand (FILE *file, rtx op, int letter)
 {
   if (letter == '.')
     {
@@ -2817,9 +2872,7 @@ print_operand (file, op, letter)
 #endif /* ASM_OUTPUT_CASE_FETCH */
 
 void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
+print_operand_address (FILE *file, rtx addr)
 {
   register rtx reg1, reg2, breg, ireg;
   rtx offset;
@@ -3125,11 +3178,9 @@ print_operand_address (file, addr)
    insn we are checking for redundancy.  TARGET is the register set by the
    clear insn.  */
 
-int
-strict_low_part_peephole_ok (mode, first_insn, target)
-     enum machine_mode mode;
-     rtx first_insn;
-     rtx target;
+bool
+strict_low_part_peephole_ok (enum machine_mode mode, rtx first_insn,
+                             rtx target)
 {
   rtx p;
 
@@ -3139,7 +3190,7 @@ strict_low_part_peephole_ok (mode, first_insn, target)
     {
       /* If it isn't an insn, then give up.  */
       if (GET_CODE (p) != INSN)
-	return 0;
+	return false;
 
       if (reg_set_p (target, p))
 	{
@@ -3148,7 +3199,7 @@ strict_low_part_peephole_ok (mode, first_insn, target)
 
 	  /* If it isn't an easy to recognize insn, then give up.  */
 	  if (! set)
-	    return 0;
+	    return false;
 
 	  dest = SET_DEST (set);
 
@@ -3156,7 +3207,7 @@ strict_low_part_peephole_ok (mode, first_insn, target)
 	     first_insn is redundant.  */
 	  if (rtx_equal_p (dest, target)
 	      && SET_SRC (set) == const0_rtx)
-	    return 1;
+	    return true;
 	  else if (GET_CODE (dest) == STRICT_LOW_PART
 		   && GET_CODE (XEXP (dest, 0)) == REG
 		   && REGNO (XEXP (dest, 0)) == REGNO (target)
@@ -3166,14 +3217,14 @@ strict_low_part_peephole_ok (mode, first_insn, target)
 	       we are using, so it is safe.  */
 	    ;
 	  else
-	    return 0;
+	    return false;
 	}
 
       p = prev_nonnote_insn (p);
 
     }
 
-  return 0;
+  return false;
 }
 
 /* Accept integer operands in the range 0..0xffffffff.  We have to check the
@@ -3181,9 +3232,7 @@ strict_low_part_peephole_ok (mode, first_insn, target)
    need some extra crud to make it work when hosted on 64-bit machines.  */
 
 int
-const_uint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+const_uint32_operand (rtx op, enum machine_mode mode)
 {
   /* It doesn't make sense to ask this question with a mode that is
      not larger than 32 bits.  */
@@ -3205,9 +3254,7 @@ const_uint32_operand (op, mode)
    contexts.  */
 
 int
-const_sint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+const_sint32_operand (rtx op, enum machine_mode mode)
 {
   /* It doesn't make sense to ask this question with a mode that is
      not larger than 32 bits.  */
@@ -3281,9 +3328,7 @@ const_sint32_operand (op, mode)
    is specified.  */
 
 int
-general_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+general_src_operand (rtx op, enum machine_mode mode)
 {
   if (TARGET_PCREL
       && GET_CODE (op) == MEM
@@ -3299,9 +3344,7 @@ general_src_operand (op, mode)
    is specified.  */
 
 int
-nonimmediate_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+nonimmediate_src_operand (rtx op, enum machine_mode mode)
 {
   if (TARGET_PCREL && GET_CODE (op) == MEM
       && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
@@ -3316,9 +3359,7 @@ nonimmediate_src_operand (op, mode)
    is specified.  */
 
 int
-memory_src_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+memory_src_operand (rtx op, enum machine_mode mode)
 {
   if (TARGET_PCREL && GET_CODE (op) == MEM
       && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
@@ -3333,24 +3374,21 @@ memory_src_operand (op, mode)
    "general_src_operand".  */
 
 int
-pcrel_address (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+pcrel_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF
 	  || GET_CODE (op) == CONST);
 }
 
 const char *
-output_andsi3 (operands)
-     rtx *operands;
+output_andsi3 (rtx *operands)
 {
   int logval;
   if (GET_CODE (operands[2]) == CONST_INT
       && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0]))
-      && !TARGET_5200)
+      && !TARGET_COLDFIRE)
     {
       if (GET_CODE (operands[0]) != REG)
         operands[0] = adjust_address (operands[0], HImode, 2);
@@ -3383,15 +3421,14 @@ output_andsi3 (operands)
 }
 
 const char *
-output_iorsi3 (operands)
-     rtx *operands;
+output_iorsi3 (rtx *operands)
 {
   register int logval;
   if (GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[2]) >> 16 == 0
       && (DATA_REG_P (operands[0])
 	  || offsettable_memref_p (operands[0]))
-      && !TARGET_5200)
+      && !TARGET_COLDFIRE)
     {
       if (GET_CODE (operands[0]) != REG)
         operands[0] = adjust_address (operands[0], HImode, 2);
@@ -3420,14 +3457,13 @@ output_iorsi3 (operands)
 }
 
 const char *
-output_xorsi3 (operands)
-     rtx *operands;
+output_xorsi3 (rtx *operands)
 {
   register int logval;
   if (GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[2]) >> 16 == 0
       && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
-      && !TARGET_5200)
+      && !TARGET_COLDFIRE)
     {
       if (! DATA_REG_P (operands[0]))
 	operands[0] = adjust_address (operands[0], HImode, 2);
@@ -3455,12 +3491,12 @@ output_xorsi3 (operands)
   return "eor%.l %2,%0";
 }
 
+#ifdef M68K_TARGET_COFF
+
 /* Output assembly to switch to section NAME with attribute FLAGS.  */
 
 static void
-m68k_coff_asm_named_section (name, flags)
-     const char *name;
-     unsigned int flags;
+m68k_coff_asm_named_section (const char *name, unsigned int flags)
 {
   char flagchar;
 
@@ -3472,28 +3508,12 @@ m68k_coff_asm_named_section (name, flags)
   fprintf (asm_out_file, "\t.section\t%s,\"%c\"\n", name, flagchar);
 }
 
-#ifdef CTOR_LIST_BEGIN
-static void
-m68k_svr3_asm_out_constructor (symbol, priority)
-     rtx symbol;
-     int priority ATTRIBUTE_UNUSED;
-{
-  rtx xop[2];
-
-  xop[1] = symbol;
-  xop[0] = gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx));
-
-  init_section ();
-  output_asm_insn (output_move_simode (xop), xop);
-}
-#endif
+#endif /* M68K_TARGET_COFF */
 
 #ifdef HPUX_ASM
 static void
-m68k_hp320_internal_label (stream, prefix, labelno)
-     FILE *stream;
-     const char *prefix;
-     unsigned long labelno;
+m68k_hp320_internal_label (FILE *stream, const char *prefix,
+                           unsigned long labelno)
 {
   if (prefix[0] == 'L' && prefix[1] == 'I')
     fprintf(stream, "\tset %s%ld,.+2\n", prefix, labelno);
@@ -3502,7 +3522,7 @@ m68k_hp320_internal_label (stream, prefix, labelno)
 }
 
 static void
-m68k_hp320_file_start ()
+m68k_hp320_file_start (void)
 {
   /* version 1: 68010.
              2: 68020 without FPU.
@@ -3513,12 +3533,10 @@ m68k_hp320_file_start ()
 #endif
 
 static void
-m68k_output_mi_thunk (file, thunk, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
-     tree function;
+m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+		      HOST_WIDE_INT delta,
+		      HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+		      tree function)
 {
   rtx xops[1];
   const char *fmt;
@@ -3573,11 +3591,7 @@ m68k_output_mi_thunk (file, thunk, delta, vcall_offset, function)
   else
     {
 #if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
-      fmt = "bra %0";
-#else
       fmt = "jmp %0";
-#endif
 #else
       fmt = "jra %0";
 #endif
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index 8ee78ba9aa9..977a034bb13 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -28,12 +28,66 @@ Boston, MA 02111-1307, USA.  */
 #define TARGET_CPU_CPP_BUILTINS()		\
   do						\
     {						\
-	builtin_define ("__mc68000__");		\
-	if (TARGET_68020)			\
-	  builtin_define ("__mc68020__");	\
-	builtin_define ("__m68k__");		\
-	builtin_assert ("cpu=m68k");		\
-	builtin_assert ("machine=m68k");	\
+      builtin_define ("__m68k__");		\
+      builtin_define_std ("mc68000");		\
+      if (TARGET_68040_ONLY)			\
+	{					\
+	  if (TARGET_68060)			\
+	    builtin_define_std ("mc68060");	\
+	  else					\
+	    builtin_define_std ("mc68040");	\
+	}					\
+      else if (TARGET_68060) /* -m68020-60 */	\
+	{					\
+	  builtin_define_std ("mc68060");	\
+	  builtin_define_std ("mc68040");	\
+	  builtin_define_std ("mc68030");	\
+	  builtin_define_std ("mc68020");	\
+	}					\
+      else if (TARGET_68040) /* -m68020-40 */	\
+	{					\
+	  builtin_define_std ("mc68040");	\
+	  builtin_define_std ("mc68030");	\
+ 	  builtin_define_std ("mc68020");	\
+	}					\
+      else if (TARGET_68030)			\
+	builtin_define_std ("mc68030");		\
+      else if (TARGET_68020)			\
+	builtin_define_std ("mc68020");		\
+      if (TARGET_68881)				\
+	builtin_define ("__HAVE_68881__");	\
+      if (TARGET_CPU32)				\
+	{					\
+	  builtin_define_std ("mc68332");	\
+	  builtin_define_std ("mcpu32");	\
+	}					\
+      if (TARGET_COLDFIRE)			\
+	builtin_define ("__mcoldfire__");	\
+      if (TARGET_5200)				\
+	builtin_define ("__mcf5200__");		\
+      if (TARGET_528x)				\
+	{					\
+	  builtin_define ("__mcf528x__");	\
+	  builtin_define ("__mcf5200__");	\
+	}					\
+      if (TARGET_CFV3)				\
+	{					\
+	  builtin_define ("__mcf5300__");	\
+	  builtin_define ("__mcf5307__");	\
+	}					\
+      if (TARGET_CFV4)				\
+	{					\
+	  builtin_define ("__mcf5400__");	\
+	  builtin_define ("__mcf5407__");	\
+	}					\
+      if (TARGET_CF_HWDIV)			\
+	builtin_define ("__mcfhwdiv__");	\
+      if (flag_pic)				\
+	builtin_define ("__pic__");		\
+      if (flag_pic > 1)				\
+	builtin_define ("__PIC__");		\
+      builtin_assert ("cpu=m68k");		\
+      builtin_assert ("machine=m68k");		\
     }						\
   while (0)
 
@@ -62,33 +116,13 @@ extern int target_flags;
 /* Macros used in the machine description to test the flags.  */
 
 /* Compile for a 68020 (not a 68000 or 68010).  */
-#define MASK_68020	1
+#define MASK_68020	(1<<0)
 #define TARGET_68020 (target_flags & MASK_68020)
 
-/* Compile 68881 insns for floating point (not library calls).  */
-#define MASK_68881	2
-#define TARGET_68881 (target_flags & MASK_68881)
-
-/* Compile using 68020 bit-field insns.  */
-#define MASK_BITFIELD	4
-#define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
-
-/* Compile using rtd insn calling sequence.
-   This will not work unless you use prototypes at least
-   for all functions that can take varying numbers of args.  */
-#define MASK_RTD	8
-#define TARGET_RTD (target_flags & MASK_RTD)
-
-/* Compile passing first two args in regs 0 and 1.
-   This exists only to test compiler features that will
-   be needed for RISC chips.  It is not usable
-   and is not intended to be usable on this cpu.  */
-#define MASK_REGPARM	16
-#define TARGET_REGPARM (target_flags & MASK_REGPARM)
-
-/* Compile with 16-bit `int'.  */
-#define MASK_SHORT	32
-#define TARGET_SHORT (target_flags & MASK_SHORT)
+/* Compile for a 68030.  This does not really make a difference in GCC,
+   it just enables the __mc68030__ predefine.  */
+#define MASK_68030	(1<<1)
+#define TARGET_68030 (target_flags & MASK_68030)
 
 /* Optimize for 68040, but still allow execution on 68020
    (-m68020-40 or -m68040).
@@ -96,11 +130,11 @@ extern int target_flags;
    of them must be emulated in software by the OS.  When TARGET_68040 is
    turned on, these instructions won't be used.  This code will still
    run on a 68030 and 68881/2.  */
-#define MASK_68040	256
+#define MASK_68040	(1<<2)	
 #define TARGET_68040 (target_flags & MASK_68040)
 
 /* Use the 68040-only fp instructions (-m68040 or -m68060).  */
-#define MASK_68040_ONLY	512
+#define MASK_68040_ONLY	(1<<3)
 #define TARGET_68040_ONLY (target_flags & MASK_68040_ONLY)
 
 /* Optimize for 68060, but still allow execution on 68020
@@ -109,24 +143,48 @@ extern int target_flags;
    of them must be emulated in software by the OS.  When TARGET_68060 is
    turned on, these instructions won't be used.  This code will still
    run on a 68030 and 68881/2.  */
-#define MASK_68060	1024
+#define MASK_68060	(1<<4)
 #define TARGET_68060 (target_flags & MASK_68060)
 
 /* Compile for mcf5200 */
-#define MASK_5200	2048
+#define MASK_5200	(1<<5)
 #define TARGET_5200 (target_flags & MASK_5200)
 
+/* Build for ColdFire v3 */
+#define MASK_CFV3	(1<<6)
+#define TARGET_CFV3	(target_flags & MASK_CFV3)
+
+/* Build for ColdFire v4 */
+#define MASK_CFV4	(1<<7)
+#define TARGET_CFV4	(target_flags & MASK_CFV4)
+
+/* Compile for ColdFire 528x */
+#define MASK_528x	(1<<8)
+#define TARGET_528x	(target_flags & MASK_528x)
+
+/* Divide support for ColdFire */
+#define MASK_CF_HWDIV	(1<<9)
+#define TARGET_CF_HWDIV	(target_flags & MASK_CF_HWDIV)
+
+/* Compile 68881 insns for floating point (not library calls).  */
+#define MASK_68881	(1<<10)
+#define TARGET_68881	(target_flags & MASK_68881)
+
+/* Compile using 68020 bit-field insns.  */
+#define MASK_BITFIELD	(1<<11)
+#define TARGET_BITFIELD (target_flags & MASK_BITFIELD)
+
+/* Compile with 16-bit `int'.  */
+#define MASK_SHORT	(1<<12)
+#define TARGET_SHORT	(target_flags & MASK_SHORT)
+
 /* Align ints to a word boundary.  This breaks compatibility with the 
    published ABI's for structures containing ints, but produces faster
    code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
    It's required for coldfire cpus without a misalignment module.  */
-#define MASK_ALIGN_INT	4096
+#define MASK_ALIGN_INT	(1<<13)
 #define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
 
-/* Compile for a CPU32 */
-	/* A 68020 without bitfields is a good heuristic for a CPU32 */
-#define TARGET_CPU32	(TARGET_68020 && !TARGET_BITFIELD)
-
 /* Use PC-relative addressing modes (without using a global offset table).
    The m68000 supports 16-bit PC-relative addressing.
    The m68020 supports 32-bit PC-relative addressing
@@ -136,13 +194,30 @@ extern int target_flags;
    treated as all containing an implicit PC-relative component, and hence
    cannot be used directly as addresses for memory writes.  See the comments
    in m68k.c for more information.  */
-#define MASK_PCREL	8192
+#define MASK_PCREL	(1<<14)
 #define TARGET_PCREL	(target_flags & MASK_PCREL)
 
 /* Relax strict alignment.  */
-#define MASK_NO_STRICT_ALIGNMENT 16384
+#define MASK_NO_STRICT_ALIGNMENT (1<<15)
 #define TARGET_STRICT_ALIGNMENT  (~target_flags & MASK_NO_STRICT_ALIGNMENT)
 
+/* Compile using rtd insn calling sequence.
+   This will not work unless you use prototypes at least
+   for all functions that can take varying numbers of args.  */
+#define MASK_RTD	(1<<16)
+#define TARGET_RTD	(target_flags & MASK_RTD)
+
+/* Compile for a CPU32.  A 68020 without bitfields is a good
+   heuristic for a CPU32.  */
+#define TARGET_CPU32	(TARGET_68020 && !TARGET_BITFIELD)
+
+/* Is the target a ColdFire?  */
+#define MASK_COLDFIRE	(MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
+#define TARGET_COLDFIRE	(target_flags & MASK_COLDFIRE)
+
+/* Which bits can be set by specifying a coldfire */
+#define MASK_ALL_CF_BITS	(MASK_COLDFIRE|MASK_CF_HWDIV)
+
 /* Macro to define tables used to set the flags.
    This is a list in braces of pairs in braces,
    each pair being { "NAME", VALUE }
@@ -150,26 +225,22 @@ extern int target_flags;
    An empty string NAME is used to identify the default VALUE.  */
 
 #define TARGET_SWITCHES							\
-  { { "68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
+  { { "68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
       N_("Generate code for a 68020") },				\
-    { "c68020", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
+    { "c68020", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
       N_("Generate code for a 68020") },				\
     { "68020", (MASK_68020|MASK_BITFIELD), "" },			\
     { "c68020", (MASK_68020|MASK_BITFIELD), "" },			\
-    { "68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
+    { "68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY	\
 		|MASK_68020|MASK_BITFIELD|MASK_68881),			\
       N_("Generate code for a 68000") },				\
-    { "c68000", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
+    { "c68000", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY	\
 		|MASK_68020|MASK_BITFIELD|MASK_68881),			\
       N_("Generate code for a 68000") },				\
     { "bitfield", MASK_BITFIELD,					\
       N_("Use the bit-field instructions") },				\
     { "nobitfield", - MASK_BITFIELD,					\
       N_("Do not use the bit-field instructions") },			\
-    { "rtd", MASK_RTD,							\
-      N_("Use different calling convention using 'rtd'") },		\
-    { "nortd", - MASK_RTD,						\
-      N_("Use normal calling convention") },				\
     { "short", MASK_SHORT,						\
       N_("Consider type `int' to be 16 bits wide") },			\
     { "noshort", - MASK_SHORT,						\
@@ -177,40 +248,56 @@ extern int target_flags;
     { "68881", MASK_68881, "" },					\
     { "soft-float", - (MASK_68040_ONLY|MASK_68881),			\
       N_("Generate code with library calls for floating point") },	\
-    { "68020-40", -(MASK_5200|MASK_68060|MASK_68040_ONLY),		\
+    { "68020-40", -(MASK_ALL_CF_BITS|MASK_68060|MASK_68040_ONLY),	\
       N_("Generate code for a 68040, without any new instructions") },	\
     { "68020-40", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040), ""},\
-    { "68020-60", -(MASK_5200|MASK_68040_ONLY),				\
+    { "68020-60", -(MASK_ALL_CF_BITS|MASK_68040_ONLY),			\
       N_("Generate code for a 68060, without any new instructions") },	\
     { "68020-60", (MASK_BITFIELD|MASK_68881|MASK_68020|MASK_68040	\
 		   |MASK_68060), "" },					\
-    { "68030", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
+    { "68030", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY),	\
       N_("Generate code for a 68030") },				\
-    { "68030", (MASK_68020|MASK_BITFIELD), "" },			\
-    { "68040", - (MASK_5200|MASK_68060),				\
+    { "68030", (MASK_68020|MASK_68030|MASK_BITFIELD), "" },		\
+    { "68040", - (MASK_ALL_CF_BITS|MASK_68060),				\
       N_("Generate code for a 68040") },				\
     { "68040", (MASK_68020|MASK_68881|MASK_BITFIELD			\
 		|MASK_68040_ONLY|MASK_68040), "" },			\
-    { "68060", - (MASK_5200|MASK_68040),				\
+    { "68060", - (MASK_ALL_CF_BITS|MASK_68040),				\
       N_("Generate code for a 68060") },				\
     { "68060", (MASK_68020|MASK_68881|MASK_BITFIELD			\
 		|MASK_68040_ONLY|MASK_68060), "" },			\
-    { "5200", - (MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
+    { "5200", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
 		|MASK_BITFIELD|MASK_68881),				\
       N_("Generate code for a 520X") },					\
     { "5200", (MASK_5200), "" },					\
+    { "5206e", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
+		|MASK_BITFIELD|MASK_68881),				\
+      N_("Generate code for a 5206e") },				\
+    { "5206e", (MASK_5200|MASK_CF_HWDIV), "" },				\
+    { "528x", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
+		|MASK_BITFIELD|MASK_68881),				\
+      N_("Generate code for a 528x") },					\
+    { "528x", (MASK_528x|MASK_CF_HWDIV), "" },				\
+    { "5307", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
+		|MASK_BITFIELD|MASK_68881),				\
+      N_("Generate code for a 5307") },					\
+    { "5307", (MASK_CFV3|MASK_CF_HWDIV), "" },				\
+    { "5407", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY|MASK_68020	\
+		|MASK_BITFIELD|MASK_68881),				\
+      N_("Generate code for a 5407") },					\
+    { "5407", (MASK_CFV4|MASK_CF_HWDIV), "" },				\
     { "68851", 0,							\
       N_("Generate code for a 68851") },				\
     { "no-68851", 0,							\
       N_("Do no generate code for a 68851") },				\
-    { "68302", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
+    { "68302", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY	\
 		  |MASK_68020|MASK_BITFIELD|MASK_68881),		\
       N_("Generate code for a 68302") },				\
-    { "68332", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
+    { "68332", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY	\
 		  |MASK_BITFIELD|MASK_68881),				\
       N_("Generate code for a 68332") },				\
     { "68332", MASK_68020, "" },					\
-    { "cpu32", - (MASK_5200|MASK_68060|MASK_68040|MASK_68040_ONLY	\
+    { "cpu32", - (MASK_ALL_CF_BITS|MASK_68060|MASK_68040|MASK_68040_ONLY	\
 		  |MASK_BITFIELD|MASK_68881),				\
       N_("Generate code for a cpu32") },				\
     { "cpu32", MASK_68020, "" },					\
@@ -224,9 +311,13 @@ extern int target_flags;
       N_("Do not use unaligned memory references") },			\
     { "no-strict-align", MASK_NO_STRICT_ALIGNMENT,			\
       N_("Use unaligned memory references") },				\
+    { "rtd", MASK_RTD,							\
+      N_("Use different calling convention using 'rtd'") },		\
+    { "nortd", - MASK_RTD,						\
+      N_("Use normal calling convention") },				\
     SUBTARGET_SWITCHES							\
     { "", TARGET_DEFAULT, "" }}
-/* TARGET_DEFAULT is defined in sun*.h and isi.h, etc.  */
+/* TARGET_DEFAULT is defined in m68k-none.h, netbsd.h, etc.  */
 
 /* This macro is similar to `TARGET_SWITCHES' but defines names of
    command options that have values.  Its definition is an
@@ -346,7 +437,7 @@ extern int target_flags;
    For the 68000, we give the data registers numbers 0-7,
    the address registers numbers 010-017,
    and the 68881 floating point registers numbers 020-027.  */
-#define FIRST_PSEUDO_REGISTER 24
+#define FIRST_PSEUDO_REGISTER 25
 
 /* This defines the register which is used to hold the offset table for PIC.  */
 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 13 : INVALID_REGNUM)
@@ -453,8 +544,11 @@ extern int target_flags;
    This is computed in `reload', in reload1.c.  */
 #define FRAME_POINTER_REQUIRED 0
 
-/* Base register for access to arguments of the function.  */
-#define ARG_POINTER_REGNUM 14
+/* Base register for access to arguments of the function.
+ * This isn't a hardware register. It will be eliminated to the
+ * stack pointer or frame pointer.
+ */
+#define ARG_POINTER_REGNUM 24
 
 /* Register in which static-chain is passed to a function.  */
 #define STATIC_CHAIN_REGNUM 8
@@ -688,12 +782,12 @@ enum reg_class {
    this says how many the stack pointer really advances by.
    On the 68000, sp@- in a byte insn really pushes a word.
    On the 5200 (coldfire), sp@- in a byte insn pushes just a byte.  */
-#define PUSH_ROUNDING(BYTES) (TARGET_5200 ? BYTES : ((BYTES) + 1) & ~1)
+#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
 
 /* We want to avoid trying to push bytes.  */
 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
   (move_by_pieces_ninsns (SIZE, ALIGN) < MOVE_RATIO \
-    && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_5200)))
+    && (((SIZE) >=16 && (ALIGN) >= 16) || (TARGET_COLDFIRE)))
 
 /* Offset of first parameter from the argument pointer register value.  */
 #define FIRST_PARM_OFFSET(FNDECL) 8
@@ -798,26 +892,17 @@ enum reg_class {
    CUM is a variable of type CUMULATIVE_ARGS which gives info about
     the preceding args and about the function being called.
    NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  */
+    (otherwise it is an extra parameter matching an ellipsis).
 
-/* On the 68000 all args are pushed, except if -mregparm is specified
-   then the first two words of arguments are passed in d0, d1.
-   *NOTE* -mregparm does not work.
-   It exists only to test register calling conventions.  */
+   On the m68k all args are always pushed.  */
 
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
 
 /* For an arg passed partly in registers and partly in memory,
    this is the number of registers used.
    For args passed entirely in registers or entirely in memory, zero.  */
 
-#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8					\
-  && 8 < ((CUM) + ((MODE) == BLKmode				\
-		      ? int_size_in_bytes (TYPE)		\
-		      : GET_MODE_SIZE (MODE))))  		\
- ? 2 - (CUM) / 4 : 0)
+#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
 
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  */
@@ -839,32 +924,6 @@ enum reg_class {
    You should override this if you define FUNCTION_EXTRA_EPILOGUE.  */
 #define USE_RETURN_INSN use_return_insn ()
 
-/* Store in the variable DEPTH the initial difference between the
-   frame pointer reg contents and the stack pointer reg contents,
-   as of the start of the function body.  This depends on the layout
-   of the fixed parts of the stack frame and on how registers are saved.
-
-   On the 68k, if we have a frame, we must add one word to its length
-   to allow for the place that a6 is stored when we do have a frame pointer.
-   Otherwise, we would need to compute the offset from the frame pointer
-   of a local variable as a function of frame_pointer_needed, which
-   is hard.  */
-
-#define INITIAL_FRAME_POINTER_OFFSET(DEPTH)			\
-{ int regno;							\
-  int offset = -4;						\
-  for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++)	\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 12;						\
-  for (regno = 0; regno < 16; regno++)				\
-    if (regs_ever_live[regno] && ! call_used_regs[regno])	\
-      offset += 4;						\
-  if (flag_pic && current_function_uses_pic_offset_table)	\
-    offset += 4;						\
-  (DEPTH) = (offset + ((get_frame_size () + 3) & -4)		\
-	     + (get_frame_size () == 0 ? 0 : 4));		\
-}
-
 /* Output assembler code for a block containing the constant parts
    of a trampoline, leaving space for the variable parts.  */
 
@@ -942,6 +1001,38 @@ __transfer_from_trampoline ()					\
   asm ("rts":);							\
 }
 
+/* Definitions for register eliminations.
+
+   This is an array of structures.  Each structure initializes one pair
+   of eliminable registers.  The "from" register number is given first,
+   followed by "to".  Eliminations of the same "from" register are listed
+   in order of preference.
+
+   There are two registers that can always be eliminated on the m68k.
+   The frame pointer and the arg pointer can be replaced by either the
+   hard frame pointer or to the stack pointer, depending upon the
+   circumstances.  The hard frame pointer is not used before reload and
+   so it is not eligible for elimination.  */
+
+#define ELIMINABLE_REGS					\
+{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },		\
+ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },	\
+ { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
+
+/* Given FROM and TO register numbers, say whether this elimination is
+   allowed.  Frame pointer elimination is automatically handled.
+
+   All other eliminations are valid.  */
+
+#define CAN_ELIMINATE(FROM, TO) \
+  ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
+
+/* Define the offset between two registers, one to be eliminated, and the other
+   its replacement, at the start of a routine.  */
+
+#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET)			\
+  (OFFSET) = m68k_initial_elimination_offset(FROM, TO)
+
 /* Addressing modes, and classification of registers for them.  */
 
 #define HAVE_POST_INCREMENT 1
@@ -1122,7 +1213,7 @@ __transfer_from_trampoline ()					\
 /* coldfire/5200 does not allow HImode index registers.  */
 #define LEGITIMATE_INDEX_REG_P(X)   \
   ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))	\
-   || (! TARGET_5200					\
+   || (! TARGET_COLDFIRE					\
        && GET_CODE (X) == SIGN_EXTEND			\
        && GET_CODE (XEXP (X, 0)) == REG			\
        && GET_MODE (XEXP (X, 0)) == HImode		\
@@ -1133,12 +1224,12 @@ __transfer_from_trampoline ()					\
 
 #define LEGITIMATE_INDEX_P(X)   \
    (LEGITIMATE_INDEX_REG_P (X)				\
-    || ((TARGET_68020 || TARGET_5200) && GET_CODE (X) == MULT \
+    || ((TARGET_68020 || TARGET_COLDFIRE) && GET_CODE (X) == MULT \
 	&& LEGITIMATE_INDEX_REG_P (XEXP (X, 0))		\
 	&& GET_CODE (XEXP (X, 1)) == CONST_INT		\
 	&& (INTVAL (XEXP (X, 1)) == 2			\
 	    || INTVAL (XEXP (X, 1)) == 4		\
-	    || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_5200))))
+	    || (INTVAL (XEXP (X, 1)) == 8 && !TARGET_COLDFIRE))))
 
 /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes.  */
 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)				\
@@ -1341,7 +1432,7 @@ __transfer_from_trampoline ()					\
 #define REGISTER_NAMES \
 {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",	\
  "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",	\
- "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
+ "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", "argptr" }
 
 /* How to renumber registers for dbx and gdb.
    On the Sun-3, the floating point registers have numbers
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 4542d73acbc..1917717076d 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -24,7 +24,7 @@
 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
 ;;- 68k ISA.  Differences include reduced support for byte and word
 ;;- operands and the removal of BCD, bitfield, rotate, and integer
-;;- divide instructions.  The TARGET_5200 flag turns the use of the
+;;- divide instructions.  The TARGET_COLDFIRE flag turns the use of the
 ;;- removed opcodes and addressing modes off.
 ;;- 
 
@@ -199,12 +199,7 @@
   ""
   "*
 {
-#ifdef ISI_OV
-  /* ISI's assembler fails to handle tstl a0.  */
-  if (! ADDRESS_REG_P (operands[0]))
-#else
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
-#endif
+  if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
     return \"tst%.l %0\";
   /* If you think that the 68020 does not support tstl a0,
      reread page B-167 of the 68020 manual more carefully.  */
@@ -338,7 +333,7 @@
   [(set (cc0)
         (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
                  (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
@@ -378,7 +373,7 @@
   [(set (cc0)
 	(compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
 		 (match_operand:SI 1 "general_operand" "r,mrKs")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   if (REG_P (operands[1])
@@ -401,14 +396,14 @@
   [(set (cc0)
         (compare (match_operand:HI 0 "nonimmediate_src_operand" "")
                  (match_operand:HI 1 "general_src_operand" "")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "m68k_last_compare_had_fp_operands = 0;")
 
 (define_insn ""
   [(set (cc0)
         (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
                  (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
@@ -437,14 +432,14 @@
   [(set (cc0)
         (compare (match_operand:QI 0 "nonimmediate_src_operand" "")
                  (match_operand:QI 1 "general_src_operand" "")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "m68k_last_compare_had_fp_operands = 0;")
 
 (define_insn ""
   [(set (cc0)
         (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
                  (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
@@ -562,7 +557,7 @@
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "di"))))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
 
 ;; This is the same as the above pattern except for the constraints.  The 'i'
@@ -573,7 +568,7 @@
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (match_operand:SI 1 "general_operand" "d"))))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
 
 (define_insn ""
@@ -614,7 +609,7 @@
   [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
+  "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
   "*
 {
   operands[1] = GEN_INT (7 - INTVAL (operands[1]));
@@ -625,7 +620,7 @@
   [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[0]) == MEM)
@@ -646,7 +641,7 @@
   [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
 			    (const_int 1)
 			    (match_operand:SI 1 "const_int_operand" "n")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[0]) == MEM)
@@ -693,7 +688,7 @@
 	(const_int 0))]
   ;; clr insns on 68000 read before writing.
   ;; This isn't so on the 68010, but we have no TARGET_68010.
-  "((TARGET_68020 || TARGET_5200)
+  "((TARGET_68020 || TARGET_COLDFIRE)
     || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
   "*
 {
@@ -717,12 +712,8 @@
 	}
     }
   /* moveq is faster on the 68000.  */
-  if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
-#if defined(MOTOROLA)
-    return \"moveq%.l %#0,%0\";
-#else
+  if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_COLDFIRE))
     return \"moveq %#0,%0\";
-#endif
   return \"clr%.l %0\";
 }")
 
@@ -772,7 +763,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
         (match_operand:SI 1 "general_src_operand" "daymSKT,n,i"))]
 
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   return output_move_simode (operands);
@@ -781,7 +772,7 @@
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
 	(match_operand:SI 1 "general_operand" "g,r<Q>"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_simode (operands);")
 
 ;; Special case of fullword move, where we need to get a non-GOT PIC
@@ -806,13 +797,13 @@
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
         (match_operand:HI 1 "general_src_operand" "gS"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "* return output_move_himode (operands);")
 
  (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
 	(match_operand:HI 1 "general_operand" "g,r<Q>"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_himode (operands);")
 
 (define_expand "movstricthi"
@@ -824,13 +815,13 @@
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
 	(match_operand:HI 1 "general_src_operand" "rmSn"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "* return output_move_stricthi (operands);")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
 	(match_operand:HI 1 "general_src_operand" "rmn,r"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_stricthi (operands);")
 
 (define_expand "movqi"
@@ -842,13 +833,13 @@
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
 	(match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "* return output_move_qimode (operands);")
 
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
 	(match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_qimode (operands);")
 
 (define_expand "movstrictqi"
@@ -860,20 +851,20 @@
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
 	(match_operand:QI 1 "general_src_operand" "dmSn"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "* return output_move_strictqi (operands);")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
 	(match_operand:QI 1 "general_src_operand" "dmn,d"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_strictqi (operands);")
 
 (define_expand "pushqi1"
   [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int -2)))
    (set (mem:QI (plus:SI (reg:SI 15) (const_int 1)))
 	(match_operand:QI 0 "general_operand" ""))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "")
 
 (define_expand "movsf"
@@ -885,7 +876,7 @@
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
 	(match_operand:SF 1 "general_operand" "rmfF"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (FP_REG_P (operands[0]))
@@ -907,7 +898,7 @@
   if (operands[1] == CONST0_RTX (SFmode)
       /* clr insns on 68000 read before writing.
 	 This isn't so on the 68010, but we have no TARGET_68010.  */
-      && ((TARGET_68020 || TARGET_5200)
+      && ((TARGET_68020 || TARGET_COLDFIRE)
 	  || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     {
       if (ADDRESS_REG_P (operands[0]))
@@ -930,13 +921,9 @@
 	    }
 	}
       /* moveq is faster on the 68000.  */
-      if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
+      if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_COLDFIRE))
 	{
-#if defined(MOTOROLA)
-	  return \"moveq%.l %#0,%0\";
-#else
 	  return \"moveq %#0,%0\";
-#endif
 	}
       return \"clr%.l %0\";
     }
@@ -946,7 +933,7 @@
 (define_insn ""
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,g")
 	(match_operand:SF 1 "general_operand" "g,r"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return \"move%.l %1,%0\";")
 
 (define_expand "movdf"
@@ -960,7 +947,7 @@
 	(match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
 ;  [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
 ;	(match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (FP_REG_P (operands[0]))
@@ -996,7 +983,7 @@
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
 	(match_operand:DF 1 "general_operand" "g,r"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_double (operands);")
 
 ;; ??? The XFmode patterns are schizophrenic about whether constants are
@@ -1075,7 +1062,7 @@
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
 	(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
-  "! TARGET_68881 && ! TARGET_5200"
+  "! TARGET_68881 && ! TARGET_COLDFIRE"
   "*
 {
   if (FP_REG_P (operands[0]))
@@ -1116,7 +1103,7 @@
 (define_insn ""
   [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
 	(match_operand:XF 1 "nonimmediate_operand" "g,r"))]
-  "! TARGET_68881 && TARGET_5200"
+  "! TARGET_68881 && TARGET_COLDFIRE"
   "* return output_move_double (operands);")
 
 (define_expand "movdi"
@@ -1135,7 +1122,7 @@
 ;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
 ;  [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
 ;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (FP_REG_P (operands[0]))
@@ -1171,7 +1158,7 @@
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
 	(match_operand:DI 1 "general_operand" "g,r"))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_move_double (operands);")
 
 ;; Thus goes after the move instructions
@@ -1286,7 +1273,7 @@
 (define_insn "*zero_extendsidi2_cf"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,m")
     (zero_extend:DI (match_operand:SI 1 "general_operand" "rm,r")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -1310,7 +1297,7 @@
 (define_insn "*zero_extendsidi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
     (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -1411,9 +1398,9 @@
     {
       if (GET_CODE (operands[1]) == REG
 	  && REGNO (operands[0]) == REGNO (operands[1]))
-	return (!TARGET_5200 ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
+	return (!TARGET_COLDFIRE ? \"and%.w %#0xFF,%0\" : \"and%.l %#0xFF,%0\");
       if (reg_mentioned_p (operands[0], operands[1]))
-	return (!TARGET_5200 ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" 
+	return (!TARGET_COLDFIRE ? \"move%.b %1,%0\;and%.w %#0xFF,%0\" 
 			     : \"move%.b %1,%0\;and%.l %#0xFF,%0\");
       return \"clr%.w %0\;move%.b %1,%0\";
     }
@@ -1503,7 +1490,7 @@
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
   else
     return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
@@ -1518,7 +1505,7 @@
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
   else
     return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
@@ -1533,7 +1520,7 @@
 {
   CC_STATUS_INIT;
   operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
   else
     return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
@@ -1565,7 +1552,7 @@
     output_asm_insn (\"add%.l %2,%3\", operands);
   else
     output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     return \"smi %0\;extb%.l %0\";
   else
     return \"smi %0\;ext%.w %0\;ext%.l %0\";
@@ -1592,7 +1579,7 @@
 (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
-  "TARGET_68020 || TARGET_5200"
+  "TARGET_68020 || TARGET_COLDFIRE"
   "extb%.l %0")
 
 ;; Conversions between float and double.
@@ -1849,7 +1836,7 @@
    && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
     output_asm_insn (\"move%.l %4,%3\", operands);
   output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     output_asm_insn (\"extb%.l %2\", operands);
   else
     output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
@@ -1866,7 +1853,7 @@
             (const_int 32))
         (match_operand:DI 2 "general_operand" "0,0,0,0")))
    (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -1961,21 +1948,11 @@
 	  if (GET_CODE (operands[1]) == CONST_INT)
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		{
-#ifdef NO_ADDSUB_Q
-		  return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
-		  return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
-		}
+		return \"addq%.l %1,%R0\;addx%.l %3,%0\";
 	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 		{
 		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
-		  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
 		  return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
 		}
 	    }
 	  return \"add%.l %1,%R0\;addx%.l %3,%0\";
@@ -2031,11 +2008,7 @@
 #else
   output_asm_insn (\"jpl %l3\", operands);
 #endif
-#ifndef NO_ADDSUB_Q
   output_asm_insn (\"addq%.l %#1,%2\", operands);
-#else
-  output_asm_insn (\"add%.l %#1,%2\", operands);
-#endif
   (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
 				CODE_LABEL_NUMBER (operands[3]));
   return \"\";
@@ -2058,14 +2031,14 @@
                  (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
 
 
-  "! TARGET_5200"
+  "! TARGET_COLDFIRE"
   "* return output_addsi3 (operands);")
 
 (define_insn "*addsi3_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
 	(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
 		 (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "* return output_addsi3 (operands);")
 
 (define_insn ""
@@ -2073,19 +2046,18 @@
 	(plus:SI (match_operand:SI 1 "general_operand" "0")
 		 (sign_extend:SI
 		  (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "add%.w %2,%0")
 
 (define_insn "addhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
 	(plus:HI (match_operand:HI 1 "general_operand" "%0,0")
 		 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     {
-#ifndef NO_ADDSUB_Q
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
 	 elsewhere in the compiler.  First check for constants out of range,
@@ -2121,7 +2093,6 @@
 	      return \"subq%.w %#8,%0\;subq%.w %2,%0\";
 	    }
 	}
-#endif
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
 #ifdef MOTOROLA  
 	    return \"lea (%c2,%0),%0\";
@@ -2142,12 +2113,11 @@
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(plus:HI (match_dup 0)
 		 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
-#ifndef NO_ADDSUB_Q
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
 	 elsewhere in the compiler.  First check for constants out of range,
@@ -2183,7 +2153,6 @@
 	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
 	    }
 	}
-#endif
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
 #ifdef MOTOROLA  
 	    return \"lea (%c1,%0),%0\";
@@ -2198,12 +2167,11 @@
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
 		 (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[1]) == CONST_INT)
     {
-#ifndef NO_ADDSUB_Q
       /* If the constant would be a negative number when interpreted as
 	 HImode, make it negative.  This is usually, but not always, done
 	 elsewhere in the compiler.  First check for constants out of range,
@@ -2239,7 +2207,6 @@
 	      return \"subq%.w %#8,%0\;subq%.w %1,%0\";
 	    }
 	}
-#endif
       if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
 #ifdef MOTOROLA  
 	    return \"lea (%c1,%0),%0\";
@@ -2254,10 +2221,9 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
 	(plus:QI (match_operand:QI 1 "general_operand" "%0,0")
 		 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
-#ifndef NO_ADDSUB_Q
   if (GET_CODE (operands[2]) == CONST_INT)
     {
       if (INTVAL (operands[2]) >= 128)
@@ -2272,7 +2238,6 @@
 	 return \"subq%.b %2,%0\";
        }
     }
-#endif
   return \"add%.b %2,%0\";
 }")
 
@@ -2280,10 +2245,9 @@
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(plus:QI (match_dup 0)
 		 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
-#ifndef NO_ADDSUB_Q
   if (GET_CODE (operands[1]) == CONST_INT)
     {
       if (INTVAL (operands[1]) >= 128)
@@ -2298,7 +2262,6 @@
 	 return \"subq%.b %1,%0\";
        }
     }
-#endif
   return \"add%.b %1,%0\";
 }")
 
@@ -2306,10 +2269,9 @@
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		 (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
-#ifndef NO_ADDSUB_Q
   if (GET_CODE (operands[1]) == CONST_INT)
     {
       if (INTVAL (operands[1]) >= 128)
@@ -2324,7 +2286,6 @@
 	 return \"subq%.b %1,%0\";
        }
     }
-#endif
   return \"add%.b %1,%0\";
 }")
 
@@ -2416,7 +2377,7 @@
         (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
             (const_int 32))))
    (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -2491,21 +2452,11 @@
 	  if (GET_CODE (operands[1]) == CONST_INT)
 	    {
 	      if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
-		{
-#ifdef NO_ADDSUB_Q
-		  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
-#else
-		  return \"subq%.l %1,%R0\;subx%.l %3,%0\";
-#endif
-		}
+		return \"subq%.l %1,%R0\;subx%.l %3,%0\";
 	      else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
 		{
 		  operands[1] = GEN_INT (-INTVAL (operands[1]));
-#ifdef NO_ADDSUB_Q
-		  return \"add%.l %1,%R0\;addx%.l %3,%0\";
-#else
 		  return \"addq%.l %1,%R0\;addx%.l %3,%0\";
-#endif
 		}
 	    }
 	  return \"sub%.l %1,%R0\;subx%.l %3,%0\";
@@ -2550,35 +2501,35 @@
 	(minus:SI (match_operand:SI 1 "general_operand" "0")
 		  (sign_extend:SI
 		   (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "sub%.w %2,%0")
 
 (define_insn "subhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
 	(minus:HI (match_operand:HI 1 "general_operand" "0,0")
 		  (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "sub%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(minus:HI (match_dup 0)
 		  (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "sub%.w %1,%0")
 
 (define_insn "subqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
 	(minus:QI (match_operand:QI 1 "general_operand" "0,0")
 		  (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "sub%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(minus:QI (match_dup 0)
 		  (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "sub%.b %1,%0")
 
 (define_expand "subdf3"
@@ -2712,7 +2663,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 	(mult:SI (match_operand:SI 1 "general_operand" "")
 		 (match_operand:SI 2 "general_operand" "")))]
-  "TARGET_68020 || TARGET_5200"
+  "TARGET_68020 || TARGET_COLDFIRE"
   "")
 
 (define_insn ""
@@ -2727,7 +2678,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(mult:SI (match_operand:SI 1 "general_operand" "%0")
 		 (match_operand:SI 2 "general_operand" "d<Q>")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "muls%.l %2,%0")
 
 (define_insn "umulhisi3"
@@ -2773,7 +2724,7 @@
 	  (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					     (zero_extend:DI (match_dup 2)))
 				    (const_int 32))))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "")
 
 (define_insn ""
@@ -2784,7 +2735,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					   (zero_extend:DI (match_dup 2)))
 				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "mulu%.l %2,%3:%0")
 
 ; Match immediate case.  For 2.4 only match things < 2^31.
@@ -2799,7 +2750,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
 					   (match_dup 2))
 				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE
    && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
   "mulu%.l %2,%3:%0")
 
@@ -2812,7 +2763,7 @@
 	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					     (sign_extend:DI (match_dup 2)))
 				    (const_int 32))))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "")
 
 (define_insn ""
@@ -2823,7 +2774,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					   (sign_extend:DI (match_dup 2)))
 				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "muls%.l %2,%3:%0")
 
 (define_insn ""
@@ -2834,7 +2785,7 @@
 	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
 					   (match_dup 2))
 				  (const_int 32))))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "muls%.l %2,%3:%0")
 
 (define_expand "umulsi3_highpart"
@@ -2846,7 +2797,7 @@
 		     (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
 	    (const_int 32))))
      (clobber (match_dup 3))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "
 {
   operands[3] = gen_reg_rtx (SImode);
@@ -2871,7 +2822,7 @@
 		   (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "mulu%.l %3,%0:%1")
 
 (define_insn "const_umulsi3_highpart"
@@ -2882,7 +2833,7 @@
 		   (match_operand:DI 3 "const_uint32_operand" "n"))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "mulu%.l %3,%0:%1")
 
 (define_expand "smulsi3_highpart"
@@ -2894,7 +2845,7 @@
 		     (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
 	    (const_int 32))))
      (clobber (match_dup 3))])]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "
 {
   operands[3] = gen_reg_rtx (SImode);
@@ -2915,7 +2866,7 @@
 		   (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "muls%.l %3,%0:%1")
 
 (define_insn "const_smulsi3_highpart"
@@ -2926,7 +2877,7 @@
 		   (match_operand:DI 3 "const_sint32_operand" "n"))
 	  (const_int 32))))
    (clobber (match_operand:SI 1 "register_operand" "=d"))]
-  "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_68060 && !TARGET_COLDFIRE"
   "muls%.l %3,%0:%1")
 
 (define_expand "muldf3"
@@ -3026,17 +2977,10 @@
   "TARGET_68881"
   "*
 {
-#ifdef FSGLMUL_USE_S
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsmul%.s %2,%0\"
-	    : \"fsglmul%.s %2,%0\");
-#else
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
     return (TARGET_68040_ONLY
 	    ? \"fsmul%.x %2,%0\"
 	    : \"fsglmul%.x %2,%0\");
-#endif
   return (TARGET_68040_ONLY
 	  ? \"fsmul%.s %f2,%0\"
 	  : \"fsglmul%.s %f2,%0\");
@@ -3134,17 +3078,10 @@
   "TARGET_68881"
   "*
 {
-#ifdef FSGLDIV_USE_S
-  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
-    return (TARGET_68040_ONLY
-	    ? \"fsdiv%.s %2,%0\"
-	    : \"fsgldiv%.s %2,%0\");
-#else
   if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
     return (TARGET_68040_ONLY
 	    ? \"fsdiv%.x %2,%0\"
 	    : \"fsgldiv%.x %2,%0\");
-#endif
   return (TARGET_68040_ONLY
 	  ? \"fsdiv%.s %f2,%0\"
 	  : \"fsgldiv%.s %f2,%0\");
@@ -3152,13 +3089,40 @@
 
 ;; Remainder instructions.
 
-(define_insn "divmodsi4"
+(define_expand "divmodsi4"
+  [(parallel
+    [(set (match_operand:SI 0 "nonimmediate_operand" "")
+          (div:SI (match_operand:SI 1 "general_operand" "")
+                  (match_operand:SI 2 "general_src_operand" "")))
+     (set (match_operand:SI 3 "nonimmediate_operand" "")
+          (mod:SI (match_dup 1) (match_dup 2)))])]
+  "TARGET_68020 || TARGET_CF_HWDIV"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+	(div:SI (match_operand:SI 1 "general_operand" "0")
+		(match_operand:SI 2 "general_src_operand" "d<Q>U")))
+   (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
+	(mod:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_CF_HWDIV"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divs%.l %2,%0\";
+  else if (find_reg_note (insn, REG_UNUSED, operands[0]))
+    return \"rems%.l %2,%3:%0\";
+  else
+    return \"rems%.l %2,%3:%0\;divs%.l %2,%0\";
+}")
+
+(define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(div:SI (match_operand:SI 1 "general_operand" "0")
 		(match_operand:SI 2 "general_src_operand" "dmSTK")))
    (set (match_operand:SI 3 "nonimmediate_operand" "=d")
 	(mod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020 && !TARGET_5200"
+  "TARGET_68020"
   "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
@@ -3167,13 +3131,40 @@
     return \"divsl%.l %2,%3:%0\";
 }")
 
-(define_insn "udivmodsi4"
+(define_expand "udivmodsi4"
+  [(parallel
+    [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+          (udiv:SI (match_operand:SI 1 "general_operand" "0")
+                   (match_operand:SI 2 "general_src_operand" "dmSTK")))
+     (set (match_operand:SI 3 "nonimmediate_operand" "=d")
+          (umod:SI (match_dup 1) (match_dup 2)))])]
+  "TARGET_68020 || TARGET_CF_HWDIV"
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
+	(udiv:SI (match_operand:SI 1 "general_operand" "0")
+		 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
+   (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
+	(umod:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_CF_HWDIV"
+  "*
+{
+  if (find_reg_note (insn, REG_UNUSED, operands[3]))
+    return \"divu%.l %2,%0\";
+  else if (find_reg_note (insn, REG_UNUSED, operands[0]))
+    return \"remu%.l %2,%3:%0\";
+  else
+    return \"remu%.l %2,%3:%0\;divu%.l %2,%0\";
+}")
+
+(define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(udiv:SI (match_operand:SI 1 "general_operand" "0")
 		 (match_operand:SI 2 "general_src_operand" "dmSTK")))
    (set (match_operand:SI 3 "nonimmediate_operand" "=d")
 	(umod:SI (match_dup 1) (match_dup 2)))]
-  "TARGET_68020 && !TARGET_5200"
+  "TARGET_68020 && !TARGET_COLDFIRE"
   "*
 {
   if (find_reg_note (insn, REG_UNUSED, operands[3]))
@@ -3188,7 +3179,7 @@
 		(match_operand:HI 2 "general_src_operand" "dmSKT")))
    (set (match_operand:HI 3 "nonimmediate_operand" "=d")
 	(mod:HI (match_dup 1) (match_dup 2)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
   "*
 {
 #ifdef MOTOROLA
@@ -3211,7 +3202,7 @@
 		 (match_operand:HI 2 "general_src_operand" "dmSKT")))
    (set (match_operand:HI 3 "nonimmediate_operand" "=d")
 	(umod:HI (match_dup 1) (match_dup 2)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
   "*
 {
 #ifdef MOTOROLA
@@ -3235,7 +3226,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
 	(and:DI (match_operand:DI 1 "general_operand" "%0,0")
 		(match_operand:DI 2 "general_operand" "dn,don")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -3312,7 +3303,7 @@
   [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
 	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
 		(match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   return output_andsi3 (operands);
@@ -3322,49 +3313,49 @@
   [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
 	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
 		(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "and%.l %2,%0")
 
 (define_insn "andhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
 	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
 		(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(and:HI (match_dup 0)
 		(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.w %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.w %1,%0")
 
 (define_insn "andqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
 	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
 		(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(and:QI (match_dup 0)
 		(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.b %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "and%.b %1,%0")
 
 ;; inclusive-or instructions
@@ -3373,7 +3364,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
     (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
         (match_operand:DI 2 "general_operand" "0,0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   int byte_mode;
@@ -3400,7 +3391,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
 	(ior:DI (match_operand:DI 1 "general_operand" "%0,0")
 		(match_operand:DI 2 "general_operand" "dn,don")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -3477,7 +3468,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
 	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
                 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
-  "! TARGET_5200"
+  "! TARGET_COLDFIRE"
   "*
 {
   return output_iorsi3 (operands);
@@ -3487,49 +3478,49 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
 	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
 		(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "or%.l %2,%0")
 
 (define_insn "iorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
 	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
 		(match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(ior:HI (match_dup 0)
 		(match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.w %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
 	(ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.w %1,%0")
 
 (define_insn "iorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
 	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
                 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
 	(ior:QI (match_dup 0)
                 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.b %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
         (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "or%.b %1,%0")
 
 ;; On all 68k models, this makes faster code in a special case.
@@ -3556,7 +3547,7 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
     (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
         (match_operand:SI 2 "general_operand" "0,0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   int byte_mode;
@@ -3579,7 +3570,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
 	(xor:DI (match_operand:DI 1 "general_operand" "%0")
 		(match_operand:DI 2 "general_operand" "dn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -3660,7 +3651,7 @@
 	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
                 (match_operand:SI 2 "general_operand" "di,dKT")))]
 
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   return output_xorsi3 (operands);
@@ -3670,49 +3661,49 @@
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
 	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
 		(match_operand:SI 2 "general_operand" "d,Ks")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "eor%.l %2,%0")
 
 (define_insn "xorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(xor:HI (match_operand:HI 1 "general_operand" "%0")
 		(match_operand:HI 2 "general_operand" "dn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
 	(xor:HI (match_dup 0)
 		(match_operand:HI 1 "general_operand" "dn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.w %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
 	(xor:HI (match_operand:HI 1 "general_operand" "dn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.w %1,%0")
 
 (define_insn "xorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(xor:QI (match_operand:QI 1 "general_operand" "%0")
 		(match_operand:QI 2 "general_operand" "dn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
 	(xor:QI (match_dup 0)
 		(match_operand:QI 1 "general_operand" "dn")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.b %1,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
 	(xor:QI (match_operand:QI 1 "general_operand" "dn")
 		(match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "eor%.b %1,%0")
 
 ;; negation instructions
@@ -3723,7 +3714,7 @@
   ""
   "
 {
-  if (TARGET_5200)
+  if (TARGET_COLDFIRE)
     emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
   else
     emit_insn (gen_negdi2_internal (operands[0], operands[1]));
@@ -3733,7 +3724,7 @@
 (define_insn "negdi2_internal"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
 	(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (which_alternative == 0)
@@ -3751,7 +3742,7 @@
 (define_insn "negdi2_5200"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(neg:DI (match_operand:DI 1 "general_operand" "0")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
@@ -3764,7 +3755,7 @@
   ""
   "
 {
-  if (TARGET_5200)
+  if (TARGET_COLDFIRE)
     emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
   else
     emit_insn (gen_negsi2_internal (operands[0], operands[1]));
@@ -3774,37 +3765,37 @@
 (define_insn "negsi2_internal"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
 	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "neg%.l %0")
 
 (define_insn "negsi2_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "neg%.l %0")
 
 (define_insn "neghi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "neg%.w %0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
 	(neg:HI (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "neg%.w %0")
 
 (define_insn "negqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "neg%.b %0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
 	(neg:QI (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "neg%.b %0")
 
 ;; If using software floating point, just flip the sign bit.
@@ -4020,7 +4011,7 @@
 (define_insn "one_cmpldi2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
 	(not:DI (match_operand:DI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -4040,7 +4031,7 @@
   ""
   "
 {
-  if (TARGET_5200)
+  if (TARGET_COLDFIRE)
     emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
   else
     emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
@@ -4050,37 +4041,37 @@
 (define_insn "one_cmplsi2_internal"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
 	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "not%.l %0")
 
 (define_insn "one_cmplsi2_5200"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
 	(not:SI (match_operand:SI 1 "general_operand" "0")))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "not%.l %0")
 
 (define_insn "one_cmplhi2"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
 	(not:HI (match_operand:HI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "not%.w %0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
 	(not:HI (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "not%.w %0")
 
 (define_insn "one_cmplqi2"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
 	(not:QI (match_operand:QI 1 "general_operand" "0")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "not%.b %0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
 	(not:QI (match_dup 0)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "not%.b %0")
 
 ;; arithmetic shift instructions
@@ -4164,7 +4155,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(ashift:DI (match_operand:DI 1 "general_operand" "0")
 		     (match_operand 2 "const_int_operand" "n")))]
-  "(!TARGET_5200
+  "(!TARGET_COLDFIRE
     && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
 	|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	|| (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
@@ -4196,7 +4187,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(ashift:DI (match_operand:DI 1 "general_operand" "")
 		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
@@ -4230,7 +4221,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
 		   (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
+  "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -4259,28 +4250,28 @@
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(ashift:HI (match_operand:HI 1 "register_operand" "0")
 		   (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsl%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(ashift:HI (match_dup 0)
 		   (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsl%.w %1,%0")
 
 (define_insn "ashlqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ashift:QI (match_operand:QI 1 "register_operand" "0")
 		   (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsl%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(ashift:QI (match_dup 0)
 		   (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsl%.b %1,%0")
 
 ;; On most 68k models, this makes faster code in a special case.
@@ -4298,7 +4289,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
+  "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -4367,7 +4358,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
 		     (match_operand 2 "const_int_operand" "n")))]
-  "(!TARGET_5200 
+  "(!TARGET_COLDFIRE 
     && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
 	|| INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	|| INTVAL (operands[2]) == 31
@@ -4407,7 +4398,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(ashiftrt:DI (match_operand:DI 1 "general_operand" "")
 		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
@@ -4442,28 +4433,28 @@
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
 		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "asr%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(ashiftrt:HI (match_dup 0)
 		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "asr%.w %1,%0")
 
 (define_insn "ashrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "asr%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(ashiftrt:QI (match_dup 0)
 		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "asr%.b %1,%0")
 
 ;; logical shift instructions
@@ -4540,7 +4531,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
 		     (match_operand 2 "const_int_operand" "n")))]
-  "(!TARGET_5200
+  "(!TARGET_COLDFIRE
     && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
 	 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
 	 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
@@ -4575,7 +4566,7 @@
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(lshiftrt:DI (match_operand:DI 1 "general_operand" "")
 		     (match_operand 2 "const_int_operand" "")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "
 {
   /* ???  This is a named pattern like this is not allowed to FAIL based
@@ -4618,7 +4609,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (match_operand:SI 2 "const_int_operand" "n")))]
-  "(! TARGET_68020 && !TARGET_5200
+  "(! TARGET_68020 && !TARGET_COLDFIRE
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -4638,28 +4629,28 @@
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
 		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsr%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(lshiftrt:HI (match_dup 0)
 		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsr%.w %1,%0")
 
 (define_insn "lshrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsr%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(lshiftrt:QI (match_dup 0)
 		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "lsr%.b %1,%0")
 
 ;; rotate instructions
@@ -4668,7 +4659,7 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(rotate:SI (match_operand:SI 1 "register_operand" "0")
 		   (match_operand:SI 2 "general_operand" "dINO")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
@@ -4686,7 +4677,7 @@
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(rotate:HI (match_operand:HI 1 "register_operand" "0")
 		   (match_operand:HI 2 "general_operand" "dIP")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
@@ -4702,7 +4693,7 @@
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(rotate:HI (match_dup 0)
 		   (match_operand:HI 1 "general_operand" "dIP")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
@@ -4718,7 +4709,7 @@
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(rotate:QI (match_operand:QI 1 "register_operand" "0")
 		   (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
@@ -4734,7 +4725,7 @@
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(rotate:QI (match_dup 0)
 		   (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
@@ -4750,35 +4741,35 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "0")
 		     (match_operand:SI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "ror%.l %2,%0")
 
 (define_insn "rotrhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(rotatert:HI (match_operand:HI 1 "register_operand" "0")
 		     (match_operand:HI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "ror%.w %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(rotatert:HI (match_dup 0)
 		     (match_operand:HI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "ror%.w %1,%0")
 
 (define_insn "rotrqi3"
   [(set (match_operand:QI 0 "register_operand" "=d")
 	(rotatert:QI (match_operand:QI 1 "register_operand" "0")
 		     (match_operand:QI 2 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "ror%.b %2,%0")
 
 (define_insn ""
   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
 	(rotatert:QI (match_dup 0)
 		     (match_operand:QI 1 "general_operand" "dI")))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "ror%.b %1,%0")
 
 
@@ -5242,7 +5233,7 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
-  "! TARGET_5200"
+  "! TARGET_COLDFIRE"
   "*
 {
   return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
@@ -5252,7 +5243,7 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
@@ -5263,7 +5254,7 @@
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro,r")
        (match_operand:DI 3 "general_operand" "r,ro")]))]
-  "! TARGET_5200"
+  "! TARGET_COLDFIRE"
   "*
 {
   return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
@@ -5274,7 +5265,7 @@
     (match_operator 1 "valid_dbcc_comparison_p"
       [(match_operand:DI 2 "general_operand" "ro,r")
        (match_operand:DI 3 "general_operand" "r,ro")]))]
-  "TARGET_5200"
+  "TARGET_COLDFIRE"
   "*
 {
   return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
@@ -5721,7 +5712,7 @@
 #endif
     }
   operands[4] = gen_label_rtx();
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     {
 #ifdef MOTOROLA
       output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
@@ -5800,7 +5791,7 @@
       return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
 #endif
     }
-  if (TARGET_68020 || TARGET_5200)
+  if (TARGET_68020 || TARGET_COLDFIRE)
     {
 #ifdef MOTOROLA
       return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
@@ -5855,7 +5846,7 @@
 	}
     }
   CC_STATUS_INIT;
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
+  if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
     output_asm_insn(\"tst%.l %0\", operands);
   else
     {
@@ -5907,7 +5898,7 @@
 	}
     }
   CC_STATUS_INIT;
-  if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
+  if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
     output_asm_insn(\"tst%.l %0\", operands);
   else
     {
@@ -6526,7 +6517,7 @@
 #else
 #ifdef SGS
 #ifdef ASM_OUTPUT_CASE_LABEL
-  if (TARGET_5200) 
+  if (TARGET_COLDFIRE) 
     {
       if (ADDRESS_REG_P (operands[0]))
 	return \"jmp 6(%%pc,%0.l)\";
@@ -6536,7 +6527,7 @@
   else
     return \"jmp 6(%%pc,%0.w)\";
 #else
-  if (TARGET_5200)
+  if (TARGET_COLDFIRE)
     {
       if (ADDRESS_REG_P (operands[0]))
 	return \"jmp 2(%%pc,%0.l)\";
@@ -6547,7 +6538,7 @@
     return \"jmp 2(%%pc,%0.w)\";
 #endif
 #else /* not SGS */
-  if (TARGET_5200)
+  if (TARGET_COLDFIRE)
     {
       if (ADDRESS_REG_P (operands[0]))
 	{
@@ -6589,7 +6580,7 @@
    (set (match_dup 0)
 	(plus:HI (match_dup 0)
 		 (const_int -1)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
@@ -6598,22 +6589,14 @@
   if (GET_CODE (operands[0]) == MEM)
     {
 #ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-      return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
       return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
 #else /* not MOTOROLA */
       return \"subqw %#1,%0\;jcc %l1\";
 #endif
     }
 #ifdef MOTOROLA
 #ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#else
   return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
-#endif
 #else /* not SGS_CMP_ORDER */
   return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
 #endif
@@ -6632,28 +6615,17 @@
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
-  "!TARGET_5200"
+  "!TARGET_COLDFIRE"
   "*
 {
   CC_STATUS_INIT;
 #ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
   if (DATA_REG_P (operands[0]))
     return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
   if (GET_CODE (operands[0]) == MEM)
     return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif /* NO_ADDSUB_Q */
 #ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
   return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
 #else /* not SGS_CMP_ORDER */
   return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
 #endif /* not SGS_CMP_ORDER */
@@ -6679,28 +6651,17 @@
    (set (match_dup 0)
 	(plus:HI (match_dup 0)
 		 (const_int -1)))]
-  "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
+  "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
   "*
 {
   CC_STATUS_INIT;
 #ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.w %#1,%0\;jbcc %l1\";
-#else
   if (DATA_REG_P (operands[0]))
     return \"dbra %0,%l1\";
   if (GET_CODE (operands[0]) == MEM)
     return \"subq%.w %#1,%0\;jbcc %l1\";
-#endif
 #ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#else
   return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
-#endif
 #else /* not SGS_CMP_ORDER */
   return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
 #endif /* not SGS_CMP_ORDER */
@@ -6738,28 +6699,17 @@
    (set (match_dup 0)
 	(plus:SI (match_dup 0)
 		 (const_int -1)))]
-  "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
+  "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
   "*
 {
   CC_STATUS_INIT;
 #ifdef MOTOROLA
-#ifdef NO_ADDSUB_Q
-  if (DATA_REG_P (operands[0]))
-    return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
-  if (GET_CODE (operands[0]) == MEM)
-    return \"sub%.l %#1,%0\;jbcc %l1\";
-#else
   if (DATA_REG_P (operands[0]))
     return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
   if (GET_CODE (operands[0]) == MEM)
     return \"subq%.l %#1,%0\;jbcc %l1\";
-#endif
 #ifdef SGS_CMP_ORDER
-#ifdef NO_ADDSUB_Q
-  return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#else
   return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
-#endif
 #else /* not SGS_CMP_ORDER */
   return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
 #endif /* not SGS_CMP_ORDER */
@@ -6832,11 +6782,6 @@
   "! flag_pic"
   "*
 #if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
-  if (GET_CODE (operands[0]) == MEM
-      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
-    return \"bsr %0\";
-#endif
   return \"jsr %0\";
 #else
   return \"jbsr %0\";
@@ -6902,11 +6847,6 @@
   "! flag_pic"
   "*
 #if defined (MOTOROLA) && !defined (USE_GAS)
-#ifdef MOTOROLA_BSR
-  if (GET_CODE (operands[1]) == MEM
-      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
-    return \"bsr %1\";
-#endif
   return \"jsr %1\";
 #else
   return \"jbsr %1\";
@@ -7015,7 +6955,6 @@
   ""
   "*
 {
-#ifndef SGS_NO_LI
   /* Recognize an insn that refers to a table of offsets.  Such an insn will
      need to refer to a label on the insn.  So output one.  Use the
      label-number of the table of offsets to generate this label.  This code,
@@ -7044,7 +6983,6 @@
 #endif /* SGS_SWITCH_TABLES */
 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
     }
-#endif /* SGS_NO_LI */
 
   return \"lea %a1,%0\";
 }")
@@ -7087,10 +7025,9 @@
       rtx xoperands[2];
       xoperands[0] = stack_pointer_rtx;
       xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
       if (INTVAL (xoperands[1]) <= 8)
 	{
-	  if (!TARGET_5200)
+	  if (!TARGET_COLDFIRE)
 	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
 	  else
 	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
@@ -7100,9 +7037,7 @@
 	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
 	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
 	}
-      else
-#endif
-        if (INTVAL (xoperands[1]) <= 0x7FFF)
+      else if (INTVAL (xoperands[1]) <= 0x7FFF)
         {
 	  if (TARGET_68040)
 	    output_asm_insn (\"add%.w %1,%0\", xoperands);
@@ -7137,10 +7072,9 @@
       rtx xoperands[2];
       xoperands[0] = stack_pointer_rtx;
       xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
-#ifndef NO_ADDSUB_Q
       if (INTVAL (xoperands[1]) <= 8)
 	{
-	  if (!TARGET_5200)
+	  if (!TARGET_COLDFIRE)
 	    output_asm_insn (\"addq%.w %1,%0\", xoperands);
 	  else
 	    output_asm_insn (\"addq%.l %1,%0\", xoperands);
@@ -7150,9 +7084,7 @@
 	  xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
 	  output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
 	}
-      else
-#endif
-        if (INTVAL (xoperands[1]) <= 0x7FFF)
+      else if (INTVAL (xoperands[1]) <= 0x7FFF)
         {
 	  if (TARGET_68040)
 	    output_asm_insn (\"add%.w %1,%0\", xoperands);
@@ -7191,7 +7123,7 @@
   xoperands[2]
     = gen_rtx_MEM (QImode, plus_constant (stack_pointer_rtx, 3));
   xoperands[3] = stack_pointer_rtx;
-  if (!TARGET_5200)
+  if (!TARGET_COLDFIRE)
     output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
   else
     output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
@@ -7213,7 +7145,7 @@
 	      || GET_CODE (operands[0]) == MEM)
 	  /* clr insns on 68000 read before writing.
 	     This isn't so on the 68010, but we have no TARGET_68010.  */
-	  && ((TARGET_68020 || TARGET_5200)
+	  && ((TARGET_68020 || TARGET_COLDFIRE)
 	      || !(GET_CODE (operands[0]) == MEM
 		   && MEM_VOLATILE_P (operands[0]))))
 	return \"clr%.w %0\";
@@ -7253,7 +7185,7 @@
      (set (match_dup 0)
 	  (plus:HI (match_dup 0)
 		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+  "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
   "*
 {
   CC_STATUS_INIT;
@@ -7276,7 +7208,7 @@
      (set (match_dup 0)
 	  (plus:SI (match_dup 0)
 		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+  "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
   "*
 {
   CC_STATUS_INIT;
@@ -7300,7 +7232,7 @@
      (set (match_dup 0)
 	  (plus:HI (match_dup 0)
 		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+  "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
   "*
 {
   CC_STATUS_INIT;
@@ -7324,7 +7256,7 @@
      (set (match_dup 0)
 	  (plus:SI (match_dup 0)
 		   (const_int -1)))])]
-  "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
+  "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
   "*
 {
   CC_STATUS_INIT;
diff --git a/gcc/config/m68k/m68kelf.h b/gcc/config/m68k/m68kelf.h
index f481871c48d..585b24f11bb 100644
--- a/gcc/config/m68k/m68kelf.h
+++ b/gcc/config/m68k/m68kelf.h
@@ -1,7 +1,7 @@
 /* m68kelf support, derived from m68kv4.h */
 
 /* Target definitions for GNU compiler for mc680x0 running System V.4
-   Copyright (C) 1991, 1993, 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1991, 1993, 2000, 2002, 2003 Free Software Foundation, Inc.
 
    Written by Ron Guilmette (rfg@netcom.com) and Fred Fish (fnf@cygnus.com).
 
@@ -22,8 +22,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* #notinclude "m68k/sgs.h"	/ * The m68k/SVR4 assembler is SGS based */
-
 /* These are necessary for -fpic/-fPIC to work correctly.  */
 #ifndef MOTOROLA
 #define MOTOROLA                /* Use MOTOROLA syntax.  */
@@ -75,7 +73,7 @@ Boston, MA 02111-1307, USA.  */
 
 #define ASM_RETURN_CASE_JUMP				\
   do {							\
-    if (TARGET_5200)					\
+    if (TARGET_COLDFIRE)				\
       {							\
 	if (ADDRESS_REG_P (operands[0]))		\
 	  return "jmp %%pc@(2,%0:l)";			\
@@ -96,7 +94,7 @@ Boston, MA 02111-1307, USA.  */
 #define REGISTER_NAMES \
 {"%d0",   "%d1",   "%d2",   "%d3",   "%d4",   "%d5",   "%d6",   "%d7",	     \
  "%a0",   "%a1",   "%a2",   "%a3",   "%a4",   "%a5",   "%a6",   "%sp",	     \
- "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7" }
+ "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7", "argptr" }
 
 /* This is how to output an assembler line that says to advance the
    location counter to a multiple of 2**LOG bytes.  */
diff --git a/gcc/config/m68k/m68kv4.h b/gcc/config/m68k/m68kv4.h
index f826f0fbf04..161d60703af 100644
--- a/gcc/config/m68k/m68kv4.h
+++ b/gcc/config/m68k/m68kv4.h
@@ -1,5 +1,5 @@
 /* Target definitions for GNU compiler for mc680x0 running System V.4
-   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000
+   Copyright (C) 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2003
    Free Software Foundation, Inc.
    Contributed by Ron Guilmette (rfg@monkeys.com) and
    Fred Fish (fnf@cygnus.com).
@@ -34,19 +34,6 @@ Boston, MA 02111-1307, USA.  */
    }						\
   while (0)
 
-/* Use SGS_* macros to control compilation in m68k.md */
-
-#define SGS_SWITCH_TABLES	/* Different switch table handling */
-
-/* TODO: convert includes to ${tm_file} list in config.gcc.  */
-#include "m68k/sgs.h"		/* The m68k/SVR4 assembler is SGS based */
-
-#include "dbxelf.h"
-#include "elfos.h"
-#include "svr4.h"		/* Pick up the generic SVR4 macros */
-
-/* See m68k.h.  7 means 68020 with 68881.  */
-
 #ifndef TARGET_DEFAULT
 #define	TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
 #endif
@@ -257,7 +244,7 @@ do {									\
   switch_table_difference_label_flag = 0;				\
 } while (0)
 
-int switch_table_difference_label_flag;
+extern int switch_table_difference_label_flag;
 
 #undef ASM_OUTPUT_COMMON
 #undef ASM_OUTPUT_LOCAL
diff --git a/gcc/config/m68k/netbsd-elf.h b/gcc/config/m68k/netbsd-elf.h
index 14fcf1a962a..74f39ad0f1d 100644
--- a/gcc/config/m68k/netbsd-elf.h
+++ b/gcc/config/m68k/netbsd-elf.h
@@ -31,8 +31,6 @@ Boston, MA 02111-1307, USA.  */
       builtin_define ("__m68k__");		\
       builtin_define ("__SVR4_ABI__");		\
       builtin_define ("__motorola__");		\
-      builtin_assert ("cpu=m68k");		\
-      builtin_assert ("machine=m68k");		\
     }						\
   while (0)
 
@@ -204,7 +202,7 @@ while (0)
 #undef ASM_OUTPUT_CASE_LABEL
 #define ASM_RETURN_CASE_JUMP				\
   do {							\
-    if (TARGET_5200)					\
+    if (TARGET_COLDFIRE)				\
       {							\
 	if (ADDRESS_REG_P (operands[0]))		\
 	  return "jmp %%pc@(2,%0:l)";			\
diff --git a/gcc/config/m68k/netbsd.h b/gcc/config/m68k/netbsd.h
index 382adc0fa17..2b4fd855a9f 100644
--- a/gcc/config/m68k/netbsd.h
+++ b/gcc/config/m68k/netbsd.h
@@ -6,18 +6,9 @@
       builtin_define_std ("m68k");		\
       builtin_define_std ("mc68000");		\
       builtin_define_std ("mc68020");		\
-      builtin_assert ("cpu=m68k");		\
-      builtin_assert ("machine=m68k");		\
     }						\
   while (0)
 
-#include <m68k/m68k.h>
-
-/* Get generic NetBSD definitions.  */
-
-#include <netbsd.h>
-#include <netbsd-aout.h>
-
 #define TARGET_DEFAULT (MASK_BITFIELD|MASK_68881|MASK_68020)
 
 #define EXTRA_SPECS \
diff --git a/gcc/config/m68k/openbsd.h b/gcc/config/m68k/openbsd.h
index f577ca5afed..8fc5198f01b 100644
--- a/gcc/config/m68k/openbsd.h
+++ b/gcc/config/m68k/openbsd.h
@@ -1,5 +1,5 @@
 /* Configuration file for an m68k OpenBSD target.
-   Copyright (C) 1999, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -29,16 +29,6 @@ Boston, MA 02111-1307, USA.  */
    }						\
   while (0)
 
-/* m68k is an old configuration that does not yet use the TARGET_CPU_DEFAULT
-   framework.  */
-#define TARGET_DEFAULT (MASK_BITFIELD | MASK_68881 | MASK_68020)
-
-#include <m68k/m68k.h>
-
-/* Get generic OpenBSD definitions.  */
-#define OBSD_OLD_GAS
-#include <openbsd.h>
-
 /* Define __HAVE_68881__ in preprocessor, unless -msoft-float is specified.
    This will control the use of inline 68881 insns in certain macros.  */
 #undef CPP_SPEC
diff --git a/gcc/config/m68k/sgs.h b/gcc/config/m68k/sgs.h
index 470c066c995..1dc44c7735c 100644
--- a/gcc/config/m68k/sgs.h
+++ b/gcc/config/m68k/sgs.h
@@ -20,16 +20,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Control assembler-syntax conditionals in m68k.md and conditionals in
-   m68k.h.  Note that some systems may also require SGS_SWAP_W and/or
-   SGS_SWITCH_TABLES to be defined as well.  */
-
-#define MOTOROLA		/* Use Motorola syntax rather than "MIT" */
-#define SGS			/* Uses SGS assembler */
-#define SGS_CMP_ORDER		/* Takes cmp operands in reverse order */
-
-#include "m68k/m68k.h"
-
 #undef INT_OP_GROUP
 #define INT_OP_GROUP INT_OP_STANDARD
 
@@ -82,7 +72,7 @@ Boston, MA 02111-1307, USA.  */
 #define REGISTER_NAMES \
 {"%d0",   "%d1",   "%d2",   "%d3",   "%d4",   "%d5",   "%d6",   "%d7",	     \
  "%a0",   "%a1",   "%a2",   "%a3",   "%a4",   "%a5",   "%fp",   "%sp",	     \
- "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7" }
+ "%fp0",  "%fp1",  "%fp2",  "%fp3",  "%fp4",  "%fp5",  "%fp6",  "%fp7", "argptr" }
 
 /* This is how to output an assembler line that says to advance the
    location counter to a multiple of 2**LOG bytes.  */
diff --git a/gcc/config/m68k/t-m68kbare b/gcc/config/m68k/t-m68kbare
index d9651d1b75b..8bb4b948c35 100644
--- a/gcc/config/m68k/t-m68kbare
+++ b/gcc/config/m68k/t-m68kbare
@@ -15,7 +15,7 @@ xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
 MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68040/m68060 m68881/msoft-float
 MULTILIB_DIRNAMES =
 MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 
-MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68681 m68060/m68681
+MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68060/m68881
 
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/m68k/t-m68kelf b/gcc/config/m68k/t-m68kelf
index 6f7e3a0edc9..686e2d49054 100644
--- a/gcc/config/m68k/t-m68kelf
+++ b/gcc/config/m68k/t-m68kelf
@@ -12,11 +12,14 @@ xfgnulib.c: $(srcdir)/config/m68k/fpgnulib.c
 	echo '#define EXTFLOAT' > xfgnulib.c
 	cat $(srcdir)/config/m68k/fpgnulib.c >> xfgnulib.c
 
-MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68040/m68060 m68881/msoft-float
+MULTILIB_OPTIONS = m68000/m68020/m5200/m5206e/m528x/m5307/m5407/mcpu32/m68040/m68060 m68881/msoft-float
 MULTILIB_DIRNAMES =
-MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020
-MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float m68060/m68881 m68060/msoft-float
-
+MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m5206e=m5272
+MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float \
+		    m5206e/m68881 m5206e/msoft-float m528x/m68881 m528x/msoft-float \
+		    m5307/m68881 m5307/msoft-float m5407/m68881 m5407/msoft-float \
+		    mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68040/msoft-float \
+		    m68060/m68881 m68060/msoft-float 
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
 
diff --git a/gcc/config/m68k/t-rtems b/gcc/config/m68k/t-rtems
new file mode 100644
index 00000000000..d0e50e22ea9
--- /dev/null
+++ b/gcc/config/m68k/t-rtems
@@ -0,0 +1,6 @@
+# Custom multilibs for RTEMS
+
+MULTILIB_OPTIONS = m68000/m68020/m5200/mcpu32/m68030/m68040/m68060 m68881/msoft-float
+MULTILIB_DIRNAMES =
+MULTILIB_MATCHES = m68000=mc68000 m68000=m68302 mcpu32=m68332 m68020=mc68020 m68030=mc68030
+MULTILIB_EXCEPTIONS = m68000/msoft-float m5200/m68881 m5200/msoft-float mcpu32/m68881 mcpu32/msoft-float m68040/m68881 m68060/m68881
diff --git a/gcc/config/mcore/mcore-pe.h b/gcc/config/mcore/mcore-pe.h
index 35055e5762f..48b65d5219e 100644
--- a/gcc/config/mcore/mcore-pe.h
+++ b/gcc/config/mcore/mcore-pe.h
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for MCore using COFF/PE.
-   Copyright (C) 1994, 1999, 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1994, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Michael Tiemann (tiemann@cygnus.com).
 
 This file is part of GNU CC.
@@ -31,12 +31,9 @@ Boston, MA 02111-1307, USA.  */
 
 /* The MCore ABI says that bitfields are unsigned by default.  */
 /* The EPOC C++ environment does not support exceptions.  */
+#undef CC1_SPEC
 #define CC1_SPEC "-funsigned-bitfields %{!DIN_GCC:-fno-rtti} %{!DIN_GCC:-fno-exceptions}"
 
-#include "svr3.h"
-#include "mcore/mcore.h"
-#include "dbxcoff.h"
-
 #undef  SDB_DEBUGGING_INFO
 #define DBX_DEBUGGING_INFO 1
 
diff --git a/gcc/config/mcore/mcore-protos.h b/gcc/config/mcore/mcore-protos.h
index 7152a57d498..ae9f402f47f 100644
--- a/gcc/config/mcore/mcore-protos.h
+++ b/gcc/config/mcore/mcore-protos.h
@@ -65,6 +65,8 @@ extern void         mcore_print_operand_address  	PARAMS ((FILE *, rtx));
 extern void         mcore_print_operand          	PARAMS ((FILE *, rtx, int));
 extern rtx          mcore_gen_compare_reg        	PARAMS ((RTX_CODE));
 extern int          mcore_symbolic_address_p     	PARAMS ((rtx));
+extern bool         mcore_r15_operand_p			PARAMS ((rtx));
+extern enum reg_class mcore_secondary_reload_class	PARAMS ((enum reg_class, enum machine_mode, rtx));
 extern enum reg_class mcore_reload_class 		PARAMS ((rtx, enum reg_class));
 extern int          mcore_is_same_reg            	PARAMS ((rtx, rtx));
 extern int          mcore_arith_S_operand         	PARAMS ((rtx));
@@ -72,7 +74,6 @@ extern int          mcore_arith_S_operand         	PARAMS ((rtx));
 #ifdef HAVE_MACHINE_MODES
 extern const char * mcore_output_move          		PARAMS ((rtx, rtx *, enum machine_mode));
 extern const char * mcore_output_movedouble    		PARAMS ((rtx *, enum machine_mode));
-extern const char * mcore_output_inline_const_forced	PARAMS ((rtx, rtx *, enum machine_mode));
 extern int          mcore_arith_reg_operand       	PARAMS ((rtx, enum machine_mode));
 extern int          mcore_general_movsrc_operand  	PARAMS ((rtx, enum machine_mode));
 extern int          mcore_general_movdst_operand  	PARAMS ((rtx, enum machine_mode));
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 59c04d6c839..fe44a1ee7fc 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -1270,7 +1270,17 @@ mcore_output_move (insn, operands, mode)
 	  if (GET_CODE (XEXP (src, 0)) == LABEL_REF) 
             return "lrw\t%0,[%1]";              /* a-R */
 	  else
-            return "ldw\t%0,%1";                 /* r-m */
+	    switch (GET_MODE (src))		/* r-m */
+	      {
+	      case SImode:
+		return "ldw\t%0,%1";
+	      case HImode:
+		return "ld.h\t%0,%1";
+	      case QImode:
+		return "ld.b\t%0,%1";
+	      default:
+		abort ();
+	      }
 	}
       else if (GET_CODE (src) == CONST_INT)
 	{
@@ -1291,100 +1301,21 @@ mcore_output_move (insn, operands, mode)
 	return "lrw\t%0, %1";                /* Into the literal pool.  */
     }
   else if (GET_CODE (dst) == MEM)               /* m-r */
-    return "stw\t%1,%0";
+    switch (GET_MODE (dst))
+      {
+      case SImode:
+	return "stw\t%1,%0";
+      case HImode:
+	return "st.h\t%1,%0";
+      case QImode:
+	return "st.b\t%1,%0";
+      default:
+	abort ();
+      }
 
   abort ();
 }
 
-/* Outputs a constant inline -- regardless of the cost.
-   Useful for things where we've gotten into trouble and think we'd
-   be doing an lrw into r15 (forbidden). This lets us get out of
-   that pickle even after register allocation.  */
-
-const char *
-mcore_output_inline_const_forced (insn, operands, mode)
-     rtx insn ATTRIBUTE_UNUSED;
-     rtx operands[];
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  unsigned long value = INTVAL (operands[1]);
-  unsigned long ovalue = value;
-  struct piece
-  {
-    int low;
-    int shift;
-  }
-  part[6];
-  int i;
-
-  if (mcore_const_ok_for_inline (value))
-    return output_inline_const (SImode, operands);
-
-  for (i = 0; (unsigned) i < ARRAY_SIZE (part); i++)
-    {
-      part[i].shift = 0;
-      part[i].low = (value & 0x1F);
-      value -= part[i].low;
-      
-      if (mcore_const_ok_for_inline (value))
-	break;
-      else
-	{
-	  value >>= 5;
-	  part[i].shift = 5;
-	  
-	  while ((value & 1) == 0)
-	    {
-	      part[i].shift++;
-	      value >>= 1;
-	    }
-	  
-	  if (mcore_const_ok_for_inline (value))
-	    break;
-	}
-    }
-  
-  /* 5 bits per iteration, a maximum of 5 times == 25 bits and leaves
-     7 bits left in the constant -- which we know we can cover with
-     a movi.  The final value can't be zero otherwise we'd have stopped
-     in the previous iteration.   */
-  if (value == 0 || ! mcore_const_ok_for_inline (value))
-    abort ();
-
-  /* Now, work our way backwards emitting the constant.  */
-
-  /* Emit the value that remains -- it will be nonzero.  */
-  operands[1] = GEN_INT (value);
-  output_asm_insn (output_inline_const (SImode, operands), operands);
- 
-  while (i >= 0)
-    {
-      /* Shift anything we've already loaded.  */
-      if (part[i].shift)
-        {
-	  operands[2] = GEN_INT (part[i].shift);
-	  output_asm_insn ("lsli       %0,%2", operands);
-	  value <<= part[i].shift;
-        }
-      
-      /* Add anything we need into the low 5 bits.  */
-      if (part[i].low != 0)
-        {
-	  operands[2] = GEN_INT (part[i].low);
-	  output_asm_insn ("addi      %0,%2", operands);
-	  value += part[i].low;
-        }
-      
-      i--;
-    }
-  
-  if (value != ovalue)          /* sanity */
-    abort ();
- 
-  /* We've output all the instructions.  */
-  return "";
-}
-
 /* Return a sequence of instructions to perform DI or DF move.
    Since the MCORE cannot move a DI or DF in one instruction, we have
    to take care when we see overlapping source and dest registers.  */
@@ -3064,36 +2995,53 @@ mcore_reorg ()
 }
 
 
-/* Return the reg_class to use when reloading the rtx X into the class
-   CLASS.  */
+/* Return true if X is something that can be moved directly into r15.  */
 
-/* If the input is (PLUS REG CONSTANT) representing a stack slot address,
-   then we want to restrict the class to LRW_REGS since that ensures that
-   will be able to safely load the constant.
+bool
+mcore_r15_operand_p (x)
+     rtx x;
+{
+  switch (GET_CODE (x))
+    {
+    case CONST_INT:
+      return mcore_const_ok_for_inline (INTVAL (x));
 
-   If the input is a constant that should be loaded with mvir1, then use
-   ONLYR1_REGS.
+    case REG:
+    case SUBREG:
+    case MEM:
+      return 1;
+
+    default:
+      return 0;
+    }
+}
+
+/* Implement SECONDARY_RELOAD_CLASS.  If CLASS contains r15, and we can't
+   directly move X into it, use r1-r14 as a temporary.  */
+enum reg_class
+mcore_secondary_reload_class (class, mode, x)
+     enum reg_class class;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+     rtx x;
+{
+  if (TEST_HARD_REG_BIT (reg_class_contents[class], 15)
+      && !mcore_r15_operand_p (x))
+    return LRW_REGS;
+  return NO_REGS;
+}
 
-   ??? We don't handle the case where we have (PLUS REG CONSTANT) and
-   the constant should be loaded with mvir1, because that can lead to cases
-   where an instruction needs two ONLYR1_REGS reloads.  */
+/* Return the reg_class to use when reloading the rtx X into the class
+   CLASS.  If X is too complex to move directly into r15, prefer to
+   use LRW_REGS instead.  */
 enum reg_class
 mcore_reload_class (x, class)
      rtx x;
      enum reg_class class;
 {
-  enum reg_class new_class;
-
-  if (class == GENERAL_REGS && CONSTANT_P (x)
-      && (GET_CODE (x) != CONST_INT
-	  || (   ! CONST_OK_FOR_I (INTVAL (x))
-	      && ! CONST_OK_FOR_M (INTVAL (x))
-	      && ! CONST_OK_FOR_N (INTVAL (x)))))
-    new_class = LRW_REGS;
-  else
-    new_class = class;
+  if (reg_class_subset_p (LRW_REGS, class) && !mcore_r15_operand_p (x))
+    return LRW_REGS;
 
-  return new_class;
+  return class;
 }
 
 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
@@ -3410,7 +3358,7 @@ mcore_mark_dllimport (decl)
       && !DECL_VIRTUAL_P (decl)
       && DECL_INITIAL (decl))
     {
-      error_with_decl (decl, "initialized variable `%s' is marked dllimport");
+      error ("%Jinitialized variable '%D' is marked dllimport", decl, decl);
       return;
     }
   
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index dddd5c15232..6a489e9fa9b 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -28,12 +28,6 @@
 #define	MCORE_STRUCT_ARGS
 /* RBE: end of "move elsewhere".  */
 
-#include "hwint.h"
-
-#ifndef HAVE_MACHINE_MODES
-#include "machmode.h"
-#endif
-
 /* Run-time Target Specification.  */
 #define TARGET_MCORE
 
@@ -179,10 +173,8 @@ extern const char * mcore_stack_increment_string;
      N_("Maximum amount for a single stack increment operation"), 0}	\
 }
 
-#ifndef CC1_SPEC
 /* The MCore ABI says that bitfields are unsigned by default.  */
 #define CC1_SPEC "-funsigned-bitfields"
-#endif
 
 /* What options are we going to default to specific settings when
    -O* happens; the user can subsequently override these settings.
@@ -611,7 +603,8 @@ extern const enum reg_class reg_class_from_letter[];
 /* Return the register class of a scratch register needed to copy IN into
    or out of a register in CLASS in MODE.  If it can be done directly,
    NO_REGS is returned.  */
-#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) NO_REGS
+#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
+  mcore_secondary_reload_class (CLASS, MODE, X)
 
 /* Return the maximum number of consecutive registers
    needed to represent mode MODE in a register of class CLASS. 
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index bfdd844c21a..700dcb2cdc9 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -1226,101 +1226,20 @@
 {
   if (GET_CODE (operands[0]) == MEM)
     operands[1] = force_reg (SImode, operands[1]);
-  else if (CONSTANT_P (operands[1])
-	   && (GET_CODE (operands[1]) != CONST_INT
-	       || (   ! CONST_OK_FOR_I (INTVAL (operands[1]))
-		   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
-		   && ! CONST_OK_FOR_N (INTVAL (operands[1]))
-                   && (! TARGET_HARDLIT ||
-                       ! mcore_const_ok_for_inline (INTVAL (operands[1])))))
-	   && ! reload_completed
-	   && ! reload_in_progress
-	   && GET_CODE (operands[0]) == REG
-	   && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-	   && (REGNO (operands[0]) == STACK_POINTER_REGNUM
-	       || REGNO (operands[0]) == LK_REG))
-    operands[1] = force_reg (SImode, operands[1]);
 }")
 
-;;; Must put a/i before r/r so that it will be preferred when the dest is
-;;; a hard register.  Must put a/R before r/m.
-;;; DO WE NEED a/i ANYMORE?
-
 (define_insn ""
-  [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,r,a,r,r,a,r,m")
-	(match_operand:SI 1 "mcore_general_movsrc_operand"  "I,M,N,i,r,c,R,m,r"))]
+  [(set (match_operand:SI 0 "mcore_general_movdst_operand" "=r,r,a,r,a,r,m")
+	(match_operand:SI 1 "mcore_general_movsrc_operand"  "r,P,i,c,R,m,r"))]
   "(register_operand (operands[0], SImode)
-       || register_operand (operands[1], SImode))
-   && ! (CONSTANT_P (operands[1])
-         && (GET_CODE (operands[1]) != CONST_INT
-	     || (   ! CONST_OK_FOR_I (INTVAL (operands[1]))
-                 && ! CONST_OK_FOR_M (INTVAL (operands[1]))
-                 && ! CONST_OK_FOR_N (INTVAL (operands[1]))))
-	 && GET_CODE (operands[0]) == REG
-	 && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
-         && (REGNO (operands[0]) == STACK_POINTER_REGNUM
-	     || REGNO (operands[0]) == LK_REG))"
+    || register_operand (operands[1], SImode))"
   "* return mcore_output_move (insn, operands, SImode);"
-  [(set_attr "type" "move,move,move,move,move,move,load,load,store")])
+  [(set_attr "type" "move,move,move,move,load,load,store")])
 
-;; This is to work around a bug in reload.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(match_operand:SI 1 "immediate_operand" "i"))]
-  "((reload_in_progress || reload_completed)
-   && CONSTANT_P (operands[1])
-   && GET_CODE (operands[1]) == CONST_INT
-   && ! CONST_OK_FOR_I (INTVAL (operands[1]))
-   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
-   && ! CONST_OK_FOR_N (INTVAL (operands[1]))
-   && GET_CODE (operands[0]) == REG
-   && REGNO (operands[0]) == LK_REG)"
-  "* return mcore_output_inline_const_forced (insn, operands, SImode);"
-  [(set_attr "type" "load")])
-
-;; (define_expand "reload_insi"
-;;   [(parallel [(match_operand:SI 0 "register_operand" "=r")
-;; 	      (match_operand:SI 1 "general_operand"  "")
-;; 	      (match_operand:DI 2 "register_operand" "=&r")])]
-;;   ""
-;;   "
-;;   {
-;;     if (CONSTANT_P (operands[1])
-;;        && GET_CODE (operands[1]) == CONST_INT
-;;        && ! CONST_OK_FOR_I (INTVAL (operands[1]))
-;;        && ! CONST_OK_FOR_M (INTVAL (operands[1]))
-;;        && ! CONST_OK_FOR_N (INTVAL (operands[1]))
-;;        && GET_CODE (operands[0]) == REG
-;;        && (REGNO (operands[0]) == STACK_POINTER_REGNUM
-;;           || REGNO (operands[0]) == LK_REG))
-;;       {
-;;         rtx tmp;
-;; 
-;; 	if (   REGNO (operands[2]) == REGNO (operands[0])
-;;             || REGNO (operands[2]) == STACK_POINTER_REGNUM
-;; 	    || REGNO (operands[2]) == LK_REG)
-;;           tmp = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
-;; 	else
-;;           tmp = gen_rtx_REG (SImode, REGNO (operands[2]));
-;; 	
-;;         emit_insn (gen_movsi (tmp, operands[1]));
-;;         emit_insn (gen_movsi (operands[0], tmp));
-;;         DONE;
-;;       }
-;;     emit_insn (gen_movsi (operands[0], operands[1]));
-;;     DONE;
-;;   }"
-;; )
-			       
-	    
-			       
 ;;
 ;; HImode
 ;;
 
-;;; ??? This isn't guaranteed to work.  It should be more like the SImode
-;;; patterns.
-
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
 	(match_operand:HI 1 "general_operand"  ""))]
@@ -1338,73 +1257,17 @@
     {
       rtx reg = gen_reg_rtx (SImode);
       emit_insn (gen_movsi (reg, operands[1]));
-      operands[1] = gen_rtx (SUBREG, HImode, reg, 0);
+      operands[1] = gen_lowpart (HImode, reg);
     }
 }")
   
 (define_insn ""
-  [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
-	(match_operand:HI 1 "mcore_general_movsrc_operand"  "r,I,M,N,c,m,r"))]
+  [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
+	(match_operand:HI 1 "mcore_general_movsrc_operand"  "r,P,i,c,m,r"))]
   "(register_operand (operands[0], HImode)
-       || register_operand (operands[1], HImode))
-   && (GET_CODE (operands[1]) != CONST_INT
-       || CONST_OK_FOR_M (INTVAL (operands[1]))
-       || CONST_OK_FOR_N (INTVAL (operands[1]))
-       || CONST_OK_FOR_I (INTVAL (operands[1])))"
-  "@
-	mov	%0,%1
-	movi	%0,%1
-	bgeni	%0,%P1
-	bmaski	%0,%N1
-	mvc	%0
-	ld.h	%0,%1
-	st.h	%1,%0"
-  [(set_attr "type" "move,move,move,move,move,load,store")])
-
-;; Like movhi, but the const_int source can't be synthesized in
-;; a single-instruction.  Fall back to the same things that 
-;; are done for movsi in such cases.  Presumes that we can
-;; modify any parts of the register that we wish.
-
-(define_insn ""
-  [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
-	(match_operand:HI 1 "const_int_operand"  "P,i"))]
-  "GET_CODE (operands[1]) == CONST_INT
-    && INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 65536"
-  "*
-{
-  if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
-      && !mcore_const_ok_for_inline (INTVAL (operands[1])))
-    {
-      /* mcore_output_move would generate lrw r15 -- a forbidden combo */
-      return mcore_output_inline_const_forced (insn, operands, SImode);
-    }
-  else
-    return mcore_output_move (insn, operands, SImode);
-}"
-  [(set_attr "type" "move")])
-
-
-;; if we're still looking around for things to use, here's a last
-;; ditch effort that just calls the move. We only let this happen
-;; if we're in the reload pass.
-;;
-(define_insn ""
-  [(set (match_operand:HI 0 "mcore_general_movdst_operand" "=r,a")
-	(match_operand:HI 1 "const_int_operand"  "P,i"))]
-  "reload_in_progress || reload_completed"
-  "*
-{
-  if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
-      && !mcore_const_ok_for_inline (INTVAL (operands[1])))
-    {
-      /* mcore_output_move would generate lrw r15 -- a forbidden combo */
-      return mcore_output_inline_const_forced (insn, operands, SImode);
-    }
-  else
-    return mcore_output_move (insn, operands, HImode);
-}"
-  [(set_attr "type" "move")])
+    || register_operand (operands[1], HImode))"
+  "* return mcore_output_move (insn, operands, HImode);"
+  [(set_attr "type" "move,move,move,move,load,store")])
 
 ;;
 ;; QImode
@@ -1427,67 +1290,18 @@
     {
       rtx reg = gen_reg_rtx (SImode);
       emit_insn (gen_movsi (reg, operands[1]));
-      operands[1] = gen_rtx (SUBREG, QImode, reg, 0);
+      operands[1] = gen_lowpart (QImode, reg);
     }
 }")
   
 (define_insn ""
-  [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,r,r,r,r,m")
-	(match_operand:QI 1 "mcore_general_movsrc_operand"  "r,I,M,N,c,m,r"))]
+  [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,r,a,r,r,m")
+	(match_operand:QI 1 "mcore_general_movsrc_operand"  "r,P,i,c,m,r"))]
   "(register_operand (operands[0], QImode)
-       || register_operand (operands[1], QImode))
-   && (GET_CODE (operands[1]) != CONST_INT
-       || CONST_OK_FOR_M (INTVAL (operands[1]))
-       || CONST_OK_FOR_N (INTVAL (operands[1]))
-       || CONST_OK_FOR_I (INTVAL (operands[1])))"
-  "@
-	mov	%0,%1
-	movi	%0,%1
-	bgeni	%0,%P1
-	bmaski	%0,%N1
-	mvc	%0
-	ld.b	%0,%1
-	st.b	%1,%0" 
-   [(set_attr "type" "move,move,move,move,move,load,store")])
-
-;; cover the case where the constant is 128..255; this isn't handled
-;; in the above case. We could if we wanted to mess with adding a 
-;; new constraint class like M,N,I.
-(define_insn ""
-  [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r")
-	(match_operand:QI 1 "const_int_operand"  ""))]
-  "GET_CODE (operands[1]) == CONST_INT
-    && INTVAL (operands[1]) > 127 && INTVAL (operands[1]) < 256"
-  "*
-{
-   /* have a constant in range 128..255; have to do 2 insns; we can
-    * do this with a movi followed by a bseti
-    */
-   operands[2] = GEN_INT (INTVAL (operands[1]) & 0x7f);
-   return \"movi\\t%0,%2\;bseti\\t%0,7\";
-}"
-  [(set_attr "type" "move")])
+    || register_operand (operands[1], QImode))"
+  "* return mcore_output_move (insn, operands, QImode);"
+   [(set_attr "type" "move,move,move,move,load,store")])
 
-;; if we're still looking around for things to use, here's a last
-;; ditch effort that just calls the move. We only let this happen
-;; if we're in the reload pass.
-;;
-(define_insn ""
-  [(set (match_operand:QI 0 "mcore_general_movdst_operand" "=r,a")
-	(match_operand:QI 1 "const_int_operand"  "P,i"))]
-  "(reload_in_progress || reload_completed)"
-  "*
-{
-  if (GET_CODE (operands[0])== REG && REGNO (operands[0]) == 15
-      && ! mcore_const_ok_for_inline (INTVAL (operands[1])))
-    {
-      /* mcore_output_move would generate lrw r15 -- a forbidden combo */
-      return mcore_output_inline_const_forced (insn, operands, SImode);
-    }
-  else
-    return mcore_output_move (insn, operands, QImode);
-}"
-  [(set_attr "type" "move")])
 
 ;; DImode
 
@@ -1502,15 +1316,12 @@
   else if (GET_CODE (operands[1]) == CONST_INT
            && ! CONST_OK_FOR_I (INTVAL (operands[1]))
 	   && ! CONST_OK_FOR_M (INTVAL (operands[1]))
-	   && ! CONST_OK_FOR_N (INTVAL (operands[1]))
-	   && ! reload_completed
-	   && ! reload_in_progress
-	   && GET_CODE (operands[0]) == REG)
+	   && ! CONST_OK_FOR_N (INTVAL (operands[1])))
     {
-      emit_move_insn (operand_subword (operands[0], 0, 1, DImode),
-	   	      operand_subword_force (operands[1], 0, DImode));
-      emit_move_insn (operand_subword (operands[0], 1, 1, DImode),
-	  	      operand_subword_force (operands[1], 1, DImode));
+      int i;
+      for (i = 0; i < UNITS_PER_WORD * 2; i += UNITS_PER_WORD)
+        emit_move_insn (simplify_gen_subreg (SImode, operands[0], DImode, i),
+		        simplify_gen_subreg (SImode, operands[1], DImode, i));
       DONE;
     }
 }")
diff --git a/gcc/config/mips/5400.md b/gcc/config/mips/5400.md
index 6934b7433df..70386fc518b 100644
--- a/gcc/config/mips/5400.md
+++ b/gcc/config/mips/5400.md
@@ -44,11 +44,10 @@
 
 
 ;; This reservation is for conditional move based on integer
-;; or floating point CC.  This could probably use some refinement
-;; as "move" type attr seems to be overloaded in rtl.
-(define_insn_reservation "ir_vr54_move" 4
+;; or floating point CC.
+(define_insn_reservation "ir_vr54_condmove" 4
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "move"))
+       (eq_attr "type" "condmove"))
   "vr54_dp0|vr54_dp1")
 
 ;; Move to/from FPU registers
@@ -64,7 +63,7 @@
 
 (define_insn_reservation "ir_vr54_arith" 1
   (and (eq_attr "cpu" "r5400")
-       (eq_attr "type" "arith,darith,const,icmp,nop"))
+       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
   "vr54_dp0|vr54_dp1")
 
 (define_insn_reservation "ir_vr54_imul_si" 3
diff --git a/gcc/config/mips/5500.md b/gcc/config/mips/5500.md
index dc85356d98b..0abee1741c2 100644
--- a/gcc/config/mips/5500.md
+++ b/gcc/config/mips/5500.md
@@ -37,11 +37,10 @@
   "vr55_mem")
 
 ;; This reservation is for conditional move based on integer
-;; or floating point CC.  This could probably use some refinement
-;; as "move" type attr seems to be overloaded in rtl.
-(define_insn_reservation "ir_vr55_move" 2
+;; or floating point CC.
+(define_insn_reservation "ir_vr55_condmove" 2
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "move"))
+       (eq_attr "type" "condmove"))
   "vr55_dp0|vr55_dp1")
 
 ;; Move to/from FPU registers
@@ -57,7 +56,7 @@
 
 (define_insn_reservation "ir_vr55_arith" 1
   (and (eq_attr "cpu" "r5500")
-       (eq_attr "type" "arith,darith,const,icmp,nop"))
+       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
   "vr55_dp0|vr55_dp1")
 
 (define_insn_reservation "ir_vr55_imul_si" 3
diff --git a/gcc/config/mips/7000.md b/gcc/config/mips/7000.md
new file mode 100644
index 00000000000..2ea6298fddf
--- /dev/null
+++ b/gcc/config/mips/7000.md
@@ -0,0 +1,211 @@
+;; DFA-based pipeline description for the RM7000.
+;;   Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to the
+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+;; MA 02111-1307, USA.
+
+;; .........................
+;;
+;; The RM7000 is a dual-issue processor that can bundle instructions as:
+;; {arith|load|store}{arith|imul|idiv|branch|float}
+;;
+;; Reference:
+;;   "RM7000 Family User Manual, PMC-2002296"
+;;
+;; .........................
+
+;; Use three automata to isolate long latency operations, reducing space.
+(define_automaton "rm7000_other, rm7000_fdiv, rm7000_idiv")
+
+;;
+;; Describe the resources.
+;;
+
+;; Global
+(define_cpu_unit "rm7_iss0,rm7_iss1" "rm7000_other")
+
+;; Integer execution unit (M-Pipe).
+(define_cpu_unit "ixum_addsub_agen" "rm7000_other")
+
+;; Integer execution unit (F-Pipe).
+(define_cpu_unit "ixuf_addsub"	"rm7000_other")
+(define_cpu_unit "ixuf_branch"	"rm7000_other")
+(define_cpu_unit "ixuf_mpydiv"	"rm7000_other")
+(define_cpu_unit "ixuf_mpydiv_iter" "rm7000_idiv")
+;; Floating-point unit (F-Pipe).
+(define_cpu_unit "fxuf_add"	"rm7000_other")
+(define_cpu_unit "fxuf_mpy"	"rm7000_other")
+(define_cpu_unit "fxuf_mpy_iter" "rm7000_fdiv")
+(define_cpu_unit "fxuf_divsqrt" "rm7000_other")
+(define_cpu_unit "fxuf_divsqrt_iter" "rm7000_fdiv")
+
+(exclusion_set "ixuf_addsub"
+	       "ixuf_branch,ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "ixuf_branch"	"ixuf_mpydiv,fxuf_add,fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "ixuf_mpydiv"	"fxuf_add,fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "fxuf_add"	"fxuf_mpy,fxuf_divsqrt")
+(exclusion_set "fxuf_mpy"	"fxuf_divsqrt")
+
+;; After branch any insn can not be issued.
+(absence_set "rm7_iss0,rm7_iss1" "ixuf_branch")
+
+;;
+;; Define reservations for unit name mnemonics or combinations.
+;;
+
+(define_reservation "rm7_iss"		"rm7_iss0|rm7_iss1")
+(define_reservation "rm7_single_dispatch" "rm7_iss0+rm7_iss1")
+
+(define_reservation "rm7_iaddsub" "rm7_iss+(ixum_addsub_agen|ixuf_addsub)")
+(define_reservation "rm7_imem"		"rm7_iss+ixum_addsub_agen")
+(define_reservation "rm7_impydiv"	"rm7_iss+ixuf_mpydiv")
+(define_reservation "rm7_impydiv_iter"	"ixuf_mpydiv_iter")
+(define_reservation "rm7_branch"	"rm7_iss+ixuf_branch")
+
+(define_reservation "rm7_fpadd"	"rm7_iss+fxuf_add")
+(define_reservation "rm7_fpmpy"	"rm7_iss+fxuf_mpy")
+(define_reservation "rm7_fpmpy_iter" "fxuf_mpy_iter")
+(define_reservation "rm7_fpdivsqr" "rm7_iss+fxuf_divsqrt")
+(define_reservation "rm7_fpdivsqr_iter" "fxuf_divsqrt_iter")
+
+;;
+;; Describe instruction reservations for integer operations.
+;;
+
+(define_insn_reservation "rm7_int_other" 1
+			 (and (eq_attr "cpu" "r7000")
+			      (eq_attr "type" "arith,darith,const,move,condmove,icmp,nop"))
+			 "rm7_iaddsub")
+
+(define_insn_reservation "rm7_ld" 2 (and (eq_attr "cpu" "r7000")
+				         (eq_attr "type" "load"))
+			 "rm7_imem")
+
+(define_insn_reservation "rm7_st" 1 (and (eq_attr "cpu" "r7000")
+				         (eq_attr "type" "store"))
+			 "rm7_imem")
+
+(define_insn_reservation "rm7_idiv_si" 36 (and (eq_attr "cpu" "r7000")
+					   (and (eq_attr "type" "idiv")
+						(eq_attr "mode" "SI")))
+			 "rm7_impydiv+(rm7_impydiv_iter*36)")
+
+(define_insn_reservation "rm7_idiv_di" 68 (and (eq_attr "cpu" "r7000")
+					   (and (eq_attr "type" "idiv")
+						(eq_attr "mode" "DI")))
+			 "rm7_impydiv+(rm7_impydiv_iter*68)")
+
+(define_insn_reservation "rm7_impy_si_mult" 5
+		 (and (eq_attr "cpu" "r7000")
+		      (and (eq_attr "type" "imul,imadd")
+			   (and (eq_attr "mode" "SI")
+				(match_operand 0 "hilo_operand" ""))))
+			 "rm7_impydiv+(rm7_impydiv_iter*3)")
+
+;; There are an additional 2 stall cycles.
+(define_insn_reservation "rm7_impy_si_mul" 2
+		 (and (eq_attr "cpu" "r7000")
+		      (and (eq_attr "type" "imul,imadd")
+			   (and (eq_attr "mode" "SI")
+				(not (match_operand 0 "hilo_operand" "")))))
+			 "rm7_impydiv")
+
+(define_insn_reservation "rm7_impy_di" 9 (and (eq_attr "cpu" "r7000")
+					  (and (eq_attr "type" "imul")
+					       (eq_attr "mode" "DI")))
+			 "rm7_impydiv+(rm7_impydiv_iter*8)")
+
+;; Move to/from HI/LO.
+(define_insn_reservation "rm7_mthilo" 3
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "hilo")
+				   (match_operand 0 "hilo_operand" "")))
+			 "rm7_impydiv")
+
+(define_insn_reservation "rm7_mfhilo" 1
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "hilo")
+				   (not (match_operand 0 "hilo_operand" ""))))
+			 "rm7_impydiv")
+
+;; Move to/from fp coprocessor.
+(define_insn_reservation "rm7_ixfer" 2 (and (eq_attr "cpu" "r7000")
+					(eq_attr "type" "xfer"))
+			 "rm7_iaddsub")
+
+(define_insn_reservation "rm7_ibr" 3 (and (eq_attr "cpu" "r7000")
+				      (eq_attr "type" "branch,jump,call"))
+			 "rm7_branch")
+
+;;
+;; Describe instruction reservations for the floating-point operations.
+;;
+(define_insn_reservation "rm7_fp_quick" 4
+			 (and (eq_attr "cpu" "r7000")
+			      (eq_attr "type" "fneg,fcmp,fabs"))
+			 "rm7_fpadd")
+
+(define_insn_reservation "rm7_fp_other" 4
+			 (and (eq_attr "cpu" "r7000")
+			      (eq_attr "type" "fadd"))
+			 "rm7_fpadd")
+
+(define_insn_reservation "rm7_fp_cvt" 4
+			 (and (eq_attr "cpu" "r7000")
+			      (eq_attr "type" "fcvt"))
+			 "rm7_fpadd")
+
+(define_insn_reservation "rm7_fp_divsqrt_df" 36
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "fdiv,fsqrt")
+				   (eq_attr "mode" "DF")))
+			 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*36)")
+
+(define_insn_reservation "rm7_fp_divsqrt_sf" 21
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "fdiv,fsqrt")
+				   (eq_attr "mode" "SF")))
+			 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*21)")
+
+(define_insn_reservation "rm7_fp_rsqrt_df" 68
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "frsqrt")
+				   (eq_attr "mode" "DF")))
+			 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*68)")
+
+(define_insn_reservation "rm7_fp_rsqrt_sf" 38
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "frsqrt")
+				   (eq_attr "mode" "SF")))
+			 "rm7_fpdivsqr+(rm7_fpdivsqr_iter*38)")
+
+(define_insn_reservation "rm7_fp_mpy_sf" 4
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "fmul,fmadd")
+				   (eq_attr "mode" "SF")))
+			 "rm7_fpmpy+rm7_fpmpy_iter")
+
+(define_insn_reservation "rm7_fp_mpy_df" 5
+			 (and (eq_attr "cpu" "r7000")
+			      (and (eq_attr "type" "fmul,fmadd")
+				   (eq_attr "mode" "DF")))
+			 "rm7_fpmpy+(rm7_fpmpy_iter*2)")
+
+;; Force single-dispatch for unknown or multi.
+(define_insn_reservation "rm7_unknown" 1 (and (eq_attr "cpu" "r7000")
+					  (eq_attr "type" "unknown,multi"))
+			 "rm7_single_dispatch")
diff --git a/gcc/config/mips/9000.md b/gcc/config/mips/9000.md
new file mode 100644
index 00000000000..124941b33ea
--- /dev/null
+++ b/gcc/config/mips/9000.md
@@ -0,0 +1,154 @@
+;; DFA-based pipeline description for the RM9000.
+;;   Copyright (C) 2003 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify it
+;; under the terms of the GNU General Public License as published
+;; by the Free Software Foundation; either version 2, or (at your
+;; option) any later version.
+
+;; GCC is distributed in the hope that it will be useful, but WITHOUT
+;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+;; License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to the
+;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+;; MA 02111-1307, USA.
+
+(define_automaton "rm9k_main, rm9k_imul, rm9k_fdiv")
+
+;; These units are for insns that can issue in either pipe.  We don't
+;; want to use constructs like "rm9k_m | rm9k_f_int" since that would
+;; needlessly make an insn prefer the M pipe.
+(define_cpu_unit "rm9k_any1" "rm9k_main")
+(define_cpu_unit "rm9k_any2" "rm9k_main")
+
+;; F and M pipe units, for instructions that must be issued by a
+;; particular pipe.  Split the F pipe into two units so that integer
+;; instructions can issue while the FPU is busy.  We don't need to
+;; split M because it is only ever reserved for a single cycle.
+(define_cpu_unit "rm9k_m" "rm9k_main")
+(define_cpu_unit "rm9k_f_int" "rm9k_main")
+(define_cpu_unit "rm9k_f_float" "rm9k_main")
+
+(exclusion_set "rm9k_f_int" "rm9k_f_float")
+
+;; Multiply/divide units.
+(define_cpu_unit "rm9k_imul" "rm9k_imul")
+(define_cpu_unit "rm9k_fdiv" "rm9k_fdiv")
+
+(define_insn_reservation "rm9k_load" 3
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "load"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_store" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "store"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_int" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "move,arith,darith,const,icmp,nop"))
+  "rm9k_any1 | rm9k_any2")
+
+(define_insn_reservation "rm9k_int_cmove" 2
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "condmove")
+	    (eq_attr "mode" "SI,DI")))
+  "rm9k_any1 | rm9k_any2")
+
+;; This applies to both 'mul' and 'mult'.
+(define_insn_reservation "rm9k_mulsi" 3
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "imul,imadd")
+	    (eq_attr "mode" "!DI")))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_muldi" 7
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "imul,imadd")
+	    (eq_attr "mode" "DI")))
+  "rm9k_f_int + rm9k_imul * 7")
+
+(define_insn_reservation "rm9k_divsi" 38
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "!DI")))
+  "rm9k_f_int + rm9k_imul * 38")
+
+(define_insn_reservation "rm9k_divdi" 70
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "idiv")
+	    (eq_attr "mode" "DI")))
+  "rm9k_f_int + rm9k_imul * 70")
+
+(define_insn_reservation "rm9k_mfhilo" 1
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "hilo")
+	    (not (match_operand 0 "hilo_operand" ""))))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_mthilo" 5
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "hilo")
+	    (match_operand 0 "hilo_operand" "")))
+  "rm9k_f_int")
+
+(define_insn_reservation "rm9k_xfer" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "xfer"))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_fquick" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "fabs,fneg,fcmp"))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fcmove" 2
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "condmove")
+	    (eq_attr "mode" "SF,DF")))
+  "rm9k_m")
+
+(define_insn_reservation "rm9k_fadd" 6
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "fadd,fcvt"))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fmuls" 6
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "SF")))
+  "rm9k_f_float")
+
+(define_insn_reservation "rm9k_fmuld" 9
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fmul,fmadd")
+	    (eq_attr "mode" "DF")))
+  "rm9k_f_float * 3")
+
+(define_insn_reservation "rm9k_fdivs" 22
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "SF")))
+  "rm9k_f_float + rm9k_fdiv * 22")
+
+(define_insn_reservation "rm9k_fdivd" 37
+  (and (eq_attr "cpu" "r9000")
+       (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+	    (eq_attr "mode" "DF")))
+  "rm9k_f_float + rm9k_fdiv * 37")
+
+(define_insn_reservation "rm9k_branch" 2
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "branch,jump,call"))
+  "rm9k_any1 | rm9k_any2")
+
+(define_insn_reservation "rm9k_unknown" 1
+  (and (eq_attr "cpu" "r9000")
+       (eq_attr "type" "unknown,multi"))
+  "rm9k_m + rm9k_f_int + rm9k_any1 + rm9k_any2")
diff --git a/gcc/config/mips/elf.h b/gcc/config/mips/elf.h
index c325410d604..61999e2c372 100644
--- a/gcc/config/mips/elf.h
+++ b/gcc/config/mips/elf.h
@@ -20,14 +20,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Use ELF.  */
-#undef  OBJECT_FORMAT_COFF
-#undef  EXTENDED_COFF
-
-/* ??? Move all SDB stuff into separate header file.  */
-#undef  SDB_DEBUGGING_INFO
-
-#define DBX_DEBUGGING_INFO 1
 #define DWARF2_DEBUGGING_INFO 1
 
 #undef  PREFERRED_DEBUGGING_TYPE
@@ -79,75 +71,15 @@ Boston, MA 02111-1307, USA.  */
 #define BSS_SECTION_ASM_OP	"\t.section\t.bss"
 #endif
 
-#undef  SBSS_SECTION_ASM_OP
-#define SBSS_SECTION_ASM_OP	"\t.section .sbss"
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro.  */
 #ifndef ASM_OUTPUT_ALIGNED_BSS
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
-do {									\
-  if (SIZE > 0 && SIZE <= (unsigned HOST_WIDE_INT)mips_section_threshold)\
-    named_section (0, ".sbss", 0);					\
-  else									\
-    bss_section ();							\
-  ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT));		\
-  last_assemble_variable_decl = DECL;					\
-  ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL);				\
-  ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1);				\
-} while (0)
+#define ASM_OUTPUT_ALIGNED_BSS mips_output_aligned_bss
 #endif
 
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef  ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    HOST_WIDE_INT size;							\
-    ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");			\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	size = int_size_in_bytes (TREE_TYPE (DECL));			\
-	ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, size);			\
-      }									\
-    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
-
-#undef  ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);		 \
-     HOST_WIDE_INT size;						 \
-									 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 size = int_size_in_bytes (TREE_TYPE (DECL));			 \
-	 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, name, size);			 \
-       }								 \
-   } while (0)
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
+
+#undef ASM_FINISH_DECLARE_OBJECT
+#define ASM_FINISH_DECLARE_OBJECT mips_finish_declare_object
 
 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
  do { fputc ( '\t', FILE);                                            \
diff --git a/gcc/config/mips/elf64.h b/gcc/config/mips/elf64.h
index 4d672774c4f..f23ec9650cb 100644
--- a/gcc/config/mips/elf64.h
+++ b/gcc/config/mips/elf64.h
@@ -20,11 +20,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#undef  OBJECT_FORMAT_COFF
-#undef  EXTENDED_COFF
-
-#undef  SDB_DEBUGGING_INFO
-#define DBX_DEBUGGING_INFO 1
 #define DWARF2_DEBUGGING_INFO 1
 
 #undef  PREFERRED_DEBUGGING_TYPE
@@ -64,49 +59,11 @@ Boston, MA 02111-1307, USA.  */
 #define TYPE_ASM_OP	"\t.type\t"
 #define SIZE_ASM_OP	"\t.size\t"
 
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
-
 #undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    HOST_WIDE_INT size;							\
-    ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");			\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	size = int_size_in_bytes (TREE_TYPE (DECL));			\
-	ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, size);			\
-      }									\
-    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
-  } while (0)
-
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
 
 #undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);		 \
-     HOST_WIDE_INT size;						 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 size = int_size_in_bytes (TREE_TYPE (DECL));			 \
-	 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, name, size);			 \
-       }								 \
-   } while (0)
+#define ASM_FINISH_DECLARE_OBJECT mips_finish_declare_object
 
 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)                            \
  do { fputc ( '\t', FILE);                                            \
diff --git a/gcc/config/mips/iris5.h b/gcc/config/mips/iris5.h
index a0d1e936d7e..51f80dcac87 100644
--- a/gcc/config/mips/iris5.h
+++ b/gcc/config/mips/iris5.h
@@ -23,9 +23,6 @@ Boston, MA 02111-1307, USA.  */
 
 #define ABICALLS_ASM_OP "\t.option pic2"
 
-/* IRIX 5 doesn't use COFF, so disable special COFF handling in collect2.c.  */
-#undef OBJECT_FORMAT_COFF
-
 /* ??? This is correct, but not very useful, because there is no file that
    uses this macro.  */
 /* ??? The best way to handle global constructors under ELF is to use .init
@@ -59,16 +56,23 @@ Boston, MA 02111-1307, USA.  */
  (DEFAULT_WORD_SWITCH_TAKES_ARG (STR)			\
   || !strcmp (STR, "rpath"))
 
+/* We must pass -D_LONGLONG always, even when -ansi is used, because IRIX 5
+   system header files require it.  This is OK, because gcc never warns
+   when long long is used in system header files.  Alternatively, we can
+   add support for the SGI builtin type __long_long.  */
+
 #define TARGET_OS_CPP_BUILTINS()			\
     do {						\
 	builtin_define_std ("host_mips");		\
 	builtin_define_std ("sgi");			\
 	builtin_define_std ("unix");			\
 	builtin_define_std ("SYSTYPE_SVR4");		\
+	builtin_define ("_LONGLONG");			\
 	builtin_define ("_MODERN_C");			\
 	builtin_define ("_SVR4_SOURCE");		\
 	builtin_define ("__DSO__");			\
-	builtin_define ("_MIPS_SIM=_MIPS_SIM_ABI32");	\
+	builtin_define ("_ABIO32=1");			\
+	builtin_define ("_MIPS_SIM=_ABIO32");		\
 	builtin_define ("_MIPS_SZPTR=32");		\
 	builtin_assert ("system=unix");			\
 	builtin_assert ("system=svr4");			\
@@ -99,6 +103,18 @@ Boston, MA 02111-1307, USA.  */
 #undef SUBTARGET_CC1_SPEC
 #define SUBTARGET_CC1_SPEC "%{static: -mno-abicalls}"
 
+/* Override mips.h default: the IRIX 5 assembler warns about -O3:
+
+   as1: Warning: <file>.s, line 1: Binasm file dictates -pic: 2
+   uld:
+   No ucode object file linked -- please use -O2 or lower.
+   
+   So avoid passing it in the first place.  */
+#undef SUBTARGET_ASM_OPTIMIZING_SPEC
+#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
+%{noasmopt:-O0} \
+%{!noasmopt:%{O|O1|O2|O3:-O2}}"
+
 #undef LINK_SPEC
 #define LINK_SPEC "\
 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} \
@@ -140,7 +156,6 @@ Boston, MA 02111-1307, USA.  */
 
 /* We don't support debugging info for now.  */
 #undef DBX_DEBUGGING_INFO
-#undef SDB_DEBUGGING_INFO
 #undef MIPS_DEBUGGING_INFO
 #undef PREFERRED_DEBUGGING_TYPE
 
diff --git a/gcc/config/mips/iris5gas.h b/gcc/config/mips/iris5gas.h
index a38108d861c..f94d1ac7676 100644
--- a/gcc/config/mips/iris5gas.h
+++ b/gcc/config/mips/iris5gas.h
@@ -3,7 +3,6 @@
 /* Enable debugging.  */
 #define DBX_DEBUGGING_INFO 1
 #define DWARF2_DEBUGGING_INFO 1
-#define SDB_DEBUGGING_INFO 1
 #define MIPS_DEBUGGING_INFO 1
 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 
diff --git a/gcc/config/mips/iris6-o32-as.h b/gcc/config/mips/iris6-o32-as.h
index 6aafc7683d7..5cda89e13cf 100644
--- a/gcc/config/mips/iris6-o32-as.h
+++ b/gcc/config/mips/iris6-o32-as.h
@@ -1,17 +1,6 @@
 /* Definitions of target machine for GNU compiler, for MIPS running IRIX 6
    (O32 ABI) using the SGI assembler.  */
 
-/* Override mips.h default: the IRIX 6 O32 assembler warns about -O3:
-
-   as: Warning: -O3 is not supported for assembly compiles for ucode
-   compilers; changing to -O2.
-   
-   So avoid passing it in the first place.  */
-#undef SUBTARGET_ASM_OPTIMIZING_SPEC
-#define SUBTARGET_ASM_OPTIMIZING_SPEC "\
-%{noasmopt:-O0} \
-%{!noasmopt:%{O|O1|O2|O3:-O2}}"
-
 /* Enforce use of O32 linker, irrespective of SGI_ABI environment variable
    and machine type (e.g., R8000 systems default to -64).  Copied from
    iris5.h, only adding -32.  The default options -call_shared -no_unresolved
diff --git a/gcc/config/mips/iris6-o32.h b/gcc/config/mips/iris6-o32.h
index 20a66946966..a525db163ae 100644
--- a/gcc/config/mips/iris6-o32.h
+++ b/gcc/config/mips/iris6-o32.h
@@ -18,48 +18,6 @@
 #undef WINT_TYPE_SIZE
 #define WINT_TYPE_SIZE 32
 
-/* Copied from iris5.h, with _MIPS_SIM definition adapted to SGI cc usage
-   and -D_LONGLONG added as in iris6.h.  */
-#undef TARGET_OS_CPP_BUILTINS
-#define TARGET_OS_CPP_BUILTINS()			\
-    do {						\
-	builtin_define_std ("host_mips");		\
-	builtin_define_std ("sgi");			\
-	builtin_define_std ("unix");			\
-	builtin_define_std ("SYSTYPE_SVR4");		\
-	builtin_define ("_LONGLONG");			\
-	builtin_define ("_MODERN_C");			\
-	builtin_define ("_SVR4_SOURCE");		\
-	builtin_define ("__DSO__");			\
-	builtin_define ("_ABIO32=1");			\
-	builtin_define ("_MIPS_SIM=_ABIO32");		\
-	builtin_define ("_MIPS_SZPTR=32");		\
-	builtin_assert ("system=unix");			\
-	builtin_assert ("system=svr4");			\
-	builtin_assert ("machine=sgi");			\
-							\
-     if (!TARGET_FLOAT64)                               \
-        builtin_define ("_MIPS_FPSET=16");              \
-     else                                               \
-        builtin_define ("_MIPS_FPSET=32");              \
-							\
-     if (!TARGET_INT64)                                 \
-        builtin_define ("_MIPS_SZINT=32");              \
-     else                                               \
-        builtin_define ("_MIPS_SZINT=64");              \
-							\
-     if (!TARGET_LONG64)				\
-	builtin_define ("_MIPS_SZLONG=32");		\
-     else						\
-	builtin_define ("_MIPS_SZLONG=64");		\
-							\
-     if (!flag_iso)					\
-       {						\
-	 builtin_define ("__EXTENSIONS__");		\
-	 builtin_define ("_SGI_SOURCE");		\
-       }						\
-} while (0);
-
 /* Enforce use of O32 assembler, irrespective of SGI_ABI environment variable
    and machine type (e.g., R8000 systems default to -64).  Gas doesn't need
    this, but doesn't hurt either.  Need to pass -mips2 to gas which defaults
diff --git a/gcc/config/mips/iris6.h b/gcc/config/mips/iris6.h
index 0bfc44bd1b5..cf68b418c3d 100644
--- a/gcc/config/mips/iris6.h
+++ b/gcc/config/mips/iris6.h
@@ -287,7 +287,7 @@ Boston, MA 02111-1307, USA.  */
 #undef EXTRA_SECTION_FUNCTIONS
 #define EXTRA_SECTION_FUNCTIONS						\
 const char *								\
-current_section_name ()							\
+current_section_name (void)						\
 {									\
   switch (in_section)							\
     {									\
@@ -307,7 +307,7 @@ current_section_name ()							\
 }									\
 									\
 unsigned int								\
-current_section_flags ()						\
+current_section_flags (void)						\
 {									\
   switch (in_section)							\
     {									\
@@ -370,51 +370,17 @@ while (0)
 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
   asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
 
-/* Write the extra assembler code needed to declare an object properly.  */
-
-#undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
-do									\
- {									\
-   HOST_WIDE_INT size;							\
-   size_directive_output = 0;						\
-   if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-     {									\
-       size_directive_output = 1;					\
-       size = int_size_in_bytes (TREE_TYPE (DECL));			\
-       ASM_OUTPUT_SIZE_DIRECTIVE (STREAM, NAME, size);			\
-     }									\
-   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
- }									\
-while (0)
-
 /* Define the `__builtin_va_list' type for the ABI.  On IRIX 6, this
    type is `char *'.  */
 #undef BUILD_VA_LIST_TYPE
 #define BUILD_VA_LIST_TYPE(VALIST) \
   (VALIST) = build_pointer_type (char_type_node)
 
-/* Output the size directive for a decl in rest_of_decl_compilation
-   in the case where we did not do so before the initializer.
-   Once we find the error_mark_node, we know that the value of
-   size_directive_output was set
-   by ASM_DECLARE_OBJECT_NAME when it was run for the same decl.  */
+#undef ASM_DECLARE_OBJECT_NAME
+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
 
 #undef ASM_FINISH_DECLARE_OBJECT
-#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END)	 \
-do {									 \
-     const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0);		 \
-     HOST_WIDE_INT size;						 \
-     if (!flag_inhibit_size_directive && DECL_SIZE (DECL)		 \
-         && ! AT_END && TOP_LEVEL					 \
-	 && DECL_INITIAL (DECL) == error_mark_node			 \
-	 && !size_directive_output)					 \
-       {								 \
-	 size_directive_output = 1;					 \
-	 size = int_size_in_bytes (TREE_TYPE (DECL));			 \
-	 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, name, size);			 \
-       }								 \
-   } while (0)
+#define ASM_FINISH_DECLARE_OBJECT mips_finish_declare_object
 
 #undef LOCAL_LABEL_PREFIX
 #define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
diff --git a/gcc/config/mips/irix6-libc-compat.c b/gcc/config/mips/irix6-libc-compat.c
index cdac9fafea4..59a148aa865 100644
--- a/gcc/config/mips/irix6-libc-compat.c
+++ b/gcc/config/mips/irix6-libc-compat.c
@@ -1,4 +1,4 @@
-/* Compensate for inconsistent structure passing conventions on IRIX 6.  */
+/* Compensate for inconsistent structure return conventions on IRIX 6.  */
 /* Compile this one with gcc.  */
 /* Copyright (C) 2001  Free Software Foundation, Inc.
 
@@ -28,7 +28,7 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* GCC doesn't correctly implement the structure and union passing and return
+/* GCC doesn't correctly implement the structure and union return
    conventions of the N32 and N64 ABIs on IRIX 6, as described in the
    MIPSpro N32 ABI Handbook, ch. 2, Calling Convention Implementations, p.7.
    The ABI requires that structures (or trailing parts of structures) smaller
@@ -38,17 +38,15 @@ Boston, MA 02111-1307, USA.  */
    While GCC is internally consistent, calling routines compiled with a
    compiler that does implement the documented ABI (like SGIs MIPSpro C
    compiler) doesn't work.  This is primarily an issue for system libraries
-   like libc.  Fortunately, there exist only very few routines that take
-   structure value arguments or return structures by value, so until the
-   underlying bug is fixed, it is possible to work around it by providing
-   wrapper functions for the few affected routines that compensate for the
-   inconsistent alignment.
+   like libc.  Fortunately, there exist only very few routines that return
+   structures by value, so until the underlying bug is fixed, it is possible
+   to work around it by providing wrappers for the few affected routines.
 
    These wrappers rely on the fact that e.g. libc contains weak versions of
    those routines, and the real implementation is provided by _-prefixed
    variants.  So we can provide our own versions, which will only be linked
    if the application uses any of the affected functions, calling the private
-   variants after shifting the arguments or results as required.
+   variants and then shifting the result as required.
 
    This is a rewrite of code created by Andy Polyakov.  */
 
@@ -61,59 +59,14 @@ Boston, MA 02111-1307, USA.  */
 
 #if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
 
-/* The affected arguments need to be shifted by
+/* The affected return values need to be shifted by
 
-	BITS_PER_WORD - (sizeof (arg) * BITS_PER_UNIT).
+	BITS_PER_WORD - (sizeof (value) * BITS_PER_UNIT).
 
-   Since only 32-bit args and results are involved, the shift count is
-   always 32.  */
+   Since only 32-bit results are involved, the shift count is always 32.  */
 #define SHIFT_BITS	32
 
-extern machreg_t inet_ntoa	PARAMS ((machreg_t));
-extern machreg_t inet_lnaof	PARAMS ((machreg_t));
-extern machreg_t inet_netof	PARAMS ((machreg_t));
-extern machreg_t inet_makeaddr	PARAMS ((machreg_t, machreg_t));
-
-extern machreg_t _inet_ntoa	PARAMS ((machreg_t));
-extern machreg_t _inet_lnaof	PARAMS ((machreg_t));
-extern machreg_t _inet_netof	PARAMS ((machreg_t));
-extern machreg_t _inet_makeaddr	PARAMS ((machreg_t, machreg_t));
-
-/* <arpa/inet.h> has
-
-	char *inet_ntoa (struct in_addr);
-
-   on both IRIX 6.2 and 6.5, with struct in_addr containing a 32-bit int.  */
-
-machreg_t
-inet_ntoa (machreg_t in)
-{
-  return _inet_ntoa (in << SHIFT_BITS);
-}
-
-/* <arpa/inet.h> has
-
-	unsigned long inet_lnaof (struct in_addr);		(IRIX 6.2)
-	in_addr_t inet_lnaof (struct in_addr);			(IRIX 6.5)
-
-   in_addr_t is a 32-bit int.  */
-
-machreg_t
-inet_lnaof (machreg_t in)
-{
-  return _inet_lnaof (in << SHIFT_BITS);
-}
-
-/* <arpa/inet.h> has
-
-	unsigned long inet_netof (struct in_addr);		(IRIX 6.2)
-	in_addr_t inet_netof (struct in_addr);			(IRIX 6.5)  */
-
-machreg_t
-inet_netof (machreg_t in)
-{
-  return _inet_netof (in << SHIFT_BITS);
-}
+extern machreg_t _inet_makeaddr (machreg_t, machreg_t);
 
 /* <arpa/inet.h> has
 
@@ -126,23 +79,4 @@ inet_makeaddr (machreg_t net, machreg_t lna)
   return _inet_makeaddr (net, lna) >> SHIFT_BITS;
 }
 
-#if _MIPS_SIM == _ABIN32
-extern machreg_t semctl		PARAMS ((machreg_t, machreg_t, machreg_t, machreg_t));
-extern machreg_t _semctl	PARAMS ((machreg_t, machreg_t, machreg_t, machreg_t));
-
-/* <sys/sem.h> has
-
-	int semctl (int, int, int, ...);
-
-   where the variadic argument is union semun if used.  union semun contains
-   an int and two pointers, so the union is already 64 bits wide under the
-   N64 ABI and alignment is not an issue.  */
-
-machreg_t
-semctl (machreg_t semid, machreg_t semnum, machreg_t cmd, machreg_t arg)
-{
-  return _semctl(semid, semnum, cmd, arg << SHIFT_BITS);
-}
-#endif /* _ABIN32 */
-
 #endif /* _ABIN32 || _ABI64 */
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index 054f5f1a298..70acf11ee99 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -34,49 +34,10 @@ Boston, MA 02111-1307, USA.  */
    used.  */
 #define BSS_SECTION_ASM_OP	"\t.section\t.bss"
 
-#define SBSS_SECTION_ASM_OP	"\t.section .sbss"
-
-/* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
-   separate, explicit argument.  If you define this macro, it is used
-   in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
-   handling the required alignment of the variable.  The alignment is
-   specified as the number of bits.
-
-   Try to use function `asm_output_aligned_bss' defined in file
-   `varasm.c' when defining this macro.  */
-#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN)	\
-do {								\
-  if (SIZE > 0 && (long)(SIZE) <= mips_section_threshold)	\
-    named_section (0, ".sbss", 0);				\
-  else								\
-    bss_section ();						\
-  ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT));	\
-  last_assemble_variable_decl = DECL;				\
-  ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL);			\
-  ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1);			\
-} while (0)
-
-/* These macros generate the special .type and .size directives which
-   are used to set the corresponding fields of the linker symbol table
-   entries in an ELF object file under SVR4.  These macros also output
-   the starting labels for the relevant functions/objects.  */
-
-/* Write the extra assembler code needed to declare an object properly.  */
+#define ASM_OUTPUT_ALIGNED_BSS mips_output_aligned_bss
 
 #undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL)			\
-  do {									\
-    HOST_WIDE_INT size;							\
-    ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object");			\
-    size_directive_output = 0;						\
-    if (!flag_inhibit_size_directive && DECL_SIZE (DECL))		\
-      {									\
-	size_directive_output = 1;					\
-	size = int_size_in_bytes (TREE_TYPE (DECL));			\
-	ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, size);			\
-      }									\
-    mips_declare_object (FILE, NAME, "", ":\n", 0);			\
-  } while (0)
+#define ASM_DECLARE_OBJECT_NAME mips_declare_object_name
 
 #undef TARGET_VERSION
 #if TARGET_ENDIAN_DEFAULT == 0
@@ -88,9 +49,6 @@ do {								\
 #undef MD_EXEC_PREFIX
 #undef MD_STARTFILE_PREFIX
 
-/* Required to keep collect2.c happy */
-#undef OBJECT_FORMAT_COFF
-
 /* If we don't set MASK_ABICALLS, we can't default to PIC.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (MASK_ABICALLS|MASK_GAS)
@@ -226,10 +184,6 @@ do {								\
 #undef ASM_OUTPUT_REG_PUSH
 #undef ASM_OUTPUT_REG_POP
 
-/* The current Linux binutils uses MIPS_STABS_ELF and doesn't support
-   COFF.  */
-#undef SDB_DEBUGGING_INFO
-
 #undef LIB_SPEC
 #define LIB_SPEC "\
 %{shared: -lc} \
diff --git a/gcc/config/mips/linux64.h b/gcc/config/mips/linux64.h
index 6ccb496b773..bac5d635c00 100644
--- a/gcc/config/mips/linux64.h
+++ b/gcc/config/mips/linux64.h
@@ -73,12 +73,6 @@ Boston, MA 02111-1307, USA.  */
 %{mabi=64:-melf64%{EB:b}%{EL:l}tsmip} \
 %{mabi=32:-melf32%{EB:b}%{EL:l}tsmip}"
 
-#undef STARTFILE_PREFIX_SPEC
-#define STARTFILE_PREFIX_SPEC "\
-%{mabi=n32: /lib32/ /usr/lib32/} \
-%{mabi=64: /lib64/ /usr/lib64/} \
-%{mabi=32: /lib/ /usr/lib/}"
-
 #undef LOCAL_LABEL_PREFIX
 #define LOCAL_LABEL_PREFIX ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
 			    ? "$" : ".")
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index 217647bbfbd..89a8cb2a420 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -26,144 +26,124 @@ Boston, MA 02111-1307, USA.  */
 #ifndef GCC_MIPS_PROTOS_H
 #define GCC_MIPS_PROTOS_H
 
-extern HOST_WIDE_INT	compute_frame_size PARAMS ((HOST_WIDE_INT));
-extern int		mips_initial_elimination_offset PARAMS ((int, int));
-extern void		iris6_asm_output_align PARAMS ((FILE *, unsigned));
-extern const char *	current_section_name PARAMS ((void));
-extern unsigned int	current_section_flags PARAMS ((void));
-extern int		mips_can_use_return_insn PARAMS ((void));
-extern void		mips_declare_object PARAMS ((FILE *, const char *,
-						     const char *,
-						     const char *, int));
-extern void		mips_expand_epilogue PARAMS ((int));
-extern void		mips_expand_prologue PARAMS ((void));
-extern void		mips_output_filename PARAMS ((FILE *, const char *));
-extern void		mips_output_lineno PARAMS ((FILE *, int));
-extern void		mips_output_ascii PARAMS ((FILE *, const char *,
-						   size_t));
-extern void		mips_order_regs_for_local_alloc PARAMS ((void));
-extern struct rtx_def * embedded_pic_fnaddr_reg PARAMS ((void));
-extern struct rtx_def *	mips16_gp_pseudo_reg PARAMS ((void));
-#ifdef ASM_OUTPUT_UNDEF_FUNCTION
-extern int		mips_output_external_libcall PARAMS ((FILE *, const char *));
-#endif /* ASM_OUTPUT_UNDEF_FUNCTION */
-extern struct rtx_def  *mips_function_value PARAMS ((tree, tree,
-						     enum machine_mode));
-
-extern unsigned int	mips_hard_regno_nregs PARAMS ((int,
-						       enum machine_mode));
-extern int              mips_return_in_memory PARAMS ((tree));
-
-extern struct rtx_def  *function_arg PARAMS ((const CUMULATIVE_ARGS *,
-					      enum machine_mode, tree, int));
-extern void		function_arg_advance PARAMS ((CUMULATIVE_ARGS *,
-						      enum machine_mode,
-						      tree, int));
-extern int		function_arg_partial_nregs
-				PARAMS ((const CUMULATIVE_ARGS *,
-					 enum machine_mode,
-					 tree, int));
-extern int		mips_setup_incoming_varargs
-				PARAMS ((const CUMULATIVE_ARGS *,
-					 enum machine_mode,
-					 tree, int));
-extern int		function_arg_pass_by_reference
-				PARAMS ((const CUMULATIVE_ARGS *,
-					 enum machine_mode, tree, int));
-extern int		mips_output_external PARAMS ((FILE *, tree,
-						      const char *));
-extern tree		mips_build_va_list PARAMS ((void));
-extern void		mips_va_start PARAMS ((tree, rtx));
-extern struct rtx_def  *mips_va_arg PARAMS ((tree, tree));
-
-extern bool		mips_expand_block_move PARAMS ((rtx, rtx, rtx));
-extern bool		mips_expand_unaligned_load PARAMS ((rtx, rtx,
-							    unsigned int,
-							    int));
-extern bool		mips_expand_unaligned_store PARAMS ((rtx, rtx,
-							     unsigned int,
-							     int));
-extern void		init_cumulative_args PARAMS ((CUMULATIVE_ARGS *,
-						      tree, rtx));
-extern void		gen_conditional_move PARAMS ((rtx *));
-extern void		mips_gen_conditional_trap PARAMS ((rtx *));
-extern void		mips_emit_fcc_reload PARAMS ((rtx, rtx, rtx));
-extern void		mips_set_return_address PARAMS ((rtx, rtx));
-extern HOST_WIDE_INT	mips_debugger_offset PARAMS ((rtx, HOST_WIDE_INT));
-extern rtx		mips_subword PARAMS ((rtx, int));
-extern bool		mips_split_64bit_move_p PARAMS ((rtx, rtx));
-extern void		mips_split_64bit_move PARAMS ((rtx, rtx));
-extern const char      *mips_output_move PARAMS ((rtx, rtx));
-extern const char      *mips_emit_prefetch PARAMS ((rtx *));
-extern const char      *mips_restore_gp PARAMS ((rtx *));
-extern void		override_options PARAMS ((void));
-extern void		mips_conditional_register_usage PARAMS ((void));
-extern void		print_operand_address PARAMS ((FILE *, rtx));
-extern void		print_operand PARAMS ((FILE *, rtx, int));
-extern struct rtx_def *	embedded_pic_offset PARAMS ((rtx));
-extern int		build_mips16_call_stub PARAMS ((rtx, rtx, rtx, int));
-extern const char	*mips_output_load_label PARAMS ((void));
-extern const char       *mips_output_conditional_branch PARAMS ((rtx, rtx *,
-								 int, int, int,
-								 int));
-extern const char	*mips_output_division PARAMS ((const char *, rtx *));
-extern int              mips_adjust_insn_length PARAMS ((rtx, int));
-extern enum reg_class	mips_secondary_reload_class PARAMS ((enum reg_class,
-							     enum machine_mode,
-							     rtx, int));
-extern bool     	mips_cannot_change_mode_class
-			  PARAMS ((enum machine_mode, enum machine_mode,
-				   enum reg_class));
-extern int              mips_class_max_nregs PARAMS ((enum reg_class,
-						      enum machine_mode));
-extern int              mips_register_move_cost PARAMS ((enum machine_mode,
-							 enum reg_class,
-							 enum reg_class));
-
-extern int		se_arith_operand PARAMS ((rtx, enum machine_mode));
-extern int		coprocessor_operand PARAMS ((rtx, enum machine_mode));
-extern int		coprocessor2_operand PARAMS ((rtx, enum machine_mode));
-extern int		mips_address_insns PARAMS ((rtx, enum machine_mode));
-extern int		mips_fetch_insns PARAMS ((rtx));
-extern int		mips_const_insns PARAMS ((rtx));
-extern bool		mips_global_pic_constant_p PARAMS ((rtx));
-extern bool		mips_legitimate_address_p PARAMS ((enum machine_mode,
-							   rtx, int));
-extern bool		mips_legitimize_address PARAMS ((rtx *,
-							 enum machine_mode));
-extern bool		mips_legitimize_move PARAMS ((enum machine_mode,
-						      rtx, rtx));
-extern rtx		mips_delegitimize_address PARAMS ((rtx));
-extern void		mips_expand_call PARAMS ((rtx, rtx, rtx, rtx, int));
-extern int              mips_reg_mode_ok_for_base_p PARAMS ((rtx,
-							     enum machine_mode,
-							     int));
-extern bool             mips_valid_pointer_mode PARAMS ((enum machine_mode));
-
-extern int		m16_uimm3_b PARAMS ((rtx, enum machine_mode));
-extern int		m16_simm4_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nsimm4_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_simm5_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nsimm5_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_uimm5_4 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nuimm5_4 PARAMS ((rtx, enum machine_mode));
-extern int		m16_simm8_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nsimm8_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_uimm8_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nuimm8_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_uimm8_m1_1 PARAMS ((rtx, enum machine_mode));
-extern int		m16_uimm8_4 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nuimm8_4 PARAMS ((rtx, enum machine_mode));
-extern int		m16_simm8_8 PARAMS ((rtx, enum machine_mode));
-extern int		m16_nsimm8_8 PARAMS ((rtx, enum machine_mode));
-extern int		m16_usym8_4 PARAMS ((rtx, enum machine_mode));
-extern int		m16_usym5_4 PARAMS ((rtx, enum machine_mode));
+extern int mips_reg_mode_ok_for_base_p (rtx, enum machine_mode, int);
+extern int mips_address_insns (rtx, enum machine_mode);
+extern int mips_const_insns (rtx);
+extern int mips_fetch_insns (rtx);
+extern bool mips_global_pic_constant_p (rtx);
+extern bool mips_legitimate_address_p (enum machine_mode, rtx, int);
+extern bool mips_legitimize_address (rtx *, enum machine_mode);
+extern bool mips_legitimize_move (enum machine_mode, rtx, rtx);
+extern rtx mips_delegitimize_address (rtx);
+
+extern int m16_uimm3_b (rtx, enum machine_mode);
+extern int m16_simm4_1 (rtx, enum machine_mode);
+extern int m16_nsimm4_1 (rtx, enum machine_mode);
+extern int m16_simm5_1 (rtx, enum machine_mode);
+extern int m16_nsimm5_1 (rtx, enum machine_mode);
+extern int m16_uimm5_4 (rtx, enum machine_mode);
+extern int m16_nuimm5_4 (rtx, enum machine_mode);
+extern int m16_simm8_1 (rtx, enum machine_mode);
+extern int m16_nsimm8_1 (rtx, enum machine_mode);
+extern int m16_uimm8_1 (rtx, enum machine_mode);
+extern int m16_nuimm8_1 (rtx, enum machine_mode);
+extern int m16_uimm8_m1_1 (rtx, enum machine_mode);
+extern int m16_uimm8_4 (rtx, enum machine_mode);
+extern int m16_nuimm8_4 (rtx, enum machine_mode);
+extern int m16_simm8_8 (rtx, enum machine_mode);
+extern int m16_nsimm8_8 (rtx, enum machine_mode);
+extern int m16_usym8_4 (rtx, enum machine_mode);
+extern int m16_usym5_4 (rtx, enum machine_mode);
 
+extern struct rtx_def *embedded_pic_fnaddr_reg (void);
+extern struct rtx_def *embedded_pic_offset (rtx);
+extern rtx mips_subword (rtx, int);
+extern bool mips_split_64bit_move_p (rtx, rtx);
+extern void mips_split_64bit_move (rtx, rtx);
+extern const char *mips_output_move (rtx, rtx);
+extern const char *mips_restore_gp (rtx *);
 #ifdef RTX_CODE
-extern rtx		gen_int_relational PARAMS ((enum rtx_code, rtx, rtx,
-						    rtx,int *));
-extern void		gen_conditional_branch PARAMS ((rtx *, enum rtx_code));
+extern rtx gen_int_relational (enum rtx_code, rtx, rtx, rtx, int *);
+extern void gen_conditional_branch (rtx *, enum rtx_code);
 #endif
-extern rtx              mips_return_addr PARAMS ((int, rtx));
+extern void gen_conditional_move (rtx *);
+extern void mips_gen_conditional_trap (rtx *);
+extern void mips_expand_call (rtx, rtx, rtx, rtx, int);
+extern void mips_emit_fcc_reload (rtx, rtx, rtx);
+extern void mips_set_return_address (rtx, rtx);
+extern bool mips_expand_block_move (rtx, rtx, rtx);
+
+extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx);
+extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
+				  tree, int);
+extern struct rtx_def *function_arg (const CUMULATIVE_ARGS *,
+				     enum machine_mode, tree, int);
+extern int function_arg_partial_nregs (const CUMULATIVE_ARGS *,
+				       enum machine_mode, tree, int);
+extern bool mips_pad_arg_upward (enum machine_mode, tree);
+extern bool mips_pad_reg_upward (enum machine_mode, tree);
+extern int mips_setup_incoming_varargs (const CUMULATIVE_ARGS *,
+					enum machine_mode, tree, int);
+extern tree mips_build_va_list (void);
+extern void mips_va_start (tree, rtx);
+extern struct rtx_def *mips_va_arg (tree, tree);
+
+extern bool mips_expand_unaligned_load (rtx, rtx, unsigned int, int);
+extern bool mips_expand_unaligned_store (rtx, rtx, unsigned int, int);
+extern void override_options (void);
+extern void mips_conditional_register_usage (void);
+extern void mips_order_regs_for_local_alloc (void);
+extern HOST_WIDE_INT mips_debugger_offset (rtx, HOST_WIDE_INT);
+
+extern void print_operand (FILE *, rtx, int);
+extern void print_operand_address (FILE *, rtx);
+extern int mips_output_external (FILE *, tree, const char *);
+#ifdef ASM_OUTPUT_UNDEF_FUNCTION
+extern int mips_output_external_libcall (FILE *, const char *);
+#endif
+extern void mips_output_filename (FILE *, const char *);
+extern void mips_output_lineno (FILE *, int);
+extern void mips_output_ascii (FILE *, const char *, size_t);
+extern void mips_output_aligned_bss (FILE *, tree, const char *,
+				     unsigned HOST_WIDE_INT, int);
+extern void mips_declare_object (FILE *, const char *, const char *,
+				 const char *, int);
+extern void mips_declare_object_name (FILE *, const char *, tree);
+extern void mips_finish_declare_object (FILE *, tree, int, int);
+
+extern HOST_WIDE_INT compute_frame_size (HOST_WIDE_INT);
+extern int mips_initial_elimination_offset (int, int);
+extern rtx mips_return_addr (int, rtx);
+extern void mips_expand_prologue (void);
+extern void mips_expand_epilogue (int);
+extern int mips_can_use_return_insn (void);
+extern struct rtx_def *mips_function_value (tree, tree, enum machine_mode);
+extern int function_arg_pass_by_reference (const CUMULATIVE_ARGS *,
+					   enum machine_mode, tree, int);
+
+extern bool mips_cannot_change_mode_class (enum machine_mode,
+					   enum machine_mode, enum reg_class);
+extern enum reg_class mips_secondary_reload_class (enum reg_class,
+						   enum machine_mode,
+						   rtx, int);
+extern int mips_class_max_nregs (enum reg_class, enum machine_mode);
+extern bool mips_valid_pointer_mode (enum machine_mode);
+extern struct rtx_def *mips16_gp_pseudo_reg (void);
+extern int build_mips16_call_stub (rtx, rtx, rtx, int);
+extern int mips_register_move_cost (enum machine_mode, enum reg_class,
+				    enum reg_class);
+
+extern int mips_adjust_insn_length (rtx, int);
+extern const char *mips_output_load_label (void);
+extern const char *mips_output_conditional_branch (rtx, rtx *, int, int,
+						   int, int);
+extern const char *mips_output_division (const char *, rtx *);
+extern unsigned int mips_hard_regno_nregs (int, enum machine_mode);
+extern int mips_return_in_memory (tree);
+extern const char *mips_emit_prefetch (rtx *);
+
+extern void iris6_asm_output_align (FILE *, unsigned);
+extern const char *current_section_name (void);
+extern unsigned int current_section_flags (void);
 
 #endif /* ! GCC_MIPS_PROTOS_H */
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index eeef802ab3c..8bd2139d9ef 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1,4 +1,4 @@
-/* Subroutines for insn-output.c for MIPS
+/* Subroutines used for MIPS code generation.
    Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
    1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Contributed by A. Lichnewsky, lich@inria.inria.fr.
@@ -23,10 +23,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
-   calling convention in 64 bit mode.  It doesn't work though, and should
-   be replaced with something better designed.  */
-
 #include "config.h"
 #include "system.h"
 #include "coretypes.h"
@@ -56,37 +52,32 @@ Boston, MA 02111-1307, USA.  */
 #include "target-def.h"
 #include "integrate.h"
 
-#ifdef __GNU_STAB__
-#define STAB_CODE_TYPE enum __stab_debug_code
-#else
-#define STAB_CODE_TYPE int
-#endif
-
-extern tree   lookup_name PARAMS ((tree));
-
 /* Enumeration for all of the relational tests, so that we can build
    arrays indexed by the test type, and not worry about the order
    of EQ, NE, etc.  */
 
 enum internal_test {
-    ITEST_EQ,
-    ITEST_NE,
-    ITEST_GT,
-    ITEST_GE,
-    ITEST_LT,
-    ITEST_LE,
-    ITEST_GTU,
-    ITEST_GEU,
-    ITEST_LTU,
-    ITEST_LEU,
-    ITEST_MAX
-  };
+  ITEST_EQ,
+  ITEST_NE,
+  ITEST_GT,
+  ITEST_GE,
+  ITEST_LT,
+  ITEST_LE,
+  ITEST_GTU,
+  ITEST_GEU,
+  ITEST_LTU,
+  ITEST_LEU,
+  ITEST_MAX
+};
 
 /* Return true if it is likely that the given mode will be accessed
    using only a single instruction.  */
 #define SINGLE_WORD_MODE_P(MODE) \
   ((MODE) != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
 
+/* True if the given SYMBOL_REF is for an internally-generated symbol.  */
+#define INTERNAL_SYMBOL_P(SYM) \
+  (XSTR (SYM, 0)[0] == '*' && XSTR (SYM, 0)[1] == LOCAL_LABEL_PREFIX[0])
 
 /* Classifies a non-literal integer constant.
 
@@ -179,127 +170,101 @@ struct mips_arg_info;
 struct mips_constant_info;
 struct mips_address_info;
 struct mips_integer_op;
-static enum mips_constant_type mips_classify_constant
-				PARAMS ((struct mips_constant_info *, rtx));
-static enum mips_symbol_type mips_classify_symbol
-				PARAMS ((rtx));
-static bool mips_valid_base_register_p
-				PARAMS ((rtx, enum machine_mode, int));
-static bool mips_symbolic_address_p
-				PARAMS ((rtx, HOST_WIDE_INT,
-					 enum machine_mode, int));
-static enum mips_address_type mips_classify_address
-				PARAMS ((struct mips_address_info *,
-					 rtx, enum machine_mode, int, int));
-static enum internal_test map_test_to_internal_test	PARAMS ((enum rtx_code));
-static void get_float_compare_codes PARAMS ((enum rtx_code, enum rtx_code *,
-					     enum rtx_code *));
-static const char *mips_reloc_string	PARAMS ((int));
-static bool mips_splittable_symbol_p	PARAMS ((enum mips_symbol_type));
-static int mips_symbol_insns		PARAMS ((enum mips_symbol_type));
-static bool mips16_unextended_reference_p
-					PARAMS ((enum machine_mode mode,
-						 rtx, rtx));
-static rtx mips_force_temporary			PARAMS ((rtx, rtx));
-static rtx mips_add_offset			PARAMS ((rtx, HOST_WIDE_INT));
-static rtx mips_load_got			PARAMS ((rtx, rtx, int));
-static rtx mips_load_got16			PARAMS ((rtx, int));
-static rtx mips_load_got32			PARAMS ((rtx, rtx, int, int));
-static rtx mips_emit_high			PARAMS ((rtx, rtx));
-static bool mips_legitimize_symbol		PARAMS ((rtx, rtx *, int));
-static rtx mips_reloc				PARAMS ((rtx, int));
-static rtx mips_lui_reloc			PARAMS ((rtx, int));
-static unsigned int mips_build_shift	PARAMS ((struct mips_integer_op *,
-						 HOST_WIDE_INT));
-static unsigned int mips_build_lower	PARAMS ((struct mips_integer_op *,
-						 unsigned HOST_WIDE_INT));
-static unsigned int mips_build_integer	PARAMS ((struct mips_integer_op *,
-						 unsigned HOST_WIDE_INT));
-static void mips_move_integer		PARAMS ((rtx, unsigned HOST_WIDE_INT));
-static void mips_legitimize_const_move		PARAMS ((enum machine_mode,
-							 rtx, rtx));
-static int m16_check_op				PARAMS ((rtx, int, int, int));
-static bool mips_function_ok_for_sibcall	PARAMS ((tree, tree));
-static void mips_block_move_straight		PARAMS ((rtx, rtx,
-							 HOST_WIDE_INT));
-static void mips_adjust_block_mem		PARAMS ((rtx, HOST_WIDE_INT,
-							 rtx *, rtx *));
-static void mips_block_move_loop		PARAMS ((rtx, rtx,
-							 HOST_WIDE_INT));
-static void mips_arg_info		PARAMS ((const CUMULATIVE_ARGS *,
-						 enum machine_mode,
-						 tree, int,
-						 struct mips_arg_info *));
-static bool mips_get_unaligned_mem		PARAMS ((rtx *, unsigned int,
-							 int, rtx *, rtx *));
-static unsigned int mips_global_pointer		PARAMS ((void));
-static bool mips_save_reg_p			PARAMS ((unsigned int));
-static rtx mips_add_large_offset_to_sp		PARAMS ((HOST_WIDE_INT));
-static void mips_set_frame_expr			PARAMS ((rtx));
-static rtx mips_frame_set			PARAMS ((rtx, int));
-static void mips_emit_frame_related_store	PARAMS ((rtx, rtx,
-							 HOST_WIDE_INT));
-static void save_restore_insns			PARAMS ((int, rtx, long));
-static void mips_gp_insn			PARAMS ((rtx, rtx));
-static void mips16_fp_args			PARAMS ((FILE *, int, int));
-static void build_mips16_function_stub		PARAMS ((FILE *));
-static void mips16_optimize_gp			PARAMS ((void));
-static rtx add_constant				PARAMS ((struct constant **,
-							rtx,
-							enum machine_mode));
-static void dump_constants			PARAMS ((struct constant *,
-							rtx));
-static rtx mips_find_symbol			PARAMS ((rtx));
-static void mips16_lay_out_constants		PARAMS ((void));
-static void mips_avoid_hazard			PARAMS ((rtx, rtx, int *,
-							 rtx *, rtx));
-static void mips_avoid_hazards			PARAMS ((void));
-static void mips_reorg				PARAMS ((void));
-static void abort_with_insn			PARAMS ((rtx, const char *))
-  ATTRIBUTE_NORETURN;
-static int symbolic_expression_p                PARAMS ((rtx));
-static bool mips_assemble_integer	  PARAMS ((rtx, unsigned int, int));
-static void mips_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void mips_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void mips_set_architecture    PARAMS ((const struct mips_cpu_info *));
-static void mips_set_tune	     PARAMS ((const struct mips_cpu_info *));
-static bool mips_strict_matching_cpu_name_p	PARAMS ((const char *,
-							 const char *));
-static bool mips_matching_cpu_name_p		PARAMS ((const char *,
-							 const char *));
-static const struct mips_cpu_info *mips_parse_cpu   PARAMS ((const char *,
-							      const char *));
-static const struct mips_cpu_info *mips_cpu_info_from_isa PARAMS ((int));
+static enum mips_constant_type
+  mips_classify_constant (struct mips_constant_info *, rtx);
+static enum mips_symbol_type mips_classify_symbol (rtx);
+static bool mips_valid_base_register_p (rtx, enum machine_mode, int);
+static bool mips_symbolic_address_p (rtx, HOST_WIDE_INT,
+				     enum machine_mode, int);
+static enum mips_address_type
+  mips_classify_address (struct mips_address_info *, rtx,
+			 enum machine_mode, int, int);
+static bool mips_splittable_symbol_p (enum mips_symbol_type);
+static int mips_symbol_insns (enum mips_symbol_type);
+static bool mips16_unextended_reference_p (enum machine_mode mode, rtx, rtx);
+static rtx mips_reloc (rtx, int);
+static rtx mips_lui_reloc (rtx, int);
+static rtx mips_force_temporary (rtx, rtx);
+static rtx mips_add_offset (rtx, HOST_WIDE_INT);
+static rtx mips_load_got (rtx, rtx, int);
+static rtx mips_load_got16 (rtx, int);
+static rtx mips_load_got32 (rtx, rtx, int, int);
+static rtx mips_emit_high (rtx, rtx);
+static bool mips_legitimize_symbol (rtx, rtx *, int);
+static unsigned int mips_build_shift (struct mips_integer_op *, HOST_WIDE_INT);
+static unsigned int mips_build_lower (struct mips_integer_op *,
+				      unsigned HOST_WIDE_INT);
+static unsigned int mips_build_integer (struct mips_integer_op *,
+					unsigned HOST_WIDE_INT);
+static void mips_move_integer (rtx, unsigned HOST_WIDE_INT);
+static void mips_legitimize_const_move (enum machine_mode, rtx, rtx);
+static int m16_check_op (rtx, int, int, int);
+static bool mips_rtx_costs (rtx, int, int, int *);
+static int mips_address_cost (rtx);
+static enum internal_test map_test_to_internal_test (enum rtx_code);
+static void get_float_compare_codes (enum rtx_code, enum rtx_code *,
+				     enum rtx_code *);
+static bool mips_function_ok_for_sibcall (tree, tree);
+static void mips_block_move_straight (rtx, rtx, HOST_WIDE_INT);
+static void mips_adjust_block_mem (rtx, HOST_WIDE_INT, rtx *, rtx *);
+static void mips_block_move_loop (rtx, rtx, HOST_WIDE_INT);
+static void mips_arg_info (const CUMULATIVE_ARGS *, enum machine_mode,
+			   tree, int, struct mips_arg_info *);
+static bool mips_get_unaligned_mem (rtx *, unsigned int, int, rtx *, rtx *);
+static void mips_set_architecture (const struct mips_cpu_info *);
+static void mips_set_tune (const struct mips_cpu_info *);
+static struct machine_function *mips_init_machine_status (void);
+static const char *mips_reloc_string (int);
+static bool mips_assemble_integer (rtx, unsigned int, int);
+static void mips_file_start (void);
+static void mips_file_end (void);
+static unsigned int mips_global_pointer	(void);
+static bool mips_save_reg_p (unsigned int);
+static rtx mips_add_large_offset_to_sp (HOST_WIDE_INT);
+static void mips_set_frame_expr (rtx);
+static rtx mips_frame_set (rtx, int);
+static void mips_emit_frame_related_store (rtx, rtx, HOST_WIDE_INT);
+static void save_restore_insns (int, rtx, long);
+static void mips_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void mips_gp_insn (rtx, rtx);
+static void mips_output_function_epilogue (FILE *, HOST_WIDE_INT);
+static int symbolic_expression_p (rtx);
+static void mips_select_rtx_section (enum machine_mode, rtx,
+				     unsigned HOST_WIDE_INT);
+static void mips_select_section (tree, int, unsigned HOST_WIDE_INT)
+				  ATTRIBUTE_UNUSED;
+static bool mips_in_small_data_p (tree);
+static void mips_encode_section_info (tree, rtx, int);
+static void mips16_fp_args (FILE *, int, int);
+static void build_mips16_function_stub (FILE *);
+static void mips16_optimize_gp (void);
+static rtx add_constant	(struct constant **, rtx, enum machine_mode);
+static void dump_constants (struct constant *, rtx);
+static rtx mips_find_symbol (rtx);
+static void mips16_lay_out_constants (void);
+static void mips_avoid_hazard (rtx, rtx, int *, rtx *, rtx);
+static void mips_avoid_hazards (void);
+static void mips_reorg (void);
+static bool mips_strict_matching_cpu_name_p (const char *, const char *);
+static bool mips_matching_cpu_name_p (const char *, const char *);
+static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
+static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
+static int mips_adjust_cost (rtx, rtx, rtx, int);
+static int mips_issue_rate (void);
+static int mips_use_dfa_pipeline_interface (void);
+
 #ifdef TARGET_IRIX6
-static void copy_file_data			PARAMS ((FILE *, FILE *));
-static void iris6_asm_named_section_1		PARAMS ((const char *,
-							 unsigned int,
-							 unsigned int));
-static void iris6_asm_named_section		PARAMS ((const char *,
-							 unsigned int));
-static int iris_section_align_entry_eq		PARAMS ((const void *, const void *));
-static hashval_t iris_section_align_entry_hash	PARAMS ((const void *));
-static int iris6_section_align_1		PARAMS ((void **, void *));
-static void iris6_file_start			PARAMS ((void));
-static void iris6_file_end			PARAMS ((void));
-static unsigned int iris6_section_type_flags	PARAMS ((tree, const char *,
-							 int));
+static void iris6_asm_named_section_1 (const char *, unsigned int,
+				       unsigned int);
+static void iris6_asm_named_section (const char *, unsigned int);
+static int iris_section_align_entry_eq (const void *, const void *);
+static hashval_t iris_section_align_entry_hash (const void *);
+static void iris6_file_start (void);
+static int iris6_section_align_1 (void **, void *);
+static void copy_file_data (FILE *, FILE *);
+static void iris6_file_end (void);
+static unsigned int iris6_section_type_flags (tree, const char *, int);
 #endif
-static int mips_adjust_cost			PARAMS ((rtx, rtx, rtx, int));
-static int mips_issue_rate			PARAMS ((void));
-
-static struct machine_function * mips_init_machine_status PARAMS ((void));
-static void mips_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
-	ATTRIBUTE_UNUSED;
-static void mips_select_rtx_section PARAMS ((enum machine_mode, rtx,
-					     unsigned HOST_WIDE_INT));
-static int mips_use_dfa_pipeline_interface      PARAMS ((void));
-static bool mips_rtx_costs			PARAMS ((rtx, int, int, int *));
-static int mips_address_cost                    PARAMS ((rtx));
-static bool mips_in_small_data_p		PARAMS ((tree));
-static void mips_encode_section_info            PARAMS ((tree, rtx, int));
-static void mips_file_start			PARAMS ((void));
-static void mips_file_end			PARAMS ((void));
 
 /* Structure to be filled in by compute_frame_size with register
    save masks, and offsets for the current function.  */
@@ -324,8 +289,7 @@ struct mips_frame_info GTY(())
 
 struct machine_function GTY(()) {
   /* Pseudo-reg holding the address of the current function when
-     generating embedded PIC code.  Created by LEGITIMIZE_ADDRESS,
-     used by mips_finalize_pic if it was created.  */
+     generating embedded PIC code.  */
   rtx embedded_pic_fnaddr_rtx;
 
   /* Pseudo-reg holding the value of $28 in a mips16 function which
@@ -353,9 +317,6 @@ struct machine_function GTY(()) {
 /* Information about a single argument.  */
 struct mips_arg_info
 {
-  /* True if the argument is a record or union type.  */
-  bool struct_p;
-
   /* True if the argument is passed in a floating-point register, or
      would have been if we hadn't run out of registers.  */
   bool fpr_p;
@@ -450,9 +411,7 @@ struct mips_integer_op {
 /* Global variables for machine-dependent things.  */
 
 /* Threshold for data being put into the small data/bss area, instead
-   of the normal data area (references to the small data/bss area take
-   1 instruction, and use the global pointer, references to the normal
-   data area takes 2 instructions).  */
+   of the normal data area.  */
 int mips_section_threshold = -1;
 
 /* Count the number of .file directives, so that .loc is up to date.  */
@@ -465,10 +424,6 @@ int sdb_label_count = 0;
 /* Next label # for each statement for Silicon Graphics IRIS systems.  */
 int sym_lineno = 0;
 
-/* Nonzero if inside of a function, because the stupid MIPS asm can't
-   handle .files inside of functions.  */
-int inside_function = 0;
-
 /* Linked list of all externals that are to be emitted when optimizing
    for the global pointer if they haven't been declared by the end of
    the program with an appropriate .comm or initialization.  */
@@ -485,14 +440,6 @@ static GTY (()) struct extern_list *extern_head = 0;
 /* Name of the file containing the current function.  */
 const char *current_function_file = "";
 
-/* Warning given that Mips ECOFF can't support changing files
-   within a function.  */
-int file_in_function_warning = FALSE;
-
-/* Whether to suppress issuing .loc's because the user attempted
-   to change the filename within a function.  */
-int ignore_line_number = FALSE;
-
 /* Number of nested .set noreorder, noat, nomacro, and volatile requests.  */
 int set_noreorder;
 int set_noat;
@@ -517,10 +464,10 @@ const struct mips_cpu_info *mips_arch_info;
 enum processor_type mips_tune;
 const struct mips_cpu_info *mips_tune_info;
 
-/* which instruction set architecture to use.  */
+/* Which instruction set architecture to use.  */
 int mips_isa;
 
-/* which abi to use.  */
+/* Which ABI to use.  */
 int mips_abi;
 
 /* Strings to hold which cpu and instruction set architecture to use.  */
@@ -529,15 +476,6 @@ const char *mips_tune_string;   /* for -mtune=<xxx> */
 const char *mips_isa_string;	/* for -mips{1,2,3,4} */
 const char *mips_abi_string;	/* for -mabi={32,n32,64,eabi} */
 
-/* Whether we are generating mips16 code.  This is a synonym for
-   TARGET_MIPS16, and exists for use as an attribute.  */
-int mips16;
-
-/* This variable is set by -mno-mips16.  We only care whether
-   -mno-mips16 appears or not, and using a string in this fashion is
-   just a way to avoid using up another bit in target_flags.  */
-const char *mips_no_mips16_string;
-
 /* Whether we are generating mips16 hard float code.  In mips16 mode
    we always set TARGET_SOFT_FLOAT; this variable is nonzero if
    -msoft-float was not specified by the user, which means that we
@@ -557,9 +495,6 @@ int mips_entry;
 /* If TRUE, we split addresses into their high and low parts in the RTL.  */
 int mips_split_addresses;
 
-/* Generating calls to position independent functions?  */
-enum mips_abicalls_type mips_abicalls;
-
 /* Mode used for saving/restoring general purpose registers.  */
 static enum machine_mode gpr_mode;
 
@@ -711,73 +646,7 @@ const enum reg_class mips_regno_to_class[] =
 };
 
 /* Map register constraint character to register class.  */
-enum reg_class mips_char_to_class[256] =
-{
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-  NO_REGS,	NO_REGS,	NO_REGS,	NO_REGS,
-};
+enum reg_class mips_char_to_class[256];
 
 /* A table describing all the processors gcc knows about.  Names are
    matched in the order listed.  The first mention of an ISA level is
@@ -819,6 +688,8 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "vr5000", PROCESSOR_R5000, 4 },
   { "vr5400", PROCESSOR_R5400, 4 },
   { "vr5500", PROCESSOR_R5500, 4 },
+  { "rm7000", PROCESSOR_R7000, 4 },
+  { "rm9000", PROCESSOR_R9000, 4 },
 
   /* MIPS32 */
   { "4kc", PROCESSOR_4KC, 32 },
@@ -918,9 +789,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
    store its components in INFO and return its type.  */
 
 static enum mips_constant_type
-mips_classify_constant (info, x)
-     struct mips_constant_info *info;
-     rtx x;
+mips_classify_constant (struct mips_constant_info *info, rtx x)
 {
   info->offset = 0;
   info->symbol = x;
@@ -966,8 +835,7 @@ mips_classify_constant (info, x)
 /* Classify symbol X, which must be a SYMBOL_REF or a LABEL_REF.  */
 
 static enum mips_symbol_type
-mips_classify_symbol (x)
-     rtx x;
+mips_classify_symbol (rtx x)
 {
   if (GET_CODE (x) == LABEL_REF)
     return (TARGET_ABICALLS ? SYMBOL_GOT_LOCAL : SYMBOL_GENERAL);
@@ -989,9 +857,7 @@ mips_classify_symbol (x)
       return SYMBOL_GENERAL;
     }
 
-  if (XSTR (x, 0)[0] == '*'
-      && strncmp (XSTR (x, 0) + 1, LOCAL_LABEL_PREFIX,
-		  sizeof LOCAL_LABEL_PREFIX - 1) == 0)
+  if (INTERNAL_SYMBOL_P (x))
     {
       /* The symbol is a local label.  For TARGET_MIPS16, SYMBOL_REF_FLAG
 	 will be set if the symbol refers to a string in the current
@@ -1016,10 +882,7 @@ mips_classify_symbol (x)
 /* This function is used to implement REG_MODE_OK_FOR_BASE_P.  */
 
 int
-mips_reg_mode_ok_for_base_p (reg, mode, strict)
-     rtx reg;
-     enum machine_mode mode;
-     int strict;
+mips_reg_mode_ok_for_base_p (rtx reg, enum machine_mode mode, int strict)
 {
   return (strict
 	  ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
@@ -1031,10 +894,7 @@ mips_reg_mode_ok_for_base_p (reg, mode, strict)
    Allow only hard registers if STRICT.  */
 
 static bool
-mips_valid_base_register_p (x, mode, strict)
-     rtx x;
-     enum machine_mode mode;
-     int strict;
+mips_valid_base_register_p (rtx x, enum machine_mode mode, int strict)
 {
   if (!strict && GET_CODE (x) == SUBREG)
     x = SUBREG_REG (x);
@@ -1059,11 +919,8 @@ mips_valid_base_register_p (x, mode, strict)
      it is better to move the address into a register first.  */
 
 static bool
-mips_symbolic_address_p (symbol, offset, mode, lea_p)
-     rtx symbol;
-     HOST_WIDE_INT offset;
-     enum machine_mode mode;
-     int lea_p;
+mips_symbolic_address_p (rtx symbol, HOST_WIDE_INT offset,
+			 enum machine_mode mode, int lea_p)
 {
   if (TARGET_EXPLICIT_RELOCS)
     return false;
@@ -1110,11 +967,8 @@ mips_symbolic_address_p (symbol, offset, mode, lea_p)
    the same as for mips_symbolic_address_p.  */
 
 static enum mips_address_type
-mips_classify_address (info, x, mode, strict, lea_p)
-     struct mips_address_info *info;
-     rtx x;
-     enum machine_mode mode;
-     int strict, lea_p;
+mips_classify_address (struct mips_address_info *info, rtx x,
+		       enum machine_mode mode, int strict, int lea_p)
 {
   switch (GET_CODE (x))
     {
@@ -1176,8 +1030,7 @@ mips_classify_address (info, x, mode, strict, lea_p)
    HIGH/LO_SUM pair.  */
 
 static bool
-mips_splittable_symbol_p (type)
-     enum mips_symbol_type type;
+mips_splittable_symbol_p (enum mips_symbol_type type)
 {
   if (TARGET_EXPLICIT_RELOCS)
     return (type == SYMBOL_GENERAL || type == SYMBOL_GOT_LOCAL);
@@ -1193,8 +1046,7 @@ mips_splittable_symbol_p (type)
    mips16 instructions as two instructions.  */
 
 static int
-mips_symbol_insns (type)
-     enum mips_symbol_type type;
+mips_symbol_insns (enum mips_symbol_type type)
 {
   switch (type)
     {
@@ -1229,7 +1081,7 @@ mips_symbol_insns (type)
 	      daddu   $at,$at,$gp
 
 	 and the final address is $at + %got_lo(symbol).  */
-      return (flag_pic == 1 ? 1 : 3);
+      return (TARGET_XGOT ? 3 : 1);
 
     case SYMBOL_GOT_LOCAL:
       /* For o32 and o64, the sequence is:
@@ -1257,9 +1109,7 @@ mips_symbol_insns (type)
    stack pointer, which have an 8-bit immediate field.  */
 
 static bool
-mips16_unextended_reference_p (mode, base, offset)
-     enum machine_mode mode;
-     rtx base, offset;
+mips16_unextended_reference_p (enum machine_mode mode, rtx base, rtx offset)
 {
   if (TARGET_MIPS16
       && GET_CODE (offset) == CONST_INT
@@ -1280,9 +1130,7 @@ mips16_unextended_reference_p (mode, base, offset)
    For mips16 code, count extended instructions as two instructions.  */
 
 int
-mips_address_insns (x, mode)
-     rtx x;
-     enum machine_mode mode;
+mips_address_insns (rtx x, enum machine_mode mode)
 {
   struct mips_address_info addr;
   int factor;
@@ -1314,8 +1162,7 @@ mips_address_insns (x, mode)
 /* Likewise for constant X.  */
 
 int
-mips_const_insns (x)
-     rtx x;
+mips_const_insns (rtx x)
 {
   struct mips_constant_info c;
   struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
@@ -1369,8 +1216,7 @@ mips_const_insns (x)
    Count extended mips16 instructions as two instructions.  */
 
 int
-mips_fetch_insns (x)
-     rtx x;
+mips_fetch_insns (rtx x)
 {
   if (GET_CODE (x) != MEM)
     abort ();
@@ -1383,8 +1229,7 @@ mips_fetch_insns (x)
    global PIC symbol.  */
 
 bool
-mips_global_pic_constant_p (op)
-     rtx op;
+mips_global_pic_constant_p (rtx op)
 {
   struct mips_constant_info c;
 
@@ -1397,9 +1242,7 @@ mips_global_pic_constant_p (op)
    where a register or 16 bit unsigned integer is needed.  */
 
 int
-uns_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+uns_arith_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
     return 1;
@@ -1411,9 +1254,7 @@ uns_arith_operand (op, mode)
 /* True if OP can be treated as a signed 16-bit constant.  */
 
 int
-const_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+const_arith_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   struct mips_constant_info c;
 
@@ -1422,79 +1263,28 @@ const_arith_operand (op, mode)
 }
 
 
-/* Return truth value of whether OP can be used as an operands
-   where a 16 bit integer is needed  */
+/* Return true if OP is a register operand or a signed 16-bit constant.  */
 
 int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_operand (rtx op, enum machine_mode mode)
 {
   return const_arith_operand (op, mode) || register_operand (op, mode);
 }
 
-/* Return truth value of whether OP can be used as an operand in a two
-   address arithmetic insn (such as set 123456,%o4) of mode MODE.  */
-
-int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
-{
-  if (GET_CODE (op) == CONST_INT)
-    return 1;
-
-  return register_operand (op, mode);
-}
-
 /* Return truth value of whether OP is an integer which fits in 16 bits.  */
 
 int
-small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
 }
 
-/* Return truth value of whether OP is a 32 bit integer which is too big to
-   be loaded with one instruction.  */
-
-int
-large_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  HOST_WIDE_INT value;
-
-  if (GET_CODE (op) != CONST_INT)
-    return 0;
-
-  value = INTVAL (op);
-
-  /* ior reg,$r0,value */
-  if ((value & ~ ((HOST_WIDE_INT) 0x0000ffff)) == 0)
-    return 0;
-
-  /* subu reg,$r0,value */
-  if (((unsigned HOST_WIDE_INT) (value + 32768)) <= 32767)
-    return 0;
-
-  /* lui reg,value>>16 */
-  if ((value & 0x0000ffff) == 0)
-    return 0;
-
-  return 1;
-}
-
 /* Return truth value of whether OP is a register or the constant 0.
-   In mips16 mode, we only accept a register, since the mips16 does
-   not have $0.  */
+   Do not accept 0 in mips16 mode since $0 is not one of the core 8
+   registers.  */
 
 int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_0_operand (rtx op, enum machine_mode mode)
 {
   switch (GET_CODE (op))
     {
@@ -1513,21 +1303,22 @@ reg_or_0_operand (op, mode)
     }
 }
 
-/* Return truth value of whether OP is a register or the constant 0,
-   even in mips16 mode.  */
+/* Accept a register or the floating point constant 1 in the appropriate mode.  */
 
 int
-true_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_const_float_1_operand (rtx op, enum machine_mode mode)
 {
+  REAL_VALUE_TYPE d;
+
   switch (GET_CODE (op))
     {
-    case CONST_INT:
-      return INTVAL (op) == 0;
-
     case CONST_DOUBLE:
-      return op == CONST0_RTX (mode);
+      if (mode != GET_MODE (op)
+	  || (mode != DFmode && mode != SFmode))
+	return 0;
+
+      REAL_VALUE_FROM_CONST_DOUBLE (d, op);
+      return REAL_VALUES_EQUAL (d, dconst1);
 
     default:
       return register_operand (op, mode);
@@ -1537,9 +1328,7 @@ true_reg_or_0_operand (op, mode)
 /* Accept the floating point constant 1 in the appropriate mode.  */
 
 int
-const_float_1_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+const_float_1_operand (rtx op, enum machine_mode mode)
 {
   REAL_VALUE_TYPE d;
 
@@ -1556,9 +1345,7 @@ const_float_1_operand (op, mode)
 /* Return true if OP is either the HI or LO register.  */
 
 int
-hilo_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+hilo_operand (rtx op, enum machine_mode mode)
 {
   return ((mode == VOIDmode || mode == GET_MODE (op))
 	  && REG_P (op) && MD_REG_P (REGNO (op)));
@@ -1567,9 +1354,7 @@ hilo_operand (op, mode)
 /* Return true if OP is an extension operator.  */
 
 int
-extend_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
+extend_operator (rtx op, enum machine_mode mode)
 {
   return ((mode == VOIDmode || mode == GET_MODE (op))
 	  && (GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND));
@@ -1578,9 +1363,7 @@ extend_operator (op, mode)
 /* Return nonzero if the code of this rtx pattern is EQ or NE.  */
 
 int
-equality_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
+equality_op (rtx op, enum machine_mode mode)
 {
   if (mode != GET_MODE (op))
     return 0;
@@ -1591,9 +1374,7 @@ equality_op (op, mode)
 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
 
 int
-cmp_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
+cmp_op (rtx op, enum machine_mode mode)
 {
   if (mode != GET_MODE (op))
     return 0;
@@ -1607,9 +1388,7 @@ cmp_op (op, mode)
    combine from erroneously altering the condition.  */
 
 int
-trap_cmp_op (op, mode)
-     rtx op;
-     enum machine_mode mode;
+trap_cmp_op (rtx op, enum machine_mode mode)
 {
   if (mode != GET_MODE (op))
     return 0;
@@ -1632,9 +1411,7 @@ trap_cmp_op (op, mode)
 /* Return nonzero if the operand is either the PC or a label_ref.  */
 
 int
-pc_or_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (op == pc_rtx)
     return 1;
@@ -1648,9 +1425,7 @@ pc_or_label_operand (op, mode)
 /* Test for a valid call address.  */
 
 int
-call_insn_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+call_insn_operand (rtx op, enum machine_mode mode)
 {
   struct mips_constant_info c;
 
@@ -1680,9 +1455,7 @@ call_insn_operand (op, mode)
    instruction.  */
 
 int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+move_operand (rtx op, enum machine_mode mode)
 {
   struct mips_constant_info c;
 
@@ -1702,43 +1475,16 @@ move_operand (op, mode)
    accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs.  */
 
 int
-consttable_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return CONSTANT_P (op);
 }
 
-/* Coprocessor operand; return true if rtx is a REG and refers to a
-   coprocessor.  */
-
-int
-coprocessor_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == REG
-	  && COP0_REG_FIRST <= REGNO (op)
-	  && REGNO (op) <= COP3_REG_LAST);
-}
-
-int
-coprocessor2_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return (GET_CODE (op) == REG
-	  && COP2_REG_FIRST <= REGNO (op)
-	  && REGNO (op) <= COP2_REG_LAST);
-}
-
-/* Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
+/* Return 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
    possibly with an offset.  */
 
 int
-symbolic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   struct mips_constant_info c;
 
@@ -1752,10 +1498,7 @@ symbolic_operand (op, mode)
    is called during reload.  */
 
 bool
-mips_legitimate_address_p (mode, x, strict)
-     enum machine_mode mode;
-     rtx x;
-     int strict;
+mips_legitimate_address_p (enum machine_mode mode, rtx x, int strict)
 {
   struct mips_address_info addr;
 
@@ -1767,9 +1510,7 @@ mips_legitimate_address_p (mode, x, strict)
    RELOC to symbolic address ADDR.  */
 
 static rtx
-mips_reloc (addr, reloc)
-     rtx addr;
-     int reloc;
+mips_reloc (rtx addr, int reloc)
 {
   struct mips_constant_info c;
   rtx x;
@@ -1786,9 +1527,7 @@ mips_reloc (addr, reloc)
    used as the right hand side of an LUISI or LUIDI pattern.  */
 
 static rtx
-mips_lui_reloc (addr, reloc)
-     rtx addr;
-     int reloc;
+mips_lui_reloc (rtx addr, int reloc)
 {
   return gen_rtx_UNSPEC (Pmode,
 			 gen_rtvec (1, mips_reloc (addr, reloc)),
@@ -1802,8 +1541,7 @@ mips_lui_reloc (addr, reloc)
    The operation happens in Pmode.  */
 
 static rtx
-mips_force_temporary (dest, value)
-     rtx dest, value;
+mips_force_temporary (rtx dest, rtx value)
 {
   if (dest == 0)
     return force_reg (Pmode, value);
@@ -1820,9 +1558,7 @@ mips_force_temporary (dest, value)
    create a temporary register if OFFSET is not a SMALL_OPERAND.  */
 
 static rtx
-mips_add_offset (reg, offset)
-     rtx reg;
-     HOST_WIDE_INT offset;
+mips_add_offset (rtx reg, HOST_WIDE_INT offset)
 {
   if (!SMALL_OPERAND (offset))
     reg = expand_simple_binop (GET_MODE (reg), PLUS,
@@ -1838,9 +1574,7 @@ mips_add_offset (reg, offset)
    sought and RELOC is the relocation that should be used.  */
 
 static rtx
-mips_load_got (base, addr, reloc)
-     rtx base, addr;
-     int reloc;
+mips_load_got (rtx base, rtx addr, int reloc)
 {
   rtx mem;
 
@@ -1864,9 +1598,7 @@ mips_load_got (base, addr, reloc)
    The returned address may be used on the right hand side of a SET.  */
 
 static rtx
-mips_load_got16 (addr, reloc)
-     rtx addr;
-     int reloc;
+mips_load_got16 (rtx addr, int reloc)
 {
   return mips_load_got (pic_offset_table_rtx, addr, reloc);
 }
@@ -1878,9 +1610,7 @@ mips_load_got16 (addr, reloc)
    to use a temporary, or null if new registers can be created at will.  */
 
 static rtx
-mips_load_got32 (temp, addr, high_reloc, low_reloc)
-     rtx temp, addr;
-     int high_reloc, low_reloc;
+mips_load_got32 (rtx temp, rtx addr, int high_reloc, int low_reloc)
 {
   rtx x;
 
@@ -1895,8 +1625,7 @@ mips_load_got32 (temp, addr, high_reloc, low_reloc)
    Use DEST as the register if non-null.  */
 
 static rtx
-mips_emit_high (dest, addr)
-     rtx dest, addr;
+mips_emit_high (rtx dest, rtx addr)
 {
   rtx high, x;
 
@@ -1923,9 +1652,7 @@ mips_emit_high (dest, addr)
    can be created at will.  */
 
 static bool
-mips_legitimize_symbol (dest, xloc, offsetable_p)
-     rtx dest, *xloc;
-     int offsetable_p;
+mips_legitimize_symbol (rtx dest, rtx *xloc, int offsetable_p)
 {
   struct mips_constant_info c;
   enum mips_symbol_type symbol_type;
@@ -1995,9 +1722,7 @@ mips_legitimize_symbol (dest, xloc, offsetable_p)
    the memory being accessed.  */
 
 bool
-mips_legitimize_address (xloc, mode)
-     rtx *xloc;
-     enum machine_mode mode;
+mips_legitimize_address (rtx *xloc, enum machine_mode mode)
 {
   if (mips_legitimize_symbol (0, xloc, !SINGLE_WORD_MODE_P (mode)))
     return true;
@@ -2022,9 +1747,7 @@ mips_legitimize_address (xloc, mode)
    Assume that the final action in the sequence should be a left shift.  */
 
 static unsigned int
-mips_build_shift (codes, value)
-     struct mips_integer_op *codes;
-     HOST_WIDE_INT value;
+mips_build_shift (struct mips_integer_op *codes, HOST_WIDE_INT value)
 {
   unsigned int i, shift;
 
@@ -2045,9 +1768,7 @@ mips_build_shift (codes, value)
    an IOR or PLUS operation.  */
 
 static unsigned int
-mips_build_lower (codes, value)
-     struct mips_integer_op *codes;
-     unsigned HOST_WIDE_INT value;
+mips_build_lower (struct mips_integer_op *codes, unsigned HOST_WIDE_INT value)
 {
   unsigned HOST_WIDE_INT high;
   unsigned int i;
@@ -2078,9 +1799,8 @@ mips_build_lower (codes, value)
    Return the number of operations needed.  */
 
 static unsigned int
-mips_build_integer (codes, value)
-     struct mips_integer_op *codes;
-     unsigned HOST_WIDE_INT value;
+mips_build_integer (struct mips_integer_op *codes,
+		    unsigned HOST_WIDE_INT value)
 {
   if (SMALL_OPERAND (value)
       || SMALL_OPERAND_UNSIGNED (value)
@@ -2128,9 +1848,7 @@ mips_build_integer (codes, value)
 /* Move VALUE into register DEST.  */
 
 static void
-mips_move_integer (dest, value)
-     rtx dest;
-     unsigned HOST_WIDE_INT value;
+mips_move_integer (rtx dest, unsigned HOST_WIDE_INT value)
 {
   struct mips_integer_op codes[MIPS_MAX_INTEGER_OPS];
   enum machine_mode mode;
@@ -2161,9 +1879,7 @@ mips_move_integer (dest, value)
    move_operand.  */
 
 static void
-mips_legitimize_const_move (mode, dest, src)
-     enum machine_mode mode;
-     rtx dest, src;
+mips_legitimize_const_move (enum machine_mode mode, rtx dest, rtx src)
 {
   rtx temp;
 
@@ -2187,10 +1903,10 @@ mips_legitimize_const_move (mode, dest, src)
       && GET_CODE (src) == SYMBOL_REF
       && mips_classify_symbol (src) == SYMBOL_GOT_GLOBAL)
     {
-      if (flag_pic == 1)
-	src = mips_load_got16 (src, RELOC_GOT_DISP);
-      else
+      if (TARGET_XGOT)
 	src = mips_load_got32 (temp, src, RELOC_GOT_HI, RELOC_GOT_LO);
+      else
+	src = mips_load_got16 (src, RELOC_GOT_DISP);
       emit_insn (gen_rtx_SET (VOIDmode, dest, src));
       return;
     }
@@ -2221,9 +1937,7 @@ mips_legitimize_const_move (mode, dest, src)
    sequence that is valid.  */
 
 bool
-mips_legitimize_move (mode, dest, src)
-     enum machine_mode mode;
-     rtx dest, src;
+mips_legitimize_move (enum machine_mode mode, rtx dest, rtx src)
 {
   if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode))
     {
@@ -2248,11 +1962,10 @@ mips_legitimize_move (mode, dest, src)
 
 
 /* Convert GOT and GP-relative accesses back into their original form.
-   Used by bothh TARGET_DELEGITIMIZE_ADDRESS and FIND_BASE_TERM.  */
+   Used by both TARGET_DELEGITIMIZE_ADDRESS and FIND_BASE_TERM.  */
 
 rtx
-mips_delegitimize_address (x)
-     rtx x;
+mips_delegitimize_address (rtx x)
 {
   struct mips_constant_info c;
 
@@ -2278,11 +1991,7 @@ mips_delegitimize_address (x)
    there aren't nearly enough letters available.  */
 
 static int
-m16_check_op (op, low, high, mask)
-     rtx op;
-     int low;
-     int high;
-     int mask;
+m16_check_op (rtx op, int low, int high, int mask)
 {
   return (GET_CODE (op) == CONST_INT
 	  && INTVAL (op) >= low
@@ -2291,129 +2000,97 @@ m16_check_op (op, low, high, mask)
 }
 
 int
-m16_uimm3_b (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_uimm3_b (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, 0x1, 0x8, 0);
 }
 
 int
-m16_simm4_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_simm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x8, 0x7, 0);
 }
 
 int
-m16_nsimm4_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nsimm4_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x7, 0x8, 0);
 }
 
 int
-m16_simm5_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_simm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x10, 0xf, 0);
 }
 
 int
-m16_nsimm5_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nsimm5_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0xf, 0x10, 0);
 }
 
 int
-m16_uimm5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_uimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
 }
 
 int
-m16_nuimm5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nuimm5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
 }
 
 int
-m16_simm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_simm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x80, 0x7f, 0);
 }
 
 int
-m16_nsimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nsimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x7f, 0x80, 0);
 }
 
 int
-m16_uimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_uimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, 0x0, 0xff, 0);
 }
 
 int
-m16_nuimm8_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nuimm8_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0xff, 0x0, 0);
 }
 
 int
-m16_uimm8_m1_1 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_uimm8_m1_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, - 0x1, 0xfe, 0);
 }
 
 int
-m16_uimm8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_uimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, 0x0, 0xff << 2, 3);
 }
 
 int
-m16_nuimm8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nuimm8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
 }
 
 int
-m16_simm8_8 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_simm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
 }
 
 int
-m16_nsimm8_8 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_nsimm8_8 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
 }
@@ -2424,16 +2101,12 @@ m16_nsimm8_8 (op, mode)
    referencing instruction.  */
 
 int
-m16_usym8_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_usym8_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == SYMBOL_REF
       && SYMBOL_REF_FLAG (op)
       && cfun->machine->insns_len > 0
-      && XSTR (op, 0)[0] == '*'
-      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
-		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
+      && INTERNAL_SYMBOL_P (op)
       && (cfun->machine->insns_len + get_pool_size () + mips_string_length
 	  < 4 * 0x100))
     {
@@ -2451,16 +2124,12 @@ m16_usym8_4 (op, mode)
 }
 
 int
-m16_usym5_4 (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+m16_usym5_4 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == SYMBOL_REF
       && SYMBOL_REF_FLAG (op)
       && cfun->machine->insns_len > 0
-      && XSTR (op, 0)[0] == '*'
-      && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
-		  sizeof LOCAL_LABEL_PREFIX - 1) == 0
+      && INTERNAL_SYMBOL_P (op)
       && (cfun->machine->insns_len + get_pool_size () + mips_string_length
 	  < 4 * 0x20))
     {
@@ -2478,10 +2147,7 @@ m16_usym5_4 (op, mode)
 }
 
 static bool
-mips_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code;
-     int *total;
+mips_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   enum machine_mode mode = GET_MODE (x);
 
@@ -2508,8 +2174,8 @@ mips_rtx_costs (x, code, outer_code, total)
             *total = COSTS_N_INSNS (1);
           return true;
         }
-      /* We can use cmpi for an xor with an unsigned 16 bit value.  */
 
+      /* We can use cmpi for an xor with an unsigned 16 bit value.  */
       if ((outer_code) == XOR
           && INTVAL (x) >= 0 && INTVAL (x) < 0x10000)
         {
@@ -2673,6 +2339,10 @@ mips_rtx_costs (x, code, outer_code, total)
         *total = COSTS_N_INSNS (2);
       else if (TUNE_MIPS5400 || TUNE_MIPS5500)
         *total = COSTS_N_INSNS ((mode == DImode) ? 4 : 3);
+      else if (TUNE_MIPS7000)
+        *total = COSTS_N_INSNS (mode == DImode ? 9 : 5);
+      else if (TUNE_MIPS9000)
+        *total = COSTS_N_INSNS (mode == DImode ? 8 : 3);
       else if (TUNE_MIPS6000)
         *total = COSTS_N_INSNS (17);
       else if (TUNE_MIPS5000)
@@ -2755,8 +2425,7 @@ mips_rtx_costs (x, code, outer_code, total)
    If ADDR is not a valid address, its cost is irrelevant.  */
 
 static int
-mips_address_cost (addr)
-     rtx addr;
+mips_address_cost (rtx addr)
 {
   return mips_address_insns (addr, SImode);
 }
@@ -2766,7 +2435,7 @@ mips_address_cost (addr)
    pseudo is emitted in the beginning of the function.  */
 
 rtx
-embedded_pic_fnaddr_reg ()
+embedded_pic_fnaddr_reg (void)
 {
   if (cfun->machine->embedded_pic_fnaddr_rtx == NULL)
     {
@@ -2799,8 +2468,7 @@ embedded_pic_fnaddr_reg ()
    X is the symbol whose offset from the current function we want.  */
 
 rtx
-embedded_pic_offset (x)
-     rtx x;
+embedded_pic_offset (rtx x)
 {
   /* Make sure it is emitted.  */
   embedded_pic_fnaddr_reg ();
@@ -2816,9 +2484,7 @@ embedded_pic_offset (x)
    false to select the low part.  */
 
 rtx
-mips_subword (op, high_p)
-     rtx op;
-     int high_p;
+mips_subword (rtx op, int high_p)
 {
   unsigned int byte;
   enum machine_mode mode;
@@ -2850,8 +2516,7 @@ mips_subword (op, high_p)
 /* Return true if a 64-bit move from SRC to DEST should be split into two.  */
 
 bool
-mips_split_64bit_move_p (dest, src)
-     rtx dest, src;
+mips_split_64bit_move_p (rtx dest, rtx src)
 {
   if (TARGET_64BIT)
     return false;
@@ -2889,8 +2554,7 @@ mips_split_64bit_move_p (dest, src)
    load_df_high and store_df_high instead.  */
 
 void
-mips_split_64bit_move (dest, src)
-     rtx dest, src;
+mips_split_64bit_move (rtx dest, rtx src)
 {
   if (FP_REG_RTX_P (dest))
     {
@@ -2930,8 +2594,7 @@ mips_split_64bit_move (dest, src)
    that SRC is operand 1 and DEST is operand 0.  */
 
 const char *
-mips_output_move (dest, src)
-     rtx dest, src;
+mips_output_move (rtx dest, rtx src)
 {
   enum rtx_code dest_code, src_code;
   struct mips_constant_info c;
@@ -3066,8 +2729,7 @@ mips_output_move (dest, src)
    on entry.  */
 
 const char *
-mips_restore_gp (operands)
-     rtx *operands;
+mips_restore_gp (rtx *operands)
 {
   rtx loc;
 
@@ -3086,8 +2748,7 @@ mips_restore_gp (operands)
 /* Make normal rtx_code into something we can index from an array */
 
 static enum internal_test
-map_test_to_internal_test (test_code)
-     enum rtx_code test_code;
+map_test_to_internal_test (enum rtx_code test_code)
 {
   enum internal_test test = ITEST_MAX;
 
@@ -3129,16 +2790,16 @@ map_test_to_internal_test (test_code)
      return i < 5;
    }
 
-   */
+   TEST_CODE is the rtx code for the comparison.
+   CMP0 and CMP1 are the two operands to compare.
+   RESULT is the register in which the result should be stored (null for
+     branches).
+   For branches, P_INVERT points to an integer that is nonzero on return
+     if the branch should be inverted.  */
 
 rtx
-gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
-     enum rtx_code test_code;	/* relational test (EQ, etc) */
-     rtx result;		/* result to store comp. or 0 if branch */
-     rtx cmp0;			/* first operand to compare */
-     rtx cmp1;			/* second operand to compare */
-     int *p_invert;		/* NULL or ptr to hold whether branch needs */
-				/* to reverse its test */
+gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0,
+		    rtx cmp1, int *p_invert)
 {
   struct cmp_info
   {
@@ -3334,8 +2995,8 @@ gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
    and *action_code to the branch or move code.  */
 
 static void
-get_float_compare_codes (in_code, cmp_code, action_code)
-     enum rtx_code in_code, *cmp_code, *action_code;
+get_float_compare_codes (enum rtx_code in_code, enum rtx_code *cmp_code,
+			 enum rtx_code *action_code)
 {
   switch (in_code)
     {
@@ -3360,9 +3021,7 @@ get_float_compare_codes (in_code, cmp_code, action_code)
    The comparison operands are saved away by cmp{si,di,sf,df}.  */
 
 void
-gen_conditional_branch (operands, test_code)
-     rtx operands[];
-     enum rtx_code test_code;
+gen_conditional_branch (rtx *operands, enum rtx_code test_code)
 {
   enum cmp_type type = branch_type;
   rtx cmp0 = branch_cmp[0];
@@ -3412,7 +3071,7 @@ gen_conditional_branch (operands, test_code)
       break;
 
     default:
-      abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
+      fatal_insn ("bad test", gen_rtx (test_code, VOIDmode, cmp0, cmp1));
     }
 
   /* Generate the branch.  */
@@ -3434,11 +3093,10 @@ gen_conditional_branch (operands, test_code)
 }
 
 /* Emit the common code for conditional moves.  OPERANDS is the array
-   of operands passed to the conditional move defined_expand.  */
+   of operands passed to the conditional move define_expand.  */
 
 void
-gen_conditional_move (operands)
-     rtx *operands;
+gen_conditional_move (rtx *operands)
 {
   rtx op0 = branch_cmp[0];
   rtx op1 = branch_cmp[1];
@@ -3520,12 +3178,11 @@ gen_conditional_move (operands)
 						operands[2], operands[3])));
 }
 
-/* Emit the common code for conditional moves.  OPERANDS is the array
-   of operands passed to the conditional move defined_expand.  */
+/* Emit a conditional trap.  OPERANDS is the array of operands passed to
+   the conditional_trap expander.  */
 
 void
-mips_gen_conditional_trap (operands)
-     rtx operands[];
+mips_gen_conditional_trap (rtx *operands)
 {
   rtx op0, op1;
   enum rtx_code cmp_code = GET_CODE (operands[0]);
@@ -3565,15 +3222,11 @@ mips_gen_conditional_trap (operands)
    function, ARGS_SIZE is the size of the arguments and AUX is
    the value passed to us by mips_function_arg.  SIBCALL_P is true
    if we are expanding a sibling call, false if we're expanding
-   normal call.  */
+   a normal call.  */
 
 void
-mips_expand_call (result, addr, args_size, aux, sibcall_p)
-     rtx result, addr, args_size, aux;
-     int sibcall_p;
+mips_expand_call (rtx result, rtx addr, rtx args_size, rtx aux, int sibcall_p)
 {
-  int i;
-
   if (!call_insn_operand (addr, VOIDmode))
     {
       /* When generating PIC, try to allow global functions to be
@@ -3582,24 +3235,14 @@ mips_expand_call (result, addr, args_size, aux, sibcall_p)
 	  && GET_CODE (addr) == SYMBOL_REF
 	  && mips_classify_symbol (addr) == SYMBOL_GOT_GLOBAL)
 	{
-	  if (flag_pic == 1)
-	    addr = mips_load_got16 (addr, RELOC_CALL16);
-	  else
+	  if (TARGET_XGOT)
 	    addr = mips_load_got32 (0, addr, RELOC_CALL_HI, RELOC_CALL_LO);
+	  else
+	    addr = mips_load_got16 (addr, RELOC_CALL16);
 	}
       addr = force_reg (Pmode, addr);
     }
 
-  /* In order to pass small structures by value in registers
-     compatibly with the MIPS compiler, we need to shift the value
-     into the high part of the register.  Function_arg has encoded
-     a PARALLEL rtx, holding a vector of adjustments to be made
-     as the next_arg_reg variable, so we split up the insns,
-     and emit them separately.  */
-  if (aux != 0 && GET_CODE (aux) == PARALLEL)
-    for (i = 0; i < XVECLEN (aux, 0); i++)
-      emit_insn (XVECEXP (aux, 0, i));
-
   if (TARGET_MIPS16
       && mips16_hard_float
       && build_mips16_call_stub (result, addr, args_size,
@@ -3630,9 +3273,8 @@ mips_expand_call (result, addr, args_size, aux, sibcall_p)
 /* We can handle any sibcall when TARGET_SIBCALLS is true.  */
 
 static bool
-mips_function_ok_for_sibcall (decl, exp)
-     tree decl ATTRIBUTE_UNUSED;
-     tree exp ATTRIBUTE_UNUSED;
+mips_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
+			      tree exp ATTRIBUTE_UNUSED)
 {
   return TARGET_SIBCALLS;
 }
@@ -3641,9 +3283,7 @@ mips_function_ok_for_sibcall (decl, exp)
    Only for use during or after reload.  */
 
 int
-fcc_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fcc_register_operand (rtx op, enum machine_mode mode)
 {
   return ((mode == VOIDmode || mode == GET_MODE (op))
 	  && (reload_in_progress || reload_completed)
@@ -3663,8 +3303,7 @@ fcc_register_operand (op, mode)
    taken from SCRATCH.  */
 
 void
-mips_emit_fcc_reload (dest, src, scratch)
-     rtx dest, src, scratch;
+mips_emit_fcc_reload (rtx dest, rtx src, rtx scratch)
 {
   rtx fp1, fp2;
 
@@ -3687,8 +3326,7 @@ mips_emit_fcc_reload (dest, src, scratch)
    ADDRESS and SCRATCH are both word-mode GPRs.  */
 
 void
-mips_set_return_address (address, scratch)
-     rtx address, scratch;
+mips_set_return_address (rtx address, rtx scratch)
 {
   HOST_WIDE_INT gp_offset;
 
@@ -3716,9 +3354,7 @@ mips_set_return_address (address, scratch)
    Assume that the areas do not overlap.  */
 
 static void
-mips_block_move_straight (dest, src, length)
-     rtx dest, src;
-     HOST_WIDE_INT length;
+mips_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length)
 {
   HOST_WIDE_INT offset, delta;
   unsigned HOST_WIDE_INT bits;
@@ -3792,9 +3428,8 @@ mips_block_move_straight (dest, src, length)
    register.  Store them in *LOOP_REG and *LOOP_MEM respectively.  */
 
 static void
-mips_adjust_block_mem (mem, length, loop_reg, loop_mem)
-     rtx mem, *loop_reg, *loop_mem;
-     HOST_WIDE_INT length;
+mips_adjust_block_mem (rtx mem, HOST_WIDE_INT length,
+		       rtx *loop_reg, rtx *loop_mem)
 {
   *loop_reg = copy_addr_to_reg (XEXP (mem, 0));
 
@@ -3810,9 +3445,7 @@ mips_adjust_block_mem (mem, length, loop_reg, loop_mem)
    memory regions do not overlap.  */
 
 static void
-mips_block_move_loop (dest, src, length)
-     rtx dest, src;
-     HOST_WIDE_INT length;
+mips_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length)
 {
   rtx label, src_reg, dest_reg, final_src;
   HOST_WIDE_INT leftover;
@@ -3855,8 +3488,7 @@ mips_block_move_loop (dest, src, length)
 /* Expand a movstrsi instruction.  */
 
 bool
-mips_expand_block_move (dest, src, length)
-     rtx dest, src, length;
+mips_expand_block_move (rtx dest, rtx src, rtx length)
 {
   if (GET_CODE (length) == CONST_INT)
     {
@@ -3879,10 +3511,8 @@ mips_expand_block_move (dest, src, length)
 /* Initialize CUMULATIVE_ARGS for a function.  */
 
 void
-init_cumulative_args (cum, fntype, libname)
-     CUMULATIVE_ARGS *cum;		/* argument info to initialize */
-     tree fntype;			/* tree ptr for function decl */
-     rtx libname ATTRIBUTE_UNUSED;	/* SYMBOL_REF of library name or 0 */
+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
+		      rtx libname ATTRIBUTE_UNUSED)
 {
   static CUMULATIVE_ARGS zero_cum;
   tree param, next_param;
@@ -3921,45 +3551,40 @@ init_cumulative_args (cum, fntype, libname)
     }
 }
 
+
+/* Fill INFO with information about a single argument.  CUM is the
+   cumulative state for earlier arguments.  MODE is the mode of this
+   argument and TYPE is its type (if known).  NAMED is true if this
+   is a named (fixed) argument rather than a variable one.  */
+
 static void
-mips_arg_info (cum, mode, type, named, info)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     struct mips_arg_info *info;
+mips_arg_info (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
+	       tree type, int named, struct mips_arg_info *info)
 {
   bool even_reg_p;
   unsigned int num_words, max_regs;
 
-  info->struct_p = (type != 0
-		    && (TREE_CODE (type) == RECORD_TYPE
-			|| TREE_CODE (type) == UNION_TYPE
-			|| TREE_CODE (type) == QUAL_UNION_TYPE));
-
   /* Decide whether this argument should go in a floating-point register,
      assuming one is free.  Later code checks for availability.  */
 
-  info->fpr_p = false;
-  if (GET_MODE_CLASS (mode) == MODE_FLOAT
-      && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE)
-    {
-      switch (mips_abi)
-	{
-	case ABI_32:
-	case ABI_O64:
-	  info->fpr_p = (!cum->gp_reg_found && cum->arg_number < 2);
-	  break;
+  info->fpr_p = (GET_MODE_CLASS (mode) == MODE_FLOAT
+		 && GET_MODE_SIZE (mode) <= UNITS_PER_FPVALUE);
 
-	case ABI_EABI:
-	  info->fpr_p = true;
-	  break;
+  if (info->fpr_p)
+    switch (mips_abi)
+      {
+      case ABI_32:
+      case ABI_O64:
+	info->fpr_p = (!cum->gp_reg_found
+		       && cum->arg_number < 2
+		       && (type == 0 || FLOAT_TYPE_P (type)));
+	break;
 
-	default:
-	  info->fpr_p = named;
-	  break;
-	}
-    }
+      case ABI_N32:
+      case ABI_64:
+	info->fpr_p = (named && (type == 0 || FLOAT_TYPE_P (type)));
+	break;
+      }
 
   /* Now decide whether the argument must go in an even-numbered register.  */
 
@@ -4013,49 +3638,16 @@ mips_arg_info (cum, mode, type, named, info)
 }
 
 
-/* Advance the argument to the next argument position.  */
+/* Implement FUNCTION_ARG_ADVANCE.  */
 
 void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;	/* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* whether or not the argument was named */
+function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+		      tree type, int named)
 {
   struct mips_arg_info info;
 
   mips_arg_info (cum, mode, type, named, &info);
 
-  /* The following is a hack in order to pass 1 byte structures
-     the same way that the MIPS compiler does (namely by passing
-     the structure in the high byte or half word of the register).
-     This also makes varargs work.  If we have such a structure,
-     we save the adjustment RTL, and the call define expands will
-     emit them.  For the VOIDmode argument (argument after the
-     last real argument), pass back a parallel vector holding each
-     of the adjustments.  */
-
-  /* ??? This scheme requires everything smaller than the word size to
-     shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
-     that would mean every int needs to be shifted left, which is very
-     inefficient.  Let's not carry this compatibility to the 64 bit
-     calling convention for now.  */
-
-  if (info.struct_p
-      && info.reg_words == 1
-      && info.num_bytes < UNITS_PER_WORD
-      && !TARGET_64BIT
-      && mips_abi != ABI_EABI)
-    {
-      rtx amount = GEN_INT (BITS_PER_WORD - info.num_bytes * BITS_PER_UNIT);
-      rtx reg = gen_rtx_REG (word_mode, GP_ARG_FIRST + info.reg_offset);
-
-      if (TARGET_64BIT)
-	cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashldi3 (reg, reg, amount));
-      else
-	cum->adjust[cum->num_adjusts++] = PATTERN (gen_ashlsi3 (reg, reg, amount));
-    }
-
   if (!info.fpr_p)
     cum->gp_reg_found = true;
 
@@ -4076,32 +3668,21 @@ function_arg_advance (cum, mode, type, named)
   cum->arg_number++;
 }
 
-/* Return an RTL expression containing the register for the given mode,
-   or 0 if the argument is to be passed on the stack.  */
+/* Implement FUNCTION_ARG.  */
 
 struct rtx_def *
-function_arg (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum; /* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* != 0 for normal args, == 0 for ... args */
+function_arg (const CUMULATIVE_ARGS *cum, enum machine_mode mode,
+	      tree type, int named)
 {
   struct mips_arg_info info;
 
   /* We will be called with a mode of VOIDmode after the last argument
      has been seen.  Whatever we return will be passed to the call
-     insn.  If we need any shifts for small structures, return them in
-     a PARALLEL; in that case, stuff the mips16 fp_code in as the
-     mode.  Otherwise, if we need a mips16 fp_code, return a REG
-     with the code stored as the mode.  */
+     insn.  If we need a mips16 fp_code, return a REG with the code
+     stored as the mode.  */
   if (mode == VOIDmode)
     {
-      if (cum->num_adjusts > 0)
-	return gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
-				 gen_rtvec_v (cum->num_adjusts,
-					      (rtx *) cum->adjust));
-
-      else if (TARGET_MIPS16 && cum->fp_code != 0)
+      if (TARGET_MIPS16 && cum->fp_code != 0)
 	return gen_rtx_REG ((enum machine_mode) cum->fp_code, 0);
 
       else
@@ -4119,8 +3700,7 @@ function_arg (cum, mode, type, named)
       && (mips_abi == ABI_N32 || mips_abi == ABI_64)
       && TYPE_SIZE_UNIT (type)
       && host_integerp (TYPE_SIZE_UNIT (type), 1)
-      && named
-      && mode != DFmode)
+      && named)
     {
       /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
 	 structure contains a double in its entirety, then that 64 bit
@@ -4185,32 +3765,75 @@ function_arg (cum, mode, type, named)
     return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset);
 }
 
+
+/* Implement FUNCTION_ARG_PARTIAL_NREGS.  */
+
 int
-function_arg_partial_nregs (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum; /* current arg information */
-     enum machine_mode mode;	/* current arg mode */
-     tree type;			/* type of the argument or 0 if lib support */
-     int named;			/* != 0 for normal args, == 0 for ... args */
+function_arg_partial_nregs (const CUMULATIVE_ARGS *cum,
+			    enum machine_mode mode, tree type, int named)
 {
   struct mips_arg_info info;
 
   mips_arg_info (cum, mode, type, named, &info);
   return info.stack_words > 0 ? info.reg_words : 0;
 }
+
+
+/* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
+   upward rather than downward.  In other words, return true if the
+   first byte of the stack slot has useful data, false if the last
+   byte does.  */
+
+bool
+mips_pad_arg_upward (enum machine_mode mode, tree type)
+{
+  /* On little-endian targets, the first byte of every stack argument
+     is passed in the first byte of the stack slot.  */
+  if (!BYTES_BIG_ENDIAN)
+    return true;
+
+  /* Otherwise, integral types are padded downward: the last byte of a
+     stack argument is passed in the last byte of the stack slot.  */
+  if (type != 0
+      ? INTEGRAL_TYPE_P (type) || POINTER_TYPE_P (type)
+      : GET_MODE_CLASS (mode) == MODE_INT)
+    return false;
+
+  /* Other types are padded upward for o32, o64, n32 and n64.  */
+  if (mips_abi != ABI_EABI)
+    return true;
+
+  /* Arguments smaller than a stack slot are padded downward.  */
+  if (mode != BLKmode)
+    return (GET_MODE_BITSIZE (mode) >= PARM_BOUNDARY);
+  else
+    return (int_size_in_bytes (type) >= (PARM_BOUNDARY / BITS_PER_UNIT));
+}
+
+
+/* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...).  Return !BYTES_BIG_ENDIAN
+   if the least significant byte of the register has useful data.  Return
+   the opposite if the most significant byte does.  */
+
+bool
+mips_pad_reg_upward (enum machine_mode mode, tree type)
+{
+  /* No shifting is required for floating-point arguments.  */
+  if (type != 0 ? FLOAT_TYPE_P (type) : GET_MODE_CLASS (mode) == MODE_FLOAT)
+    return !BYTES_BIG_ENDIAN;
+
+  /* Otherwise, apply the same padding to register arguments as we do
+     to stack arguments.  */
+  return mips_pad_arg_upward (mode, type);
+}
 
 int
-mips_setup_incoming_varargs (cum, mode, type, no_rtl)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int no_rtl;
+mips_setup_incoming_varargs (const CUMULATIVE_ARGS *cum,
+			     enum machine_mode mode, tree type, int no_rtl)
 {
   CUMULATIVE_ARGS local_cum;
   int gp_saved, fp_saved;
 
-  if (mips_abi == ABI_32 || mips_abi == ABI_O64)
-    return 0;
-
   /* The caller has advanced CUM up to, but not beyond, the last named
      argument.  Advance a local copy of CUM past the last "real" named
      argument, to find out how many registers are left over.  */
@@ -4231,19 +3854,22 @@ mips_setup_incoming_varargs (cum, mode, type, no_rtl)
 	  rtx ptr, mem;
 
 	  ptr = virtual_incoming_args_rtx;
-	  if (mips_abi == ABI_EABI)
-	    ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
-	  mem = gen_rtx_MEM (BLKmode, ptr);
+	  switch (mips_abi)
+	    {
+	    case ABI_32:
+	    case ABI_O64:
+	      ptr = plus_constant (ptr, local_cum.num_gprs * UNITS_PER_WORD);
+	      break;
 
-	  /* va_arg is an array access in this case, which causes
-	     it to get MEM_IN_STRUCT_P set.  We must set it here
-	     so that the insn scheduler won't assume that these
-	     stores can't possibly overlap with the va_arg loads.  */
-	  if (mips_abi != ABI_EABI && BYTES_BIG_ENDIAN)
-	    MEM_SET_IN_STRUCT_P (mem, 1);
+	    case ABI_EABI:
+	      ptr = plus_constant (ptr, -gp_saved * UNITS_PER_WORD);
+	      break;
+	    }
+	  mem = gen_rtx_MEM (BLKmode, ptr);
+	  set_mem_alias_set (mem, get_varargs_alias_set ());
 
-	  move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, mem,
-			       gp_saved);
+	  move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST,
+			       mem, gp_saved);
 	}
       if (fp_saved > 0)
 	{
@@ -4263,13 +3889,20 @@ mips_setup_incoming_varargs (cum, mode, type, no_rtl)
 
 	  for (i = local_cum.num_fprs; i < MAX_ARGS_IN_REGISTERS; i += FP_INC)
 	    {
-	      rtx ptr = plus_constant (virtual_incoming_args_rtx, off);
-	      emit_move_insn (gen_rtx_MEM (mode, ptr),
-			      gen_rtx_REG (mode, FP_ARG_FIRST + i));
+	      rtx ptr, mem;
+
+	      ptr = plus_constant (virtual_incoming_args_rtx, off);
+	      mem = gen_rtx_MEM (mode, ptr);
+	      set_mem_alias_set (mem, get_varargs_alias_set ());
+	      emit_move_insn (mem, gen_rtx_REG (mode, FP_ARG_FIRST + i));
 	      off += UNITS_PER_HWFPVALUE;
 	    }
 	}
     }
+  if (mips_abi == ABI_32 || mips_abi == ABI_O64)
+    /* No need for pretend arguments: the register parameter area was
+       allocated by the caller.  */
+    return 0;
   return (gp_saved * UNITS_PER_WORD) + (fp_saved * UNITS_PER_FPREG);
 }
 
@@ -4295,7 +3928,7 @@ mips_setup_incoming_varargs (cum, mode, type, no_rtl)
 
 
 tree
-mips_build_va_list ()
+mips_build_va_list (void)
 {
   if (EABI_FLOAT_VARARGS_P)
     {
@@ -4342,12 +3975,10 @@ mips_build_va_list ()
     return ptr_type_node;
 }
 
-/* Implement va_start.   stdarg_p is always 1.  */
+/* Implement va_start.  */
 
 void
-mips_va_start (valist, nextarg)
-     tree valist;
-     rtx nextarg;
+mips_va_start (tree valist, rtx nextarg)
 {
   const CUMULATIVE_ARGS *cum = &current_function_args_info;
 
@@ -4440,148 +4071,10 @@ mips_va_start (valist, nextarg)
     std_expand_builtin_va_start (valist, nextarg);
 }
 
-/* Return true if it is possible to use left/right accesses for a
-   bitfield of WIDTH bits starting BITPOS bits into *OP.  When
-   returning true, update *OP, *LEFT and *RIGHT as follows:
-
-   *OP is a BLKmode reference to the whole field.
-
-   *LEFT is a QImode reference to the first byte if big endian or
-   the last byte if little endian.  This address can be used in the
-   left-side instructions (lwl, swl, ldl, sdl).
-
-   *RIGHT is a QImode reference to the opposite end of the field and
-   can be used in the parterning right-side instruction.  */
-
-static bool
-mips_get_unaligned_mem (op, width, bitpos, left, right)
-     rtx *op, *left, *right;
-     unsigned int width;
-     int bitpos;
-{
-  rtx first, last;
-
-  /* Check that the operand really is a MEM.  Not all the extv and
-     extzv predicates are checked.  */
-  if (GET_CODE (*op) != MEM)
-    return false;
-
-  /* Check that the size is valid.  */
-  if (width != 32 && (!TARGET_64BIT || width != 64))
-    return false;
-
-  /* We can only access byte-aligned values.  Since we are always passed
-     a reference to the first byte of the field, it is not necessary to
-     do anything with BITPOS after this check.  */
-  if (bitpos % BITS_PER_UNIT != 0)
-    return false;
-
-  /* Reject aligned bitfields: we want to use a normal load or store
-     instead of a left/right pair.  */
-  if (MEM_ALIGN (*op) >= width)
-    return false;
-
-  /* Adjust *OP to refer to the whole field.  This also has the effect
-     of legitimizing *OP's address for BLKmode, possibly simplifying it.  */
-  *op = adjust_address (*op, BLKmode, 0);
-  set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
-
-  /* Get references to both ends of the field.  We deliberately don't
-     use the original QImode *OP for FIRST since the new BLKmode one
-     might have a simpler address.  */
-  first = adjust_address (*op, QImode, 0);
-  last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
-
-  /* Allocate to LEFT and RIGHT according to endiannes.  LEFT should
-     be the upper word and RIGHT the lower word.  */
-  if (TARGET_BIG_ENDIAN)
-    *left = first, *right = last;
-  else
-    *left = last, *right = first;
-
-  return true;
-}
-
-
-/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
-   Return true on success.  We only handle cases where zero_extract is
-   equivalent to sign_extract.  */
-
-bool
-mips_expand_unaligned_load (dest, src, width, bitpos)
-     rtx dest, src;
-     unsigned int width;
-     int bitpos;
-{
-  rtx left, right;
-
-  /* If TARGET_64BIT, the destination of a 32-bit load will be a
-     paradoxical word_mode subreg.  This is the only case in which
-     we allow the destination to be larger than the source.  */
-  if (GET_CODE (dest) == SUBREG
-      && GET_MODE (dest) == DImode
-      && SUBREG_BYTE (dest) == 0
-      && GET_MODE (SUBREG_REG (dest)) == SImode)
-    dest = SUBREG_REG (dest);
-
-  /* After the above adjustment, the destination must be the same
-     width as the source.  */
-  if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
-    return false;
-
-  if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
-    return false;
-
-  if (GET_MODE (dest) == DImode)
-    {
-      emit_insn (gen_mov_ldl (dest, src, left));
-      emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
-			      right, copy_rtx (dest)));
-    }
-  else
-    {
-      emit_insn (gen_mov_lwl (dest, src, left));
-      emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
-			      right, copy_rtx (dest)));
-    }
-  return true;
-}
-
-
-/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC).  Return
-   true on success.  */
-
-bool
-mips_expand_unaligned_store (dest, src, width, bitpos)
-     rtx dest, src;
-     unsigned int width;
-     int bitpos;
-{
-  rtx left, right;
-
-  if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
-    return false;
-
-  src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
-
-  if (GET_MODE (src) == DImode)
-    {
-      emit_insn (gen_mov_sdl (dest, src, left));
-      emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
-    }
-  else
-    {
-      emit_insn (gen_mov_swl (dest, src, left));
-      emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
-    }
-  return true;
-}
-
 /* Implement va_arg.  */
 
 rtx
-mips_va_arg (valist, type)
-     tree valist, type;
+mips_va_arg (tree valist, tree type)
 {
   HOST_WIDE_INT size, rsize;
   rtx addr_rtx;
@@ -4659,11 +4152,11 @@ mips_va_arg (valist, type)
 
 		 TOP be the top of the register save area;
 		 OFF be the offset from TOP of the next register;
-		 ADDR_RTX be the address of the argument; and
+		 ADDR_RTX be the address of the argument;
 		 RSIZE be the number of bytes used to store the argument
-		   when it's in the register save area
+		   when it's in the register save area;
 		 OSIZE be the number of bytes used to store it when it's
-		   in the stack overflow area
+		   in the stack overflow area; and
 		 PADDING be (BYTES_BIG_ENDIAN ? OSIZE - RSIZE : 0)
 
 	     The code we want is:
@@ -4687,8 +4180,8 @@ mips_va_arg (valist, type)
 	  lab_over = gen_label_rtx ();
 
 	  ovfl = build (COMPONENT_REF, TREE_TYPE (f_ovfl), valist, f_ovfl);
-
-	  if (TREE_CODE (type) == REAL_TYPE)
+	  if (GET_MODE_CLASS (TYPE_MODE (type)) == MODE_FLOAT
+	      && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FPVALUE)
 	    {
 	      top = build (COMPONENT_REF, TREE_TYPE (f_ftop), valist, f_ftop);
 	      off = build (COMPONENT_REF, TREE_TYPE (f_foff), valist, f_foff);
@@ -4810,24 +4303,140 @@ mips_va_arg (valist, type)
     }
 }
 
-/* Abort after printing out a specific insn.  */
+/* Return true if it is possible to use left/right accesses for a
+   bitfield of WIDTH bits starting BITPOS bits into *OP.  When
+   returning true, update *OP, *LEFT and *RIGHT as follows:
 
-static void
-abort_with_insn (insn, reason)
-     rtx insn;
-     const char *reason;
+   *OP is a BLKmode reference to the whole field.
+
+   *LEFT is a QImode reference to the first byte if big endian or
+   the last byte if little endian.  This address can be used in the
+   left-side instructions (lwl, swl, ldl, sdl).
+
+   *RIGHT is a QImode reference to the opposite end of the field and
+   can be used in the parterning right-side instruction.  */
+
+static bool
+mips_get_unaligned_mem (rtx *op, unsigned int width, int bitpos,
+			rtx *left, rtx *right)
 {
-  error (reason);
-  debug_rtx (insn);
-  abort ();
+  rtx first, last;
+
+  /* Check that the operand really is a MEM.  Not all the extv and
+     extzv predicates are checked.  */
+  if (GET_CODE (*op) != MEM)
+    return false;
+
+  /* Check that the size is valid.  */
+  if (width != 32 && (!TARGET_64BIT || width != 64))
+    return false;
+
+  /* We can only access byte-aligned values.  Since we are always passed
+     a reference to the first byte of the field, it is not necessary to
+     do anything with BITPOS after this check.  */
+  if (bitpos % BITS_PER_UNIT != 0)
+    return false;
+
+  /* Reject aligned bitfields: we want to use a normal load or store
+     instead of a left/right pair.  */
+  if (MEM_ALIGN (*op) >= width)
+    return false;
+
+  /* Adjust *OP to refer to the whole field.  This also has the effect
+     of legitimizing *OP's address for BLKmode, possibly simplifying it.  */
+  *op = adjust_address (*op, BLKmode, 0);
+  set_mem_size (*op, GEN_INT (width / BITS_PER_UNIT));
+
+  /* Get references to both ends of the field.  We deliberately don't
+     use the original QImode *OP for FIRST since the new BLKmode one
+     might have a simpler address.  */
+  first = adjust_address (*op, QImode, 0);
+  last = adjust_address (*op, QImode, width / BITS_PER_UNIT - 1);
+
+  /* Allocate to LEFT and RIGHT according to endiannes.  LEFT should
+     be the upper word and RIGHT the lower word.  */
+  if (TARGET_BIG_ENDIAN)
+    *left = first, *right = last;
+  else
+    *left = last, *right = first;
+
+  return true;
+}
+
+
+/* Try to emit the equivalent of (set DEST (zero_extract SRC WIDTH BITPOS)).
+   Return true on success.  We only handle cases where zero_extract is
+   equivalent to sign_extract.  */
+
+bool
+mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
+{
+  rtx left, right;
+
+  /* If TARGET_64BIT, the destination of a 32-bit load will be a
+     paradoxical word_mode subreg.  This is the only case in which
+     we allow the destination to be larger than the source.  */
+  if (GET_CODE (dest) == SUBREG
+      && GET_MODE (dest) == DImode
+      && SUBREG_BYTE (dest) == 0
+      && GET_MODE (SUBREG_REG (dest)) == SImode)
+    dest = SUBREG_REG (dest);
+
+  /* After the above adjustment, the destination must be the same
+     width as the source.  */
+  if (GET_MODE_BITSIZE (GET_MODE (dest)) != width)
+    return false;
+
+  if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
+    return false;
+
+  if (GET_MODE (dest) == DImode)
+    {
+      emit_insn (gen_mov_ldl (dest, src, left));
+      emit_insn (gen_mov_ldr (copy_rtx (dest), copy_rtx (src),
+			      right, copy_rtx (dest)));
+    }
+  else
+    {
+      emit_insn (gen_mov_lwl (dest, src, left));
+      emit_insn (gen_mov_lwr (copy_rtx (dest), copy_rtx (src),
+			      right, copy_rtx (dest)));
+    }
+  return true;
+}
+
+
+/* Try to expand (set (zero_extract DEST WIDTH BITPOS) SRC).  Return
+   true on success.  */
+
+bool
+mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
+{
+  rtx left, right;
+
+  if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
+    return false;
+
+  src = gen_lowpart (mode_for_size (width, MODE_INT, 0), src);
+
+  if (GET_MODE (src) == DImode)
+    {
+      emit_insn (gen_mov_sdl (dest, src, left));
+      emit_insn (gen_mov_sdr (copy_rtx (dest), copy_rtx (src), right));
+    }
+  else
+    {
+      emit_insn (gen_mov_swl (dest, src, left));
+      emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
+    }
+  return true;
 }
 
 /* Set up globals to generate code for the ISA or processor
    described by INFO.  */
 
 static void
-mips_set_architecture (info)
-     const struct mips_cpu_info *info;
+mips_set_architecture (const struct mips_cpu_info *info)
 {
   if (info != 0)
     {
@@ -4841,8 +4450,7 @@ mips_set_architecture (info)
 /* Likewise for tuning.  */
 
 static void
-mips_set_tune (info)
-     const struct mips_cpu_info *info;
+mips_set_tune (const struct mips_cpu_info *info)
 {
   if (info != 0)
     {
@@ -4856,7 +4464,7 @@ mips_set_tune (info)
    of the normal data area, and detect any conflicts in the switches.  */
 
 void
-override_options ()
+override_options (void)
 {
   int i, start, regno;
   enum machine_mode mode;
@@ -4888,38 +4496,25 @@ override_options ()
   if (mips_arch_string != 0)
     mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
 
-  if (mips_tune_string != 0)
-    mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
-
   if (mips_isa_string != 0)
     {
       /* Handle -mipsN.  */
+      char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
+      const struct mips_cpu_info *isa_info;
 
-      if (strcmp (mips_isa_string, "16") == 0)
-	{
-	  /* -mips16 specifies an ASE rather than a processor, so don't
-	     change mips_arch here.  -mno-mips16 overrides -mips16.  */
-	  if (mips_no_mips16_string == NULL)
-	    target_flags |= MASK_MIPS16;
-	}
-      else
-	{
-	  char *whole_isa_str = concat ("mips", mips_isa_string, NULL);
-	  const struct mips_cpu_info *isa_info;
-
-	  isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
-	  free (whole_isa_str);
+      isa_info = mips_parse_cpu ("-mips option", whole_isa_str);
+      free (whole_isa_str);
 
-	  /* -march takes precedence over -mipsN, since it is more descriptive.
-	     There's no harm in specifying both as long as the ISA levels
-	     are the same.  */
-	  if (mips_arch_info != 0 && mips_isa != isa_info->isa)
-	    error ("-mips%s conflicts with the other architecture options, which specify a MIPS%d processor",
-		   mips_isa_string, mips_isa);
+      /* -march takes precedence over -mipsN, since it is more descriptive.
+	 There's no harm in specifying both as long as the ISA levels
+	 are the same.  */
+      if (mips_arch_info != 0 && mips_isa != isa_info->isa)
+	error ("-mips%s conflicts with the other architecture options, "
+	       "which specify a MIPS%d processor",
+	       mips_isa_string, mips_isa);
 
-	  /* Set architecture based on the given option.  */
-	  mips_set_architecture (isa_info);
-	}
+      /* Set architecture based on the given option.  */
+      mips_set_architecture (isa_info);
     }
 
   if (mips_arch_info == 0)
@@ -4937,6 +4532,9 @@ override_options ()
 	   mips_arch_info->name);
 
   /* Optimize for mips_arch, unless -mtune selects a different processor.  */
+  if (mips_tune_string != 0)
+    mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
+
   if (mips_tune_info == 0)
     mips_set_tune (mips_arch_info);
 
@@ -5043,20 +4641,23 @@ override_options ()
   if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY)
     warning ("generation of Branch Likely instructions enabled, but not supported by architecture");
 
+  /* The effect of -mabicalls isn't defined for the EABI.  */
+  if (mips_abi == ABI_EABI && TARGET_ABICALLS)
+    {
+      error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
+      target_flags &= ~MASK_ABICALLS;
+    }
+
   /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined.  We need
      to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work.  */
   /* ??? -non_shared turns off pic code generation, but this is not
      implemented.  */
   if (TARGET_ABICALLS)
     {
-      mips_abicalls = MIPS_ABICALLS_YES;
-      if (flag_pic == 0)
-	flag_pic = 1;
+      flag_pic = 1;
       if (mips_section_threshold > 0)
 	warning ("-G is incompatible with PIC code which is the default");
     }
-  else
-    mips_abicalls = MIPS_ABICALLS_NO;
 
   /* The MIPS and SGI o32 assemblers expect small-data variables to
      be declared before they are used.  Although we once had code to
@@ -5065,6 +4666,13 @@ override_options ()
   if (!TARGET_EXPLICIT_RELOCS && !TARGET_GAS)
     mips_section_threshold = 0;
 
+  /* We switch to small data sections using ".section", which the native
+     o32 irix assemblers don't understand.  Disable -G accordingly.
+     We must do this regardless of command-line options since otherwise
+     the compiler would abort.  */
+  if (!targetm.have_named_sections)
+    mips_section_threshold = 0;
+
   /* -membedded-pic is a form of PIC code suitable for embedded
      systems.  All calls are made using PC relative addressing, and
      all data is addressed using the $gp register.  This requires gas,
@@ -5164,13 +4772,6 @@ override_options ()
 	mips_entry = 1;
     }
 
-  /* We copy TARGET_MIPS16 into the mips16 global variable, so that
-     attributes can access it.  */
-  if (TARGET_MIPS16)
-    mips16 = 1;
-  else
-    mips16 = 0;
-
   /* When using explicit relocs, we call dbr_schedule from within
      mips_reorg.  */
   if (TARGET_EXPLICIT_RELOCS)
@@ -5244,12 +4845,7 @@ override_options ()
   mips_dbx_regno[HI_REGNUM] = MD_DBX_FIRST + 0;
   mips_dbx_regno[LO_REGNUM] = MD_DBX_FIRST + 1;
 
-  /* Set up array giving whether a given register can hold a given mode.
-     At present, restrict ints from being in FP registers, because reload
-     is a little enthusiastic about storing extra values in FP registers,
-     and this is not good for things like OS kernels.  Also, due to the
-     mandatory delay, it is as fast to load from cached memory as to move
-     from the FP register.  */
+  /* Set up array giving whether a given register can hold a given mode.  */
 
   for (mode = VOIDmode;
        mode != MAX_MACHINE_MODE;
@@ -5325,7 +4921,7 @@ override_options ()
 /* Implement CONDITIONAL_REGISTER_USAGE.  */
 
 void
-mips_conditional_register_usage ()
+mips_conditional_register_usage (void)
 {
   if (!TARGET_HARD_FLOAT)
     {
@@ -5380,7 +4976,7 @@ mips_conditional_register_usage ()
 
 /* Allocate a chunk of memory for per-function machine-dependent data.  */
 static struct machine_function *
-mips_init_machine_status ()
+mips_init_machine_status (void)
 {
   return ((struct machine_function *)
 	  ggc_alloc_cleared (sizeof (struct machine_function)));
@@ -5392,7 +4988,7 @@ mips_init_machine_status ()
    encouraging the compiler to use a cmp instead.  */
 
 void
-mips_order_regs_for_local_alloc ()
+mips_order_regs_for_local_alloc (void)
 {
   register int i;
 
@@ -5419,9 +5015,7 @@ mips_order_regs_for_local_alloc ()
    the initial adjustments.  */
 
 HOST_WIDE_INT
-mips_debugger_offset (addr, offset)
-     rtx addr;
-     HOST_WIDE_INT offset;
+mips_debugger_offset (rtx addr, HOST_WIDE_INT offset)
 {
   rtx offset2 = const0_rtx;
   rtx reg = eliminate_constant_term (addr, &offset2);
@@ -5446,37 +5040,18 @@ mips_debugger_offset (addr, offset)
   /* sdbout_parms does not want this to crash for unrecognized cases.  */
 #if 0
   else if (reg != arg_pointer_rtx)
-    abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer");
+    fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
+		addr);
 #endif
 
   return offset;
 }
 
-/* A C compound statement to output to stdio stream STREAM the
-   assembler syntax for an instruction operand X.  X is an RTL
-   expression.
-
-   CODE is a value that can be used to specify one of several ways
-   of printing the operand.  It is used when identical operands
-   must be printed differently depending on the context.  CODE
-   comes from the `%' specification that was used to request
-   printing of the operand.  If the specification was just `%DIGIT'
-   then CODE is 0; if the specification was `%LTR DIGIT' then CODE
-   is the ASCII code for LTR.
-
-   If X is a register, this macro should print the register's name.
-   The names can be found in an array `reg_names' whose type is
-   `char *[]'.  `reg_names' is initialized from `REGISTER_NAMES'.
-
-   When the machine description has a specification `%PUNCT' (a `%'
-   followed by a punctuation character), this macro is called with
-   a null pointer for X and the punctuation character for CODE.
-
-   The MIPS specific codes are:
-
-   'X'  X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
-   'x'  X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
-   'h'  X is HIGH, prints %hi(X),
+/* Implement the PRINT_OPERAND macro.  The MIPS-specific operand codes are:
+
+   'X'  OP is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
+   'x'  OP is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
+   'h'  OP is HIGH, prints %hi(X),
    'd'  output integer constant in decimal,
    'z'	if the operand is 0, use $0 instead of normal operand.
    'D'  print second part of double-word register or memory operand.
@@ -5486,13 +5061,16 @@ mips_debugger_offset (addr, offset)
    'F'  print part of opcode for a floating-point branch condition.
    'N'  print part of opcode for a branch condition, inverted.
    'W'  print part of opcode for a floating-point branch condition, inverted.
-   'S'  X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
+   'S'  OP is CODE_LABEL, print with prefix of "LS" (for embedded switch).
    'B'  print 'z' for EQ, 'n' for NE
    'b'  print 'n' for EQ, 'z' for NE
    'T'  print 'f' for EQ, 't' for NE
    't'  print 't' for EQ, 'f' for NE
    'Z'  print register and a comma, but print nothing for $fcc0
    'R'  print the reloc associated with LO_SUM
+
+   The punctuation characters are:
+
    '('	Turn on .set noreorder
    ')'	Turn on .set reorder
    '['	Turn on .set noat
@@ -5515,10 +5093,7 @@ mips_debugger_offset (addr, offset)
    '~'	Output a branch alignment to LABEL_ALIGN(NULL).  */
 
 void
-print_operand (file, op, letter)
-     FILE *file;		/* file to write to */
-     rtx op;			/* operand to print */
-     int letter;		/* %<letter> or 0 */
+print_operand (FILE *file, rtx op, int letter)
 {
   register enum rtx_code code;
   struct mips_constant_info c;
@@ -5663,9 +5238,6 @@ print_operand (file, op, letter)
 
   code = GET_CODE (op);
 
-  if (code == SIGN_EXTEND)
-    op = XEXP (op, 0), code = GET_CODE (op);
-
   if (letter == 'R')
     {
       if (TARGET_ABICALLS && TARGET_NEWABI)
@@ -5699,7 +5271,7 @@ print_operand (file, op, letter)
       case LTU: fputs ("ltu", file); break;
       case LEU: fputs ("leu", file); break;
       default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
+	fatal_insn ("PRINT_OPERAND, invalid insn for %%C", op);
       }
 
   else if (letter == 'N')
@@ -5716,7 +5288,7 @@ print_operand (file, op, letter)
       case LTU: fputs ("geu", file); break;
       case LEU: fputs ("gtu", file); break;
       default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
+	fatal_insn ("PRINT_OPERAND, invalid insn for %%N", op);
       }
 
   else if (letter == 'F')
@@ -5725,7 +5297,7 @@ print_operand (file, op, letter)
       case EQ: fputs ("c1f", file); break;
       case NE: fputs ("c1t", file); break;
       default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
+	fatal_insn ("PRINT_OPERAND, invalid insn for %%F", op);
       }
 
   else if (letter == 'W')
@@ -5734,7 +5306,7 @@ print_operand (file, op, letter)
       case EQ: fputs ("c1t", file); break;
       case NE: fputs ("c1f", file); break;
       default:
-	abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
+	fatal_insn ("PRINT_OPERAND, invalid insn for %%W", op);
       }
 
   else if (letter == 'S')
@@ -5835,8 +5407,7 @@ print_operand (file, op, letter)
 /* Return the assembly operator used for the given type of relocation.  */
 
 static const char *
-mips_reloc_string (reloc)
-     int reloc;
+mips_reloc_string (int reloc)
 {
   switch (reloc)
     {
@@ -5857,9 +5428,7 @@ mips_reloc_string (reloc)
 /* Output address operand X to FILE.   */
 
 void
-print_operand_address (file, x)
-     FILE *file;
-     rtx x;
+print_operand_address (FILE *file, rtx x)
 {
   struct mips_address_info addr;
 
@@ -5891,10 +5460,7 @@ print_operand_address (file, x)
    such an integer here.  */
 
 static bool
-mips_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+mips_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if ((TARGET_64BIT || TARGET_GAS) && size == 8 && aligned_p)
     {
@@ -5918,10 +5484,7 @@ mips_assemble_integer (x, size, aligned_p)
    than .sbss or .sdata.  */
 
 int
-mips_output_external (file, decl, name)
-     FILE *file ATTRIBUTE_UNUSED;
-     tree decl;
-     const char *name;
+mips_output_external (FILE *file ATTRIBUTE_UNUSED, tree decl, const char *name)
 {
   register struct extern_list *p;
 
@@ -5956,9 +5519,7 @@ mips_output_external (file, decl, name)
 
 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
 int
-mips_output_external_libcall (file, name)
-     FILE *file ATTRIBUTE_UNUSED;
-     const char *name;
+mips_output_external_libcall (FILE *file ATTRIBUTE_UNUSED, const char *name)
 {
   register struct extern_list *p;
 
@@ -5972,14 +5533,11 @@ mips_output_external_libcall (file, name)
 }
 #endif
 
-/* Emit a new filename to a stream.  If this is MIPS ECOFF, watch out
-   for .file's that start within a function.  If we are smuggling stabs, try to
+/* Emit a new filename to a stream.  If we are smuggling stabs, try to
    put out a MIPS ECOFF file and a stab.  */
 
 void
-mips_output_filename (stream, name)
-     FILE *stream;
-     const char *name;
+mips_output_filename (FILE *stream, const char *name)
 {
   char ltext_label_name[100];
 
@@ -6007,23 +5565,11 @@ mips_output_filename (stream, name)
     }
 
   else if (name != current_function_file
-      && strcmp (name, current_function_file) != 0)
+	   && strcmp (name, current_function_file) != 0)
     {
-      if (inside_function && !TARGET_GAS)
-	{
-	  if (!file_in_function_warning)
-	    {
-	      file_in_function_warning = 1;
-	      ignore_line_number = 1;
-	      warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
-	    }
-	}
-      else
-	{
-	  SET_FILE_NUMBER ();
-	  current_function_file = name;
-	  ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
-	}
+      SET_FILE_NUMBER ();
+      current_function_file = name;
+      ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
     }
 }
 
@@ -6033,9 +5579,7 @@ mips_output_filename (stream, name)
    file.  */
 
 void
-mips_output_lineno (stream, line)
-     FILE *stream;
-     int line;
+mips_output_lineno (FILE *stream, int line)
 {
   if (write_symbols == DBX_DEBUG)
     {
@@ -6046,10 +5590,7 @@ mips_output_lineno (stream, line)
     }
   else
     {
-      fprintf (stream, "\n\t%s.loc\t%d %d\n",
-	       (ignore_line_number) ? "#" : "",
-	       num_source_filenames, line);
-
+      fprintf (stream, "\n\t.loc\t%d %d\n", num_source_filenames, line);
       LABEL_AFTER_LOC (stream);
     }
 }
@@ -6057,10 +5598,7 @@ mips_output_lineno (stream, line)
 /* Output an ASCII string, in a space-saving way.  */
 
 void
-mips_output_ascii (stream, string_param, len)
-     FILE *stream;
-     const char *string_param;
-     size_t len;
+mips_output_ascii (FILE *stream, const char *string_param, size_t len)
 {
   size_t i;
   int cur_pos = 17;
@@ -6133,16 +5671,10 @@ mips_output_ascii (stream, string_param, len)
   fprintf (stream, "\"\n");
 }
 
-/* Output at beginning of assembler file.
-
-   If we are optimizing to use the global pointer, create a temporary file to
-   hold all of the text stuff, and write it out to the end. This is needed
-   because the MIPS assembler is evidently one pass, and if it hasn't seen the
-   relevant .comm/.lcomm/.extern/.sdata declaration when the code is
-   processed, it generates a two instruction sequence.  */
+/* Implement TARGET_ASM_FILE_START.  */
 
 static void
-mips_file_start ()
+mips_file_start (void)
 {
   default_file_start ();
 
@@ -6203,14 +5735,33 @@ mips_file_start ()
 	     ASM_COMMENT_START,
 	     mips_section_threshold, mips_arch_info->name, mips_isa);
 }
+
+#ifdef BSS_SECTION_ASM_OP
+/* Implement ASM_OUTPUT_ALIGNED_BSS.  This differs from the default only
+   in the use of sbss.  */
+
+void
+mips_output_aligned_bss (FILE *stream, tree decl, const char *name,
+			 unsigned HOST_WIDE_INT size, int align)
+{
+  extern tree last_assemble_variable_decl;
+
+  if (mips_in_small_data_p (decl))
+    named_section (0, ".sbss", 0);
+  else
+    bss_section ();
+  ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
+  last_assemble_variable_decl = decl;
+  ASM_DECLARE_OBJECT_NAME (stream, name, decl);
+  ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
+}
+#endif
 
-/* If we are optimizing the global pointer, emit the text section now and any
-   small externs which did not have .comm, etc that are needed.  Also, give a
-   warning if the data area is more than 32K and -pic because 3 instructions
-   are needed to reference the data pointers.  */
+/* Implement TARGET_ASM_FILE_END.  When using assembler macros, emit
+   .externs for any small-data variables that turned out to be external.  */
 
 static void
-mips_file_end ()
+mips_file_end (void)
 {
   tree name_tree;
   struct extern_list *p;
@@ -6247,12 +5798,8 @@ mips_file_end ()
    .extern for it.  */
 
 void
-mips_declare_object (stream, name, init_string, final_string, size)
-     FILE *stream;
-     const char *name;
-     const char *init_string;
-     const char *final_string;
-     int size;
+mips_declare_object (FILE *stream, const char *name, const char *init_string,
+		     const char *final_string, int size)
 {
   fputs (init_string, stream);		/* "", "\t.comm\t", or "\t.lcomm\t" */
   assemble_name (stream, name);
@@ -6264,13 +5811,63 @@ mips_declare_object (stream, name, init_string, final_string, size)
       TREE_ASM_WRITTEN (name_tree) = 1;
     }
 }
+
+#ifdef ASM_OUTPUT_SIZE_DIRECTIVE
+extern int size_directive_output;
+
+/* Implement ASM_DECLARE_OBJECT_NAME.  This is like most of the standard ELF
+   definitions except that it uses mips_declare_object() to emit the label.  */
+
+void
+mips_declare_object_name (FILE *stream, const char *name,
+			  tree decl ATTRIBUTE_UNUSED)
+{
+#ifdef ASM_OUTPUT_TYPE_DIRECTIVE
+  ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
+#endif
+
+  size_directive_output = 0;
+  if (!flag_inhibit_size_directive && DECL_SIZE (decl))
+    {
+      HOST_WIDE_INT size;
+
+      size_directive_output = 1;
+      size = int_size_in_bytes (TREE_TYPE (decl));
+      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
+    }
+
+  mips_declare_object (stream, name, "", ":\n", 0);
+}
+
+/* Implement ASM_FINISH_DECLARE_OBJECT.  This is generic ELF stuff.  */
+
+void
+mips_finish_declare_object (FILE *stream, tree decl, int top_level, int at_end)
+{
+  const char *name;
+
+  name = XSTR (XEXP (DECL_RTL (decl), 0), 0);
+  if (!flag_inhibit_size_directive
+      && DECL_SIZE (decl) != 0
+      && !at_end && top_level
+      && DECL_INITIAL (decl) == error_mark_node
+      && !size_directive_output)
+    {
+      HOST_WIDE_INT size;
+
+      size_directive_output = 1;
+      size = int_size_in_bytes (TREE_TYPE (decl));
+      ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
+    }
+}
+#endif
 
 /* Return the register that should be used as the global pointer
    within this function.  Return 0 if the function doesn't need
    a global pointer.  */
 
 static unsigned int
-mips_global_pointer ()
+mips_global_pointer (void)
 {
   unsigned int regno;
 
@@ -6320,8 +5917,7 @@ mips_global_pointer ()
 /* Return true if the current function must save REGNO.  */
 
 static bool
-mips_save_reg_p (regno)
-     unsigned int regno;
+mips_save_reg_p (unsigned int regno)
 {
   /* We only need to save $gp for NewABI PIC.  */
   if (regno == GLOBAL_POINTER_REGNUM)
@@ -6359,7 +5955,7 @@ mips_save_reg_p (regno)
       if (regno == GP_REG_FIRST + 31
 	  && mips16_hard_float
 	  && !mips_entry
-	  && !aggregate_value_p (return_type)
+	  && !aggregate_value_p (return_type, current_function_decl)
 	  && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
 	  && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
 	return true;
@@ -6377,7 +5973,7 @@ mips_save_reg_p (regno)
 
 
 /* Return the bytes needed to compute the frame pointer from the current
-   stack pointer.
+   stack pointer.  SIZE is the size (in bytes) of the local variables.
 
    Mips stack frames look like:
 
@@ -6430,8 +6026,7 @@ mips_save_reg_p (regno)
 */
 
 HOST_WIDE_INT
-compute_frame_size (size)
-     HOST_WIDE_INT size;	/* # of var. bytes allocated */
+compute_frame_size (HOST_WIDE_INT size)
 {
   unsigned int regno;
   HOST_WIDE_INT total_size;	/* # bytes that the entire frame takes up */
@@ -6570,8 +6165,7 @@ compute_frame_size (size)
    hard frame pointer.  */
 
 int
-mips_initial_elimination_offset (from, to)
-     int from, to;
+mips_initial_elimination_offset (int from, int to)
 {
   int offset;
 
@@ -6610,9 +6204,7 @@ mips_initial_elimination_offset (from, to)
 /* Implement RETURN_ADDR_RTX.  Note, we do not support moving
    back to a previous frame.  */
 rtx
-mips_return_addr (count, frame)
-     int count;
-     rtx frame ATTRIBUTE_UNUSED;
+mips_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
 {
   if (count != 0)
     return const0_rtx;
@@ -6628,8 +6220,7 @@ mips_return_addr (count, frame)
    OFFSET is too large to add in a single instruction.  */
 
 static rtx
-mips_add_large_offset_to_sp (offset)
-     HOST_WIDE_INT offset;
+mips_add_large_offset_to_sp (HOST_WIDE_INT offset)
 {
   rtx reg = gen_rtx_REG (Pmode, MIPS_TEMP2_REGNUM);
   rtx offset_rtx = GEN_INT (offset);
@@ -6646,8 +6237,7 @@ mips_add_large_offset_to_sp (offset)
    the operation described by FRAME_PATTERN.  */
 
 static void
-mips_set_frame_expr (frame_pattern)
-     rtx frame_pattern;
+mips_set_frame_expr (rtx frame_pattern)
 {
   rtx insn;
 
@@ -6662,9 +6252,7 @@ mips_set_frame_expr (frame_pattern)
    REG must be a single register.  */
 
 static rtx
-mips_frame_set (reg, offset)
-     rtx reg;
-     int offset;
+mips_frame_set (rtx reg, int offset)
 {
   rtx address = plus_constant (stack_pointer_rtx, offset);
   rtx set = gen_rtx_SET (VOIDmode, gen_rtx_MEM (GET_MODE (reg), address), reg);
@@ -6678,10 +6266,7 @@ mips_frame_set (reg, offset)
    function may be asked to store an FPR pair.  */
 
 static void
-mips_emit_frame_related_store (mem, reg, offset)
-     rtx mem;
-     rtx reg;
-     HOST_WIDE_INT offset;
+mips_emit_frame_related_store (rtx mem, rtx reg, HOST_WIDE_INT offset)
 {
   if (GET_MODE (reg) == DFmode && mips_split_64bit_move_p (mem, reg))
     mips_split_64bit_move (mem, reg);
@@ -6703,11 +6288,15 @@ mips_emit_frame_related_store (mem, reg, offset)
     mips_set_frame_expr (mips_frame_set (reg, offset));
 }
 
+
+/* Emit instructions to save or restore the registers in
+   cfun->machine->frame.mask and cfun->machine->frame.fmask.
+   STORE_P is true to save registers (meaning we are expanding
+   the prologue).  If nonnull, LARGE_REG stores the value LARGE_OFFSET,
+   which the caller thinks might be useful to us.  */
+
 static void
-save_restore_insns (store_p, large_reg, large_offset)
-     int store_p;	/* true if this is prologue */
-     rtx large_reg;	/* register holding large offset constant or NULL */
-     long large_offset;	/* large constant offset value */
+save_restore_insns (int store_p, rtx large_reg, long large_offset)
 {
   long mask = cfun->machine->frame.mask;
   long fmask = cfun->machine->frame.fmask;
@@ -6907,9 +6496,7 @@ save_restore_insns (store_p, large_reg, large_offset)
 /* Set up the stack and frame (if desired) for the function.  */
 
 static void
-mips_output_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+mips_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
 #ifndef FUNCTION_NAME_ALREADY_DECLARED
   const char *fnname;
@@ -6935,8 +6522,6 @@ mips_output_function_prologue (file, size)
       && current_function_args_info.fp_code != 0)
     build_mips16_function_stub (file);
 
-  inside_function = 1;
-
 #ifndef FUNCTION_NAME_ALREADY_DECLARED
   /* Get the function name the same way that toplev.c does before calling
      assemble_start_function.  This is needed so that the name used here
@@ -7115,8 +6700,7 @@ mips_output_function_prologue (file, size)
    explicit reloc code, mark the instruction as potentially dead.  */
 
 static void
-mips_gp_insn (dest, src)
-     rtx dest, src;
+mips_gp_insn (rtx dest, rtx src)
 {
   rtx insn;
 
@@ -7135,31 +6719,24 @@ mips_gp_insn (dest, src)
 /* Expand the prologue into a bunch of separate insns.  */
 
 void
-mips_expand_prologue ()
+mips_expand_prologue (void)
 {
-  int regno;
   HOST_WIDE_INT tsize;
   rtx tmp_rtx = 0;
-  int last_arg_is_vararg_marker = 0;
   tree fndecl = current_function_decl;
   tree fntype = TREE_TYPE (fndecl);
   tree fnargs = DECL_ARGUMENTS (fndecl);
-  rtx next_arg_reg;
-  int i;
-  tree next_arg;
   tree cur_arg;
   CUMULATIVE_ARGS args_so_far;
   rtx reg_18_save = NULL_RTX;
-  int store_args_on_stack = (mips_abi == ABI_32 || mips_abi == ABI_O64)
-                            && (! mips_entry || mips_can_use_return_insn ());
 
   if (cfun->machine->global_pointer > 0)
     REGNO (pic_offset_table_rtx) = cfun->machine->global_pointer;
 
   /* If struct value address is treated as the first argument, make it so.  */
-  if (aggregate_value_p (DECL_RESULT (fndecl))
+  if (aggregate_value_p (DECL_RESULT (fndecl), fndecl)
       && ! current_function_returns_pcc_struct
-      && struct_value_incoming_rtx == 0)
+      && targetm.calls.struct_value_rtx (fndecl, 0) == 0)
     {
       tree type = build_pointer_type (fntype);
       tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
@@ -7169,130 +6746,27 @@ mips_expand_prologue ()
       fnargs = function_result_decl;
     }
 
-  /* For arguments passed in registers, find the register number
-     of the first argument in the variable part of the argument list,
-     otherwise GP_ARG_LAST+1.  Note also if the last argument is
-     the varargs special argument, and treat it as part of the
-     variable arguments.
-
-     This is only needed if store_args_on_stack is true.  */
-
+  /* Go through the function arguments, leaving args_so_far reflecting
+     the final state.  */
   INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, current_function_decl);
-  regno = GP_ARG_FIRST;
-
-  for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
+  for (cur_arg = fnargs; cur_arg != 0; cur_arg = TREE_CHAIN (cur_arg))
     {
-      tree passed_type = DECL_ARG_TYPE (cur_arg);
-      enum machine_mode passed_mode = TYPE_MODE (passed_type);
-      rtx entry_parm;
+      tree passed_type;
+      enum machine_mode passed_mode;
 
+      passed_type = DECL_ARG_TYPE (cur_arg);
       if (TREE_ADDRESSABLE (passed_type))
 	{
 	  passed_type = build_pointer_type (passed_type);
 	  passed_mode = Pmode;
 	}
-
-      entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
-
-      FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
-      next_arg = TREE_CHAIN (cur_arg);
-
-      if (entry_parm && store_args_on_stack)
-	{
-	  if (next_arg == 0
-	      && DECL_NAME (cur_arg)
-	      && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
-				"__builtin_va_alist"))
-		  || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
-				   "va_alist"))))
-	    {
-	      last_arg_is_vararg_marker = 1;
-	      if (GET_CODE (entry_parm) == REG)
-		regno = REGNO (entry_parm);
-	      else
-		regno = GP_ARG_LAST + 1;
-	      break;
-	    }
-	  else
-	    {
-	      int words;
-
-	      if (GET_CODE (entry_parm) != REG)
-	        abort ();
-
-	      /* passed in a register, so will get homed automatically */
-	      if (GET_MODE (entry_parm) == BLKmode)
-		words = (int_size_in_bytes (passed_type) + 3) / 4;
-	      else
-		words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
-
-	      regno = REGNO (entry_parm) + words - 1;
-	    }
-	}
       else
-	{
-	  regno = GP_ARG_LAST+1;
-	  break;
-	}
-    }
-
-  /* In order to pass small structures by value in registers compatibly with
-     the MIPS compiler, we need to shift the value into the high part of the
-     register.  Function_arg has encoded a PARALLEL rtx, holding a vector of
-     adjustments to be made as the next_arg_reg variable, so we split up the
-     insns, and emit them separately.  */
-
-  next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
-  if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
-    {
-      rtvec adjust = XVEC (next_arg_reg, 0);
-      int num = GET_NUM_ELEM (adjust);
-
-      for (i = 0; i < num; i++)
-	{
-	  rtx insn, pattern;
-
-	  pattern = RTVEC_ELT (adjust, i);
-	  if (GET_CODE (pattern) != SET
-	      || GET_CODE (SET_SRC (pattern)) != ASHIFT)
-	    abort_with_insn (pattern, "insn is not a shift");
-	  PUT_CODE (SET_SRC (pattern), ASHIFTRT);
-
-	  insn = emit_insn (pattern);
-
-	  /* Global life information isn't valid at this point, so we
-	     can't check whether these shifts are actually used.  Mark
-	     them MAYBE_DEAD so that flow2 will remove them, and not
-	     complain about dead code in the prologue.  */
-	  REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
-					       REG_NOTES (insn));
-	}
+	passed_mode = TYPE_MODE (passed_type);
+      FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
     }
 
   tsize = compute_frame_size (get_frame_size ());
 
-  /* If this function is a varargs function, store any registers that
-     would normally hold arguments ($4 - $7) on the stack.  */
-  if (store_args_on_stack
-      && ((TYPE_ARG_TYPES (fntype) != 0
-	   && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
-	       != void_type_node))
-	  || last_arg_is_vararg_marker))
-    {
-      int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
-      rtx ptr = stack_pointer_rtx;
-
-      for (; regno <= GP_ARG_LAST; regno++)
-	{
-	  if (offset != 0)
-	    ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
-	  emit_move_insn (gen_rtx (MEM, gpr_mode, ptr),
-			  gen_rtx (REG, gpr_mode, regno));
-
-	  offset += GET_MODE_SIZE (gpr_mode);
-	}
-    }
-
   /* If we are using the entry pseudo instruction, it will
      automatically subtract 32 from the stack pointer, so we don't
      need to.  The entry pseudo instruction is emitted by
@@ -7374,27 +6848,24 @@ mips_expand_prologue ()
     {
       rtx tsize_rtx = GEN_INT (tsize);
 
-      /* If we are doing svr4-abi, sp move is done by
-         function_prologue.  In mips16 mode with a large frame, we
-         save the registers before adjusting the stack.  */
-      if (!TARGET_MIPS16 || tsize <= 32767)
+      /* In mips16 mode with a large frame, we save the registers before
+         adjusting the stack.  */
+      if (!TARGET_MIPS16 || tsize <= 32768)
 	{
-	  rtx adjustment_rtx;
-
-	  if (tsize > 32767)
+	  if (tsize > 32768)
 	    {
+	      rtx adjustment_rtx;
+
 	      adjustment_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
 	      emit_move_insn (adjustment_rtx, tsize_rtx);
+	      emit_insn (gen_sub3_insn (stack_pointer_rtx,
+					stack_pointer_rtx,
+					adjustment_rtx));
 	    }
 	  else
-	    adjustment_rtx = tsize_rtx;
-
-	  if (Pmode == DImode)
-	    emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
-				   adjustment_rtx));
-	  else
-	    emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
-				   adjustment_rtx));
+	    emit_insn (gen_add3_insn (stack_pointer_rtx,
+				      stack_pointer_rtx,
+				      GEN_INT (-tsize)));
 
 	  mips_set_frame_expr
 	    (gen_rtx_SET (VOIDmode, stack_pointer_rtx,
@@ -7410,7 +6881,7 @@ mips_expand_prologue ()
 	emit_insn (gen_cprestore
 		   (GEN_INT (current_function_outgoing_args_size)));
 
-      if (TARGET_MIPS16 && tsize > 32767)
+      if (TARGET_MIPS16 && tsize > 32768)
 	{
 	  rtx reg_rtx;
 
@@ -7420,14 +6891,9 @@ mips_expand_prologue ()
 	  reg_rtx = gen_rtx (REG, Pmode, 3);
   	  emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
   	  emit_move_insn (reg_rtx, tsize_rtx);
-  	  if (Pmode == DImode)
-	    emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
-				   hard_frame_pointer_rtx,
-				   reg_rtx));
-	  else
-	    emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
-				   hard_frame_pointer_rtx,
-				   reg_rtx));
+	  emit_insn (gen_sub3_insn (hard_frame_pointer_rtx,
+				    hard_frame_pointer_rtx,
+				    reg_rtx));
 	  emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
 	}
 
@@ -7513,9 +6979,8 @@ mips_expand_prologue ()
 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
 
 static void
-mips_output_function_epilogue (file, size)
-     FILE *file ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED,
+			       HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   rtx string;
 
@@ -7542,10 +7007,6 @@ mips_output_function_epilogue (file, size)
     }
 #endif
 
-  /* Reset state info for each function.  */
-  inside_function = 0;
-  ignore_line_number = 0;
-
   while (string_constants != NULL)
     {
       struct string_constant *next;
@@ -7575,8 +7036,7 @@ mips_output_function_epilogue (file, size)
    "epilogue" pattern.  */
 
 void
-mips_expand_epilogue (sibcall_p)
-     int sibcall_p;
+mips_expand_epilogue (int sibcall_p)
 {
   HOST_WIDE_INT tsize = cfun->machine->frame.total_size;
   rtx tsize_rtx = GEN_INT (tsize);
@@ -7724,7 +7184,7 @@ mips_expand_epilogue (sibcall_p)
    was created.  */
 
 int
-mips_can_use_return_insn ()
+mips_can_use_return_insn (void)
 {
   tree return_type;
 
@@ -7741,7 +7201,7 @@ mips_can_use_return_insn ()
      registers.  */
   if (TARGET_MIPS16
       && mips16_hard_float
-      && ! aggregate_value_p (return_type)
+      && ! aggregate_value_p (return_type, current_function_decl)
       && GET_MODE_CLASS (DECL_MODE (return_type)) == MODE_FLOAT
       && GET_MODE_SIZE (DECL_MODE (return_type)) <= UNITS_PER_FPVALUE)
     return 0;
@@ -7755,8 +7215,7 @@ mips_can_use_return_insn ()
 /* Returns nonzero if X contains a SYMBOL_REF.  */
 
 static int
-symbolic_expression_p (x)
-     rtx x;
+symbolic_expression_p (rtx x)
 {
   if (GET_CODE (x) == SYMBOL_REF)
     return 1;
@@ -7779,10 +7238,8 @@ symbolic_expression_p (x)
    mode MODE.  */
 
 static void
-mips_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align;
+mips_select_rtx_section (enum machine_mode mode, rtx x,
+			 unsigned HOST_WIDE_INT align)
 {
   if (TARGET_MIPS16)
     {
@@ -7822,10 +7279,8 @@ mips_select_rtx_section (mode, x, align)
    any relocatable expression.  */
 
 static void
-mips_select_section (decl, reloc, align)
-     tree decl;
-     int reloc;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+mips_select_section (tree decl, int reloc,
+		     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
   if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
       && TREE_CODE (decl) == STRING_CST
@@ -7835,8 +7290,11 @@ mips_select_section (decl, reloc, align)
        For mips16 code, put strings in the text section so that a PC
        relative load instruction can be used to get their address.  */
     text_section ();
-  else
+  else if (targetm.have_named_sections)
     default_elf_select_section (decl, reloc, align);
+  else
+    /* The native irix o32 assembler doesn't support named sections.  */
+    default_select_section (decl, reloc, align);
 }
 
 
@@ -7844,8 +7302,7 @@ mips_select_section (decl, reloc, align)
    access DECL using %gp_rel(...)($gp).  */
 
 static bool
-mips_in_small_data_p (decl)
-     tree decl;
+mips_in_small_data_p (tree decl)
 {
   HOST_WIDE_INT size;
 
@@ -7878,16 +7335,6 @@ mips_in_small_data_p (decl)
 	  && (!DECL_INITIAL (decl) || TREE_CONSTANT (DECL_INITIAL (decl))))
 	return false;
     }
-  else if (TARGET_MIPS16)
-    {
-      /* Alhough it seems strange to have separate rules for -mips16,
-	 this behaviour is long-standing.  */
-      if (TREE_PUBLIC (decl)
-	  && (DECL_COMMON (decl)
-	      || DECL_ONE_ONLY (decl)
-	      || DECL_WEAK (decl)))
-	return false;
-    }
 
   size = int_size_in_bytes (TREE_TYPE (decl));
   return (size > 0 && size <= mips_section_threshold);
@@ -7907,10 +7354,7 @@ mips_in_small_data_p (decl)
    should treat the symbol as SYMBOL_GOT_LOCAL.  */
 
 static void
-mips_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+mips_encode_section_info (tree decl, rtx rtl, int first)
 {
   rtx symbol;
 
@@ -7990,17 +7434,14 @@ mips_encode_section_info (decl, rtl, first)
 
   default_encode_section_info (decl, rtl, first);
 }
-
-
 
-/* Return register to use for a function return value with VALTYPE for
-   function FUNC.  MODE is used instead of VALTYPE for LIBCALLs.  */
+/* Implement FUNCTION_VALUE and LIBCALL_VALUE.  For normal calls,
+   VALTYPE is the return type and MODE is VOIDmode.  For libcalls,
+   VALTYPE is null and MODE is the mode of the return value.  */
 
 rtx
-mips_function_value (valtype, func, mode)
-     tree valtype;
-     tree func ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
+mips_function_value (tree valtype, tree func ATTRIBUTE_UNUSED,
+		     enum machine_mode mode)
 {
   int reg = GP_RETURN;
   enum mode_class mclass;
@@ -8123,31 +7564,13 @@ mips_function_value (valtype, func, mode)
    nonzero when an argument must be passed by reference.  */
 
 int
-function_arg_pass_by_reference (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg_pass_by_reference (const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
+				enum machine_mode mode, tree type,
+				int named ATTRIBUTE_UNUSED)
 {
   int size;
 
-  if (mips_abi == ABI_32 || mips_abi == ABI_O64)
-    return 0;
-
-  /* We must pass by reference if we would be both passing in registers
-     and the stack.  This is because any subsequent partial arg would be
-     handled incorrectly in this case.
-
-     ??? This is really a kludge.  We should either fix GCC so that such
-     a situation causes an abort and then do something in the MIPS port
-     to prevent it, or add code to function.c to properly handle the case.  */
-  /* ??? cum can be NULL when called from mips_va_arg.  The problem handled
-     here hopefully is not relevant to mips_va_arg.  */
-  if (cum && MUST_PASS_IN_STACK (mode, type)
-      && FUNCTION_ARG (*cum, mode, type, named) != 0)
-    return 1;
-
-  /* Otherwise, we only do this if EABI is selected.  */
+  /* The EABI is the only one to pass args by reference.  */
   if (mips_abi != ABI_EABI)
     return 0;
 
@@ -8177,9 +7600,8 @@ function_arg_pass_by_reference (cum, mode, type, named)
    mode to a 64-bit mode.  */
 
 bool
-mips_cannot_change_mode_class (from, to, class)
-     enum machine_mode from, to;
-     enum reg_class class;
+mips_cannot_change_mode_class (enum machine_mode from,
+			       enum machine_mode to, enum reg_class class)
 {
   if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
     {
@@ -8199,55 +7621,14 @@ mips_cannot_change_mode_class (from, to, class)
    NO_REGS means that no secondary register is required.  */
 
 enum reg_class
-mips_secondary_reload_class (class, mode, x, in_p)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx x;
-     int in_p;
+mips_secondary_reload_class (enum reg_class class,
+			     enum machine_mode mode, rtx x, int in_p)
 {
   enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
   int regno = -1;
   int gp_reg_p;
 
-  if (GET_CODE (x) == SIGN_EXTEND)
-    {
-      int off = 0;
-
-      x = XEXP (x, 0);
-
-      /* We may be called with reg_renumber NULL from regclass.
-	 ??? This is probably a bug.  */
-      if (reg_renumber)
-	regno = true_regnum (x);
-      else
-	{
-	  while (GET_CODE (x) == SUBREG)
-	    {
-	      off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
-					  GET_MODE (SUBREG_REG (x)),
-					  SUBREG_BYTE (x),
-					  GET_MODE (x));
-	      x = SUBREG_REG (x);
-	    }
-
-	  if (GET_CODE (x) == REG)
-	    regno = REGNO (x) + off;
-	}
-
-      /* 64-bit floating-point registers don't store 32-bit values
-	 in sign-extended form.  The only way we can reload
-	 (sign_extend:DI (reg:SI $f0)) is by moving $f0 into
-	 an integer register using a 32-bit move.  */
-      if (FP_REG_P (regno))
-	return (class == GR_REGS ? NO_REGS : GR_REGS);
-
-      /* For the same reason, we can only reload (sign_extend:DI FOO) into
-	 a floating-point register when FOO is an integer register. */
-      if (class == FP_REGS)
-	return (GP_REG_P (regno) ? NO_REGS : GR_REGS);
-    }
-
-  else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+  if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
     regno = true_regnum (x);
 
   gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
@@ -8354,16 +7735,14 @@ mips_secondary_reload_class (class, mode, x, in_p)
    since -msingle-float disallows multi-FPR values.  */
 
 int
-mips_class_max_nregs (class, mode)
-     enum reg_class class ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
+mips_class_max_nregs (enum reg_class class ATTRIBUTE_UNUSED,
+		      enum machine_mode mode)
 {
   return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
 }
 
 bool
-mips_valid_pointer_mode (mode)
-     enum machine_mode mode;
+mips_valid_pointer_mode (enum machine_mode mode)
 {
   return (mode == SImode || (TARGET_64BIT && mode == DImode));
 }
@@ -8374,7 +7753,7 @@ mips_valid_pointer_mode (mode)
    hold the $gp value.  */
 
 rtx
-mips16_gp_pseudo_reg ()
+mips16_gp_pseudo_reg (void)
 {
   if (cfun->machine->mips16_gp_pseudo_rtx == NULL_RTX)
     {
@@ -8416,10 +7795,7 @@ mips16_gp_pseudo_reg ()
    we are copying from the floating point registers.  */
 
 static void
-mips16_fp_args (file, fp_code, from_fp_p)
-     FILE *file;
-     int fp_code;
-     int from_fp_p;
+mips16_fp_args (FILE *file, int fp_code, int from_fp_p)
 {
   const char *s;
   int gparg, fparg;
@@ -8479,8 +7855,7 @@ mips16_fp_args (file, fp_code, from_fp_p)
    then jumps to the 16 bit code.  */
 
 static void
-build_mips16_function_stub (file)
-     FILE *file;
+build_mips16_function_stub (FILE *file)
 {
   const char *fnname;
   char *secname, *stubname;
@@ -8587,11 +7962,7 @@ static struct mips16_stub *mips16_stubs;
    value if it builds the call instruction itself.  */
 
 int
-build_mips16_call_stub (retval, fn, arg_size, fp_code)
-     rtx retval;
-     rtx fn;
-     rtx arg_size;
-     int fp_code;
+build_mips16_call_stub (rtx retval, rtx fn, rtx arg_size, int fp_code)
 {
   int fpret;
   const char *fnname;
@@ -8895,7 +8266,7 @@ build_mips16_call_stub (retval, fn, arg_size, fp_code)
    generated is correct, so we do not need to catch all cases.  */
 
 static void
-mips16_optimize_gp ()
+mips16_optimize_gp (void)
 {
   rtx gpcopy, slot, insn;
 
@@ -9112,10 +8483,7 @@ struct constant
 /* Add a constant to the list in *PCONSTANTS.  */
 
 static rtx
-add_constant (pconstants, val, mode)
-     struct constant **pconstants;
-     rtx val;
-     enum machine_mode mode;
+add_constant (struct constant **pconstants, rtx val, enum machine_mode mode)
 {
   struct constant *c;
 
@@ -9135,9 +8503,7 @@ add_constant (pconstants, val, mode)
 /* Dump out the constants in CONSTANTS after INSN.  */
 
 static void
-dump_constants (constants, insn)
-     struct constant *constants;
-     rtx insn;
+dump_constants (struct constant *constants, rtx insn)
 {
   struct constant *c;
   int align;
@@ -9210,8 +8576,7 @@ dump_constants (constants, insn)
 /* Find the symbol in an address expression.  */
 
 static rtx
-mips_find_symbol (addr)
-     rtx addr;
+mips_find_symbol (rtx addr)
 {
   if (GET_CODE (addr) == MEM)
     addr = XEXP (addr, 0);
@@ -9237,7 +8602,7 @@ mips_find_symbol (addr)
    PC relative loads that are out of range.  */
 
 static void
-mips16_lay_out_constants ()
+mips16_lay_out_constants (void)
 {
   int insns_len, max_internal_pool_size, pool_size, addr, first_constant_ref;
   rtx first, insn;
@@ -9446,9 +8811,8 @@ mips16_lay_out_constants ()
    LO_REG is an rtx for the LO register, used in dependence checking.  */
 
 static void
-mips_avoid_hazard (after, insn, hilo_delay, delayed_reg, lo_reg)
-     rtx after, insn, *delayed_reg, lo_reg;
-     int *hilo_delay;
+mips_avoid_hazard (rtx after, rtx insn, int *hilo_delay,
+		   rtx *delayed_reg, rtx lo_reg)
 {
   rtx pattern, set;
   int nops, ninsns;
@@ -9514,7 +8878,7 @@ mips_avoid_hazard (after, insn, hilo_delay, delayed_reg, lo_reg)
    .set nomacro.  */
 
 static void
-mips_avoid_hazards ()
+mips_avoid_hazards (void)
 {
   rtx insn, last_insn, lo_reg, delayed_reg;
   int hilo_delay, i;
@@ -9550,7 +8914,7 @@ mips_avoid_hazards ()
 /* Implement TARGET_MACHINE_DEPENDENT_REORG.  */
 
 static void
-mips_reorg ()
+mips_reorg (void)
 {
   if (TARGET_MIPS16)
     {
@@ -9599,9 +8963,8 @@ mips_reorg ()
    we need to use.  This gets pretty messy, but it is feasible.  */
 
 int
-mips_register_move_cost (mode, to, from)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     enum reg_class to, from;
+mips_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+			 enum reg_class to, enum reg_class from)
 {
   if (from == M16_REGS && GR_REG_CLASS_P (to))
     return 2;
@@ -9669,9 +9032,7 @@ mips_register_move_cost (mode, to, from)
    attributes in the machine-description file.  */
 
 int
-mips_adjust_insn_length (insn, length)
-     rtx insn;
-     int length;
+mips_adjust_insn_length (rtx insn, int length)
 {
   /* A unconditional jump has an unfilled delay slot if it is not part
      of a sequence.  A conditional jump normally has a delay slot, but
@@ -9709,7 +9070,7 @@ mips_adjust_insn_length (insn, length)
    of a label into $1.  */
 
 const char *
-mips_output_load_label ()
+mips_output_load_label (void)
 {
   if (TARGET_EXPLICIT_RELOCS)
     switch (mips_abi)
@@ -9750,18 +9111,8 @@ mips_output_load_label ()
    That tells us whether to generate a simple conditional branch, or a
    reversed conditional branch around a `jr' instruction.  */
 const char *
-mips_output_conditional_branch (insn,
-				operands,
-				two_operands_p,
-				float_p,
-				inverted_p,
-				length)
-     rtx insn;
-     rtx *operands;
-     int two_operands_p;
-     int float_p;
-     int inverted_p;
-     int length;
+mips_output_conditional_branch (rtx insn, rtx *operands, int two_operands_p,
+				int float_p, int inverted_p, int length)
 {
   static char buffer[200];
   /* The kind of comparison we are doing.  */
@@ -9949,95 +9300,6 @@ mips_output_conditional_branch (insn,
         return "";
       }
 
-    /* We do not currently use this code.  It handles jumps to
-       arbitrary locations, using `jr', even across a 256MB boundary.
-       We could add a -mhuge switch, and then use this code instead of
-       the `j' alternative above when -mhuge was used.  */
-#if 0
-    case 16:
-    case 20:
-      {
-	/* Generate a reversed conditional branch around a `jr'
-	   instruction:
-
-		 .set noreorder
-		 .set nomacro
-		 .set noat
-		 bc    l
-		 la    $at, target
-		 jr    $at
-		 .set at
-		 .set macro
-		 .set reorder
-	      l:
-
-	   Not pretty, but allows a conditional branch anywhere in the
-	   32-bit address space.  If the original branch is annulled,
-	   then the instruction in the delay slot should be executed
-	   only if the branch is taken.  The la instruction is really
-	   a macro which will usually take eight bytes, but sometimes
-	   takes only four, if the instruction to which we're jumping
-	   gets its own entry in the global pointer table, which will
-	   happen if its a case label.  The assembler will then
-	   generate only a four-byte sequence, rather than eight, and
-	   there seems to be no way to tell it not to.  Thus, we can't
-	   just use a `.+x' addressing form; we don't know what value
-	   to give for `x'.
-
-	   So, we resort to using the explicit relocation syntax
-	   available in the assembler and do:
-
-	      lw $at,%got_page(target)($gp)
-	      daddiu $at,$at,%got_ofst(target)
-
-	   That way, this always takes up eight bytes, and we can use
-	   the `.+x' form.  Of course, these explicit machinations
-	   with relocation will not work with old assemblers.  Then
-	   again, neither do out-of-range branches, so we haven't lost
-	   anything.  */
-
-	/* The target of the reversed branch.  */
-	const char *const target
-	  = ((mips_branch_likely || length == 20) ? ".+20" : ".+16");
-	const char *at_register = mips_reg_names[ASSEMBLER_SCRATCH_REGNUM];
-	const char *gp_register = mips_reg_names[PIC_OFFSET_TABLE_REGNUM];
-	char *c;
-
-	strcpy (buffer, "%(%<%[");
-	c = strchr (buffer, '\0');
-	/* Generate the reversed comparison.  This takes four
-	   bytes.  */
-	if (float_p)
-	  sprintf (c, "%%*b%s\t%%Z2%s",
-		   inverted_p ? comp : inverted_comp,
-		   target);
-	else
-	  sprintf (c, "%%*b%s%s\t%s%s,%s",
-		   inverted_p ? comp : inverted_comp,
-		   need_z_p ? "z" : "",
-		   op1,
-		   op2,
-		   target);
-	c = strchr (buffer, '\0');
-	/* Generate the load-address, and jump.  This takes twelve
-	   bytes, for a total of 16.  */
-	sprintf (c,
-		 "\n\tlw\t%s,%%%%got_page(%%1)(%s)\n\tdaddiu\t%s,%s,%%%%got_ofst(%%1)\n\tjr\t%s",
-		 at_register,
-		 gp_register,
-		 at_register,
-		 at_register,
-		 at_register);
-	if (length == 20)
-	  /* The delay slot was unfilled.  Since we're inside
-	     .noreorder, the assembler will not fill in the NOP for
-	     us, so we must do it ourselves.  */
-	  strcat (buffer, "\n\tnop");
-	strcat (buffer, "%]%>%)");
-	return buffer;
-      }
-#endif
-
     default:
       abort ();
     }
@@ -10052,9 +9314,7 @@ mips_output_conditional_branch (insn,
    operand 2 is zero.  Otherwise just return DIVISION itself.  */
 
 const char *
-mips_output_division (division, operands)
-     const char *division;
-     rtx *operands;
+mips_output_division (const char *division, rtx *operands)
 {
   if (TARGET_CHECK_ZERO_DIV)
     {
@@ -10074,8 +9334,7 @@ mips_output_division (division, operands)
    Note: this function is shared between GCC and GAS.  */
 
 static bool
-mips_strict_matching_cpu_name_p (canonical, given)
-     const char *canonical, *given;
+mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
 {
   while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
     given++, canonical++;
@@ -10091,8 +9350,7 @@ mips_strict_matching_cpu_name_p (canonical, given)
    Note: this function is shared between GCC and GAS.  */
 
 static bool
-mips_matching_cpu_name_p (canonical, given)
-     const char *canonical, *given;
+mips_matching_cpu_name_p (const char *canonical, const char *given)
 {
   /* First see if the name matches exactly, or with a final "000"
      turned into "k".  */
@@ -10127,8 +9385,7 @@ mips_matching_cpu_name_p (canonical, given)
    A similar function exists in GAS.  */
 
 static const struct mips_cpu_info *
-mips_parse_cpu (option, cpu_string)
-     const char *option, *cpu_string;
+mips_parse_cpu (const char *option, const char *cpu_string)
 {
   const struct mips_cpu_info *p;
   const char *s;
@@ -10169,8 +9426,7 @@ mips_parse_cpu (option, cpu_string)
    if the ISA isn't valid.  */
 
 static const struct mips_cpu_info *
-mips_cpu_info_from_isa (isa)
-     int isa;
+mips_cpu_info_from_isa (int isa)
 {
   const struct mips_cpu_info *p;
 
@@ -10187,21 +9443,19 @@ mips_cpu_info_from_isa (isa)
 
    On the MIPS, ignore the cost of anti- and output-dependencies.  */
 static int
-mips_adjust_cost (insn, link, dep, cost)
-     rtx insn ATTRIBUTE_UNUSED;
-     rtx link;
-     rtx dep ATTRIBUTE_UNUSED;
-     int cost;
+mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED, rtx link,
+		  rtx dep ATTRIBUTE_UNUSED, int cost)
 {
   if (REG_NOTE_KIND (link) != 0)
     return 0;	/* Anti or output dependence.  */
   return cost;
 }
 
+/* Implement HARD_REGNO_NREGS.  The size of FP registers are controlled
+   by UNITS_PER_FPREG.  All other registers are word sized.  */
+
 unsigned int
-mips_hard_regno_nregs (regno, mode)
-    int regno;
-    enum machine_mode mode;
+mips_hard_regno_nregs (int regno, enum machine_mode mode)
 {
   if (! FP_REG_P (regno))
     return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
@@ -10209,15 +9463,15 @@ mips_hard_regno_nregs (regno, mode)
     return ((GET_MODE_SIZE (mode) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG);
 }
 
+/* Implement RETURN_IN_MEMORY.  Under the old (i.e., 32 and O64 ABIs)
+   all BLKmode objects are returned in memory.  Under the new (N32 and
+   64-bit MIPS ABIs) small structures are returned in a register.
+   Objects with varying size must still be returned in memory, of
+   course.  */
+
 int
-mips_return_in_memory (type)
-     tree type;
+mips_return_in_memory (tree type)
 {
-  /* Under the old (i.e., 32 and O64 ABIs) all BLKmode objects are
-     returned in memory.  Under the new (N32 and 64-bit MIPS ABIs) small
-     structures are returned in a register.  Objects with varying size
-     must still be returned in memory, of course.  */
-
   if (mips_abi == ABI_32 || mips_abi == ABI_O64)
     return (TYPE_MODE (type) == BLKmode);
   else
@@ -10226,13 +9480,15 @@ mips_return_in_memory (type)
 }
 
 static int
-mips_issue_rate ()
+mips_issue_rate (void)
 {
   switch (mips_tune)
     {
-    case PROCESSOR_R3000: return 1;
-    case PROCESSOR_R5400: return 2;
-    case PROCESSOR_R5500: return 2;
+    case PROCESSOR_R5400:
+    case PROCESSOR_R5500:
+    case PROCESSOR_R7000:
+    case PROCESSOR_R9000:
+      return 2;
 
     default:
       return 1;
@@ -10246,12 +9502,14 @@ mips_issue_rate ()
    processors that have a DFA pipeline description.  */
 
 static int
-mips_use_dfa_pipeline_interface ()
+mips_use_dfa_pipeline_interface (void)
 {
   switch (mips_tune)
     {
     case PROCESSOR_R5400:
     case PROCESSOR_R5500:
+    case PROCESSOR_R7000:
+    case PROCESSOR_R9000:
     case PROCESSOR_SR71000:
       return true;
 
@@ -10262,33 +9520,32 @@ mips_use_dfa_pipeline_interface ()
 
 
 const char *
-mips_emit_prefetch (operands)
-     rtx operands[];
+mips_emit_prefetch (rtx *operands)
 {
- /* For the mips32/64 architectures the hint fields are arranged
-    by operation (load/store) and locality (normal/streamed/retained).
-    Irritatingly, numbers 2 and 3 are reserved leaving no simple
-    algorithm for figuring the hint.  */
+  /* For the mips32/64 architectures the hint fields are arranged
+     by operation (load/store) and locality (normal/streamed/retained).
+     Irritatingly, numbers 2 and 3 are reserved leaving no simple
+     algorithm for figuring the hint.  */
 
-    int write = INTVAL (operands[1]);
-    int locality = INTVAL (operands[2]);
+  int write = INTVAL (operands[1]);
+  int locality = INTVAL (operands[2]);
 
-    static const char * const alt[2][4] = {
-	{
-	 "pref\t4,%a0",
-	 "pref\t0,%a0",
-	 "pref\t0,%a0",
-	 "pref\t6,%a0"
-	},
-	{
-	 "pref\t5,%a0",
-	 "pref\t1,%a0",
-	 "pref\t1,%a0",
-	 "pref\t7,%a0"
-	}
-    };
+  static const char * const alt[2][4] = {
+    {
+      "pref\t4,%a0",
+      "pref\t0,%a0",
+      "pref\t0,%a0",
+      "pref\t6,%a0"
+    },
+    {
+      "pref\t5,%a0",
+      "pref\t1,%a0",
+      "pref\t1,%a0",
+      "pref\t7,%a0"
+    }
+  };
 
-    return alt[write][locality];
+  return alt[write][locality];
 }
 
 
@@ -10297,10 +9554,8 @@ mips_emit_prefetch (operands)
 /* Output assembly to switch to section NAME with attribute FLAGS.  */
 
 static void
-iris6_asm_named_section_1 (name, flags, align)
-     const char *name;
-     unsigned int flags;
-     unsigned int align;
+iris6_asm_named_section_1 (const char *name, unsigned int flags,
+			   unsigned int align)
 {
   unsigned int sh_type, sh_flags, sh_entsize;
 
@@ -10332,9 +9587,7 @@ iris6_asm_named_section_1 (name, flags, align)
 }
 
 static void
-iris6_asm_named_section (name, flags)
-     const char *name;
-     unsigned int flags;
+iris6_asm_named_section (const char *name, unsigned int flags)
 {
   iris6_asm_named_section_1 (name, flags, 0);
 }
@@ -10353,9 +9606,7 @@ static htab_t iris_section_align_htab;
 static FILE *iris_orig_asm_out_file;
 
 static int
-iris_section_align_entry_eq (p1, p2)
-     const void *p1;
-     const void *p2;
+iris_section_align_entry_eq (const void *p1, const void *p2)
 {
   const struct iris_section_align_entry *old = p1;
   const char *new = p2;
@@ -10364,17 +9615,14 @@ iris_section_align_entry_eq (p1, p2)
 }
 
 static hashval_t
-iris_section_align_entry_hash (p)
-     const void *p;
+iris_section_align_entry_hash (const void *p)
 {
   const struct iris_section_align_entry *old = p;
   return htab_hash_string (old->name);
 }
 
 void
-iris6_asm_output_align (file, log)
-     FILE *file;
-     unsigned int log;
+iris6_asm_output_align (FILE *file, unsigned int log)
 {
   const char *section = current_section_name ();
   struct iris_section_align_entry **slot, *entry;
@@ -10407,7 +9655,7 @@ iris6_asm_output_align (file, log)
    beginning of the file with the proper alignment attached.  */
 
 static void
-iris6_file_start ()
+iris6_file_start (void)
 {
   mips_file_start ();
 
@@ -10419,9 +9667,7 @@ iris6_file_start ()
 }
 
 static int
-iris6_section_align_1 (slot, data)
-     void **slot;
-     void *data ATTRIBUTE_UNUSED;
+iris6_section_align_1 (void **slot, void *data ATTRIBUTE_UNUSED)
 {
   const struct iris_section_align_entry *entry
     = *(const struct iris_section_align_entry **) slot;
@@ -10431,8 +9677,7 @@ iris6_section_align_1 (slot, data)
 }
 
 static void
-copy_file_data (to, from)
-     FILE *to, *from;
+copy_file_data (FILE *to, FILE *from)
 {
   char buffer[8192];
   size_t len;
@@ -10452,7 +9697,7 @@ copy_file_data (to, from)
 }
 
 static void
-iris6_file_end ()
+iris6_file_end (void)
 {
   /* Emit section directives with the proper alignment at the top of the
      real output file.  */
@@ -10472,10 +9717,7 @@ iris6_file_end ()
    default code.  */
 
 static unsigned int
-iris6_section_type_flags (decl, section, relocs_p)
-     tree decl;
-     const char *section;
-     int relocs_p;
+iris6_section_type_flags (tree decl, const char *section, int relocs_p)
 {
   unsigned int flags;
 
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 2193f98e04b..b72399ee02c 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -26,8 +26,6 @@ Boston, MA 02111-1307, USA.  */
 
 /* Standard GCC variables that we reference.  */
 
-extern char	call_used_regs[];
-extern int	may_call_alloca;
 extern int	target_flags;
 
 /* MIPS external variables defined in mips.c.  */
@@ -65,14 +63,13 @@ enum processor_type {
   PROCESSOR_R5000,
   PROCESSOR_R5400,
   PROCESSOR_R5500,
+  PROCESSOR_R7000,
   PROCESSOR_R8000,
+  PROCESSOR_R9000,
   PROCESSOR_SB1,
   PROCESSOR_SR71000
 };
 
-/* Recast the cpu class to be the cpu attribute.  */
-#define mips_cpu_attr ((enum attr_cpu)mips_tune)
-
 /* Which ABI to use.  ABI_32 (original 32, or o32), ABI_N32 (n32),
    ABI_64 (n64) are all defined by SGI.  ABI_O64 is o32 extended
    to work on a 64 bit machine.  */
@@ -83,16 +80,6 @@ enum processor_type {
 #define ABI_EABI 3
 #define ABI_O64  4
 
-/* Whether to emit abicalls code sequences or not.  */
-
-enum mips_abicalls_type {
-  MIPS_ABICALLS_NO,
-  MIPS_ABICALLS_YES
-};
-
-/* Recast the abicalls class to be the abicalls attribute.  */
-#define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
-
 /* Information about one recognized processor.  Defined here for the
    benefit of TARGET_CPU_CPP_BUILTINS.  */
 struct mips_cpu_info {
@@ -114,11 +101,6 @@ extern char mips_reg_names[][8];	/* register names (a0 vs. $4).  */
 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
 extern const char *current_function_file; /* filename current function is in */
 extern int num_source_filenames;	/* current .file # */
-extern int inside_function;		/* != 0 if inside of a function */
-extern int ignore_line_number;		/* != 0 if we are to ignore next .loc */
-extern int file_in_function_warning;	/* warning given about .file in func */
-extern int sdb_label_count;		/* block start/end next label # */
-extern int sdb_begin_function_line;     /* Starting Line of current function */
 extern int mips_section_threshold;	/* # bytes of data/sdata cutoff */
 extern int sym_lineno;			/* sgi next label # for each stmt */
 extern int set_noreorder;		/* # of nested .set noreorder's  */
@@ -131,9 +113,8 @@ extern GTY(()) rtx branch_cmp[2];	/* operands for compare */
 extern enum cmp_type branch_type;	/* what type of branch to use */
 extern enum processor_type mips_arch;   /* which cpu to codegen for */
 extern enum processor_type mips_tune;   /* which cpu to schedule for */
-extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
 extern int mips_isa;			/* architectural level */
-extern int mips16;			/* whether generating mips16 code */
+extern int mips_abi;			/* which ABI to use */
 extern int mips16_hard_float;		/* mips16 without -msoft-float */
 extern int mips_entry;			/* generate entry/exit for mips16 */
 extern const char *mips_arch_string;    /* for -march=<xxx> */
@@ -141,7 +122,6 @@ extern const char *mips_tune_string;    /* for -mtune=<xxx> */
 extern const char *mips_isa_string;	/* for -mips{1,2,3,4} */
 extern const char *mips_abi_string;	/* for -mabi={32,n32,64} */
 extern const char *mips_entry_string;	/* for -mentry */
-extern const char *mips_no_mips16_string;/* for -mno-mips16 */
 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
 extern int mips_string_length;		/* length of strings for mips16 */
 extern const struct mips_cpu_info mips_cpu_info_table[];
@@ -173,7 +153,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define MASK_SOFT_FLOAT	   0x00000100	/* software floating point */
 #define MASK_FLOAT64	   0x00000200	/* fp registers are 64 bits */
 #define MASK_ABICALLS	   0x00000400	/* emit .abicalls/.cprestore/.cpload */
-#define MASK_UNUSED1	   0x00000800	/* Unused Mask.  */
+#define MASK_XGOT	   0x00000800	/* emit big-got PIC */
 #define MASK_LONG_CALLS	   0x00001000	/* Always call through a register */
 #define MASK_64BIT	   0x00002000	/* Use 64 bit GP registers and insns */
 #define MASK_EMBEDDED_PIC  0x00004000	/* Generate embedded PIC code */
@@ -190,6 +170,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define MASK_UNINIT_CONST_IN_RODATA \
 			   0x00800000	/* Store uninitialized
 					   consts in rodata */
+#define MASK_FIX_SB1       0x01000000   /* Work around SB-1 errata. */
 
 					/* Debug switches, not documented */
 #define MASK_DEBUG	0		/* unused */
@@ -237,6 +218,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 
 					/* .abicalls, etc from Pyramid V.4 */
 #define TARGET_ABICALLS		(target_flags & MASK_ABICALLS)
+#define TARGET_XGOT		(target_flags & MASK_XGOT)
 
 					/* software floating point */
 #define TARGET_SOFT_FLOAT	(target_flags & MASK_SOFT_FLOAT)
@@ -275,6 +257,7 @@ extern const struct mips_cpu_info *mips_tune_info;
 
 #define TARGET_BRANCHLIKELY	(target_flags & MASK_BRANCHLIKELY)
 
+#define TARGET_FIX_SB1		(target_flags & MASK_FIX_SB1)
 
 /* True if we should use NewABI-style relocation operators for
    symbolic addresses.  This is never true for mips16 code,
@@ -334,6 +317,8 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TARGET_MIPS5KC              (mips_arch == PROCESSOR_5KC)
 #define TARGET_MIPS5400             (mips_arch == PROCESSOR_R5400)
 #define TARGET_MIPS5500             (mips_arch == PROCESSOR_R5500)
+#define TARGET_MIPS7000             (mips_arch == PROCESSOR_R7000)
+#define TARGET_MIPS9000             (mips_arch == PROCESSOR_R9000)
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
 
@@ -345,6 +330,8 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define TUNE_MIPS5400               (mips_tune == PROCESSOR_R5400)
 #define TUNE_MIPS5500               (mips_tune == PROCESSOR_R5500)
 #define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)
+#define TUNE_MIPS7000               (mips_tune == PROCESSOR_R7000)
+#define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1)
 #define TUNE_SR71K                  (mips_tune == PROCESSOR_SR71000)
 
@@ -380,7 +367,7 @@ extern const struct mips_cpu_info *mips_tune_info;
       /* We do this here because __mips is defined below	\
 	 and so we can't use builtin_define_std.  */		\
       if (!flag_iso)						\
-	  builtin_define ("mips");				\
+	builtin_define ("mips");				\
 								\
       /* Treat _R3000 and _R4000 like register-size defines,	\
 	 which is how they've historically been used.  */	\
@@ -396,12 +383,12 @@ extern const struct mips_cpu_info *mips_tune_info;
 	  builtin_define ("_R3000");				\
 	}							\
       if (TARGET_FLOAT64)					\
-	  builtin_define ("__mips_fpr=64");			\
+	builtin_define ("__mips_fpr=64");			\
       else							\
-	  builtin_define ("__mips_fpr=32");			\
+	builtin_define ("__mips_fpr=32");			\
 								\
       if (TARGET_MIPS16)					\
-	  builtin_define ("__mips16");				\
+	builtin_define ("__mips16");				\
 								\
       MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info);	\
       MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info);	\
@@ -446,12 +433,12 @@ extern const struct mips_cpu_info *mips_tune_info;
 	}							\
 								\
       if (TARGET_HARD_FLOAT)					\
-	  builtin_define ("__mips_hard_float");			\
+	builtin_define ("__mips_hard_float");			\
       else if (TARGET_SOFT_FLOAT)				\
-	  builtin_define ("__mips_soft_float");			\
+	builtin_define ("__mips_soft_float");			\
 								\
       if (TARGET_SINGLE_FLOAT)					\
-	  builtin_define ("__mips_single_float");		\
+	builtin_define ("__mips_single_float");		\
 								\
       if (TARGET_BIG_ENDIAN)					\
 	{							\
@@ -528,9 +515,9 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("Use GP relative sdata/sbss sections (now ignored)")},		\
   {"gpopt",		  0,						\
      N_("Use GP relative sdata/sbss sections (now ignored)")},		\
-  {"no-gpOPT",		  0,					\
+  {"no-gpOPT",		  0,					        \
      N_("Don't use GP relative sdata/sbss sections (now ignored)")},	\
-  {"no-gpopt",		  0,					\
+  {"no-gpopt",		  0,					        \
      N_("Don't use GP relative sdata/sbss sections (now ignored)")},	\
   {"stats",		  0,						\
      N_("Output compiler statistics (now ignored)")},			\
@@ -596,6 +583,10 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("Work around early 4300 hardware bug")},			\
   {"no-fix4300",         -MASK_4300_MUL_FIX,				\
      N_("Don't work around early 4300 hardware bug")},			\
+  {"fix-sb1",             MASK_FIX_SB1,					\
+     N_("Work around errata for early SB-1 revision 2 cores")},		\
+  {"no-fix-sb1",         -MASK_FIX_SB1,					\
+     N_("Don't work around errata for early SB-1 revision 2 cores")},	\
   {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV,			\
      N_("Trap on integer divide by zero")},				\
   {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV,			\
@@ -608,6 +599,14 @@ extern const struct mips_cpu_info *mips_tune_info;
      N_("Use NewABI-style %reloc() assembly operators")},		\
   {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS,				\
      N_("Use assembler macros instead of relocation operators")},	\
+  {"ips16",		  MASK_MIPS16,					\
+     N_("Generate mips16 code") },					\
+  {"no-mips16",		 -MASK_MIPS16,					\
+     N_("Generate normal-mode code") },					\
+  {"xgot",		  MASK_XGOT,					\
+     N_("Lift restrictions on GOT size") },				\
+  {"no-xgot",		 -MASK_XGOT,					\
+     N_("Do not lift restrictions on GOT size") },			\
   {"debug",		  MASK_DEBUG,					\
      NULL},								\
   {"debuga",		  MASK_DEBUG_A,					\
@@ -734,8 +733,6 @@ extern const struct mips_cpu_info *mips_tune_info;
       N_("Specify a Standard MIPS ISA"), 0},				\
   { "entry",	&mips_entry_string,					\
       N_("Use mips16 entry/exit psuedo ops"), 0},			\
-  { "no-mips16", &mips_no_mips16_string,				\
-      N_("Don't use MIPS16 instructions"), 0},				\
   { "no-flush-func", &mips_cache_flush_func,				\
       N_("Don't call any cache flush functions"), 0},			\
   { "flush-func=", &mips_cache_flush_func,				\
@@ -767,6 +764,8 @@ extern const struct mips_cpu_info *mips_tune_info;
 #define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
                                   || TARGET_MIPS5400                    \
                                   || TARGET_MIPS5500                    \
+                                  || TARGET_MIPS7000                    \
+                                  || TARGET_MIPS9000                    \
                                   || ISA_MIPS32	                        \
                                   || ISA_MIPS32R2                       \
                                   || ISA_MIPS64)                        \
@@ -936,35 +935,13 @@ extern const struct mips_cpu_info *mips_tune_info;
    which write to the HI and LO registers.  Most targets require a
    two-instruction gap.  */
 #define ISA_HAS_HILO_INTERLOCKS	(TARGET_MIPS5500 || TARGET_SB1)
-
-/* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
-   -mips2 sets -mfp32 and -mgp32.  This can be overridden by an explicit
-   -mfp32, -mfp64, -mgp32 or -mgp64.  -mfp64 sets MASK_FLOAT64 in
-   target_flags, and -mgp64 sets MASK_64BIT.
-
-   Setting MASK_64BIT in target_flags will cause gcc to assume that
-   registers are 64 bits wide.  int, long and void * will be 32 bit;
-   this may be changed with -mint64 or -mlong64.
-
-   The gen* programs link code that refers to MASK_64BIT.  They don't
-   actually use the information in target_flags; they just refer to
-   it.  */
 
-/* Switch  Recognition by gcc.c.  Add -G xx support */
+/* Add -G xx support.  */
 
 #undef  SWITCH_TAKES_ARG
 #define SWITCH_TAKES_ARG(CHAR)						\
   (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
 
-/* Sometimes certain combinations of command options do not make sense
-   on a particular target machine.  You can define a macro
-   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
-   defined, is executed once just after all the command options have
-   been parsed.
-
-   On the MIPS, it is used to handle -G.  We also use it to set up all
-   of the tables referenced in the other macros.  */
-
 #define OVERRIDE_OPTIONS override_options ()
 
 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
@@ -1002,8 +979,6 @@ extern const struct mips_cpu_info *mips_tune_info;
 
 #define SUBTARGET_TARGET_SWITCHES
 
-extern int mips_abi;
-
 #ifndef MIPS_ABI_DEFAULT
 #define MIPS_ABI_DEFAULT ABI_32
 #endif
@@ -1112,49 +1087,10 @@ extern int mips_abi;
 %{membedded-pic} \
 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
-%{mgp32} %{mgp64} %{march=*} \
+%{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
 %(target_asm_spec) \
 %(subtarget_asm_spec)"
 
-/* Specify to run a post-processor, mips-tfile after the assembler
-   has run to stuff the mips debug information into the object file.
-   This is needed because the $#!%^ MIPS assembler provides no way
-   of specifying such information in the assembly file.  If we are
-   cross compiling, disable mips-tfile unless the user specifies
-   -mmips-tfile.  */
-
-#ifndef ASM_FINAL_SPEC
-#if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
-/* GAS */
-#define ASM_FINAL_SPEC "\
-%{mmips-as: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#else
-/* not GAS */
-#define ASM_FINAL_SPEC "\
-%{!mgas: %{!mno-mips-tfile: \
-	\n mips-tfile %{v*: -v} \
-		%{K: -I %b.o~} \
-		%{!K: %{save-temps: -I %b.o~}} \
-		%{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
-		%{.s:%i} %{!.s:%g.s}}}"
-
-#endif
-#endif	/* ASM_FINAL_SPEC */
-
-/* Redefinition of libraries used.  Mips doesn't support normal
-   UNIX style profiling via calling _mcount.  It does offer
-   profiling that samples the PC, so do what we can...  */
-
-#ifndef LIB_SPEC
-#define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
-#endif
-
 /* Extra switches sometimes passed to the linker.  */
 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
   will interpret it as a -b option.  */
@@ -1176,9 +1112,6 @@ extern int mips_abi;
 #endif
 
 /* CC1_SPEC is the set of arguments to pass to the compiler proper.  */
-/* Note, we will need to adjust the following if we ever find a MIPS variant
-   that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
-   that show up in this case.  */
 
 #ifndef CC1_SPEC
 #define CC1_SPEC "\
@@ -1239,32 +1172,9 @@ extern int mips_abi;
 #endif
 
 
-/* Print subsidiary information on the compiler version in use.  */
-
-#define MIPS_VERSION "[AL 1.1, MM 40]"
-
-#ifndef MACHINE_TYPE
-#define MACHINE_TYPE "BSD Mips"
-#endif
-
-#ifndef TARGET_VERSION_INTERNAL
-#define TARGET_VERSION_INTERNAL(STREAM)					\
-  fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
-#endif
-
-#ifndef TARGET_VERSION
-#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
-#endif
-
-
-#define SDB_DEBUGGING_INFO 1		/* generate info for mips-tfile */
 #define DBX_DEBUGGING_INFO 1		/* generate stabs (OSF/rose) */
 #define MIPS_DEBUGGING_INFO 1		/* MIPS specific debugging info */
 
-#ifndef PREFERRED_DEBUGGING_TYPE	/* assume SDB_DEBUGGING_INFO */
-#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
-#endif
-
 /* By default, turn on GDB extensions.  */
 #define DEFAULT_GDB_EXTENSIONS 1
 
@@ -1292,12 +1202,6 @@ extern int mips_abi;
 #define USER_LABEL_PREFIX	""
 #endif
 
-/* Forward references to tags are allowed.  */
-#define SDB_ALLOW_FORWARD_REFERENCES
-
-/* Unknown tags are also allowed.  */
-#define SDB_ALLOW_UNKNOWN_REFERENCES
-
 /* On Sun 4, this limit is 2048.  We use 1500 to be safe,
    since the length can run past this up to a continuation point.  */
 #undef DBX_CONTIN_LENGTH
@@ -1306,10 +1210,7 @@ extern int mips_abi;
 /* How to renumber registers for dbx and gdb.  */
 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
 
-/* The mapping from gcc register number to DWARF 2 CFA column number.
-   This mapping does not allow for tracking register 0, since SGI's broken
-   dwarf reader thinks column 0 is used for the frame address, but since
-   register 0 is fixed this is not a problem.  */
+/* The mapping from gcc register number to DWARF 2 CFA column number.  */
 #define DWARF_FRAME_REGNUM(REG)				\
   (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
 
@@ -1320,7 +1221,9 @@ extern int mips_abi;
 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
 
 /* Describe how we implement __builtin_eh_return.  */
-#define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
+#define EH_RETURN_DATA_REGNO(N) \
+  ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
+
 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
 
 /* Offsets recorded in opcodes are a multiple of this alignment factor.
@@ -1330,60 +1233,6 @@ extern int mips_abi;
 
 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
 
-#define PUT_SDB_DEF(a)					\
-do {							\
-  fprintf (asm_out_file, "\t%s.def\t",			\
-	   (TARGET_GAS) ? "" : "#");			\
-  ASM_OUTPUT_LABELREF (asm_out_file, a); 		\
-  fputc (';', asm_out_file);				\
-} while (0)
-
-#define PUT_SDB_PLAIN_DEF(a)				\
-do {							\
-  fprintf (asm_out_file, "\t%s.def\t.%s;",		\
-	   (TARGET_GAS) ? "" : "#", (a));		\
-} while (0)
-
-/* For block start and end, we create labels, so that
-   later we can figure out where the correct offset is.
-   The normal .ent/.end serve well enough for functions,
-   so those are just commented out.  */
-
-#define PUT_SDB_BLOCK_START(LINE)			\
-do {							\
-  fprintf (asm_out_file,				\
-	   "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",		\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_BLOCK_END(LINE)				\
-do {							\
-  fprintf (asm_out_file,				\
-	   "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",		\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (TARGET_GAS) ? "" : "#",			\
-	   LOCAL_LABEL_PREFIX,				\
-	   sdb_label_count,				\
-	   (LINE));					\
-  sdb_label_count++;					\
-} while (0)
-
-#define PUT_SDB_FUNCTION_START(LINE)
-
-#define PUT_SDB_FUNCTION_END(LINE)			\
-do {							\
-  ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line, 0); \
-} while (0)
-
-#define PUT_SDB_EPILOGUE_END(NAME)
-
 /* Correct the offset of automatic variables and arguments.  Note that
    the MIPS debug format wants all automatic variables and arguments
    to be in terms of the virtual frame pointer (stack pointer before
@@ -1395,22 +1244,11 @@ do {							\
   mips_debugger_offset (X, (HOST_WIDE_INT) 0)
 #define DEBUGGER_ARG_OFFSET(OFFSET, X)			\
   mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
-
-/* Tell collect that the object format is ECOFF */
-#define OBJECT_FORMAT_COFF	/* Object file looks like COFF */
-#define EXTENDED_COFF		/* ECOFF, not normal coff */
 
 /* Target machine storage layout */
 
-/* Define this if most significant bit is lowest numbered
-   in instructions that operate on numbered bit-fields.
-*/
 #define BITS_BIG_ENDIAN 0
-
-/* Define this if most significant byte of a word is the lowest numbered.  */
 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
-
-/* Define this if most significant word of a multiword number is the lowest.  */
 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
 
 /* Define this to set the endianness to use in libgcc2.c, which can
@@ -1446,11 +1284,6 @@ do {							\
 /* The number of bytes in a double.  */
 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
 
-/* A C expression for the size in bits of the type `int' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
-
 /* Tell the preprocessor the maximum size of wchar_t.  */
 #ifndef MAX_WCHAR_TYPE_SIZE
 #ifndef WCHAR_TYPE_SIZE
@@ -1458,36 +1291,16 @@ do {							\
 #endif
 #endif
 
-/* A C expression for the size in bits of the type `short' on the
-   target machine.  If you don't define this, the default is half a
-   word.  (If this would be less than one storage unit, it is
-   rounded up to one unit.)  */
+/* Set the sizes of the core types.  */
 #define SHORT_TYPE_SIZE 16
-
-/* A C expression for the size in bits of the type `long' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
+#define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
-#define MAX_LONG_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long long' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
 #define LONG_LONG_TYPE_SIZE 64
 
-/* A C expression for the size in bits of the type `float' on the
-   target machine.  If you don't define this, the default is one
-   word.  */
-#define FLOAT_TYPE_SIZE 32
+#define MAX_LONG_TYPE_SIZE 64
 
-/* A C expression for the size in bits of the type `double' on the
-   target machine.  If you don't define this, the default is two
-   words.  */
+#define FLOAT_TYPE_SIZE 32
 #define DOUBLE_TYPE_SIZE 64
-
-/* A C expression for the size in bits of the type `long double' on
-   the target machine.  If you don't define this, the default is two
-   words.  */
 #define LONG_DOUBLE_TYPE_SIZE \
   (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
 
@@ -1530,8 +1343,7 @@ do {							\
 /* There is no point aligning anything to a rounder boundary than this.  */
 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
 
-/* Set this nonzero if move instructions will actually fail to work
-   when given unaligned data.  */
+/* All accesses must be aligned.  */
 #define STRICT_ALIGNMENT 1
 
 /* Define this if you wish to imitate the way many other C compilers
@@ -1592,27 +1404,18 @@ do {							\
 	|| TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 
 
-/* Force right-alignment for small varargs in 32 bit little_endian mode */
-
-#define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
-
-/* Define this macro if an argument declared as `char' or `short' in a
-   prototype should actually be passed as an `int'.  In addition to
-   avoiding errors in certain cases of mismatch, it also makes for
-   better code on certain machines.  */
+#define PAD_VARARGS_DOWN \
+  (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
 
+/* Arguments declared as 'char' or 'short' in a prototype should be
+   passed as 'int's.  */
 #define PROMOTE_PROTOTYPES 1
 
 /* Define if operations between registers always perform the operation
    on the full register even if a narrower mode is specified.  */
 #define WORD_REGISTER_OPERATIONS
 
-/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
-   will either zero-extend or sign-extend.  The value of this macro should
-   be the code that says which one of the two operations is implicitly
-   done, NIL if none.
-
-   When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
+/* When in 64 bit mode, move insns will sign extend SImode and CCmode
    moves.  All other references are zero extended.  */
 #define LOAD_EXTEND_OP(MODE) \
   (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
@@ -1647,26 +1450,22 @@ do {							\
 
 /* Standard register usage.  */
 
-/* Number of actual hardware registers.
-   The hardware registers are assigned numbers for the compiler
-   from 0 to just below FIRST_PSEUDO_REGISTER.
-   All registers that the compiler knows about must be given numbers,
-   even those that are not normally considered general registers.
+/* Number of hardware registers.  We have:
 
-   On the Mips, we have 32 integer registers, 32 floating point
-   registers, 8 condition code registers, and the special registers
-   hi and lo.  After that we have 32 COP0 registers, 32 COP2 registers,
-   and 32 COP3 registers.  (COP1 is the floating-point processor.)
-   The 8 condition code registers are only used if mips_isa >= 4.  */
+   - 32 integer registers
+   - 32 floating point registers
+   - 8 condition code registers
+   - 2 accumulator registers (hi and lo)
+   - 32 registers each for coprocessors 0, 2 and 3
+   - 6 dummy entries that were used at various times in the past.  */
 
 #define FIRST_PSEUDO_REGISTER 176
 
-/* 1 for registers that have pervasive standard uses
-   and are not available for the register allocator.
-
-   On the MIPS, see conventions, page D-2  */
+/* By default, fix the kernel registers ($26 and $27), the global
+   pointer ($28) and the stack pointer ($29).  This can change
+   depending on the command-line options.
 
-/* Regarding coprocessor registers: without evidence to the contrary,
+   Regarding coprocessor registers: without evidence to the contrary,
    it's best to assume that each coprocessor register has a unique
    use.  This can be overridden, in, e.g., override_options() or
    CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
@@ -1691,8 +1490,10 @@ do {							\
 }
 
 
-/* Don't mark $31 as a call-clobbered register.  The idea is that
-   it's really the call instructions themselves which clobber $31.
+/* Set up this array for o32 by default.
+
+   Note that we don't mark $31 as a call-clobbered register.  The idea is
+   that it's really the call instructions themselves which clobber $31.
    We don't care what the called function does with it afterwards.
 
    This approach makes it easier to implement sibcalls.  Unlike normal
@@ -1718,14 +1519,8 @@ do {							\
   1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1			\
 }
 
-/* Like `CALL_USED_REGISTERS' but used to overcome a historical
-   problem which makes CALL_USED_REGISTERS *always* include
-   all the FIXED_REGISTERS.  Until this problem has been
-   resolved this macro can be used to overcome this situation.
-   In particular, block_propagate() requires this list
-   be accurate, or we can remove registers which should be live.
-   This macro is used in regs_invalidated_by_call.  */
 
+/* Define this since $28, though fixed, is call-saved in many ABIs.  */
 
 #define CALL_REALLY_USED_REGISTERS                                      \
 { /* General registers.  */                                             \
@@ -1790,8 +1585,8 @@ do {							\
 #define HI_REGNUM	(MD_REG_FIRST + 0)
 #define LO_REGNUM	(MD_REG_FIRST + 1)
 
-/* FPSW_REGNUM is the single condition code used if mips_isa < 4.  If
-   mips_isa >= 4, it should not be used, and an arbitrary ST_REG
+/* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
+   If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
    should be used instead.  */
 #define FPSW_REGNUM	ST_REG_FIRST
 
@@ -1822,24 +1617,10 @@ do {							\
   (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2'			\
    : COP3_REG_P (REGNO) ? '3' : '?')
 
-/* Return number of consecutive hard regs needed starting at reg REGNO
-   to hold something of mode MODE.
-   This is ordinarily the length in words of a value of mode MODE
-   but can be less for certain modes in special long registers.
-
-   On the MIPS, all general registers are one word long.  Except on
-   the R4000 with the FR bit set, the floating point uses register
-   pairs, with the second register not being allocable.  */
 
 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
 
-/* Value is 1 if hard register REGNO can hold a value of machine-mode
-   MODE.  In 32 bit mode, require that DImode and DFmode be in even
-   registers.  For DImode, this makes some of the insns easier to
-   write, since you don't have to worry about a DImode value in
-   registers 3 & 4, producing a result in 4 & 5.
-
-   To make the code simpler HARD_REGNO_MODE_OK now just references an
+/* To make the code simpler, HARD_REGNO_MODE_OK just references an
    array built in override_options.  Because machmodes.h is not yet
    included before this file is processed, the MODE bound can't be
    expressed here.  */
@@ -1859,25 +1640,15 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
    == (GET_MODE_CLASS (MODE2) == MODE_FLOAT ||				\
        GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
 
-/* MIPS pc is not overloaded on a register.	*/
-/* #define PC_REGNUM xx				*/
-
 /* Register to use for pushing function arguments.  */
 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
 
-/* Offset from the stack pointer to the first available location.  Use
-   the default value zero.  */
-/* #define STACK_POINTER_OFFSET 0 */
-
 /* Base register for access to local variables of the function.  We
    pretend that the frame pointer is $1, and then eliminate it to
    HARD_FRAME_POINTER_REGNUM.  We can get away with this because $1 is
    a fixed register, and will not be used for anything else.  */
 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
 
-/* Temporary scratch register for use by the assembler.  */
-#define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
-
 /* $30 is not available on the mips16, so we use $17 as the frame
    pointer.  */
 #define HARD_FRAME_POINTER_REGNUM \
@@ -1895,14 +1666,7 @@ extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
 /* Register in which static-chain is passed to a function.  */
 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
 
-/* If the structure value address is passed in a register, then
-   `STRUCT_VALUE_REGNUM' should be the number of that register.  */
-/* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place
-   where the address is passed.  If it returns 0, the address is
-   passed as an "invisible" first argument.  */
+/* Pass structure addresses as an "invisible" first argument.  */
 #define STRUCT_VALUE 0
 
 /* Mips registers used in prologue/epilogue code when the stack frame
@@ -2040,31 +1804,31 @@ enum reg_class
    sub-initializer must be suitable as an initializer for the type
    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 
-#define REG_CLASS_CONTENTS						\
-{									\
+#define REG_CLASS_CONTENTS						                                \
+{									                                \
   { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* no registers */	\
   { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 nonarg regs */\
   { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 registers */	\
   { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 T register */	\
   { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* mips16 and T regs */ \
   { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* SVR4 PIC function address register */ \
-  { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* Every other GPR */ \
+  { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* Every other GPR */   \
   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* integer registers */	\
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },	/* floating registers*/	\
   { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* hi register */	\
   { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },	/* lo register */	\
   { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 },	/* mul/div registers */	\
-  { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
-  { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
-  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
+  { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },   /* cop0 registers */    \
+  { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },   /* cop2 registers */    \
+  { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff },   /* cop3 registers */    \
   { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },	/* union classes */     \
   { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 },				\
   { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 },				\
-  { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },			\
-  { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },	\
-  { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
-  { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
-  { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
+  { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 },			        \
+  { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 },	                        \
+  { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff },                           \
+  { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff },                           \
+  { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff },                           \
   { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 },	/* status registers */	\
   { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff }	/* all registers */	\
 }
@@ -2347,36 +2111,6 @@ extern enum reg_class mips_char_to_class[256];
    + (TARGET_ABICALLS && !TARGET_NEWABI					\
       ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
 
-/* Offset from the stack pointer register to an item dynamically
-   allocated on the stack, e.g., by `alloca'.
-
-   The default value for this macro is `STACK_POINTER_OFFSET' plus the
-   length of the outgoing arguments.  The default is correct for most
-   machines.  See `function.c' for details.
-
-   The MIPS ABI states that functions which dynamically allocate the
-   stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
-   we are trying to create a second frame pointer to the function, so
-   allocate some stack space to make it happy.
-
-   However, the linker currently complains about linking any code that
-   dynamically allocates stack space, and there seems to be a bug in
-   STACK_DYNAMIC_OFFSET, so don't define this right now.  */
-
-#if 0
-#define STACK_DYNAMIC_OFFSET(FUNDECL)					\
-  ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
-	? 4*UNITS_PER_WORD						\
-	: current_function_outgoing_args_size)
-#endif
-
-/* The return address for the current frame is in r31 if this is a leaf
-   function.  Otherwise, it is on the stack.  It is at a variable offset
-   from sp/fp/ap, so we define a fake hard register rap which is a
-   pointer to the return address on the stack.  This always gets eliminated
-   during reload to be either the frame pointer or the stack pointer plus
-   an offset.  */
-
 #define RETURN_ADDR_RTX mips_return_addr
 
 /* Since the mips16 ISA mode is encoded in the least-significant bit
@@ -2391,33 +2125,7 @@ extern enum reg_class mips_char_to_class[256];
 
 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
 
-/* If defined, this macro specifies a table of register pairs used to
-   eliminate unneeded registers that point into the stack frame.  If
-   it is not defined, the only elimination attempted by the compiler
-   is to replace references to the frame pointer with references to
-   the stack pointer.
-
-   The definition of this macro is a list of structure
-   initializations, each of which specifies an original and
-   replacement register.
-
-   On some machines, the position of the argument pointer is not
-   known until the compilation is completed.  In such a case, a
-   separate hard register must be used for the argument pointer.
-   This register can be eliminated by replacing it with either the
-   frame pointer or the argument pointer, depending on whether or not
-   the frame pointer has been eliminated.
-
-   In this case, you might specify:
-        #define ELIMINABLE_REGS  \
-        {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
-         {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
-         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
-
-   Note that the elimination of the argument pointer with the stack
-   pointer is specified first since that is the preferred elimination.
-
-   The eliminations to $17 are only used on the mips16.  See the
+/* The eliminations to $17 are only used for mips16 code.  See the
    definition of HARD_FRAME_POINTER_REGNUM.  */
 
 #define ELIMINABLE_REGS							\
@@ -2428,88 +2136,37 @@ extern enum reg_class mips_char_to_class[256];
  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30},				\
  { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
 
-/* A C expression that returns nonzero if the compiler is allowed to
-   try to replace register number FROM-REG with register number
-   TO-REG.  This macro need only be defined if `ELIMINABLE_REGS' is
-   defined, and will usually be the constant 1, since most of the
-   cases preventing register elimination are things that the compiler
-   already knows about.
-
-   When not in mips16 and mips64, we can always eliminate to the
-   frame pointer.  We can eliminate to the stack pointer unless
-   a frame pointer is needed.  In mips16 mode, we need a frame
-   pointer for a large frame; otherwise, reload may be unable
-   to compute the address of a local variable, since there is
-   no way to add a large constant to the stack pointer
+/* We can always eliminate to the hard frame pointer.  We can eliminate
+   to the stack pointer unless a frame pointer is needed.
+
+   In mips16 mode, we need a frame pointer for a large frame; otherwise,
+   reload may be unable to compute the address of a local variable,
+   since there is no way to add a large constant to the stack pointer
    without using a temporary register.
 
-   In mips16, for some instructions (eg lwu), we can't eliminate the
+   Also, for some mips16 instructions (eg lwu), we can't eliminate the
    frame pointer for the stack pointer.  These instructions are
-   only generated in TARGET_64BIT mode.
-   */
-
+   only generated in TARGET_64BIT mode.  */
 #define CAN_ELIMINATE(FROM, TO)						\
-   (((TO) == HARD_FRAME_POINTER_REGNUM 				        \
-	  || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed	\
-	      && ! (TARGET_MIPS16 && TARGET_64BIT)			\
-	      && (! TARGET_MIPS16					\
-	          || compute_frame_size (get_frame_size ()) < 32768))))
+  ((TO) == HARD_FRAME_POINTER_REGNUM 				        \
+   || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed		\
+       && !(TARGET_MIPS16 && TARGET_64BIT)				\
+       && (!TARGET_MIPS16						\
+	   || compute_frame_size (get_frame_size ()) < 32768)))
 
 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
-	(OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
-
-/* If we generate an insn to push BYTES bytes,
-   this says how many the stack pointer really advances by.
-   On the VAX, sp@- in a byte insn really pushes a word.  */
-
-/* #define PUSH_ROUNDING(BYTES) 0 */
-
-/* If defined, the maximum amount of space required for outgoing
-   arguments will be computed and placed into the variable
-   `current_function_outgoing_args_size'.  No space will be pushed
-   onto the stack for each call; instead, the function prologue
-   should increase the stack frame size by this amount.
+  (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
 
-   It is not proper to define both `PUSH_ROUNDING' and
-   `ACCUMULATE_OUTGOING_ARGS'.  */
+/* Allocate stack space for arguments at the beginning of each function.  */
 #define ACCUMULATE_OUTGOING_ARGS 1
 
-/* Offset from the argument pointer register to the first argument's
-   address.  On some machines it may depend on the data type of the
-   function.
-
-   If `ARGS_GROW_DOWNWARD', this is the offset to the location above
-   the first argument's address.
-
-   On the MIPS, we must skip the first argument position if we are
-   returning a structure or a union, to account for its address being
-   passed in $4.  However, at the current time, this produces a compiler
-   that can't bootstrap, so comment it out for now.  */
-
-#if 0
-#define FIRST_PARM_OFFSET(FNDECL)					\
-  (FNDECL != 0								\
-   && TREE_TYPE (FNDECL) != 0						\
-   && TREE_TYPE (TREE_TYPE (FNDECL)) != 0				\
-   && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE	\
-       || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE)	\
-		? UNITS_PER_WORD					\
-		: 0)
-#else
+/* The argument pointer always points to the first argument.  */
 #define FIRST_PARM_OFFSET(FNDECL) 0
-#endif
-
-/* When a parameter is passed in a register, stack space is still
-   allocated for it.  For the MIPS, stack space must be allocated, cf
-   Asm Lang Prog Guide page 7-8.
-
-   BEWARE that some space is also allocated for non existing arguments
-   in register. In case an argument list is of form GF used registers
-   are a0 (a2,a3), but we should push over a1...  */
 
-#define REG_PARM_STACK_SPACE(FNDECL) 					 \
-  ((mips_abi == ABI_32 || mips_abi == ABI_O64)				 \
-   ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
+/* o32 and o64 reserve stack space for all argument registers.  */
+#define REG_PARM_STACK_SPACE(FNDECL) 			\
+  ((mips_abi == ABI_32 || mips_abi == ABI_O64)		\
+   ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)		\
    : 0)
 
 /* Define this if it is the responsibility of the caller to
@@ -2524,35 +2181,8 @@ extern enum reg_class mips_char_to_class[256];
    ? 64 : 128)
 
 
-/* A C expression that should indicate the number of bytes of its
-   own arguments that a function pops on returning, or 0
-   if the function pops no arguments and the caller must therefore
-   pop them all after the function returns.
-
-   FUNDECL is the declaration node of the function (as a tree).
-
-   FUNTYPE is a C variable whose value is a tree node that
-   describes the function in question.  Normally it is a node of
-   type `FUNCTION_TYPE' that describes the data type of the function.
-   From this it is possible to obtain the data types of the value
-   and arguments (if known).
-
-   When a call to a library function is being considered, FUNTYPE
-   will contain an identifier node for the library function.  Thus,
-   if you need to distinguish among various library functions, you
-   can do so by their names.  Note that "library function" in this
-   context means a function used to perform arithmetic, whose name
-   is known specially in the compiler and was not mentioned in the
-   C code being compiled.
-
-   STACK-SIZE is the number of bytes of arguments passed on the
-   stack.  If a variable number of bytes is passed, it is zero, and
-   argument popping will always be the responsibility of the
-   calling function.  */
-
 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 
-
 /* Symbolic macros for the registers used to return integer and floating
    point values.  */
 
@@ -2573,19 +2203,9 @@ extern enum reg_class mips_char_to_class[256];
 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 
-/* Define how to find the value returned by a library function
-   assuming the value has mode MODE.  Because we define
-   PROMOTE_FUNCTION_RETURN, we must promote the mode just as
-   PROMOTE_MODE does.  */
-
 #define LIBCALL_VALUE(MODE) \
   mips_function_value (NULL_TREE, NULL, (MODE))
 
-/* Define how to find the value returned by a function.
-   VALTYPE is the data type of the value (as a tree).
-   If the precise function being called is known, FUNC is its FUNCTION_DECL;
-   otherwise, FUNC is 0.  */
-
 #define FUNCTION_VALUE(VALTYPE, FUNC) \
   mips_function_value ((VALTYPE), (FUNC), VOIDmode)
 
@@ -2607,26 +2227,7 @@ extern enum reg_class mips_char_to_class[256];
 	&& ((N) % FP_INC == 0) && mips_abi != ABI_O64))		\
    && !fixed_regs[N])
 
-/* A C expression which can inhibit the returning of certain function
-   values in registers, based on the type of value.  A nonzero value says
-   to return the function value in memory, just as large structures are
-   always returned.  Here TYPE will be a C expression of type
-   `tree', representing the data type of the value.
-
-   Note that values of mode `BLKmode' must be explicitly
-   handled by this macro.  Also, the option `-fpcc-struct-return'
-   takes effect regardless of this macro.  On most systems, it is
-   possible to leave the macro undefined; this causes a default
-   definition to be used, whose value is the constant 1 for BLKmode
-   values, and 0 otherwise.
-
-   GCC normally converts 1 byte structures into chars, 2 byte
-   structs into shorts, and 4 byte structs into ints, and returns
-   them this way.  Defining the following macro overrides this,
-   to give us MIPS cc compatibility.  */
-
-#define RETURN_IN_MEMORY(TYPE)	\
-	mips_return_in_memory (TYPE)
+#define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
 
 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
 	(PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE),	\
@@ -2634,19 +2235,12 @@ extern enum reg_class mips_char_to_class[256];
 
 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
 
-/* Define a data type for recording info about an argument list
-   during the scan of that argument list.  This data type should
-   hold all necessary information about the function itself
-   and about the args processed so far, enough to enable macros
-   such as FUNCTION_ARG to determine where the next arg should go.
-
-   This structure has to cope with two different argument allocation
+/* This structure has to cope with two different argument allocation
    schemes.  Most MIPS ABIs view the arguments as a struct, of which the
    first N words go in registers and the rest go on the stack.  If I < N,
    the Ith word might go in Ith integer argument register or the
-   Ith floating-point one.  In some cases, it has to go in both (see
-   function_arg).  For these ABIs, we only need to remember the number
-   of words passed so far.
+   Ith floating-point one.  For these ABIs, we only need to remember
+   the number of words passed so far.
 
    The EABI instead allocates the integer and floating-point arguments
    separately.  The first N words of FP arguments go in FP registers,
@@ -2700,15 +2294,6 @@ typedef struct mips_args {
 
   /* True if the function has a prototype.  */
   int prototype;
-
-  /* When a structure does not take up a full register, the argument
-     should sometimes be shifted left so that it occupies the high part
-     of the register.  These two fields describe an array of ashl
-     patterns for doing this.  See function_arg_advance, which creates
-     the shift patterns, and function_arg, which returns them when given
-     a VOIDmode argument.  */
-  unsigned int num_adjusts;
-  rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
 } CUMULATIVE_ARGS;
 
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
@@ -2766,35 +2351,23 @@ typedef struct mips_args {
 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)		\
   function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
 
-#define FUNCTION_ARG_PADDING(MODE, TYPE)				\
-  (! BYTES_BIG_ENDIAN							\
-   ? upward								\
-   : (((MODE) == BLKmode						\
-       ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST		\
-	  && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
-       : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY			\
-	  && (mips_abi == ABI_32					\
-	      || mips_abi == ABI_O64					\
-	      || mips_abi == ABI_EABI					\
-	      || GET_MODE_CLASS (MODE) == MODE_INT)))			\
-      ? downward : upward))
+#define FUNCTION_ARG_PADDING(MODE, TYPE)		\
+  (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
+
+#define BLOCK_REG_PADDING(MODE, TYPE, FIRST)		\
+  (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
 
 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED)		\
   (mips_abi == ABI_EABI && (NAMED)					\
    && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
 
-/* Modified version of the macro in expr.h.  */
+/* Modified version of the macro in expr.h.  Only return true if
+   the type has a variable size or if the front end requires it
+   to be passed by reference.  */
 #define MUST_PASS_IN_STACK(MODE,TYPE)			\
   ((TYPE) != 0						\
    && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST	\
-       || TREE_ADDRESSABLE (TYPE)			\
-       || ((MODE) == BLKmode 				\
-	   && mips_abi != ABI_32 && mips_abi != ABI_O64 \
-	   && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
-		 && 0 == (int_size_in_bytes (TYPE)	\
-			  % (PARM_BOUNDARY / BITS_PER_UNIT))) \
-	   && (FUNCTION_ARG_PADDING (MODE, TYPE)	\
-	       == (BYTES_BIG_ENDIAN ? upward : downward)))))
+       || TREE_ADDRESSABLE (TYPE)))
 
 /* True if using EABI and varargs can be passed in floating-point
    registers.  Under these conditions, we need a more complex form
@@ -3090,9 +2663,7 @@ typedef struct mips_args {
 
 /* Specify the machine mode that this machine uses
    for the index in the tablejump instruction.
-   ??? Using HImode in mips16 mode can cause overflow.  However, the
-   overflow is no more likely than the overflow in a branch
-   instruction.  Large functions can currently break in both ways.  */
+   ??? Using HImode in mips16 mode can cause overflow. */
 #define CASE_VECTOR_MODE \
   (TARGET_MIPS16 ? HImode : ptr_mode)
 
@@ -3226,13 +2797,11 @@ typedef struct mips_args {
   {"symbolic_operand",		{ CONST, SYMBOL_REF, LABEL_REF }},	\
   {"const_arith_operand",	{ CONST, CONST_INT }},			\
   {"arith_operand",		{ REG, CONST_INT, CONST, SUBREG, ADDRESSOF }},	\
-  {"arith32_operand",		{ REG, CONST_INT, SUBREG, ADDRESSOF }},		\
   {"reg_or_0_operand",		{ REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
-  {"true_reg_or_0_operand",	{ REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
   {"small_int",			{ CONST_INT }},				\
-  {"large_int",			{ CONST_INT }},				\
   {"mips_const_double_ok",	{ CONST_DOUBLE }},			\
   {"const_float_1_operand",	{ CONST_DOUBLE }},			\
+  {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}},               \
   {"simple_memory_operand",	{ MEM, SUBREG }},			\
   {"equality_op",		{ EQ, NE }},				\
   {"cmp_op",			{ EQ, NE, GT, GE, GTU, GEU, LT, LE,	\
@@ -3641,12 +3210,7 @@ do									\
 while (0)
 
 
-/* How to tell the debugger about changes of source files.  Note, the
-   mips ECOFF format cannot deal with changes of files inside of
-   functions, which means the output of parser generators like bison
-   is generally not debuggable without using the -l switch.  Lose,
-   lose, lose.  Silicon graphics seems to want all .file's hardwired
-   to 1.  */
+/* How to tell the debugger about changes of source files.  */
 
 #ifndef SET_FILE_NUMBER
 #define SET_FILE_NUMBER() ++num_source_filenames
@@ -3688,23 +3252,9 @@ while (0)
 	$Lc[0-9]+	Label for use in s<xx> operation.
 	$Le[0-9]+	End blocks for MIPS debug support  */
 
-/* A C statement (sans semicolon) to output to the stdio stream
-   STREAM any text necessary for declaring the name NAME of an
-   initialized variable which is being defined.  This macro must
-   output the label definition (perhaps using `ASM_OUTPUT_LABEL').
-   The argument DECL is the `VAR_DECL' tree node representing the
-   variable.
-
-   If this macro is not defined, then the variable name is defined
-   in the usual manner as a label (by means of `ASM_OUTPUT_LABEL').  */
-
 #undef ASM_DECLARE_OBJECT_NAME
-#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL)			\
-do									\
- {									\
-   mips_declare_object (STREAM, NAME, "", ":\n", 0);			\
- }									\
-while (0)
+#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
+  mips_declare_object (STREAM, NAME, "", ":\n", 0)
 
 /* Globalizing directive for a label.  */
 #define GLOBAL_ASM_OP "\t.globl\t"
@@ -3810,7 +3360,7 @@ do {									\
 do {									\
   if (TARGET_EMBEDDED_PIC || TARGET_MIPS16)				\
     function_section (current_function_decl);				\
-  (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM);			\
+  (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM);		\
 } while (0)
 
 /* This is how to output an assembler line
@@ -3899,29 +3449,14 @@ while (0)
 #define ASM_COMMENT_START " #"
 #endif
 
-
-/* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
-   and mips-tdump.c to print them out.
-
-   These must match the corresponding definitions in gdb/mipsread.c.
-   Unfortunately, gcc and gdb do not currently share any directories.  */
-
-#define CODE_MASK 0x8F300
-#define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
-#define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
-#define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
-
-
 /* Default definitions for size_t and ptrdiff_t.  We must override the
    definitions from ../svr4.h on mips-*-linux-gnu.  */
 
-#ifndef SIZE_TYPE
+#undef SIZE_TYPE
 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
-#endif
 
-#ifndef PTRDIFF_TYPE
+#undef PTRDIFF_TYPE
 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
-#endif
 
 /* See mips_expand_prologue's use of loadgp for when this should be
    true.  */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 0be11733250..7b5f1b7433c 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -30,29 +30,29 @@
   [(UNSPEC_LOAD_DF_LOW		 0)
    (UNSPEC_LOAD_DF_HIGH		 1)
    (UNSPEC_STORE_DF_HIGH	 2)
-   (UNSPEC_GET_FNADDR		 4)
-   (UNSPEC_BLOCKAGE		 6)
-   (UNSPEC_CPRESTORE		 8)
-   (UNSPEC_EH_RECEIVER		10)
-   (UNSPEC_EH_RETURN		11)
-   (UNSPEC_CONSTTABLE_QI	12)
-   (UNSPEC_CONSTTABLE_HI	13)
-   (UNSPEC_CONSTTABLE_SI	14)
-   (UNSPEC_CONSTTABLE_DI	15)
-   (UNSPEC_CONSTTABLE_SF	16)
-   (UNSPEC_CONSTTABLE_DF	17)
-   (UNSPEC_ALIGN_2		18)
-   (UNSPEC_ALIGN_4		19)
-   (UNSPEC_ALIGN_8		20)
-   (UNSPEC_HIGH			22)
-   (UNSPEC_LWL			23)
-   (UNSPEC_LWR			24)
-   (UNSPEC_SWL			25)
-   (UNSPEC_SWR			26)
-   (UNSPEC_LDL			27)
-   (UNSPEC_LDR			28)
-   (UNSPEC_SDL			29)
-   (UNSPEC_SDR			30)
+   (UNSPEC_GET_FNADDR		 3)
+   (UNSPEC_BLOCKAGE		 4)
+   (UNSPEC_CPRESTORE		 5)
+   (UNSPEC_EH_RECEIVER		 6)
+   (UNSPEC_EH_RETURN		 7)
+   (UNSPEC_CONSTTABLE_QI	 8)
+   (UNSPEC_CONSTTABLE_HI	 9)
+   (UNSPEC_CONSTTABLE_SI	10)
+   (UNSPEC_CONSTTABLE_DI	11)
+   (UNSPEC_CONSTTABLE_SF	12)
+   (UNSPEC_CONSTTABLE_DF	13)
+   (UNSPEC_ALIGN_2		14)
+   (UNSPEC_ALIGN_4		15)
+   (UNSPEC_ALIGN_8		16)
+   (UNSPEC_HIGH			17)
+   (UNSPEC_LWL			18)
+   (UNSPEC_LWR			19)
+   (UNSPEC_SWL			20)
+   (UNSPEC_SWR			21)
+   (UNSPEC_LDL			22)
+   (UNSPEC_LDR			23)
+   (UNSPEC_SDL			24)
+   (UNSPEC_SDR			25)
 
    ;; Constants used in relocation unspecs.  RELOC_GOT_PAGE and RELOC_GOT_DISP
    ;; are really only available for n32 and n64.  However, it is convenient
@@ -69,7 +69,6 @@
    (RELOC_LOADGP_HI		108)
    (RELOC_LOADGP_LO		109)])
 
-
 ;; ....................
 ;;
 ;;	Attributes
@@ -81,10 +80,12 @@
 (define_attr "jal" "unset,direct,indirect"
   (const_string "unset"))
 
-;; True for multi-instruction jal macros.  jal is always a macro
-;; in SVR4 PIC since it includes an instruction to restore $gp.
-;; Direct jals are also macros in NewABI PIC since they load the
-;; target address into $25.
+;; This attribute is YES if the instruction is a jal macro (not a
+;; real jal instruction).
+;;
+;; jal is always a macro in SVR4 PIC since it includes an instruction to
+;; restore $gp.  Direct jals are also macros in NewABI PIC since they
+;; load the target address into $25.
 (define_attr "jal_macro" "no,yes"
   (cond [(eq_attr "jal" "direct")
 	 (symbol_ref "TARGET_ABICALLS != 0")
@@ -100,6 +101,7 @@
 ;; store	store instruction(s)
 ;; prefetch	memory prefetch
 ;; move		data movement within same register set
+;; condmove	conditional moves
 ;; xfer		transfer to/from coprocessor
 ;; hilo		transfer of hi/lo registers
 ;; arith	integer arithmetic instruction
@@ -122,30 +124,53 @@
 ;; multi	multiword sequence (or user asm statements)
 ;; nop		no operation
 (define_attr "type"
-  "unknown,branch,jump,call,load,store,prefetch,move,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
+  "unknown,branch,jump,call,load,store,prefetch,move,condmove,xfer,hilo,const,arith,darith,imul,imadd,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,multi,nop"
   (cond [(eq_attr "jal" "!unset")
 	 (const_string "call")]
 	(const_string "unknown")))
 
 ;; Main data type used by the insn
-(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
+(define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
+  (const_string "unknown"))
 
 ;; Is this an extended instruction in mips16 mode?
 (define_attr "extended_mips16" "no,yes"
   (const_string "no"))
 
-;; Length (in # of bytes).  A conditional branch is allowed only to a
-;; location within a signed 18-bit offset of the delay slot.  If that
-;; provides too smal a range, we use the `j' instruction.  This
-;; instruction takes a 28-bit value, but that value is not an offset.
-;; Instead, it's bitwise-ored with the high-order four bits of the
-;; instruction in the delay slot, which means it cannot be used to
-;; cross a 256MB boundary.  We could fall back back on the jr,
-;; instruction which allows full access to the entire address space,
-;; but we do not do so at present.
-
+;; Length of instruction in bytes.
 (define_attr "length" ""
-   (cond [(eq_attr "type" "branch")
+   (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
+	  ;; If a branch is outside this range, we have a choice of two
+	  ;; sequences.  For PIC, an out-of-range branch like:
+	  ;;
+	  ;;	bne	r1,r2,target
+	  ;;	dslot
+	  ;;
+	  ;; becomes the equivalent of:
+	  ;;
+	  ;;	beq	r1,r2,1f
+	  ;;	dslot
+	  ;;	la	$at,target
+	  ;;	jr	$at
+	  ;;	nop
+	  ;; 1:
+	  ;;
+	  ;; where the load address can be up to three instructions long
+	  ;; (lw, nop, addiu).
+	  ;;
+	  ;; The non-PIC case is similar except that we use a direct
+	  ;; jump instead of an la/jr pair.  Since the target of this
+	  ;; jump is an absolute 28-bit bit address (the other bits
+	  ;; coming from the address of the delay slot) this form cannot
+	  ;; cross a 256MB boundary.  We could provide the option of
+	  ;; using la/jr in this case too, but we do not do so at
+	  ;; present.
+	  ;;
+	  ;; Note that this value does not account for the delay slot
+	  ;; instruction, whose length is added separately.  If the RTL
+	  ;; pattern has no explicit delay slot, mips_adjust_insn_length
+	  ;; will add the length of the implicit nop.
+	  (eq_attr "type" "branch")
           (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 4))))
                      (const_int 131072))
                  (const_int 4)
@@ -153,12 +178,14 @@
 		     (const_int 0))
 		 (const_int 24)
 		 ] (const_int 12))
+
 	  (eq_attr "type" "const")
 	  (symbol_ref "mips_const_insns (operands[1]) * 4")
 	  (eq_attr "type" "load")
 	  (symbol_ref "mips_fetch_insns (operands[1]) * 4")
 	  (eq_attr "type" "store")
 	  (symbol_ref "mips_fetch_insns (operands[0]) * 4")
+
 	  ;; In the worst case, a call macro will take 8 instructions:
 	  ;;
 	  ;;	 lui $25,%call_hi(FOO)
@@ -171,9 +198,11 @@
 	  ;;	 nop
 	  (eq_attr "jal_macro" "yes")
 	  (const_int 32)
+
 	  (and (eq_attr "extended_mips16" "yes")
 	       (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
 	  (const_int 8)
+
 	  (and (eq_attr "type" "idiv")
 	       (ne (symbol_ref "TARGET_CHECK_ZERO_DIV") (const_int 0)))
 	  (cond [(ne (symbol_ref "TARGET_MIPS16") (const_int 0))
@@ -183,19 +212,9 @@
 
 ;; Attribute describing the processor.  This attribute must match exactly
 ;; with the processor_type enumeration in mips.h.
-
-;; Attribute describing the processor
-;; (define_attr "cpu" "default,r3000,r6000,r4000"
-;;   (const
-;;    (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000"))   (const_string "r3000")
-;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000"))   (const_string "r4000")
-;;           (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000"))   (const_string "r6000")]
-;;          (const_string "default"))))
-
-;; ??? Fix everything that tests this attribute.
 (define_attr "cpu"
-  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r8000,sb1,sr71000"
-  (const (symbol_ref "mips_cpu_attr")))
+  "default,4kc,5kc,20kc,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
+  (const (symbol_ref "mips_tune")))
 
 ;; The type of hardware hazard associated with this instruction.
 ;; DELAY means that the next instruction cannot read the result
@@ -238,28 +257,24 @@
 		(const_string "no")))
 
 ;; Attribute defining whether or not we can use the branch-likely instructions
-
 (define_attr "branch_likely" "no,yes"
   (const
    (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
 		 (const_string "yes")
 		 (const_string "no"))))
 
-
 ;; Describe a user's asm statement.
 (define_asm_attributes
   [(set_attr "type" "multi")])
-
 
-
 ;; .........................
 ;;
-;;	Delay slots, can't describe load/fcmp/xfer delay slots here
+;;	Branch, call and jump delay slots
 ;;
 ;; .........................
 
 (define_delay (and (eq_attr "type" "branch")
-		   (eq (symbol_ref "mips16") (const_int 0)))
+		   (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
   [(eq_attr "can_delay" "yes")
    (nil)
    (and (eq_attr "branch_likely" "yes")
@@ -275,9 +290,7 @@
   [(eq_attr "can_delay" "yes")
    (nil)
    (nil)])
-
 
-
 ;; .........................
 ;;
 ;;	Functional units
@@ -319,7 +332,7 @@
 ;; selecting instructions to between the two instructions.
 
 (define_function_unit "imuldiv" 1 0
-  (and (eq_attr "type" "hilo") (ne (symbol_ref "mips16") (const_int 0)))
+  (and (eq_attr "type" "hilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
   1 5)
 
 (define_function_unit "imuldiv"  1 0
@@ -592,39 +605,14 @@
        (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
   58 58)
 
-;; The following functional units do not use the cpu type, and use
-;; much less memory in genattrtab.c.
-
-;; (define_function_unit "memory"   1 0 (eq_attr "type" "load")                                3 0)
-;; (define_function_unit "memory"   1 0 (eq_attr "type" "store")                               1 0)
-;;
-;; (define_function_unit "fp_comp"  1 0 (eq_attr "type" "fcmp")                                2 0)
-;;
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer")                                2 0)
-;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo")                                3 0)
-;;
-;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "imul")                               17 0)
-;; (define_function_unit "imuldiv"  1 1 (eq_attr "type" "idiv")                               38 0)
-;;
-;; (define_function_unit "adder"    1 1 (eq_attr "type" "fadd")                                4 0)
-;; (define_function_unit "adder"    1 1 (eq_attr "type" "fabs,fneg")                           2 0)
-;;
-;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF"))    7 0)
-;; (define_function_unit "mult"     1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF"))    8 0)
-;;
-;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF"))   23 0)
-;; (define_function_unit "divide"   1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF"))   36 0)
-;;
-;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF"))  54 0)
-;; (define_function_unit "sqrt"     1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
-
 ;; Include scheduling descriptions.
 
 (include "5400.md")
 (include "5500.md")
+(include "7000.md")
+(include "9000.md")
 (include "sr71k.md")
-
-
+
 ;;
 ;;  ....................
 ;;
@@ -636,39 +624,46 @@
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 0))]
   ""
-  "*
 {
   if (ISA_HAS_COND_TRAP)
-    return \"teq\\t$0,$0\";
+    return "teq\t$0,$0";
   /* The IRIX 6 O32 assembler requires the first break operand.  */
-  else if (TARGET_MIPS16 || ! TARGET_GAS)
-    return \"break 0\";
+  else if (TARGET_MIPS16 || !TARGET_GAS)
+    return "break 0";
   else
-    return \"break\";
-}")
+    return "break";
+})
 
 (define_expand "conditional_trap"
   [(trap_if (match_operator 0 "cmp_op"
 			    [(match_dup 2) (match_dup 3)])
 	    (match_operand 1 "const_int_operand" ""))]
   "ISA_HAS_COND_TRAP"
-  "
 {
-  mips_gen_conditional_trap (operands);
-  DONE;
-}")
-
-;; Match a TRAP_IF with 2nd arg of 0.  The div_trap_* insns match a
-;; 2nd arg of any CONST_INT, so this insn must appear first.
-;; gen_div_trap always generates TRAP_IF with 2nd arg of 6 or 7.
+  if (operands[1] == const0_rtx)
+    {
+      mips_gen_conditional_trap (operands);
+      DONE;
+    }
+  else
+    FAIL;
+})
 
 (define_insn ""
   [(trap_if (match_operator 0 "trap_cmp_op"
-                            [(match_operand:SI 1 "reg_or_0_operand" "d")
-                             (match_operand:SI 2 "nonmemory_operand" "dI")])
+                            [(match_operand:SI 1 "reg_or_0_operand" "dJ")
+                             (match_operand:SI 2 "arith_operand" "dI")])
 	    (const_int 0))]
   "ISA_HAS_COND_TRAP"
-  "t%C0\\t%z1,%z2")
+  "t%C0\t%z1,%z2")
+
+(define_insn ""
+  [(trap_if (match_operator 0 "trap_cmp_op"
+                            [(match_operand:DI 1 "reg_or_0_operand" "dJ")
+                             (match_operand:DI 2 "arith_operand" "dI")])
+	    (const_int 0))]
+  "TARGET_64BIT && ISA_HAS_COND_TRAP"
+  "t%C0\t%z1,%z2")
 
 ;;
 ;;  ....................
@@ -683,7 +678,7 @@
 	(plus:DF (match_operand:DF 1 "register_operand" "f")
 		 (match_operand:DF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "add.d\\t%0,%1,%2"
+  "add.d\t%0,%1,%2"
   [(set_attr "type"	"fadd")
    (set_attr "mode"	"DF")])
 
@@ -692,7 +687,7 @@
 	(plus:SF (match_operand:SF 1 "register_operand" "f")
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "add.s\\t%0,%1,%2"
+  "add.s\t%0,%1,%2"
   [(set_attr "type"	"fadd")
    (set_attr "mode"	"SF")])
 
@@ -701,7 +696,6 @@
 	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
 		 (match_operand:SI 2 "arith_operand" "")))]
   ""
-  "
 {
   /* If a large stack adjustment was forced into a register, we may be
      asked to generate rtx such as:
@@ -723,7 +717,7 @@
       emit_move_insn (operands[0], tmp);
       DONE;
     }
-}")
+})
 
 (define_insn "addsi3_internal"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -731,8 +725,8 @@
 		 (match_operand:SI 2 "arith_operand" "d,Q")))]
   "!TARGET_MIPS16"
   "@
-    addu\\t%0,%z1,%2
-    addiu\\t%0,%z1,%2"
+    addu\t%0,%z1,%2
+    addiu\t%0,%z1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -745,7 +739,7 @@
 	(plus:SI (reg:SI 29)
 		 (match_operand:SI 0 "small_int" "I")))]
   "TARGET_MIPS16"
-  "addu\\t%$,%$,%0"
+  "addu\t%$,%$,%0"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
@@ -757,7 +751,7 @@
 	(plus:SI (reg:SI 29)
 		 (match_operand:SI 1 "small_int" "I")))]
   "TARGET_MIPS16"
-  "addu\\t%0,%$,%1"
+  "addu\t%0,%$,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_uimm8_4" "")
@@ -781,12 +775,12 @@
        || REGNO (operands[2]) == ARG_POINTER_REGNUM
        || REGNO (operands[2]) == FRAME_POINTER_REGNUM
        || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
-  "*
 {
   if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"addu\\t%0,%2\";
-  return \"addu\\t%0,%1,%2\";
-}"
+    return "addu\t%0,%2";
+  else
+    return "addu\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -819,7 +813,6 @@
 	   && INTVAL (operands[1]) >= - 0x80 - 0x80))"
   [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -833,7 +826,7 @@
       operands[1] = GEN_INT (- 0x80);
       operands[2] = GEN_INT (val + 0x80);
     }
-}")
+})
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -852,7 +845,6 @@
 	   && INTVAL (operands[2]) >= - 0x8 - 0x80))"
   [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[2]);
 
@@ -866,7 +858,7 @@
       operands[2] = GEN_INT (- 0x8);
       operands[3] = GEN_INT (val + 0x8);
     }
-}")
+})
 
 (define_expand "adddi3"
   [(parallel [(set (match_operand:DI 0 "register_operand" "")
@@ -874,7 +866,6 @@
 			    (match_operand:DI 2 "arith_operand" "")))
 	      (clobber (match_dup 3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
 {
   /* If a large stack adjustment was forced into a register, we may be
      asked to generate rtx such as:
@@ -905,7 +896,7 @@
     }
 
   operands[3] = gen_reg_rtx (SImode);
-}")
+})
 
 (define_insn "adddi3_internal_1"
   [(set (match_operand:DI 0 "register_operand" "=d,&d")
@@ -913,13 +904,12 @@
 		 (match_operand:DI 2 "register_operand" "d,d")))
    (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
 {
   return (REGNO (operands[0]) == REGNO (operands[1])
 	  && REGNO (operands[0]) == REGNO (operands[2]))
-    ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
-    : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
-}"
+    ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
+    : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -991,9 +981,9 @@
    (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
   "@
-   addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
-   move\\t%L0,%L1\;move\\t%M0,%M1
-   subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
+   addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
+   move\t%L0,%L1\;move\t%M0,%M1
+   subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"12,8,16")])
@@ -1052,8 +1042,8 @@
 		 (match_operand:DI 2 "arith_operand" "d,Q")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "@
-    daddu\\t%0,%z1,%2
-    daddiu\\t%0,%z1,%2"
+    daddu\t%0,%z1,%2
+    daddiu\t%0,%z1,%2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
@@ -1066,7 +1056,7 @@
 	(plus:DI (reg:DI 29)
 		 (match_operand:DI 0 "small_int" "I")))]
   "TARGET_MIPS16 && TARGET_64BIT"
-  "daddu\\t%$,%$,%0"
+  "daddu\t%$,%$,%0"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_simm8_8" "")
@@ -1078,7 +1068,7 @@
 	(plus:DI (reg:DI 29)
 		 (match_operand:DI 1 "small_int" "I")))]
   "TARGET_MIPS16 && TARGET_64BIT"
-  "daddu\\t%0,%$,%1"
+  "daddu\t%0,%$,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_uimm5_4" "")
@@ -1102,12 +1092,12 @@
        || REGNO (operands[2]) == ARG_POINTER_REGNUM
        || REGNO (operands[2]) == FRAME_POINTER_REGNUM
        || REGNO (operands[2]) == STACK_POINTER_REGNUM)"
-  "*
 {
   if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"daddu\\t%0,%2\";
-  return \"daddu\\t%0,%1,%2\";
-}"
+    return "daddu\t%0,%2";
+  else
+    return "daddu\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -1140,7 +1130,6 @@
 	   && INTVAL (operands[1]) >= - 0x10 - 0x10))"
   [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -1154,7 +1143,7 @@
       operands[1] = GEN_INT (- 0x10);
       operands[2] = GEN_INT (val + 0x10);
     }
-}")
+})
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1173,7 +1162,6 @@
 	   && INTVAL (operands[2]) >= - 0x8 - 0x10))"
   [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
    (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[2]);
 
@@ -1187,7 +1175,7 @@
       operands[2] = GEN_INT (- 0x8);
       operands[3] = GEN_INT (val + 0x8);
     }
-}")
+})
 
 (define_insn "addsi3_internal_2"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -1195,8 +1183,8 @@
 				 (match_operand:SI 2 "arith_operand" "d,Q"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "@
-    addu\\t%0,%z1,%2
-    addiu\\t%0,%z1,%2"
+    addu\t%0,%z1,%2
+    addiu\t%0,%z1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -1205,12 +1193,12 @@
 	(sign_extend:DI (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
 				 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
   "TARGET_MIPS16 && TARGET_64BIT"
-  "*
 {
   if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"addu\\t%0,%2\";
-  return \"addu\\t%0,%1,%2\";
-}"
+    return "addu\t%0,%2";
+  else
+    return "addu\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -1221,7 +1209,6 @@
 			       (const_int 4)
 			       (const_int 8))
 		 (const_int 4)])])
-
 
 ;;
 ;;  ....................
@@ -1236,7 +1223,7 @@
 	(minus:DF (match_operand:DF 1 "register_operand" "f")
 		  (match_operand:DF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sub.d\\t%0,%1,%2"
+  "sub.d\t%0,%1,%2"
   [(set_attr "type"	"fadd")
    (set_attr "mode"	"DF")])
 
@@ -1245,165 +1232,32 @@
 	(minus:SF (match_operand:SF 1 "register_operand" "f")
 		  (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "sub.s\\t%0,%1,%2"
+  "sub.s\t%0,%1,%2"
   [(set_attr "type"	"fadd")
    (set_attr "mode"	"SF")])
 
 (define_expand "subsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		  (match_operand:SI 2 "arith_operand" "dI")))]
+  [(set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_operand:SI 1 "register_operand" "")
+		  (match_operand:SI 2 "register_operand" "")))]
   ""
-  "
-{
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (INTVAL (operands[2]) == -32768
-	  || (TARGET_MIPS16
-	      && INTVAL (operands[2]) == -0x4000)))
-    operands[2] = force_reg (SImode, operands[2]);
-}")
+  "")
 
 (define_insn "subsi3_internal"
   [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-		  (match_operand:SI 2 "arith_operand" "dI")))]
-  "!TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "subu\\t%0,%z1,%2"
+	(minus:SI (match_operand:SI 1 "register_operand" "d")
+		  (match_operand:SI 2 "register_operand" "d")))]
+  ""
+  "subu\t%0,%z1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:SI 29)
-	(minus:SI (reg:SI 29)
-		  (match_operand:SI 0 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "addu\\t%$,%$,%n0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
-				      (const_int 4)
-				      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(minus:SI (reg:SI 29)
-		  (match_operand:SI 1 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "addu\\t%0,%$,%n1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 1 "m16_nuimm8_4" "")
-				      (const_int 4)
-				      (const_int 8)))])
-
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-	(minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-		  (match_operand:SI 2 "arith_operand" "I,O,d")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"subu\\t%0,%2\";
-  return \"subu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (const_int 4)])])
-
-;; On the mips16, we can sometimes split a subtract of a constant
-;; which is a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are setting a
-;; register to a register minus a constant, and one where we are
-;; simply subtracting a constant from a register.
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_dup 0)
-		  (match_operand:SI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0x80
-	&& INTVAL (operands[1]) <= 0x80 + 0x80)
-       || (INTVAL (operands[1]) < - 0x7f
-	   && INTVAL (operands[1]) >= - 0x7f - 0x7f))"
-  [(set (match_dup 0) (minus:SI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0x80);
-      operands[2] = GEN_INT (val - 0x80);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x7f);
-      operands[2] = GEN_INT (val + 0x7f);
-    }
-}")
-
-(define_split
-  [(set (match_operand:SI 0 "register_operand" "")
-	(minus:SI (match_operand:SI 1 "register_operand" "")
-		  (match_operand:SI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x8
-	&& INTVAL (operands[2]) <= 0x8 + 0x80)
-       || (INTVAL (operands[2]) < - 0x7
-	   && INTVAL (operands[2]) >= - 0x7 - 0x7f))"
-  [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x8);
-      operands[3] = GEN_INT (val - 0x8);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x7);
-      operands[3] = GEN_INT (val + 0x7);
-    }
-}")
-
 (define_expand "subdi3"
   [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
 		   (minus:DI (match_operand:DI 1 "register_operand" "d")
 			     (match_operand:DI 2 "register_operand" "d")))
 	      (clobber (match_dup 3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
 {
   if (TARGET_64BIT)
     {
@@ -1413,7 +1267,7 @@
     }
 
   operands[3] = gen_reg_rtx (SImode);
-}")
+})
 
 (define_insn "subdi3_internal"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -1421,7 +1275,7 @@
 		  (match_operand:DI 2 "register_operand" "d")))
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
+  "sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -1482,247 +1336,24 @@
 		  (match_dup 3)))]
   "")
 
-(define_insn "subdi3_internal_2"
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
-		  (match_operand:DI 2 "small_int" "P,J,N")))
-   (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
-  "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && INTVAL (operands[2]) != -32768"
-  "@
-   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
-   move\\t%L0,%L1\;move\\t%M0,%M1
-   sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
-  [(set_attr "type"	"darith")
-   (set_attr "mode"	"DI")
-   (set_attr "length"	"12,8,16")])
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 0)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 4)
-	(minus:SI (subreg:SI (match_dup 1) 4)
-		  (match_dup 3)))]
-  "")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "small_int" "")))
-   (clobber (match_operand:SI 3 "register_operand" ""))]
-  "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
-   && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
-   && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
-   && INTVAL (operands[2]) > 0"
-
-  [(set (match_dup 3)
-	(ltu:SI (subreg:SI (match_dup 1) 4)
-		(match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 4)
-	(minus:SI (subreg:SI (match_dup 1) 4)
-		  (match_dup 2)))
-
-   (set (subreg:SI (match_dup 0) 0)
-	(minus:SI (subreg:SI (match_dup 1) 0)
-		  (match_dup 3)))]
-  "")
-
 (define_insn "subdi3_internal_3"
   [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ")
-		  (match_operand:DI 2 "arith_operand" "dI")))]
-  "TARGET_64BIT && !TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"daddu\\t%0,%z1,%n2\"
-    : \"dsubu\\t%0,%z1,%2\";
-}"
+	(minus:DI (match_operand:DI 1 "register_operand" "d")
+		  (match_operand:DI 2 "register_operand" "d")))]
+  "TARGET_64BIT"
+  "dsubu\t%0,%1,%2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
-;; For the mips16, we need to recognize stack pointer subtractions
-;; explicitly, since we don't have a constraint for $sp.  These insns
-;; will be generated by the save_restore_insns functions.
-
-(define_insn ""
-  [(set (reg:DI 29)
-	(minus:DI (reg:DI 29)
-		  (match_operand:DI 0 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "daddu\\t%$,%$,%n0"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nsimm8_8" "")
-				      (const_int 4)
-				      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d")
-	(minus:DI (reg:DI 29)
-		  (match_operand:DI 1 "small_int" "I")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "daddu\\t%0,%$,%n1"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set (attr "length")	(if_then_else (match_operand:VOID 0 "m16_nuimm5_4" "")
-				      (const_int 4)
-				      (const_int 8)))])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(minus:DI (match_operand:DI 1 "register_operand" "0,d,d")
-		  (match_operand:DI 2 "arith_operand" "I,O,d")))]
-  "TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"dsubu\\t%0,%2\";
-  return \"dsubu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"DI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm5_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (const_int 4)])])
-
-;; On the mips16, we can sometimes split an add of a constant which is
-;; a 4 byte instruction into two adds which are both 2 byte
-;; instructions.  There are two cases: one where we are adding a
-;; constant plus a register to another register, and one where we are
-;; simply adding a constant to a register.
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_dup 0)
-		  (match_operand:DI 1 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == CONST_INT
-   && ((INTVAL (operands[1]) > 0x10
-	&& INTVAL (operands[1]) <= 0x10 + 0x10)
-       || (INTVAL (operands[1]) < - 0xf
-	   && INTVAL (operands[1]) >= - 0xf - 0xf))"
-  [(set (match_dup 0) (minus:DI (match_dup 0) (match_dup 1)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[1]);
-
-  if (val >= 0)
-    {
-      operands[1] = GEN_INT (0xf);
-      operands[2] = GEN_INT (val - 0xf);
-    }
-  else
-    {
-      operands[1] = GEN_INT (- 0x10);
-      operands[2] = GEN_INT (val + 0x10);
-    }
-}")
-
-(define_split
-  [(set (match_operand:DI 0 "register_operand" "")
-	(minus:DI (match_operand:DI 1 "register_operand" "")
-		  (match_operand:DI 2 "const_int_operand" "")))]
-  "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
-   && GET_CODE (operands[0]) == REG
-   && M16_REG_P (REGNO (operands[0]))
-   && GET_CODE (operands[1]) == REG
-   && M16_REG_P (REGNO (operands[1]))
-   && REGNO (operands[0]) != REGNO (operands[1])
-   && GET_CODE (operands[2]) == CONST_INT
-   && ((INTVAL (operands[2]) > 0x8
-	&& INTVAL (operands[2]) <= 0x8 + 0x10)
-       || (INTVAL (operands[2]) < - 0x7
-	   && INTVAL (operands[2]) >= - 0x7 - 0xf))"
-  [(set (match_dup 0) (minus:DI (match_dup 1) (match_dup 2)))
-   (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 3)))]
-  "
-{
-  HOST_WIDE_INT val = INTVAL (operands[2]);
-
-  if (val >= 0)
-    {
-      operands[2] = GEN_INT (0x8);
-      operands[3] = GEN_INT (val - 0x8);
-    }
-  else
-    {
-      operands[2] = GEN_INT (- 0x7);
-      operands[3] = GEN_INT (val + 0x7);
-    }
-}")
-
 (define_insn "subsi3_internal_2"
   [(set (match_operand:DI 0 "register_operand" "=d")
-	(sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
-				  (match_operand:SI 2 "arith_operand" "dI"))))]
-  "TARGET_64BIT && !TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
-  "*
-{
-  return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
-    ? \"addu\\t%0,%z1,%n2\"
-    : \"subu\\t%0,%z1,%2\";
-}"
+	(sign_extend:DI
+	    (minus:SI (match_operand:SI 1 "register_operand" "d")
+		      (match_operand:SI 2 "register_operand" "d"))))]
+  "TARGET_64BIT"
+  "subu\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
-
-(define_insn ""
-  [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-	(sign_extend:DI (minus:SI (match_operand:SI 1 "register_operand" "0,d,d")
-				  (match_operand:SI 2 "arith_operand" "I,O,d"))))]
-  "TARGET_64BIT && TARGET_MIPS16
-   && (GET_CODE (operands[2]) != CONST_INT
-       || (INTVAL (operands[2]) != -32768 && INTVAL (operands[2]) != -0x4000))"
-  "*
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]))
-    return \"subu\\t%0,%2\";
-  return \"subu\\t%0,%1,%2\";
-}"
-  [(set_attr "type"	"arith")
-   (set_attr "mode"	"SI")
-   (set_attr_alternative "length"
-		[(if_then_else (match_operand:VOID 2 "m16_nsimm8_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (if_then_else (match_operand:VOID 2 "m16_nsimm4_1" "")
-			       (const_int 4)
-			       (const_int 8))
-		 (const_int 4)])])
-
-
 
 ;;
 ;;  ....................
@@ -1732,87 +1363,63 @@
 ;;  ....................
 ;;
 
-;; Early Vr4300 silicon has a CPU bug where multiplies with certain
-;; operands may corrupt immediately following multiplies. This is a
-;; simple fix to insert NOPs.
-
 (define_expand "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (match_operand:DF 1 "register_operand" "f")
 		 (match_operand:DF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
-{
-  if (!TARGET_MIPS4300)
-    emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
-  else
-    emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
+  "")
 
 (define_insn "muldf3_internal"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (match_operand:DF 1 "register_operand" "f")
 		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
-  "mul.d\\t%0,%1,%2"
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
+  "mul.d\t%0,%1,%2"
   [(set_attr "type"	"fmul")
    (set_attr "mode"	"DF")])
 
+;; Early VR4300 silicon has a CPU bug where multiplies with certain
+;; operands may corrupt immediately following multiplies. This is a
+;; simple fix to insert NOPs.
+
 (define_insn "muldf3_r4300"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(mult:DF (match_operand:DF 1 "register_operand" "f")
 		 (match_operand:DF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
-  "*
-{
-  output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
-  if (TARGET_4300_MUL_FIX)
-    output_asm_insn (\"nop\", operands);
-  return \"\";
-}"
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
+  "mul.d\t%0,%1,%2\;nop"
   [(set_attr "type"	"fmul")
    (set_attr "mode"	"DF")
-   (set_attr "length"	"8")])	;; mul.d + nop
+   (set_attr "length"	"8")])
 
 (define_expand "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(mult:SF (match_operand:SF 1 "register_operand" "f")
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "
-{
-  if (!TARGET_MIPS4300)
-    emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
-  else
-    emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
+  "")
 
 (define_insn "mulsf3_internal"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(mult:SF (match_operand:SF 1 "register_operand" "f")
 		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
-  "mul.s\\t%0,%1,%2"
+  "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
+  "mul.s\t%0,%1,%2"
   [(set_attr "type"	"fmul")
    (set_attr "mode"	"SF")])
 
+;; See muldf3_r4300.
+
 (define_insn "mulsf3_r4300"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(mult:SF (match_operand:SF 1 "register_operand" "f")
 		 (match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT && TARGET_MIPS4300"
-  "*
-{
-  output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
-  if (TARGET_4300_MUL_FIX)
-    output_asm_insn (\"nop\", operands);
-  return \"\";
-}"
+  "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
+  "mul.s\t%0,%1,%2\;nop"
   [(set_attr "type"	"fmul")
    (set_attr "mode"	"SF")
-   (set_attr "length"	"8")])	;; mul.s + nop
+   (set_attr "length"	"8")])
 
 
 ;; ??? The R4000 (only) has a cpu bug.  If a double-word shift executes while
@@ -1824,7 +1431,6 @@
 	(mult:SI (match_operand:SI 1 "register_operand" "")
 		 (match_operand:SI 2 "register_operand" "")))]
   ""
-  "
 {
   if (GENERATE_MULT3_SI || TARGET_MAD)
     emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
@@ -1833,7 +1439,7 @@
   else
     emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
   DONE;
-}")
+})
 
 (define_insn "mulsi3_mult3"
   [(set (match_operand:SI 0 "register_operand" "=d,l")
@@ -1843,19 +1449,20 @@
    (clobber (match_scratch:SI 4 "=l,X"))]
   "GENERATE_MULT3_SI
    || TARGET_MAD"
-  "*
 {
   if (which_alternative == 1)
-    return \"mult\\t%1,%2\";
+    return "mult\t%1,%2";
   if (TARGET_MAD
       || TARGET_MIPS5400
       || TARGET_MIPS5500
+      || TARGET_MIPS7000
+      || TARGET_MIPS9000
       || ISA_MIPS32
       || ISA_MIPS32R2
       || ISA_MIPS64)
-    return \"mul\\t%0,%1,%2\";
-  return \"mult\\t%0,%1,%2\";
-}"
+    return "mul\t%0,%1,%2";
+  return "mult\t%0,%1,%2";
+}
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
 
@@ -1894,7 +1501,7 @@
 		 (match_operand:SI 2 "register_operand" "d")))
    (clobber (match_scratch:SI 3 "=h"))]
   "!TARGET_MIPS4000 || TARGET_MIPS16"
-  "mult\\t%1,%2"
+  "mult\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
 
@@ -1933,15 +1540,14 @@
   "(TARGET_MIPS3900
    || ISA_HAS_MADD_MSUB)
    && !TARGET_MIPS16"
-  "*
 {
-  static const char *const madd[] = { \"madd\\t%1,%2\", \"madd\\t%0,%1,%2\" };
+  static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
   if (which_alternative == 2)
-    return \"#\";
+    return "#";
   if (ISA_HAS_MADD_MSUB && which_alternative != 0)
-    return \"#\";
+    return "#";
   return madd[which_alternative];
-}"
+}
   [(set_attr "type"	"imadd,imadd,multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"4,4,8")])
@@ -1994,15 +1600,14 @@
    (clobber (match_scratch:SI 4 "=h,h"))
    (clobber (match_scratch:SI 5 "=X,3"))]
   "ISA_HAS_MACC"
-  "*
 {
   if (which_alternative == 1)
-    return \"macc\\t%0,%1,%2\";
+    return "macc\t%0,%1,%2";
   else if (TARGET_MIPS5500)
-    return \"madd\\t%1,%2\";
+    return "madd\t%1,%2";
   else
-    return \"macc\\t%.,%1,%2\";
-}"
+    return "macc\t%.,%1,%2";
+}
   [(set_attr "type" "imadd")
    (set_attr "mode" "SI")])
 
@@ -2018,7 +1623,7 @@
 		 (match_dup 0)))
    (clobber (match_scratch:SI 4 "=h"))]
   "ISA_HAS_MACC && reload_completed"
-  "macc\\t%3,%1,%2"
+  "macc\t%3,%1,%2"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
 
@@ -2140,12 +1745,10 @@
    (clobber (match_scratch:SI 5 "=X,1,l"))
    (clobber (match_scratch:SI 6 "=X,X,&d"))]
   "ISA_HAS_MADD_MSUB"
-  "*
-{
-  if (which_alternative != 0)
-    return \"#\";
-  return \"msub\\t%2,%3\";
-}"
+  "@
+   msub\t%2,%3
+   #
+   #"
   [(set_attr "type"     "imadd,multi,multi")
    (set_attr "mode"     "SI")
    (set_attr "length"   "4,8,8")])
@@ -2198,8 +1801,8 @@
    (clobber (match_scratch:SI              4                    "=X,l"))]
   "ISA_HAS_MULS"
   "@
-   muls\\t$0,%1,%2
-   muls\\t%0,%1,%2"
+   muls\t$0,%1,%2
+   muls\t%0,%1,%2"
   [(set_attr "type"     "imul")
    (set_attr "mode"     "SI")])
 
@@ -2211,15 +1814,14 @@
    (clobber (match_scratch:SI 4 "=h,h"))
    (clobber (match_scratch:SI 5 "=X,1"))]
   "ISA_HAS_MSAC"
-  "*
 {
   if (which_alternative == 1)
-    return \"msac\\t%0,%2,%3\";
+    return "msac\t%0,%2,%3";
   else if (TARGET_MIPS5500)
-    return \"msub\\t%2,%3\";
+    return "msub\t%2,%3";
   else
-    return \"msac\\t$0,%2,%3\";
-}"
+    return "msac\t$0,%2,%3";
+}
   [(set_attr "type"     "imadd")
    (set_attr "mode"     "SI")])
 
@@ -2228,15 +1830,13 @@
 	(mult:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "register_operand" "")))]
   "TARGET_64BIT"
-
-  "
 {
   if (GENERATE_MULT3_DI || TARGET_MIPS4000)
     emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
   else
     emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
   DONE;
-}")
+})
 
 (define_insn "muldi3_internal"
   [(set (match_operand:DI 0 "register_operand" "=l")
@@ -2244,7 +1844,7 @@
 		 (match_operand:DI 2 "register_operand" "d")))
    (clobber (match_scratch:DI 3 "=h"))]
   "TARGET_64BIT && !TARGET_MIPS4000"
-  "dmult\\t%1,%2"
+  "dmult\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"DI")])
 
@@ -2255,12 +1855,12 @@
    (clobber (match_scratch:DI 3 "=h"))
    (clobber (match_scratch:DI 4 "=l"))]
   "TARGET_64BIT && (GENERATE_MULT3_DI || TARGET_MIPS4000)"
-  {
-    if (GENERATE_MULT3_DI)
-      return "dmult\t%0,%1,%2";
-    else
-      return "dmult\t%1,%2\n\tmflo\t%0";
-  }
+{
+  if (GENERATE_MULT3_DI)
+    return "dmult\t%0,%1,%2";
+  else
+    return "dmult\t%1,%2\;mflo\t%0";
+}
   [(set_attr "type"	"imul")
    (set_attr "mode"	"DI")
    (set (attr "length")
@@ -2280,13 +1880,13 @@
        (clobber (scratch:DI))
        (clobber (scratch:DI))])]
   ""
-  {
-    if (!TARGET_64BIT)
-      {
-	emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2]));
-	DONE;
-      }
-   })
+{
+  if (!TARGET_64BIT)
+    {
+      emit_insn (gen_mulsidi3_32bit (operands[0], operands[1], operands[2]));
+      DONE;
+    }
+})
 
 (define_insn "mulsidi3_32bit"
   [(set (match_operand:DI 0 "register_operand" "=x")
@@ -2294,7 +1894,7 @@
 	   (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	   (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
   "!TARGET_64BIT"
-  "mult\\t%1,%2"
+  "mult\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
 
@@ -2359,12 +1959,12 @@
 	      (match_operator:DI 5 "extend_operator" [(match_dup 3)]))
 	   (const_int 32)))]
   "TARGET_64BIT && GET_CODE (operands[4]) == GET_CODE (operands[5])"
-  {
-    if (GET_CODE (operands[4]) == SIGN_EXTEND)
-      return "mult\t%2,%3";
-    else
-      return "multu\t%2,%3";
-  }
+{
+  if (GET_CODE (operands[4]) == SIGN_EXTEND)
+    return "mult\t%2,%3";
+  else
+    return "multu\t%2,%3";
+}
   [(set_attr "type" "imul")
    (set_attr "mode" "SI")])
 
@@ -2378,14 +1978,14 @@
        (clobber (scratch:DI))
        (clobber (scratch:DI))])]
   ""
-  {
-    if (!TARGET_64BIT)
-      {
-        emit_insn (gen_umulsidi3_32bit (operands[0], operands[1],
-					operands[2]));
-	DONE;
-      }
-  })
+{
+  if (!TARGET_64BIT)
+    {
+      emit_insn (gen_umulsidi3_32bit (operands[0], operands[1],
+				      operands[2]));
+      DONE;
+    }
+})
 
 (define_insn "umulsidi3_32bit"
   [(set (match_operand:DI 0 "register_operand" "=x")
@@ -2393,7 +1993,7 @@
 	   (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	   (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
   "!TARGET_64BIT"
-  "multu\\t%1,%2"
+  "multu\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")])
 
@@ -2405,7 +2005,7 @@
 	  (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	  (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
   "!TARGET_64BIT && ISA_HAS_MULS"
-  "muls\\t$0,%1,%2"
+  "muls\t$0,%1,%2"
   [(set_attr "type"     "imul")
    (set_attr "length"   "4")
    (set_attr "mode"     "SI")])
@@ -2417,7 +2017,7 @@
 	  (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	  (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
   "!TARGET_64BIT && ISA_HAS_MULS"
-  "mulsu\\t$0,%1,%2"
+  "mulsu\t$0,%1,%2"
   [(set_attr "type"     "imul")
    (set_attr "length"   "4")
    (set_attr "mode"     "SI")])
@@ -2430,13 +2030,12 @@
 	      (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
   "!TARGET_64BIT && ISA_HAS_MSAC"
-  "*
 {
   if (TARGET_MIPS5500)
-    return \"msub\\t%1,%2\";
+    return "msub\t%1,%2";
   else
-    return \"msac\\t$0,%1,%2\";
-}"
+    return "msac\t$0,%1,%2";
+}
   [(set_attr "type"     "imadd")
    (set_attr "length"   "4")
    (set_attr "mode"     "SI")])
@@ -2449,13 +2048,12 @@
 	      (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
 	      (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
   "!TARGET_64BIT && ISA_HAS_MSAC"
-  "*
 {
   if (TARGET_MIPS5500)
-    return \"msubu\\t%1,%2\";
+    return "msubu\t%1,%2";
   else
-    return \"msacu\\t$0,%1,%2\";
-}"
+    return "msacu\t$0,%1,%2";
+}
   [(set_attr "type"     "imadd")
    (set_attr "length"   "4")
    (set_attr "mode"     "SI")])
@@ -2469,7 +2067,6 @@
 		   (zero_extend:DI (match_operand:SI 2 "register_operand" "")))
 	  (const_int 32))))]
   ""
-  "
 {
   if (ISA_HAS_MULHI)
     emit_insn (gen_umulsi3_highpart_mulhi_internal (operands[0], operands[1],
@@ -2478,7 +2075,7 @@
     emit_insn (gen_umulsi3_highpart_internal (operands[0], operands[1],
 					      operands[2]));
   DONE;
-}")
+})
 
 (define_insn "umulsi3_highpart_internal"
   [(set (match_operand:SI 0 "register_operand" "=h")
@@ -2489,7 +2086,7 @@
 	  (const_int 32))))
    (clobber (match_scratch:SI 3 "=l"))]
   "!ISA_HAS_MULHI"
-  "multu\\t%1,%2"
+  "multu\t%1,%2"
   [(set_attr "type"   "imul")
    (set_attr "mode"   "SI")
    (set_attr "length" "4")])
@@ -2505,8 +2102,8 @@
    (clobber (match_scratch:SI 4 "=X,h"))]
   "ISA_HAS_MULHI"
   "@
-   multu\\t%1,%2
-   mulhiu\\t%0,%1,%2"
+   multu\t%1,%2
+   mulhiu\t%0,%1,%2"
   [(set_attr "type"   "imul")
    (set_attr "mode"   "SI")
    (set_attr "length" "4")])
@@ -2523,8 +2120,8 @@
    (clobber (match_scratch:SI 4 "=X,h"))]
   "ISA_HAS_MULHI"
   "@
-   mulshiu\\t%.,%1,%2
-   mulshiu\\t%0,%1,%2"
+   mulshiu\t%.,%1,%2
+   mulshiu\t%0,%1,%2"
   [(set_attr "type"   "imul")
    (set_attr "mode"   "SI")
    (set_attr "length" "4")])
@@ -2537,7 +2134,6 @@
 		   (sign_extend:DI (match_operand:SI 2 "register_operand" "")))
          (const_int 32))))]
   ""
-  "
 {
   if (ISA_HAS_MULHI)
     emit_insn (gen_smulsi3_highpart_mulhi_internal (operands[0], operands[1],
@@ -2546,7 +2142,7 @@
     emit_insn (gen_smulsi3_highpart_internal (operands[0], operands[1],
 					      operands[2]));
   DONE;
-}")
+})
 
 (define_insn "smulsi3_highpart_internal"
   [(set (match_operand:SI 0 "register_operand" "=h")
@@ -2557,7 +2153,7 @@
 	  (const_int 32))))
    (clobber (match_scratch:SI 3 "=l"))]
   "!ISA_HAS_MULHI"
-  "mult\\t%1,%2"
+  "mult\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"SI")
    (set_attr "length"   "4")])
@@ -2573,8 +2169,8 @@
    (clobber (match_scratch:SI 4 "=X,h"))]
   "ISA_HAS_MULHI"
   "@
-   mult\\t%1,%2
-   mulhi\\t%0,%1,%2"
+   mult\t%1,%2
+   mulhi\t%0,%1,%2"
   [(set_attr "type"   "imul")
    (set_attr "mode"   "SI")
    (set_attr "length" "4")])
@@ -2591,8 +2187,8 @@
    (clobber (match_scratch:SI 4 "=X,h"))]
   "ISA_HAS_MULHI"
   "@
-   mulshi\\t%.,%1,%2
-   mulshi\\t%0,%1,%2"
+   mulshi\t%.,%1,%2
+   mulshi\t%0,%1,%2"
   [(set_attr "type"   "imul")
    (set_attr "mode"   "SI")])
 
@@ -2606,7 +2202,7 @@
          (const_int 64))))
    (clobber (match_scratch:DI 3 "=l"))]
   "TARGET_64BIT"
-  "dmult\\t%1,%2"
+  "dmult\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"DI")])
 
@@ -2620,7 +2216,7 @@
 	  (const_int 64))))
    (clobber (match_scratch:DI 3 "=l"))]
   "TARGET_64BIT"
-  "dmultu\\t%1,%2"
+  "dmultu\t%1,%2"
   [(set_attr "type"	"imul")
    (set_attr "mode"	"DI")])
 
@@ -2635,7 +2231,7 @@
 		 (match_dup 0)))
    (clobber (match_scratch:SI 3 "=h"))]
   "TARGET_MAD"
-  "mad\\t%1,%2"
+  "mad\t%1,%2"
   [(set_attr "type"	"imadd")
    (set_attr "mode"	"SI")])
 
@@ -2647,15 +2243,14 @@
 	 (match_operand:DI 3 "register_operand" "0")))]
   "(TARGET_MAD || ISA_HAS_MACC)
    && !TARGET_64BIT"
-  "*
 {
   if (TARGET_MAD)
-    return \"madu\\t%1,%2\";
+    return "madu\t%1,%2";
   else if (TARGET_MIPS5500)
-    return \"maddu\\t%1,%2\";
+    return "maddu\t%1,%2";
   else
-    return \"maccu\\t%.,%1,%2\";
-}"
+    return "maccu\t%.,%1,%2";
+}
   [(set_attr "type"   "imadd")
    (set_attr "mode"   "SI")])
 
@@ -2668,15 +2263,14 @@
 	 (match_operand:DI 3 "register_operand" "0")))]
   "(TARGET_MAD || ISA_HAS_MACC)
    && !TARGET_64BIT"
-  "*
 {
   if (TARGET_MAD)
-    return \"mad\\t%1,%2\";
+    return "mad\t%1,%2";
   else if (TARGET_MIPS5500)
-    return \"madd\\t%1,%2\";
+    return "madd\t%1,%2";
   else
-    return \"macc\\t%.,%1,%2\";
-}"
+    return "macc\t%.,%1,%2";
+}
   [(set_attr "type"   "imadd")
    (set_attr "mode"   "SI")])
 
@@ -2688,7 +2282,7 @@
 			  (match_operand:DF 2 "register_operand" "f"))
 		 (match_operand:DF 3 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
-  "madd.d\\t%0,%3,%1,%2"
+  "madd.d\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"DF")])
 
@@ -2698,7 +2292,7 @@
 			  (match_operand:SF 2 "register_operand" "f"))
 		 (match_operand:SF 3 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "madd.s\\t%0,%3,%1,%2"
+  "madd.s\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")])
 
@@ -2708,7 +2302,7 @@
 			   (match_operand:DF 2 "register_operand" "f"))
 		  (match_operand:DF 3 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
-  "msub.d\\t%0,%3,%1,%2"
+  "msub.d\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"DF")])
 
@@ -2719,7 +2313,7 @@
 		  (match_operand:SF 3 "register_operand" "f")))]
 
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "msub.s\\t%0,%3,%1,%2"
+  "msub.s\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")])
 
@@ -2729,7 +2323,7 @@
 				  (match_operand:DF 2 "register_operand" "f"))
 			 (match_operand:DF 3 "register_operand" "f"))))]
   "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
-  "nmadd.d\\t%0,%3,%1,%2"
+  "nmadd.d\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"DF")])
 
@@ -2739,7 +2333,7 @@
 				  (match_operand:SF 2 "register_operand" "f"))
 			 (match_operand:SF 3 "register_operand" "f"))))]
   "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "nmadd.s\\t%0,%3,%1,%2"
+  "nmadd.s\t%0,%3,%1,%2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")])
 
@@ -2749,7 +2343,7 @@
 		  (mult:DF (match_operand:DF 2 "register_operand" "f")
 			   (match_operand:DF 3 "register_operand" "f"))))]
   "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FUSED_MADD"
-  "nmsub.d\\t%0,%1,%2,%3"
+  "nmsub.d\t%0,%1,%2,%3"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"DF")])
 
@@ -2759,7 +2353,7 @@
 		  (mult:SF (match_operand:SF 2 "register_operand" "f")
 			   (match_operand:SF 3 "register_operand" "f"))))]
   "ISA_HAS_NMADD_NMSUB && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
-  "nmsub.s\\t%0,%1,%2,%3"
+  "nmsub.s\t%0,%1,%2,%3"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")])
 
@@ -2771,41 +2365,127 @@
 ;;  ....................
 ;;
 
-(define_insn "divdf3"
+(define_expand "divdf3"
+  [(set (match_operand:DF 0 "register_operand" "")
+	(div:DF (match_operand:DF 1 "reg_or_const_float_1_operand" "")
+		(match_operand:DF 2 "register_operand" "")))]
+  "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
+{
+  if (const_float_1_operand (operands[1], DFmode))
+    if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+      FAIL;
+})
+
+;; This pattern works around the early SB-1 rev2 core "F1" erratum:
+;;
+;; If an mfc1 or dmfc1 happens to access the floating point register
+;; file at the same time a long latency operation (div, sqrt, recip,
+;; sqrt) iterates an intermediate result back through the floating
+;; point register file bypass, then instead returning the correct
+;; register value the mfc1 or dmfc1 operation returns the intermediate
+;; result of the long latency operation.
+;;
+;; The workaround is to insert an unconditional 'mov' from/to the
+;; long latency op destination register.
+
+(define_insn "*divdf3"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "register_operand" "f")
 		(match_operand:DF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "div.d\\t%0,%1,%2"
+{
+  if (TARGET_FIX_SB1)
+    return "div.d\t%0,%1,%2\;mov.d\t%0,%0";
+  else
+    return "div.d\t%0,%1,%2";
+}
   [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"DF")])
+   (set_attr "mode"	"DF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
+
 
-(define_insn "divsf3"
+(define_expand "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(div:SF (match_operand:SF 1 "reg_or_const_float_1_operand" "")
+		(match_operand:SF 2 "register_operand" "")))]
+  "TARGET_HARD_FLOAT"
+{
+  if (const_float_1_operand (operands[1], SFmode))
+    if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
+      FAIL;
+})
+
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
+;;
+;; This pattern works around the early SB-1 rev2 core "F2" erratum:
+;;
+;; In certain cases, div.s and div.ps may have a rounding error
+;; and/or wrong inexact flag.
+;;
+;; Therefore, we only allow div.s if not working around SB-1 rev2
+;; errata, or if working around those errata and a slight loss of
+;; precision is OK (i.e., flag_unsafe_math_optimizations is set).
+(define_insn "*divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(div:SF (match_operand:SF 1 "register_operand" "f")
 		(match_operand:SF 2 "register_operand" "f")))]
-  "TARGET_HARD_FLOAT"
-  "div.s\\t%0,%1,%2"
+  "TARGET_HARD_FLOAT && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)"
+{
+  if (TARGET_FIX_SB1)
+    return "div.s\t%0,%1,%2\;mov.s\t%0,%0";
+  else
+    return "div.s\t%0,%1,%2";
+}
   [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"SF")])
+   (set_attr "mode"	"SF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
 		(match_operand:DF 2 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
-  "recip.d\\t%0,%2"
+{
+  if (TARGET_FIX_SB1)
+    return "recip.d\t%0,%2\;mov.d\t%0,%0";
+  else
+    return "recip.d\t%0,%2";
+}
   [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"DF")])
+   (set_attr "mode"	"DF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
 		(match_operand:SF 2 "register_operand" "f")))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
-  "recip.s\\t%0,%2"
+{
+  if (TARGET_FIX_SB1)
+    return "recip.s\t%0,%2\;mov.s\t%0,%0";
+  else
+    return "recip.s\t%0,%2";
+}
   [(set_attr "type"	"fdiv")
-   (set_attr "mode"	"SF")])
+   (set_attr "mode"	"SF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
 (define_insn "divmodsi4"
   [(set (match_operand:SI 0 "register_operand" "=l")
@@ -2815,7 +2495,7 @@
 	(mod:SI (match_dup 1)
 		(match_dup 2)))]
   ""
-  { return mips_output_division ("div\\t$0,%1,%2", operands); }
+  { return mips_output_division ("div\t$0,%1,%2", operands); }
   [(set_attr "type"	"idiv")
    (set_attr "mode"	"SI")])
 
@@ -2827,7 +2507,7 @@
 	(mod:DI (match_dup 1)
 		(match_dup 2)))]
   "TARGET_64BIT"
-  { return mips_output_division ("ddiv\\t$0,%1,%2", operands); }
+  { return mips_output_division ("ddiv\t$0,%1,%2", operands); }
   [(set_attr "type"	"idiv")
    (set_attr "mode"	"DI")])
 
@@ -2839,7 +2519,7 @@
 	(umod:SI (match_dup 1)
 		 (match_dup 2)))]
   ""
-  { return mips_output_division ("divu\\t$0,%1,%2", operands); }
+  { return mips_output_division ("divu\t$0,%1,%2", operands); }
   [(set_attr "type"	"idiv")
    (set_attr "mode"	"SI")])
 
@@ -2851,9 +2531,10 @@
 	(umod:DI (match_dup 1)
 		 (match_dup 2)))]
   "TARGET_64BIT"
-  { return mips_output_division ("ddivu\\t$0,%1,%2", operands); }
+  { return mips_output_division ("ddivu\t$0,%1,%2", operands); }
   [(set_attr "type"	"idiv")
    (set_attr "mode"	"DI")])
+
 ;;
 ;;  ....................
 ;;
@@ -2861,40 +2542,83 @@
 ;;
 ;;  ....................
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
-  "sqrt.d\\t%0,%1"
+{
+  if (TARGET_FIX_SB1)
+    return "sqrt.d\t%0,%1\;mov.d\t%0,%0";
+  else
+    return "sqrt.d\t%0,%1";
+}
   [(set_attr "type"	"fsqrt")
-   (set_attr "mode"	"DF")])
+   (set_attr "mode"	"DF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
-  "sqrt.s\\t%0,%1"
+{
+  if (TARGET_FIX_SB1)
+    return "sqrt.s\t%0,%1\;mov.s\t%0,%0";
+  else
+    return "sqrt.s\t%0,%1";
+}
   [(set_attr "type"	"fsqrt")
-   (set_attr "mode"	"SF")])
+   (set_attr "mode"	"SF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(div:DF (match_operand:DF 1 "const_float_1_operand" "")
 		(sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_unsafe_math_optimizations"
-  "rsqrt.d\\t%0,%2"
+{
+  if (TARGET_FIX_SB1)
+    return "rsqrt.d\t%0,%2\;mov.d\t%0,%0";
+  else
+    return "rsqrt.d\t%0,%2";
+}
   [(set_attr "type"	"frsqrt")
-   (set_attr "mode"	"DF")])
+   (set_attr "mode"	"DF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
+;; This pattern works around the early SB-1 rev2 core "F1" erratum (see
+;; "divdf3" comment for details).
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
 		(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations"
-  "rsqrt.s\\t%0,%2"
+{
+  if (TARGET_FIX_SB1)
+    return "rsqrt.s\t%0,%2\;mov.s\t%0,%0";
+  else
+    return "rsqrt.s\t%0,%2";
+}
   [(set_attr "type"	"frsqrt")
-   (set_attr "mode"	"SF")])
-
+   (set_attr "mode"	"SF")
+   (set (attr "length")
+        (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
+                      (const_int 8)
+                      (const_int 4)))])
 
 ;;
 ;;  ....................
@@ -2910,20 +2634,19 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(abs:SI (match_operand:SI 1 "register_operand" "d")))]
   "!TARGET_MIPS16"
-  "*
 {
   operands[2] = const0_rtx;
 
   if (REGNO (operands[0]) == REGNO (operands[1]))
     {
       if (GENERATE_BRANCHLIKELY)
-	return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
+	return "%(bltzl\t%1,1f\;subu\t%0,%z2,%0\n%~1:%)";
       else
-	return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n%~1:\";
+	return "bgez\t%1,1f%#\;subu\t%0,%z2,%0\n%~1:";
     }
   else
-    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n%~1:%)\";
-}"
+    return "%(bgez\t%1,1f\;move\t%0,%1\;subu\t%0,%z2,%0\n%~1:%)";
+}
   [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"12")])
@@ -2932,7 +2655,6 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(abs:DI (match_operand:DI 1 "register_operand" "d")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
   unsigned int regno1;
   operands[2] = const0_rtx;
@@ -2943,10 +2665,10 @@
     regno1 = REGNO (XEXP (operands[1], 0));
 
   if (REGNO (operands[0]) == regno1)
-    return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
+    return "%(bltzl\t%1,1f\;dsubu\t%0,%z2,%0\n%~1:%)";
   else
-    return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n%~1:%)\";
-}"
+    return "%(bgez\t%1,1f\;move\t%0,%1\;dsubu\t%0,%z2,%0\n%~1:%)";
+}
   [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"12")])
@@ -2955,7 +2677,7 @@
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(abs:DF (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "abs.d\\t%0,%1"
+  "abs.d\t%0,%1"
   [(set_attr "type"	"fabs")
    (set_attr "mode"	"DF")])
 
@@ -2963,10 +2685,9 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "abs.s\\t%0,%1"
+  "abs.s\t%0,%1"
   [(set_attr "type"	"fabs")
    (set_attr "mode"	"SF")])
-
 
 ;;
 ;;  ....................
@@ -2982,30 +2703,27 @@
    (clobber (match_scratch:SI 2 "=&d"))
    (clobber (match_scratch:SI 3 "=&d"))]
   "!TARGET_MIPS16"
-  "*
 {
-  operands[4] = const0_rtx;
-
   if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
-    return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-%~1:\\tand\\t%2,%1,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%1,%1,1\\n\\
-%~2:%)\";
-
-  return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-%~1:\\tand\\t%2,%3,0x0001\\n\\
-\\taddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tsrl\\t%3,%3,1\\n\\
-%~2:%)\";
-}"
+    return "%(\
+move\t%0,%.\;\
+beq\t%1,%.,2f\n\
+%~1:\tand\t%2,%1,0x0001\;\
+addu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+srl\t%1,%1,1\n\
+%~2:%)";
+
+  return "%(\
+move\t%0,%.\;\
+move\t%3,%1\;\
+beq\t%3,%.,2f\n\
+%~1:\tand\t%2,%3,0x0001\;\
+addu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+srl\t%3,%3,1\n\
+%~2:%)";
+}
   [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"28")])
@@ -3016,36 +2734,31 @@ move\\t%0,%z4\\n\\
    (clobber (match_scratch:DI 2 "=&d"))
    (clobber (match_scratch:DI 3 "=&d"))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
-  operands[4] = const0_rtx;
-
   if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
-    return \"%(\\
-move\\t%0,%z4\\n\\
-\\tbeq\\t%1,%z4,2f\\n\\
-%~1:\\tand\\t%2,%1,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%1,%1,1\\n\\
-%~2:%)\";
-
-  return \"%(\\
-move\\t%0,%z4\\n\\
-\\tmove\\t%3,%1\\n\\
-\\tbeq\\t%3,%z4,2f\\n\\
-%~1:\\tand\\t%2,%3,0x0001\\n\\
-\\tdaddu\\t%0,%0,1\\n\\
-\\tbeq\\t%2,%z4,1b\\n\\
-\\tdsrl\\t%3,%3,1\\n\\
-%~2:%)\";
-}"
+    return "%(\
+move\t%0,%.\;\
+beq\t%1,%.,2f\n\
+%~1:\tand\t%2,%1,0x0001\;\
+daddu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+dsrl\t%1,%1,1\n\
+%~2:%)";
+
+  return "%(\
+move\t%0,%.\;\
+move\t%3,%1\;\
+beq\t%3,%.,2f\n\
+%~1:\tand\t%2,%3,0x0001\;\
+daddu\t%0,%0,1\;\
+beq\t%2,%.,1b\;\
+dsrl\t%3,%3,1\n\
+%~2:%)";
+}
   [(set_attr "type"	"multi")
    (set_attr "mode"	"DI")
    (set_attr "length"	"28")])
-
 
-
 ;;
 ;;  ...................
 ;;
@@ -3058,7 +2771,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(clz:SI (match_operand:SI 1 "register_operand" "d")))]
   "ISA_HAS_CLZ_CLO"
-  "clz\\t%0,%1"
+  "clz\t%0,%1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
 
@@ -3066,10 +2779,10 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(clz:DI (match_operand:DI 1 "register_operand" "d")))]
   "ISA_HAS_DCLZ_DCLO"
-  "dclz\\t%0,%1"
+  "dclz\t%0,%1"
   [(set_attr "type" "arith")
    (set_attr "mode" "DI")])
-
+
 ;;
 ;;  ....................
 ;;
@@ -3081,13 +2794,12 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(neg:SI (match_operand:SI 1 "register_operand" "d")))]
   ""
-  "*
 {
   if (TARGET_MIPS16)
-    return \"neg\\t%0,%1\";
-  operands[2] = const0_rtx;
-  return \"subu\\t%0,%z2,%1\";
-}"
+    return "neg\t%0,%1";
+  else
+    return "subu\t%0,%.,%1";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3096,7 +2808,6 @@ move\\t%0,%z4\\n\\
 		   (neg:DI (match_operand:DI 1 "register_operand" "d")))
 	      (clobber (match_dup 2))])]
   "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-  "
 {
   if (TARGET_64BIT)
     {
@@ -3105,18 +2816,14 @@ move\\t%0,%z4\\n\\
     }
 
   operands[2] = gen_reg_rtx (SImode);
-}")
+})
 
 (define_insn "negdi2_internal"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(neg:DI (match_operand:DI 1 "register_operand" "d")))
    (clobber (match_operand:SI 2 "register_operand" "=d"))]
   "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  operands[3] = const0_rtx;
-  return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
-}"
+  "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -3125,11 +2832,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(neg:DI (match_operand:DI 1 "register_operand" "d")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
-{
-  operands[2] = const0_rtx;
-  return \"dsubu\\t%0,%z2,%1\";
-}"
+  "dsubu\t%0,%.,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -3137,7 +2840,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "neg.d\\t%0,%1"
+  "neg.d\t%0,%1"
   [(set_attr "type"	"fneg")
    (set_attr "mode"	"DF")])
 
@@ -3145,7 +2848,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "neg.s\\t%0,%1"
+  "neg.s\t%0,%1"
   [(set_attr "type"	"fneg")
    (set_attr "mode"	"SF")])
 
@@ -3153,13 +2856,12 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(not:SI (match_operand:SI 1 "register_operand" "d")))]
   ""
-  "*
 {
   if (TARGET_MIPS16)
-    return \"not\\t%0,%1\";
-  operands[2] = const0_rtx;
-  return \"nor\\t%0,%z2,%1\";
-}"
+    return "not\t%0,%1";
+  else
+    return "nor\t%0,%.,%1";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3167,12 +2869,12 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(not:DI (match_operand:DI 1 "register_operand" "d")))]
   "TARGET_64BIT"
-  "*
 {
   if (TARGET_MIPS16)
-    return \"not\\t%0,%1\";
-  return \"nor\\t%0,%.,%1\";
-}"
+    return "not\t%0,%1";
+  else
+    return "nor\t%0,%.,%1";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
@@ -3184,7 +2886,7 @@ move\\t%0,%z4\\n\\
 ;;  ....................
 ;;
 
-;; Many of these instructions uses trivial define_expands, because we
+;; Many of these instructions use trivial define_expands, because we
 ;; want to use a different set of constraints when TARGET_MIPS16.
 
 (define_expand "andsi3"
@@ -3192,14 +2894,13 @@ move\\t%0,%z4\\n\\
 	(and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
   ""
-  "
 {
   if (TARGET_MIPS16)
     {
       operands[1] = force_reg (SImode, operands[1]);
       operands[2] = force_reg (SImode, operands[2]);
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3207,8 +2908,8 @@ move\\t%0,%z4\\n\\
 		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
   "!TARGET_MIPS16"
   "@
-   and\\t%0,%1,%2
-   andi\\t%0,%1,%x2"
+   and\t%0,%1,%2
+   andi\t%0,%1,%x2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3217,7 +2918,7 @@ move\\t%0,%z4\\n\\
 	(and:SI (match_operand:SI 1 "register_operand" "%0")
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
-  "and\\t%0,%2"
+  "and\t%0,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3226,14 +2927,13 @@ move\\t%0,%z4\\n\\
 	(and:DI (match_operand:DI 1 "register_operand" "")
 		(match_operand:DI 2 "uns_arith_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   if (TARGET_MIPS16)
     {
       operands[1] = force_reg (DImode, operands[1]);
       operands[2] = force_reg (DImode, operands[2]);
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3241,8 +2941,8 @@ move\\t%0,%z4\\n\\
 		(match_operand:DI 2 "uns_arith_operand" "d,K")))]
   "TARGET_64BIT && !TARGET_MIPS16"
   "@
-   and\\t%0,%1,%2
-   andi\\t%0,%1,%x2"
+   and\t%0,%1,%2
+   andi\t%0,%1,%x2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
@@ -3251,7 +2951,7 @@ move\\t%0,%z4\\n\\
 	(and:DI (match_operand:DI 1 "register_operand" "0")
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "and\\t%0,%2"
+  "and\t%0,%2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
@@ -3260,14 +2960,13 @@ move\\t%0,%z4\\n\\
 	(ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
 		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
   ""
-  "
 {
   if (TARGET_MIPS16)
     {
       operands[1] = force_reg (SImode, operands[1]);
       operands[2] = force_reg (SImode, operands[2]);
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3275,8 +2974,8 @@ move\\t%0,%z4\\n\\
 		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
   "!TARGET_MIPS16"
   "@
-   or\\t%0,%1,%2
-   ori\\t%0,%1,%x2"
+   or\t%0,%1,%2
+   ori\t%0,%1,%x2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3285,7 +2984,7 @@ move\\t%0,%z4\\n\\
 	(ior:SI (match_operand:SI 1 "register_operand" "%0")
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
-  "or\\t%0,%2"
+  "or\t%0,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3294,14 +2993,13 @@ move\\t%0,%z4\\n\\
 	(ior:DI (match_operand:DI 1 "register_operand" "")
 		(match_operand:DI 2 "uns_arith_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   if (TARGET_MIPS16)
     {
       operands[1] = force_reg (DImode, operands[1]);
       operands[2] = force_reg (DImode, operands[2]);
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3336,8 +3034,8 @@ move\\t%0,%z4\\n\\
 		(match_operand:SI 2 "uns_arith_operand" "d,K")))]
   "!TARGET_MIPS16"
   "@
-   xor\\t%0,%1,%2
-   xori\\t%0,%1,%x2"
+   xor\t%0,%1,%2
+   xori\t%0,%1,%x2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3347,9 +3045,9 @@ move\\t%0,%z4\\n\\
 		(match_operand:SI 2 "uns_arith_operand" "d,K,d")))]
   "TARGET_MIPS16"
   "@
-   xor\\t%0,%2
-   cmpi\\t%1,%2
-   cmp\\t%1,%2"
+   xor\t%0,%2
+   cmpi\t%1,%2
+   cmp\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -3364,14 +3062,13 @@ move\\t%0,%z4\\n\\
 	(xor:DI (match_operand:DI 1 "register_operand" "")
 		(match_operand:DI 2 "uns_arith_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   if (TARGET_MIPS16)
     {
       operands[1] = force_reg (DImode, operands[1]);
       operands[2] = force_reg (DImode, operands[2]);
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3390,9 +3087,9 @@ move\\t%0,%z4\\n\\
 		(match_operand:DI 2 "uns_arith_operand" "d,K,d")))]
   "TARGET_64BIT && TARGET_MIPS16"
   "@
-   xor\\t%0,%2
-   cmpi\\t%1,%2
-   cmp\\t%1,%2"
+   xor\t%0,%2
+   cmpi\t%1,%2
+   cmp\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -3407,7 +3104,7 @@ move\\t%0,%z4\\n\\
 	(and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
 		(not:SI (match_operand:SI 2 "register_operand" "d"))))]
   "!TARGET_MIPS16"
-  "nor\\t%0,%z1,%z2"
+  "nor\t%0,%z1,%z2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -3416,7 +3113,7 @@ move\\t%0,%z4\\n\\
 	(and:DI (not:DI (match_operand:DI 1 "register_operand" "d"))
 		(not:DI (match_operand:DI 2 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "nor\\t%0,%z1,%z2"
+  "nor\t%0,%z1,%z2"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")])
 
@@ -3433,7 +3130,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "cvt.s.d\\t%0,%1"
+  "cvt.s.d\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"SF")])
 
@@ -3490,7 +3187,7 @@ move\\t%0,%z4\\n\\
         (truncate:SI (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
                                   (match_operand:DI 2 "small_int" "I"))))]
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
-  "dsra\\t%0,%1,%2"
+  "dsra\t%0,%1,%2"
   [(set_attr "type" "darith")
    (set_attr "mode" "SI")])
 
@@ -3499,7 +3196,7 @@ move\\t%0,%z4\\n\\
         (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
                                   (const_int 32))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "dsra\\t%0,%1,32"
+  "dsra\t%0,%1,32"
   [(set_attr "type" "darith")
    (set_attr "mode" "SI")])
 
@@ -3545,7 +3242,7 @@ move\\t%0,%z4\\n\\
         (zero_extend:SI (truncate:HI
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xffff"
+  "andi\t%0,%1,0xffff"
   [(set_attr "type"     "darith")
    (set_attr "mode"     "SI")])
 
@@ -3554,7 +3251,7 @@ move\\t%0,%z4\\n\\
         (zero_extend:SI (truncate:QI
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xff"
+  "andi\t%0,%1,0xff"
   [(set_attr "type"     "darith")
    (set_attr "mode"     "SI")])
 
@@ -3563,10 +3260,9 @@ move\\t%0,%z4\\n\\
         (zero_extend:HI (truncate:QI
                          (match_operand:DI 1 "register_operand" "d"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "andi\\t%0,%1,0xff"
+  "andi\t%0,%1,0xff"
   [(set_attr "type"     "darith")
    (set_attr "mode"     "HI")])
-
 
 ;;
 ;;  ....................
@@ -3604,7 +3300,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "")
         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
   ""
-  "
 {
   if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
     {
@@ -3614,7 +3309,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_andsi3 (operands[0], op, temp));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3639,7 +3334,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "")
         (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
     {
@@ -3649,7 +3343,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_anddi3 (operands[0], op, temp));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3674,7 +3368,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:HI 0 "register_operand" "")
 	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
   ""
-  "
 {
   if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
     {
@@ -3685,7 +3378,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_andsi3 (op0, op1, temp));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=d,d")
@@ -3710,7 +3403,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
   ""
-  "
 {
   if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
     {
@@ -3720,7 +3412,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_andsi3 (operands[0], op, temp));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3745,7 +3437,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "")
 	(zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   if (TARGET_MIPS16 && GET_CODE (operands[1]) != MEM)
     {
@@ -3755,7 +3446,7 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_anddi3 (operands[0], op, temp));
       DONE;
     }
-}")
+})
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3790,15 +3481,14 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "register_operand" "")
         (sign_extend:DI (match_operand:SI 1 "move_operand" "")))]
   "TARGET_64BIT"
-  "
 {
- if (symbolic_operand (operands[1], SImode))
-   {
-      emit_move_insn (operands[0], convert_memory_address (DImode, operands[1]));
+  if (symbolic_operand (operands[1], SImode))
+    {
+      emit_move_insn (operands[0],
+		      convert_memory_address (DImode, operands[1]));
       DONE;
-   }
-
-}")
+    }
+})
 
 (define_insn "*extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3852,14 +3542,14 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "")
         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
   ""
-  "
-   if (ISA_HAS_SEB_SEH)
-     {
-        emit_insn (gen_extendhisi2_hw (operands[0],
-				       force_reg (HImode, operands[1])));
-        DONE;
-     }
-")
+{
+  if (ISA_HAS_SEB_SEH)
+    {
+      emit_insn (gen_extendhisi2_hw (operands[0],
+				     force_reg (HImode, operands[1])));
+      DONE;
+    }
+})
 
 (define_insn "*extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -3889,7 +3579,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
   "ISA_HAS_SEB_SEH"
-  "seh\\t%0,%1"
+  "seh\t%0,%1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
 
@@ -3929,14 +3619,14 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "")
         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
   ""
-  "
-   if (ISA_HAS_SEB_SEH)
-     {
-       emit_insn (gen_extendqisi2_hw (operands[0],
-                                      force_reg (QImode, operands[1])));
-       DONE;
-     }
-")
+{
+  if (ISA_HAS_SEB_SEH)
+    {
+      emit_insn (gen_extendqisi2_hw (operands[0],
+				     force_reg (QImode, operands[1])));
+      DONE;
+    }
+})
 
 (define_insn "*extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -3966,7 +3656,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
   "ISA_HAS_SEB_SEH"
-  "seb\\t%0,%1"
+  "seb\t%0,%1"
   [(set_attr "type" "arith")
    (set_attr "mode" "SI")])
 
@@ -4004,12 +3694,10 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "cvt.d.s\\t%0,%1"
+  "cvt.d.s\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")])
-
 
-
 ;;
 ;;  ....................
 ;;
@@ -4043,11 +3731,12 @@ move\\t%0,%z4\\n\\
 	(fix:SI (match_operand:DF 1 "register_operand" "f")))
    (clobber (match_scratch:DF 2 "=d"))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
-  {
-    if (set_nomacro)
-      return ".set\tmacro\n\ttrunc.w.d %0,%1,%2\n\t.set\tmacro";
+{
+  if (set_nomacro)
+    return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
+  else
     return "trunc.w.d %0,%1,%2";
-  }
+}
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
    (set_attr "length"	"36")])
@@ -4078,23 +3767,16 @@ move\\t%0,%z4\\n\\
 	(fix:SI (match_operand:SF 1 "register_operand" "f")))
    (clobber (match_scratch:SF 2 "=d"))]
   "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
-  {
-    if (set_nomacro)
-      return ".set\tmacro\n\ttrunc.w.s %0,%1,%2\n\t.set\tmacro";
+{
+  if (set_nomacro)
+    return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
+  else
     return "trunc.w.s %0,%1,%2";
-  }
+}
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
    (set_attr "length"	"36")])
 
-;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU.  It is not mentioned at all
-;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
-
-;;; Deleting this means that we now need two libgcc2.a libraries.  One for
-;;; the 32 bit calling convention and one for the 64 bit calling convention.
-
-;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
@@ -4106,9 +3788,6 @@ move\\t%0,%z4\\n\\
    (set_attr "length"	"4")])
 
 
-;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
-;;; but not in the chapter that describes the FPU.  It is not mentioned at all
-;;; in the 1991 manuals.  The r4000 at Cygnus does not have this instruction.
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
 	(fix:DI (match_operand:SF 1 "register_operand" "f")))]
@@ -4123,7 +3802,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float:DF (match_operand:SI 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "cvt.d.w\\t%0,%1"
+  "cvt.d.w\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4")])
@@ -4133,7 +3812,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(float:DF (match_operand:DI 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
-  "cvt.d.l\\t%0,%1"
+  "cvt.d.l\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"DF")
    (set_attr "length"	"4")])
@@ -4143,7 +3822,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:SI 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "cvt.s.w\\t%0,%1"
+  "cvt.s.w\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
@@ -4153,7 +3832,7 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:DI 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
-  "cvt.s.l\\t%0,%1"
+  "cvt.s.l\t%0,%1"
   [(set_attr "type"	"fcvt")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
@@ -4163,7 +3842,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "register_operand" "")
 	(unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
 {
   rtx reg1 = gen_reg_rtx (DFmode);
   rtx reg2 = gen_reg_rtx (DFmode);
@@ -4202,14 +3880,13 @@ move\\t%0,%z4\\n\\
       emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
       DONE;
     }
-}")
+})
 
 
 (define_expand "fixuns_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "")
 	(unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "
 {
   rtx reg1 = gen_reg_rtx (DFmode);
   rtx reg2 = gen_reg_rtx (DFmode);
@@ -4220,42 +3897,38 @@ move\\t%0,%z4\\n\\
 
   real_2expN (&offset, 63);
 
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
-      do_pending_stack_adjust ();
+  emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
+  do_pending_stack_adjust ();
 
-      emit_insn (gen_cmpdf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
+  emit_insn (gen_cmpdf (operands[1], reg1));
+  emit_jump_insn (gen_bge (label1));
 
-      emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
-				   gen_rtx_LABEL_REF (VOIDmode, label2)));
-      emit_barrier ();
+  emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
+  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+			       gen_rtx_LABEL_REF (VOIDmode, label2)));
+  emit_barrier ();
 
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
-      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
+  emit_label (label1);
+  emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
+  emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
+  emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
-      emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
-      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+  emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
+  emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
 
-      emit_label (label2);
+  emit_label (label2);
 
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
+  /* allow REG_NOTES to be set on last insn (labels don't have enough
+     fields, and can't be used for REG_NOTES anyway).  */
+  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+  DONE;
+})
 
 
 (define_expand "fixuns_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "")
 	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   rtx reg1 = gen_reg_rtx (SFmode);
   rtx reg2 = gen_reg_rtx (SFmode);
@@ -4266,42 +3939,38 @@ move\\t%0,%z4\\n\\
 
   real_2expN (&offset, 31);
 
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
-      do_pending_stack_adjust ();
+  emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+  do_pending_stack_adjust ();
 
-      emit_insn (gen_cmpsf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
+  emit_insn (gen_cmpsf (operands[1], reg1));
+  emit_jump_insn (gen_bge (label1));
 
-      emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
-				   gen_rtx_LABEL_REF (VOIDmode, label2)));
-      emit_barrier ();
+  emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
+  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+			       gen_rtx_LABEL_REF (VOIDmode, label2)));
+  emit_barrier ();
 
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
-				     (BITMASK_HIGH, SImode)));
+  emit_label (label1);
+  emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+  emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
+				 (BITMASK_HIGH, SImode)));
 
-      emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
-      emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
+  emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
+  emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
 
-      emit_label (label2);
+  emit_label (label2);
 
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
+  /* allow REG_NOTES to be set on last insn (labels don't have enough
+     fields, and can't be used for REG_NOTES anyway).  */
+  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+  DONE;
+})
 
 
 (define_expand "fixuns_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "")
 	(unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
-  "
 {
   rtx reg1 = gen_reg_rtx (SFmode);
   rtx reg2 = gen_reg_rtx (SFmode);
@@ -4312,36 +3981,32 @@ move\\t%0,%z4\\n\\
 
   real_2expN (&offset, 63);
 
-  if (reg1)			/* turn off complaints about unreached code */
-    {
-      emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
-      do_pending_stack_adjust ();
+  emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
+  do_pending_stack_adjust ();
 
-      emit_insn (gen_cmpsf (operands[1], reg1));
-      emit_jump_insn (gen_bge (label1));
+  emit_insn (gen_cmpsf (operands[1], reg1));
+  emit_jump_insn (gen_bge (label1));
 
-      emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
-      emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
-				   gen_rtx_LABEL_REF (VOIDmode, label2)));
-      emit_barrier ();
+  emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
+  emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
+			       gen_rtx_LABEL_REF (VOIDmode, label2)));
+  emit_barrier ();
 
-      emit_label (label1);
-      emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
-      emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
+  emit_label (label1);
+  emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
+  emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
+  emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
-      emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
-      emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
+  emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
+  emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
 
-      emit_label (label2);
-
-      /* allow REG_NOTES to be set on last insn (labels don't have enough
-	 fields, and can't be used for REG_NOTES anyway).  */
-      emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
-      DONE;
-    }
-}")
+  emit_label (label2);
 
+  /* allow REG_NOTES to be set on last insn (labels don't have enough
+     fields, and can't be used for REG_NOTES anyway).  */
+  emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
+  DONE;
+})
 
 ;;
 ;;  ....................
@@ -4358,14 +4023,14 @@ move\\t%0,%z4\\n\\
 		      (match_operand 2 "immediate_operand" "")
 		      (match_operand 3 "immediate_operand" "")))]
   "!TARGET_MIPS16"
-  {
-    if (mips_expand_unaligned_load (operands[0], operands[1],
-				    INTVAL (operands[2]),
-				    INTVAL (operands[3])))
-      DONE;
-    else
-      FAIL;
-  })
+{
+  if (mips_expand_unaligned_load (operands[0], operands[1],
+				  INTVAL (operands[2]),
+				  INTVAL (operands[3])))
+    DONE;
+  else
+    FAIL;
+})
 
 (define_expand "extzv"
   [(set (match_operand 0 "register_operand" "")
@@ -4373,14 +4038,14 @@ move\\t%0,%z4\\n\\
 		      (match_operand 2 "immediate_operand" "")
 		      (match_operand 3 "immediate_operand" "")))]
   "!TARGET_MIPS16"
-  {
-    if (mips_expand_unaligned_load (operands[0], operands[1],
-				    INTVAL (operands[2]),
-				    INTVAL (operands[3])))
-      DONE;
-    else
-      FAIL;
-  })
+{
+  if (mips_expand_unaligned_load (operands[0], operands[1],
+				  INTVAL (operands[2]),
+				  INTVAL (operands[3])))
+    DONE;
+  else
+    FAIL;
+})
 
 (define_expand "insv"
   [(set (zero_extract (match_operand:QI 0 "memory_operand" "")
@@ -4388,14 +4053,14 @@ move\\t%0,%z4\\n\\
 		      (match_operand 2 "immediate_operand" ""))
 	(match_operand 3 "reg_or_0_operand" ""))]
   "!TARGET_MIPS16"
-  {
-    if (mips_expand_unaligned_store (operands[0], operands[3],
-				     INTVAL (operands[1]),
-				     INTVAL (operands[2])))
-      DONE;
-    else
-      FAIL;
-  })
+{
+  if (mips_expand_unaligned_store (operands[0], operands[3],
+				   INTVAL (operands[1]),
+				   INTVAL (operands[2])))
+    DONE;
+  else
+    FAIL;
+})
 
 ;; Unaligned word moves generated by the bit field patterns.
 ;;
@@ -4520,7 +4185,7 @@ move\\t%0,%z4\\n\\
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "immediate_operand" "")))]
   "!TARGET_MIPS16"
-  "addiu\\t%0,%1,%R2"
+  "addiu\t%0,%1,%R2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -4529,7 +4194,7 @@ move\\t%0,%z4\\n\\
 	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:DI 2 "immediate_operand" "")))]
   "!TARGET_MIPS16 && TARGET_64BIT"
-  "daddiu\\t%0,%1,%R2"
+  "daddiu\t%0,%1,%R2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -4543,7 +4208,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(match_operand:DI 1 "" ""))]
   ""
-  "
 {
   if (mips_legitimize_move (DImode, operands[0], operands[1]))
     DONE;
@@ -4564,7 +4228,7 @@ move\\t%0,%z4\\n\\
       emit_move_insn (operands[0], force_reg (DImode, temp));
       DONE;
     }
-}")
+})
 
 ;; For mips16, we need a special case to handle storing $31 into
 ;; memory, since we don't have a constraint to match $31.  This
@@ -4662,7 +4326,6 @@ move\\t%0,%z4\\n\\
 	   && (INTVAL (operands[1]) & 7) != 0))"
   [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -4682,7 +4345,7 @@ move\\t%0,%z4\\n\\
       operands[1] = GEN_INT (off);
       operands[2] = GEN_INT (val - off);
     }
-}")
+})
 
 ;; 32-bit Integer moves
 
@@ -4694,7 +4357,6 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 	(match_operand:SI 1 "" ""))]
   ""
-  "
 {
   if (mips_legitimize_move (SImode, operands[0], operands[1]))
     DONE;
@@ -4715,7 +4377,7 @@ move\\t%0,%z4\\n\\
       emit_move_insn (operands[0], force_reg (SImode, temp));
       DONE;
     }
-}")
+})
 
 ;; We can only store $ra directly into a small sp offset.  Should the
 ;; offset be too wide, non-constant or not sp-based, leave it up to
@@ -4726,7 +4388,7 @@ move\\t%0,%z4\\n\\
 			 (match_operand:SI 0 "small_int" "n")))
 	(reg:SI 31))]
   "TARGET_MIPS16"
-  "sw\\t$31,%0($sp)"
+  "sw\t$31,%0($sp)"
   [(set_attr "type"	"store")
    (set_attr "mode"	"SI")
    (set_attr_alternative
@@ -4797,7 +4459,6 @@ move\\t%0,%z4\\n\\
 	   && (INTVAL (operands[1]) & 3) != 0))"
   [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -4817,7 +4478,7 @@ move\\t%0,%z4\\n\\
       operands[1] = GEN_INT (off);
       operands[2] = GEN_INT (val - off);
     }
-}")
+})
 
 ;; On the mips16, we can split a load of certain constants into a load
 ;; and an add.  This turns a 4 byte instruction into 2 2 byte
@@ -4834,13 +4495,12 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[1]) <= 0xff + 0x7f"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
-  "
 {
   int val = INTVAL (operands[1]);
 
   operands[1] = GEN_INT (0xff);
   operands[2] = GEN_INT (val - 0xff);
-}")
+})
 
 ;; On the mips16, we can split a load of a negative constant into a
 ;; load and a neg.  That's what mips_output_move will generate anyhow.
@@ -4856,10 +4516,7 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[1]) > - 0x8000"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 0) (neg:SI (match_dup 0)))]
-  "
-{
-  operands[1] = GEN_INT (- INTVAL (operands[1]));
-}")
+  { operands[1] = GEN_INT (- INTVAL (operands[1])); })
 
 ;; This insn handles moving CCmode values.  It's really just a
 ;; slightly simplified copy of movsi_internal2, with additional cases
@@ -4894,22 +4551,20 @@ move\\t%0,%z4\\n\\
 	(match_operand:CC 1 "general_operand" ""))
    (clobber (match_operand:TF 2 "register_operand" "=&f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
-  "
 {
   mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
 
 (define_expand "reload_outcc"
   [(set (match_operand:CC 0 "fcc_register_operand" "=z")
 	(match_operand:CC 1 "register_operand" ""))
    (clobber (match_operand:TF 2 "register_operand" "=&f"))]
   "ISA_HAS_8CC && TARGET_HARD_FLOAT"
-  "
 {
   mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
 
 ;; MIPS4 supports loading and storing a floating point register from
 ;; the sum of two general registers.  We use two versions for each of
@@ -4929,7 +4584,7 @@ move\\t%0,%z4\\n\\
 	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "lwxc1\\t%0,%1(%2)"
+  "lwxc1\t%0,%1(%2)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SF")
    (set_attr "length"   "4")])
@@ -4939,7 +4594,7 @@ move\\t%0,%z4\\n\\
 	(mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
 			 (match_operand:DI 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "lwxc1\\t%0,%1(%2)"
+  "lwxc1\t%0,%1(%2)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SF")
    (set_attr "length"   "4")])
@@ -4949,7 +4604,7 @@ move\\t%0,%z4\\n\\
 	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
 			 (match_operand:SI 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "ldxc1\\t%0,%1(%2)"
+  "ldxc1\t%0,%1(%2)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"DF")
    (set_attr "length"   "4")])
@@ -4959,7 +4614,7 @@ move\\t%0,%z4\\n\\
 	(mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
 			 (match_operand:DI 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "ldxc1\\t%0,%1(%2)"
+  "ldxc1\t%0,%1(%2)"
   [(set_attr "type"	"load")
    (set_attr "mode"	"DF")
    (set_attr "length"   "4")])
@@ -4969,7 +4624,7 @@ move\\t%0,%z4\\n\\
 			 (match_operand:SI 2 "register_operand" "d")))
 	(match_operand:SF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "swxc1\\t%0,%1(%2)"
+  "swxc1\t%0,%1(%2)"
   [(set_attr "type"	"store")
    (set_attr "mode"	"SF")
    (set_attr "length"   "4")])
@@ -4979,7 +4634,7 @@ move\\t%0,%z4\\n\\
 			 (match_operand:DI 2 "register_operand" "d")))
 	(match_operand:SF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "swxc1\\t%0,%1(%2)"
+  "swxc1\t%0,%1(%2)"
   [(set_attr "type"	"store")
    (set_attr "mode"	"SF")
    (set_attr "length"   "4")])
@@ -4989,7 +4644,7 @@ move\\t%0,%z4\\n\\
 			 (match_operand:SI 2 "register_operand" "d")))
 	(match_operand:DF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sdxc1\\t%0,%1(%2)"
+  "sdxc1\t%0,%1(%2)"
   [(set_attr "type"	"store")
    (set_attr "mode"	"DF")
    (set_attr "length"   "4")])
@@ -4999,7 +4654,7 @@ move\\t%0,%z4\\n\\
 			 (match_operand:DI 2 "register_operand" "d")))
 	(match_operand:DF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sdxc1\\t%0,%1(%2)"
+  "sdxc1\t%0,%1(%2)"
   [(set_attr "type"	"store")
    (set_attr "mode"	"DF")
    (set_attr "length"   "4")])
@@ -5009,13 +4664,12 @@ move\\t%0,%z4\\n\\
 ;; Unlike most other insns, the move insns can't be split with
 ;; different predicates, because register spilling and other parts of
 ;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
+;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
   ""
-  "
 {
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], HImode)
@@ -5028,10 +4682,7 @@ move\\t%0,%z4\\n\\
       emit_move_insn (operands[0], temp);
       DONE;
     }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
+})
 
 (define_insn "movhi_internal"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
@@ -5107,7 +4758,6 @@ move\\t%0,%z4\\n\\
 	   && (INTVAL (operands[1]) & 1) != 0))"
   [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -5127,20 +4777,19 @@ move\\t%0,%z4\\n\\
       operands[1] = GEN_INT (off);
       operands[2] = GEN_INT (val - off);
     }
-}")
+})
 
 ;; 8-bit Integer moves
 
 ;; Unlike most other insns, the move insns can't be split with
 ;; different predicates, because register spilling and other parts of
 ;; the compiler, have memoized the insn number already.
-;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
+;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 	(match_operand:QI 1 "general_operand" ""))]
   ""
-  "
 {
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], QImode)
@@ -5153,10 +4802,7 @@ move\\t%0,%z4\\n\\
       emit_move_insn (operands[0], temp);
       DONE;
     }
-}")
-
-;; The difference between these two is whether or not ints are allowed
-;; in FP registers (off by default, use -mdebugh to enable).
+})
 
 (define_insn "movqi_internal"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x,*d")
@@ -5216,7 +4862,6 @@ move\\t%0,%z4\\n\\
 	   && INTVAL (operands[1]) <= 31 + 0x7f))"
   [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
    (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
-  "
 {
   HOST_WIDE_INT val = INTVAL (operands[1]);
 
@@ -5227,7 +4872,7 @@ move\\t%0,%z4\\n\\
       operands[1] = GEN_INT (0x7f);
       operands[2] = GEN_INT (val - 0x7f);
     }
-}")
+})
 
 ;; 32-bit floating point moves
 
@@ -5235,13 +4880,12 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
   ""
-  "
 {
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], SFmode)
       && !nonmemory_operand (operands[1], SFmode))
     operands[1] = force_reg (SFmode, operands[1]);
-}")
+})
 
 (define_insn "movsf_internal1"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
@@ -5283,13 +4927,12 @@ move\\t%0,%z4\\n\\
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
-  "
 {
   if ((reload_in_progress | reload_completed) == 0
       && !register_operand (operands[0], DFmode)
       && !nonmemory_operand (operands[1], DFmode))
     operands[1] = force_reg (DFmode, operands[1]);
-}")
+})
 
 (define_insn "movdf_internal1a"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,*f,*d,*d,*d,*m")
@@ -5341,10 +4984,10 @@ move\\t%0,%z4\\n\\
   "reload_completed && !TARGET_64BIT
    && mips_split_64bit_move_p (operands[0], operands[1])"
   [(const_int 0)]
-  {
-    mips_split_64bit_move (operands[0], operands[1]);
-    DONE;
-  })
+{
+  mips_split_64bit_move (operands[0], operands[1]);
+  DONE;
+})
 
 (define_split
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
@@ -5352,10 +4995,10 @@ move\\t%0,%z4\\n\\
   "reload_completed && !TARGET_64BIT
    && mips_split_64bit_move_p (operands[0], operands[1])"
   [(const_int 0)]
-  {
-    mips_split_64bit_move (operands[0], operands[1]);
-    DONE;
-  })
+{
+  mips_split_64bit_move (operands[0], operands[1]);
+  DONE;
+})
 
 ;; Patterns for loading or storing part of a paired floating point
 ;; register.  We need them because odd-numbered floating-point registers
@@ -5367,10 +5010,10 @@ move\\t%0,%z4\\n\\
 	(unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
 		   UNSPEC_LOAD_DF_LOW))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
-  {
-    operands[0] = mips_subword (operands[0], 0);
-    return mips_output_move (operands[0], operands[1]);
-  }
+{
+  operands[0] = mips_subword (operands[0], 0);
+  return mips_output_move (operands[0], operands[1]);
+}
   [(set_attr "type"	"xfer,load")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
@@ -5383,10 +5026,10 @@ move\\t%0,%z4\\n\\
 		    (match_operand:DF 2 "register_operand" "0,0")]
 		   UNSPEC_LOAD_DF_HIGH))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
-  {
-    operands[0] = mips_subword (operands[0], 1);
-    return mips_output_move (operands[0], operands[1]);
-  }
+{
+  operands[0] = mips_subword (operands[0], 1);
+  return mips_output_move (operands[0], operands[1]);
+}
   [(set_attr "type"	"xfer,load")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
@@ -5398,10 +5041,10 @@ move\\t%0,%z4\\n\\
 	(unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
 		   UNSPEC_STORE_DF_HIGH))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
-  {
-    operands[1] = mips_subword (operands[1], 1);
-    return mips_output_move (operands[0], operands[1]);
-  }
+{
+  operands[1] = mips_subword (operands[1], 1);
+  return mips_output_move (operands[0], operands[1]);
+}
   [(set_attr "type"	"xfer,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"4")])
@@ -5441,12 +5084,12 @@ move\\t%0,%z4\\n\\
 	      (use (match_operand:SI 2 "" ""))
 	      (use (match_operand:SI 3 "const_int_operand" ""))])]
   "!TARGET_MIPS16 && !TARGET_MEMCPY"
-  {
-    if (mips_expand_block_move (operands[0], operands[1], operands[2]))
-      DONE;
-    else
-      FAIL;
-  })
+{
+  if (mips_expand_block_move (operands[0], operands[1], operands[2]))
+    DONE;
+  else
+    FAIL;
+})
 
 ;;
 ;;  ....................
@@ -5455,7 +5098,7 @@ move\\t%0,%z4\\n\\
 ;;
 ;;  ....................
 
-;; Many of these instructions uses trivial define_expands, because we
+;; Many of these instructions use trivial define_expands, because we
 ;; want to use a different set of constraints when TARGET_MIPS16.
 
 (define_expand "ashlsi3"
@@ -5463,7 +5106,6 @@ move\\t%0,%z4\\n\\
 	(ashift:SI (match_operand:SI 1 "register_operand" "d")
 		   (match_operand:SI 2 "arith_operand" "dI")))]
   ""
-  "
 {
   /* On the mips16, a shift of more than 8 is a four byte instruction,
      so, for a shift between 8 and 16, it is just as fast to do two
@@ -5487,20 +5129,19 @@ move\\t%0,%z4\\n\\
 					GEN_INT (INTVAL (operands[2]) - 8)));
       DONE;
     }
-}")
+})
 
 (define_insn "ashlsi3_internal1"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashift:SI (match_operand:SI 1 "register_operand" "d")
 		   (match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"sll\\t%0,%1,%2\";
-}"
+  return "sll\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -5509,13 +5150,12 @@ move\\t%0,%z4\\n\\
        (sign_extend:DI (ashift:SI (match_operand:SI 1 "register_operand" "d")
                                   (match_operand:SI 2 "arith_operand" "dI"))))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"sll\\t%0,%1,%2\";
-}"
+  return "sll\t%0,%1,%2";
+}
   [(set_attr "type"    "arith")
    (set_attr "mode"    "DI")])
 
@@ -5525,16 +5165,15 @@ move\\t%0,%z4\\n\\
 	(ashift:SI (match_operand:SI 1 "register_operand" "0,d")
 		   (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
-  "*
 {
   if (which_alternative == 0)
-    return \"sll\\t%0,%2\";
+    return "sll\t%0,%2";
 
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"sll\\t%0,%1,%2\";
-}"
+  return "sll\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -5555,10 +5194,7 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (ashift:SI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "ashldi3"
   [(parallel [(set (match_operand:DI 0 "register_operand" "")
@@ -5566,7 +5202,6 @@ move\\t%0,%z4\\n\\
 			      (match_operand:SI 2 "arith_operand" "")))
 	      (clobber (match_dup  3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
 {
   if (TARGET_64BIT)
     {
@@ -5599,7 +5234,7 @@ move\\t%0,%z4\\n\\
     }
 
   operands[3] = gen_reg_rtx (SImode);
-}")
+})
 
 
 (define_insn "ashldi3_internal"
@@ -5608,27 +5243,22 @@ move\\t%0,%z4\\n\\
 		   (match_operand:SI 2 "register_operand" "d")))
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  operands[4] = const0_rtx;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f%#\\n\\
-\\tsll\\t%M0,%L1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%L0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsll\\t%M0,%M1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsrl\\t%3,%L1,%3\\n\\
-\\tor\\t%M0,%M0,%3\\n\\
-%~2:\\n\\
-\\tsll\\t%L0,%L1,%2\\n\\
-%~3:\";
-}"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sll\t%M0,%L1,%2\;\
+%(b\t3f\;\
+move\t%L0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+sll\t%M0,%M1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+srl\t%3,%L1,%3\;\
+or\t%M0,%M0,%3\n\
+%~2:\;\
+sll\t%L0,%L1,%2\n\
+%~3:"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"48")])
@@ -5641,12 +5271,10 @@ move\\t%0,%z4\\n\\
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (INTVAL (operands[2]) & 32) != 0"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  operands[4] = const0_rtx;
-  return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
-}"
+  return "sll\t%M0,%L1,%2\;move\t%L0,%.";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -5694,16 +5322,14 @@ move\\t%0,%z4\\n\\
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (INTVAL (operands[2]) & 63) < 32
    && (INTVAL (operands[2]) & 63) != 0"
-  "*
 {
   int amount = INTVAL (operands[2]);
 
   operands[2] = GEN_INT (amount & 31);
-  operands[4] = const0_rtx;
-  operands[5] = GEN_INT ((-amount) & 31);
+  operands[4] = GEN_INT ((-amount) & 31);
 
-  return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
-}"
+  return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -5736,12 +5362,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 0)
 	(ashift:SI (subreg:SI (match_dup 1) 0)
 		   (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_split
@@ -5771,12 +5396,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 4)
 	(ashift:SI (subreg:SI (match_dup 1) 4)
 		   (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_insn "ashldi3_internal4"
@@ -5784,13 +5408,12 @@ move\\t%0,%z4\\n\\
 	(ashift:DI (match_operand:DI 1 "register_operand" "d")
 		   (match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsll\\t%0,%1,%2\";
-}"
+  return "dsll\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -5799,16 +5422,15 @@ move\\t%0,%z4\\n\\
 	(ashift:DI (match_operand:DI 1 "register_operand" "0,d")
 		   (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "*
 {
   if (which_alternative == 0)
-    return \"dsll\\t%0,%2\";
+    return "dsll\t%0,%2";
 
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsll\\t%0,%1,%2\";
-}"
+  return "dsll\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -5831,17 +5453,13 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (ashift:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   ""
-  "
 {
   /* On the mips16, a shift of more than 8 is a four byte instruction,
      so, for a shift between 8 and 16, it is just as fast to do two
@@ -5861,20 +5479,19 @@ move\\t%0,%z4\\n\\
 					GEN_INT (INTVAL (operands[2]) - 8)));
       DONE;
     }
-}")
+})
 
 (define_insn "ashrsi3_internal1"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"sra\\t%0,%1,%2\";
-}"
+  return "sra\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -5883,16 +5500,15 @@ move\\t%0,%z4\\n\\
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
 		     (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
-  "*
 {
   if (which_alternative == 0)
-    return \"sra\\t%0,%2\";
+    return "sra\t%0,%2";
 
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"sra\\t%0,%1,%2\";
-}"
+  return "sra\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -5914,10 +5530,7 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "ashrdi3"
   [(parallel [(set (match_operand:DI 0 "register_operand" "")
@@ -5925,7 +5538,6 @@ move\\t%0,%z4\\n\\
 				(match_operand:SI 2 "arith_operand" "")))
 	      (clobber (match_dup  3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
 {
   if (TARGET_64BIT)
     {
@@ -5954,7 +5566,7 @@ move\\t%0,%z4\\n\\
     }
 
   operands[3] = gen_reg_rtx (SImode);
-}")
+})
 
 
 (define_insn "ashrdi3_internal"
@@ -5963,27 +5575,22 @@ move\\t%0,%z4\\n\\
 		     (match_operand:SI 2 "register_operand" "d")))
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  operands[4] = const0_rtx;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f%#\\n\\
-\\tsra\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tsra\\t%M0,%M1,31%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsra\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+sra\t%L0,%M1,%2\;\
+%(b\t3f\;\
+sra\t%M0,%M1,31%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+sra\t%M0,%M1,%2\n\
+%~3:"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"48")])
@@ -5995,11 +5602,10 @@ move\\t%0,%z4\\n\\
 		     (match_operand:SI 2 "small_int" "IJK")))
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
-}"
+  return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -6047,15 +5653,14 @@ move\\t%0,%z4\\n\\
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (INTVAL (operands[2]) & 63) < 32
    && (INTVAL (operands[2]) & 63) != 0"
-  "*
 {
   int amount = INTVAL (operands[2]);
 
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
 
-  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
-}"
+  return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -6088,12 +5693,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 4)
 	(ashiftrt:SI (subreg:SI (match_dup 1) 4)
 		     (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_split
@@ -6123,12 +5727,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 0)
 	(ashiftrt:SI (subreg:SI (match_dup 1) 0)
 		     (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_insn "ashrdi3_internal4"
@@ -6136,13 +5739,12 @@ move\\t%0,%z4\\n\\
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsra\\t%0,%1,%2\";
-}"
+  return "dsra\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -6151,13 +5753,12 @@ move\\t%0,%z4\\n\\
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
 		     (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsra\\t%0,%2\";
-}"
+  return "dsra\t%0,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -6179,17 +5780,13 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (ashiftrt:DI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (ashiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 (define_expand "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   ""
-  "
 {
   /* On the mips16, a shift of more than 8 is a four byte instruction,
      so, for a shift between 8 and 16, it is just as fast to do two
@@ -6209,20 +5806,19 @@ move\\t%0,%z4\\n\\
 					GEN_INT (INTVAL (operands[2]) - 8)));
       DONE;
     }
-}")
+})
 
 (define_insn "lshrsi3_internal1"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"srl\\t%0,%1,%2\";
-}"
+  return "srl\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -6231,16 +5827,15 @@ move\\t%0,%z4\\n\\
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,d")
 		     (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
-  "*
 {
   if (which_alternative == 0)
-    return \"srl\\t%0,%2\";
+    return "srl\t%0,%2";
 
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
 
-  return \"srl\\t%0,%1,%2\";
-}"
+  return "srl\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -6262,10 +5857,7 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (lshiftrt:SI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 ;; If we load a byte on the mips16 as a bitfield, the resulting
 ;; sequence of instructions is too complicated for combine, because it
@@ -6280,7 +5872,7 @@ move\\t%0,%z4\\n\\
 	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
 		     (match_operand:SI 2 "immediate_operand" "I")))]
   "0 && TARGET_MIPS16"
-  "lw\\t%0,%1\;srl\\t%0,%2"
+  "lw\t%0,%1\;srl\t%0,%2"
   [(set_attr "type"	"load")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -6303,7 +5895,6 @@ move\\t%0,%z4\\n\\
 				(match_operand:SI 2 "arith_operand" "")))
 	      (clobber (match_dup  3))])]
   "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-  "
 {
   if (TARGET_64BIT)
     {
@@ -6332,7 +5923,7 @@ move\\t%0,%z4\\n\\
     }
 
   operands[3] = gen_reg_rtx (SImode);
-}")
+})
 
 
 (define_insn "lshrdi3_internal"
@@ -6341,27 +5932,22 @@ move\\t%0,%z4\\n\\
 		     (match_operand:SI 2 "register_operand" "d")))
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-  "*
-{
-  operands[4] = const0_rtx;
-
-  return \"sll\\t%3,%2,26\\n\\
-\\tbgez\\t%3,1f%#\\n\\
-\\tsrl\\t%L0,%M1,%2\\n\\
-\\t%(b\\t3f\\n\\
-\\tmove\\t%M0,%z4%)\\n\\
-\\n\\
-%~1:\\n\\
-\\t%(beq\\t%3,%z4,2f\\n\\
-\\tsrl\\t%L0,%L1,%2%)\\n\\
-\\n\\
-\\tsubu\\t%3,%z4,%2\\n\\
-\\tsll\\t%3,%M1,%3\\n\\
-\\tor\\t%L0,%L0,%3\\n\\
-%~2:\\n\\
-\\tsrl\\t%M0,%M1,%2\\n\\
-%~3:\";
-}"
+  "sll\t%3,%2,26\;\
+bgez\t%3,1f%#\;\
+srl\t%L0,%M1,%2\;\
+%(b\t3f\;\
+move\t%M0,%.%)\
+\n\n\
+%~1:\;\
+%(beq\t%3,%.,2f\;\
+srl\t%L0,%L1,%2%)\
+\n\;\
+subu\t%3,%.,%2\;\
+sll\t%3,%M1,%3\;\
+or\t%L0,%L0,%3\n\
+%~2:\;\
+srl\t%M0,%M1,%2\n\
+%~3:"
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"48")])
@@ -6374,12 +5960,10 @@ move\\t%0,%z4\\n\\
    (clobber (match_operand:SI 3 "register_operand" "=d"))]
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (INTVAL (operands[2]) & 32) != 0"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
-  operands[4] = const0_rtx;
-  return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
-}"
+  return "srl\t%L0,%M1,%2\;move\t%M0,%.";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -6427,15 +6011,14 @@ move\\t%0,%z4\\n\\
   "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
    && (INTVAL (operands[2]) & 63) < 32
    && (INTVAL (operands[2]) & 63) != 0"
-  "*
 {
   int amount = INTVAL (operands[2]);
 
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
 
-  return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
-}"
+  return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
+}
   [(set_attr "type"	"darith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -6468,12 +6051,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 4)
 	(lshiftrt:SI (subreg:SI (match_dup 1) 4)
 		     (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_split
@@ -6503,12 +6085,11 @@ move\\t%0,%z4\\n\\
    (set (subreg:SI (match_dup 0) 0)
 	(lshiftrt:SI (subreg:SI (match_dup 1) 0)
 		     (match_dup 2)))]
-  "
 {
   int amount = INTVAL (operands[2]);
   operands[2] = GEN_INT (amount & 31);
   operands[4] = GEN_INT ((-amount) & 31);
-}")
+})
 
 
 (define_insn "lshrdi3_internal4"
@@ -6516,13 +6097,12 @@ move\\t%0,%z4\\n\\
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
 		     (match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsrl\\t%0,%1,%2\";
-}"
+  return "dsrl\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -6531,13 +6111,12 @@ move\\t%0,%z4\\n\\
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
 		     (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "*
 {
   if (GET_CODE (operands[2]) == CONST_INT)
     operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
 
-  return \"dsrl\\t%0,%2\";
-}"
+  return "dsrl\t%0,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -6551,17 +6130,16 @@ move\\t%0,%z4\\n\\
         (rotatert:SI (match_operand:SI 1 "register_operand" "d")
                      (match_operand:SI 2 "arith_operand"    "dn")))]
   "ISA_HAS_ROTR_SI"
-  "*
 {
   if (TARGET_SR71K && GET_CODE (operands[2]) != CONST_INT)
-    return \"rorv\\t%0,%1,%2\";
+    return "rorv\t%0,%1,%2";
 
   if ((GET_CODE (operands[2]) == CONST_INT)
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 32))
     abort ();
 
-  return \"ror\\t%0,%1,%2\";
-}"
+  return "ror\t%0,%1,%2";
+}
   [(set_attr "type"     "arith")
    (set_attr "mode"     "SI")])
 
@@ -6570,23 +6148,22 @@ move\\t%0,%z4\\n\\
         (rotatert:DI (match_operand:DI 1 "register_operand" "d")
                      (match_operand:DI 2 "arith_operand"    "dn")))]
   "ISA_HAS_ROTR_DI"
-  "*
 {
-   if (TARGET_SR71K)
+  if (TARGET_SR71K)
     {
       if (GET_CODE (operands[2]) != CONST_INT)
-        return \"drorv\\t%0,%1,%2\";
+	return "drorv\t%0,%1,%2";
 
       if (INTVAL (operands[2]) >= 32 && INTVAL (operands[2]) <= 63)
-        return \"dror32\\t%0,%1,%2\";
+	return "dror32\t%0,%1,%2";
     }
 
   if ((GET_CODE (operands[2]) == CONST_INT)
       && (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) >= 64))
     abort ();
 
-  return \"dror\\t%0,%1,%2\";
-}"
+  return "dror\t%0,%1,%2";
+}
   [(set_attr "type"     "arith")
    (set_attr "mode"     "DI")])
 
@@ -6603,11 +6180,7 @@ move\\t%0,%z4\\n\\
    && INTVAL (operands[2]) <= 16"
   [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 8)))
    (set (match_dup 0) (lshiftrt:DI (match_dup 0) (match_dup 2)))]
-"
-{
-  operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
-}")
-
+  { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
 
 ;;
 ;;  ....................
@@ -6627,7 +6200,7 @@ move\\t%0,%z4\\n\\
 ;;	Different CC modes are used, based on what type of branch is
 ;;	done, so that we can constrain things appropriately.  There
 ;;	are assumptions in the rest of GCC that break if we fold the
-;;	operands into the branchs for integer operations, and use cc0
+;;	operands into the branches for integer operations, and use cc0
 ;;	for floating point, so we use the fp status register instead.
 ;;	If needed, an appropriate temporary is created to hold the
 ;;	of the integer compare.
@@ -6637,95 +6210,70 @@ move\\t%0,%z4\\n\\
 	(compare:CC (match_operand:SI 0 "register_operand" "")
 		    (match_operand:SI 1 "arith_operand" "")))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_SI;
-      DONE;
-    }
-}")
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = operands[1];
+  branch_type = CMP_SI;
+  DONE;
+})
 
 (define_expand "tstsi"
   [(set (cc0)
 	(match_operand:SI 0 "register_operand" ""))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = const0_rtx;
-      branch_type = CMP_SI;
-      DONE;
-    }
-}")
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = const0_rtx;
+  branch_type = CMP_SI;
+  DONE;
+})
 
 (define_expand "cmpdi"
   [(set (cc0)
 	(compare:CC (match_operand:DI 0 "register_operand" "")
 		    (match_operand:DI 1 "arith_operand" "")))]
   "TARGET_64BIT"
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_DI;
-      DONE;
-    }
-}")
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = operands[1];
+  branch_type = CMP_DI;
+  DONE;
+})
 
 (define_expand "tstdi"
   [(set (cc0)
 	(match_operand:DI 0 "register_operand" ""))]
   "TARGET_64BIT"
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = const0_rtx;
-      branch_type = CMP_DI;
-      DONE;
-    }
-}")
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = const0_rtx;
+  branch_type = CMP_DI;
+  DONE;
+})
 
 (define_expand "cmpdf"
   [(set (cc0)
 	(compare:CC (match_operand:DF 0 "register_operand" "")
 		    (match_operand:DF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_DF;
-      DONE;
-    }
-}")
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = operands[1];
+  branch_type = CMP_DF;
+  DONE;
+})
 
 (define_expand "cmpsf"
   [(set (cc0)
 	(compare:CC (match_operand:SF 0 "register_operand" "")
 		    (match_operand:SF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
-  if (operands[0])		/* avoid unused code message */
-    {
-      branch_cmp[0] = operands[0];
-      branch_cmp[1] = operands[1];
-      branch_type = CMP_SF;
-      DONE;
-    }
-}")
-
+  branch_cmp[0] = operands[0];
+  branch_cmp[1] = operands[1];
+  branch_type = CMP_SF;
+  DONE;
+})
 
 ;;
 ;;  ....................
@@ -6745,7 +6293,6 @@ move\\t%0,%z4\\n\\
          (label_ref (match_operand 1 "" ""))
          (pc)))]
   "TARGET_HARD_FLOAT"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6753,7 +6300,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/1,
 					 /*inverted_p=*/0,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6766,7 +6313,6 @@ move\\t%0,%z4\\n\\
          (pc)
          (label_ref (match_operand 1 "" ""))))]
   "TARGET_HARD_FLOAT"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6774,7 +6320,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/1,
 					 /*inverted_p=*/1,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6789,7 +6335,6 @@ move\\t%0,%z4\\n\\
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6797,7 +6342,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/0,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6810,7 +6355,6 @@ move\\t%0,%z4\\n\\
         (pc)
         (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6818,7 +6362,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/1,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6831,7 +6375,6 @@ move\\t%0,%z4\\n\\
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6839,7 +6382,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/0,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6852,7 +6395,6 @@ move\\t%0,%z4\\n\\
         (pc)
         (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6860,7 +6402,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/1,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6875,7 +6417,6 @@ move\\t%0,%z4\\n\\
          (label_ref (match_operand 1 "" ""))
          (pc)))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6883,7 +6424,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/0,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6896,7 +6437,6 @@ move\\t%0,%z4\\n\\
         (label_ref (match_operand 1 "" ""))
         (pc)))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6904,7 +6444,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/0,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6917,7 +6457,6 @@ move\\t%0,%z4\\n\\
          (pc)
          (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6925,7 +6464,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/1,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6938,7 +6477,6 @@ move\\t%0,%z4\\n\\
         (pc)
         (label_ref (match_operand 1 "" ""))))]
   "!TARGET_MIPS16"
-  "*
 {
   return mips_output_conditional_branch (insn,
 					 operands,
@@ -6946,7 +6484,7 @@ move\\t%0,%z4\\n\\
 					 /*float_p=*/0,
 					 /*inverted_p=*/1,
 					 get_attr_length (insn));
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")])
 
@@ -6960,23 +6498,22 @@ move\\t%0,%z4\\n\\
 	(match_operand 2 "pc_or_label_operand" "")
 	(match_operand 3 "pc_or_label_operand" "")))]
   "TARGET_MIPS16"
-  "*
 {
   if (operands[2] != pc_rtx)
     {
       if (which_alternative == 0)
-	return \"b%C0z\\t%1,%2\";
+	return "b%C0z\t%1,%2";
       else
-	return \"bt%C0z\\t%2\";
+	return "bt%C0z\t%2";
     }
   else
     {
       if (which_alternative == 0)
-	return \"b%N0z\\t%1,%3\";
+	return "b%N0z\t%1,%3";
       else
-	return \"bt%N0z\\t%3\";
+	return "bt%N0z\t%3";
     }
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -6989,23 +6526,22 @@ move\\t%0,%z4\\n\\
 	(match_operand 2 "pc_or_label_operand" "")
 	(match_operand 3 "pc_or_label_operand" "")))]
   "TARGET_MIPS16"
-  "*
 {
   if (operands[2] != pc_rtx)
     {
       if (which_alternative == 0)
-	return \"b%C0z\\t%1,%2\";
+	return "b%C0z\t%1,%2";
       else
-	return \"bt%C0z\\t%2\";
+	return "bt%C0z\t%2";
     }
   else
     {
       if (which_alternative == 0)
-	return \"b%N0z\\t%1,%3\";
+	return "b%N0z\t%1,%3";
       else
-	return \"bt%N0z\\t%3\";
+	return "bt%N0z\t%3";
     }
-}"
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -7017,14 +6553,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, UNORDERED);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, UNORDERED);
+  DONE;
+})
 
 (define_expand "bordered"
   [(set (pc)
@@ -7033,14 +6565,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-     {
-	gen_conditional_branch (operands, ORDERED);
-	DONE;
-     }
-}")
+  gen_conditional_branch (operands, ORDERED);
+  DONE;
+})
 
 (define_expand "bunlt"
   [(set (pc)
@@ -7049,14 +6577,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-     {
-	gen_conditional_branch (operands, UNLT);
-	DONE;
-     }
-}")
+  gen_conditional_branch (operands, UNLT);
+  DONE;
+})
 
 (define_expand "bunge"
   [(set (pc)
@@ -7065,11 +6589,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   gen_conditional_branch (operands, UNGE);
   DONE;
-}")
+})
 
 (define_expand "buneq"
   [(set (pc)
@@ -7078,14 +6601,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-     {
-	gen_conditional_branch (operands, UNEQ);
-	DONE;
-     }
-}")
+  gen_conditional_branch (operands, UNEQ);
+  DONE;
+})
 
 (define_expand "bltgt"
   [(set (pc)
@@ -7094,11 +6613,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   gen_conditional_branch (operands, LTGT);
   DONE;
-}")
+})
 
 (define_expand "bunle"
   [(set (pc)
@@ -7107,14 +6625,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-     {
-	gen_conditional_branch (operands, UNLE);
-	DONE;
-     }
-}")
+  gen_conditional_branch (operands, UNLE);
+  DONE;
+})
 
 (define_expand "bungt"
   [(set (pc)
@@ -7123,11 +6637,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   gen_conditional_branch (operands, UNGT);
   DONE;
-}")
+})
 
 (define_expand "beq"
   [(set (pc)
@@ -7136,14 +6649,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, EQ);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, EQ);
+  DONE;
+})
 
 (define_expand "bne"
   [(set (pc)
@@ -7152,14 +6661,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, NE);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, NE);
+  DONE;
+})
 
 (define_expand "bgt"
   [(set (pc)
@@ -7168,14 +6673,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GT);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, GT);
+  DONE;
+})
 
 (define_expand "bge"
   [(set (pc)
@@ -7184,14 +6685,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GE);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, GE);
+  DONE;
+})
 
 (define_expand "blt"
   [(set (pc)
@@ -7200,14 +6697,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LT);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, LT);
+  DONE;
+})
 
 (define_expand "ble"
   [(set (pc)
@@ -7216,14 +6709,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LE);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, LE);
+  DONE;
+})
 
 (define_expand "bgtu"
   [(set (pc)
@@ -7232,14 +6721,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GTU);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, GTU);
+  DONE;
+})
 
 (define_expand "bgeu"
   [(set (pc)
@@ -7248,15 +6733,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, GEU);
-      DONE;
-    }
-}")
-
+  gen_conditional_branch (operands, GEU);
+  DONE;
+})
 
 (define_expand "bltu"
   [(set (pc)
@@ -7265,14 +6745,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LTU);
-      DONE;
-    }
-}")
+  gen_conditional_branch (operands, LTU);
+  DONE;
+})
 
 (define_expand "bleu"
   [(set (pc)
@@ -7281,15 +6757,10 @@ move\\t%0,%z4\\n\\
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
-  if (operands[0])		/* avoid unused code warning */
-    {
-      gen_conditional_branch (operands, LEU);
-      DONE;
-    }
-}")
-
+  gen_conditional_branch (operands, LEU);
+  DONE;
+})
 
 ;;
 ;;  ....................
@@ -7303,7 +6774,6 @@ move\\t%0,%z4\\n\\
 	(eq:SI (match_dup 1)
 	       (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7322,7 +6792,7 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 
 (define_insn "seq_si_zero"
@@ -7330,7 +6800,7 @@ move\\t%0,%z4\\n\\
 	(eq:SI (match_operand:SI 1 "register_operand" "d")
 	       (const_int 0)))]
   "!TARGET_MIPS16"
-  "sltu\\t%0,%1,1"
+  "sltu\t%0,%1,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7339,7 +6809,7 @@ move\\t%0,%z4\\n\\
 	(eq:SI (match_operand:SI 1 "register_operand" "d")
 	       (const_int 0)))]
   "TARGET_MIPS16"
-  "sltu\\t%1,1"
+  "sltu\t%1,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7348,7 +6818,7 @@ move\\t%0,%z4\\n\\
 	(eq:DI (match_operand:DI 1 "register_operand" "d")
 	       (const_int 0)))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%1,1"
+  "sltu\t%0,%1,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7357,7 +6827,7 @@ move\\t%0,%z4\\n\\
 	(eq:DI (match_operand:DI 1 "register_operand" "d")
 	       (const_int 0)))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "sltu\\t%1,1"
+  "sltu\t%1,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7367,8 +6837,8 @@ move\\t%0,%z4\\n\\
 	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "@
-   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
-   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
+   xor\t%0,%1,%2\;sltu\t%0,%0,1
+   xori\t%0,%1,%2\;sltu\t%0,%0,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -7393,8 +6863,8 @@ move\\t%0,%z4\\n\\
 	       (match_operand:DI 2 "uns_arith_operand" "d,K")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "@
-   xor\\t%0,%1,%2\;sltu\\t%0,%0,1
-   xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
+   xor\t%0,%1,%2\;sltu\t%0,%0,1
+   xori\t%0,%1,%2\;sltu\t%0,%0,1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -7421,7 +6891,6 @@ move\\t%0,%z4\\n\\
 	(ne:SI (match_dup 1)
 	       (match_dup 2)))]
   "!TARGET_MIPS16"
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7440,14 +6909,14 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sne_si_zero"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ne:SI (match_operand:SI 1 "register_operand" "d")
 	       (const_int 0)))]
   "!TARGET_MIPS16"
-  "sltu\\t%0,%.,%1"
+  "sltu\t%0,%.,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7456,7 +6925,7 @@ move\\t%0,%z4\\n\\
 	(ne:DI (match_operand:DI 1 "register_operand" "d")
 	       (const_int 0)))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%.,%1"
+  "sltu\t%0,%.,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7466,8 +6935,8 @@ move\\t%0,%z4\\n\\
 	       (match_operand:SI 2 "uns_arith_operand" "d,K")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "@
-    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
-    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
+    xor\t%0,%1,%2\;sltu\t%0,%.,%0
+    xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -7492,8 +6961,8 @@ move\\t%0,%z4\\n\\
 	       (match_operand:DI 2 "uns_arith_operand" "d,K")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
   "@
-    xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
-    xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
+    xor\t%0,%1,%2\;sltu\t%0,%.,%0
+    xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -7518,7 +6987,6 @@ move\\t%0,%z4\\n\\
 	(gt:SI (match_dup 1)
 	       (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7537,14 +7005,14 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sgt_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(gt:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
   "!TARGET_MIPS16"
-  "slt\\t%0,%z2,%1"
+  "slt\t%0,%z2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7553,7 +7021,7 @@ move\\t%0,%z4\\n\\
 	(gt:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
-  "slt\\t%2,%1"
+  "slt\t%2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7562,7 +7030,7 @@ move\\t%0,%z4\\n\\
 	(gt:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1"
+  "slt\t%0,%z2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7571,7 +7039,7 @@ move\\t%0,%z4\\n\\
 	(gt:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "slt\\t%2,%1"
+  "slt\t%2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7580,7 +7048,6 @@ move\\t%0,%z4\\n\\
 	(ge:SI (match_dup 1)
 	       (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7596,14 +7063,14 @@ move\\t%0,%z4\\n\\
     }
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sge_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ge:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -7626,7 +7093,7 @@ move\\t%0,%z4\\n\\
 	(ge:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -7650,7 +7117,6 @@ move\\t%0,%z4\\n\\
 	(lt:SI (match_dup 1)
 	       (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7666,14 +7132,14 @@ move\\t%0,%z4\\n\\
     }
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "slt_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lt:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
-  "slt\\t%0,%1,%2"
+  "slt\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7682,7 +7148,7 @@ move\\t%0,%z4\\n\\
 	(lt:SI (match_operand:SI 1 "register_operand" "d,d")
 	       (match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
-  "slt\\t%1,%2"
+  "slt\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -7696,7 +7162,7 @@ move\\t%0,%z4\\n\\
 	(lt:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "slt\\t%0,%1,%2"
+  "slt\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7705,7 +7171,7 @@ move\\t%0,%z4\\n\\
 	(lt:DI (match_operand:DI 1 "register_operand" "d,d")
 	       (match_operand:DI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "slt\\t%1,%2"
+  "slt\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -7719,7 +7185,6 @@ move\\t%0,%z4\\n\\
 	(le:SI (match_dup 1)
 	       (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7738,18 +7203,17 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sle_si_const"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(le:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "small_int" "I")))]
   "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%0,%1,%2\";
-}"
+  return "slt\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7758,11 +7222,10 @@ move\\t%0,%z4\\n\\
 	(le:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "small_int" "I")))]
   "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%1,%2\";
-}"
+  return "slt\t%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
@@ -7774,11 +7237,10 @@ move\\t%0,%z4\\n\\
 	(le:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "small_int" "I")))]
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%0,%1,%2\";
-}"
+  return "slt\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7787,11 +7249,10 @@ move\\t%0,%z4\\n\\
 	(le:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "small_int" "I")))]
   "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"slt\\t%1,%2\";
-}"
+  return "slt\t%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
@@ -7803,7 +7264,7 @@ move\\t%0,%z4\\n\\
 	(le:SI (match_operand:SI 1 "register_operand" "d")
 	       (match_operand:SI 2 "register_operand" "d")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -7826,7 +7287,7 @@ move\\t%0,%z4\\n\\
 	(le:DI (match_operand:DI 1 "register_operand" "d")
 	       (match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -7850,7 +7311,6 @@ move\\t%0,%z4\\n\\
 	(gtu:SI (match_dup 1)
 		(match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7869,14 +7329,14 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sgtu_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(gtu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "reg_or_0_operand" "dJ")))]
   "!TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1"
+  "sltu\t%0,%z2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7885,7 +7345,7 @@ move\\t%0,%z4\\n\\
 	(gtu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_MIPS16"
-  "sltu\\t%2,%1"
+  "sltu\t%2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -7894,7 +7354,7 @@ move\\t%0,%z4\\n\\
 	(gtu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "reg_or_0_operand" "dJ")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1"
+  "sltu\t%0,%z2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7903,7 +7363,7 @@ move\\t%0,%z4\\n\\
 	(gtu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "sltu\\t%2,%1"
+  "sltu\t%2,%1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -7912,7 +7372,6 @@ move\\t%0,%z4\\n\\
         (geu:SI (match_dup 1)
                 (match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7928,14 +7387,14 @@ move\\t%0,%z4\\n\\
     }
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sgeu_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(geu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "arith_operand" "dI")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -7958,7 +7417,7 @@ move\\t%0,%z4\\n\\
 	(geu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
+  "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -7982,7 +7441,6 @@ move\\t%0,%z4\\n\\
 	(ltu:SI (match_dup 1)
 		(match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -7998,14 +7456,14 @@ move\\t%0,%z4\\n\\
     }
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sltu_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ltu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "arith_operand" "dI")))]
   "!TARGET_MIPS16"
-  "sltu\\t%0,%1,%2"
+  "sltu\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -8014,7 +7472,7 @@ move\\t%0,%z4\\n\\
 	(ltu:SI (match_operand:SI 1 "register_operand" "d,d")
 		(match_operand:SI 2 "arith_operand" "d,I")))]
   "TARGET_MIPS16"
-  "sltu\\t%1,%2"
+  "sltu\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr_alternative "length"
@@ -8028,7 +7486,7 @@ move\\t%0,%z4\\n\\
 	(ltu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "arith_operand" "dI")))]
   "TARGET_64BIT && !TARGET_MIPS16"
-  "sltu\\t%0,%1,%2"
+  "sltu\t%0,%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -8037,7 +7495,7 @@ move\\t%0,%z4\\n\\
 	(ltu:DI (match_operand:DI 1 "register_operand" "d,d")
 		(match_operand:DI 2 "arith_operand" "d,I")))]
   "TARGET_64BIT && TARGET_MIPS16"
-  "sltu\\t%1,%2"
+  "sltu\t%1,%2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr_alternative "length"
@@ -8051,7 +7509,6 @@ move\\t%0,%z4\\n\\
 	(leu:SI (match_dup 1)
 		(match_dup 2)))]
   ""
-  "
 {
   if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
     FAIL;
@@ -8070,18 +7527,17 @@ move\\t%0,%z4\\n\\
     operands[2] = force_reg (SImode, operands[2]);
 
   /* fall through and generate default code */
-}")
+})
 
 (define_insn "sleu_si_const"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(leu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "small_int" "I")))]
   "!TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
-  return \"sltu\\t%0,%1,%2\";
-}"
+  return "sltu\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")])
 
@@ -8090,11 +7546,10 @@ move\\t%0,%z4\\n\\
 	(leu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "small_int" "I")))]
   "TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%1,%2\";
-}"
+  return "sltu\t%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
@@ -8106,11 +7561,10 @@ move\\t%0,%z4\\n\\
 	(leu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "small_int" "I")))]
   "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
-  return \"sltu\\t%0,%1,%2\";
-}"
+  return "sltu\t%0,%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")])
 
@@ -8119,11 +7573,10 @@ move\\t%0,%z4\\n\\
 	(leu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "small_int" "I")))]
   "TARGET_64BIT && TARGET_MIPS16 && INTVAL (operands[2]) < 32767"
-  "*
 {
   operands[2] = GEN_INT (INTVAL (operands[2])+1);
-  return \"sltu\\t%1,%2\";
-}"
+  return "sltu\t%1,%2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1" "")
@@ -8135,7 +7588,7 @@ move\\t%0,%z4\\n\\
 	(leu:SI (match_operand:SI 1 "register_operand" "d")
 		(match_operand:SI 2 "register_operand" "d")))]
   "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -8158,7 +7611,7 @@ move\\t%0,%z4\\n\\
 	(leu:DI (match_operand:DI 1 "register_operand" "d")
 		(match_operand:DI 2 "register_operand" "d")))]
   "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
-  "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
+  "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"DI")
    (set_attr "length"	"8")])
@@ -8176,7 +7629,6 @@ move\\t%0,%z4\\n\\
 	(xor:DI (match_dup 0)
 		(const_int 1)))]
   "")
-
 
 ;;
 ;;  ....................
@@ -8346,7 +7798,6 @@ move\\t%0,%z4\\n\\
   "c.le.s\t%Z0%2,%1"
   [(set_attr "type" "fcmp")
    (set_attr "mode" "FPSW")])
-
 
 ;;
 ;;  ....................
@@ -8361,21 +7812,20 @@ move\\t%0,%z4\\n\\
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
   "!TARGET_MIPS16"
-  "*
 {
   if (flag_pic && ! TARGET_EMBEDDED_PIC)
     {
       if (get_attr_length (insn) <= 8)
-	return \"%*b\\t%l0%/\";
+	return "%*b\t%l0%/";
       else
 	{
 	  output_asm_insn (mips_output_load_label (), operands);
-	  return \"%*jr\\t%@%/%]\";
+	  return "%*jr\t%@%/%]";
 	}
     }
   else
-    return \"%*j\\t%l0%/\";
-}"
+    return "%*j\t%l0%/";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set (attr "length")
@@ -8397,7 +7847,7 @@ move\\t%0,%z4\\n\\
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
   "TARGET_MIPS16"
-  "b\\t%l0"
+  "b\t%l0"
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -8405,24 +7855,20 @@ move\\t%0,%z4\\n\\
 (define_expand "indirect_jump"
   [(set (pc) (match_operand 0 "register_operand" "d"))]
   ""
-  "
 {
   rtx dest;
 
-  if (operands[0])		/* eliminate unused code warnings */
-    {
-      dest = operands[0];
-      if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
-	operands[0] = copy_to_mode_reg (Pmode, dest);
+  dest = operands[0];
+  if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+    operands[0] = copy_to_mode_reg (Pmode, dest);
 
-      if (!(Pmode == DImode))
-	emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
-      else
-	emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
+  if (!(Pmode == DImode))
+    emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
+  else
+    emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
 
-      DONE;
-    }
-}")
+  DONE;
+})
 
 (define_insn "indirect_jump_internal1"
   [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
@@ -8443,35 +7889,31 @@ move\\t%0,%z4\\n\\
 	(match_operand 0 "register_operand" "d"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "
 {
-  if (operands[0])		/* eliminate unused code warnings */
+  if (TARGET_MIPS16)
     {
-      if (TARGET_MIPS16)
-	{
-	  if (GET_MODE (operands[0]) != HImode)
-	    abort ();
-	  if (!(Pmode == DImode))
-	    emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
-	  else
-	    emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
-	  DONE;
-	}
-
-      if (GET_MODE (operands[0]) != ptr_mode)
+      if (GET_MODE (operands[0]) != HImode)
 	abort ();
-
-      if (TARGET_GPWORD)
-	operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
-				    pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
-
-      if (Pmode == SImode)
-	emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+      if (!(Pmode == DImode))
+	emit_insn (gen_tablejump_mips161 (operands[0], operands[1]));
       else
-	emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
+	emit_insn (gen_tablejump_mips162 (operands[0], operands[1]));
       DONE;
     }
-}")
+
+  if (GET_MODE (operands[0]) != ptr_mode)
+    abort ();
+
+  if (TARGET_GPWORD)
+    operands[0] = expand_binop (ptr_mode, add_optab, operands[0],
+				pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
+
+  if (Pmode == SImode)
+    emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
+  else
+    emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
+  DONE;
+})
 
 (define_insn "tablejump_internal1"
   [(set (pc)
@@ -8496,52 +7938,44 @@ move\\t%0,%z4\\n\\
 		       (match_operand:HI 0 "register_operand" "d"))
 		      (label_ref:SI (match_operand 1 "" ""))))]
   "TARGET_MIPS16 && !(Pmode == DImode)"
-  "
 {
-  if (operands[0])	/* eliminate unused code warnings.  */
-    {
-      rtx t1, t2, t3;
-
-      t1 = gen_reg_rtx (SImode);
-      t2 = gen_reg_rtx (SImode);
-      t3 = gen_reg_rtx (SImode);
-      emit_insn (gen_extendhisi2 (t1, operands[0]));
-      emit_move_insn (t2, gen_rtx_LABEL_REF (SImode, operands[1]));
-      emit_insn (gen_addsi3 (t3, t1, t2));
-      emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
-      DONE;
-    }
-}")
+  rtx t1, t2, t3;
+
+  t1 = gen_reg_rtx (SImode);
+  t2 = gen_reg_rtx (SImode);
+  t3 = gen_reg_rtx (SImode);
+  emit_insn (gen_extendhisi2 (t1, operands[0]));
+  emit_move_insn (t2, gen_rtx_LABEL_REF (SImode, operands[1]));
+  emit_insn (gen_addsi3 (t3, t1, t2));
+  emit_jump_insn (gen_tablejump_internal1 (t3, operands[1]));
+  DONE;
+})
 
 (define_expand "tablejump_mips162"
   [(set (pc) (plus:DI (sign_extend:DI
 		       (match_operand:HI 0 "register_operand" "d"))
 		      (label_ref:DI (match_operand 1 "" ""))))]
   "TARGET_MIPS16 && Pmode == DImode"
-  "
 {
-  if (operands[0])	/* eliminate unused code warnings.  */
-    {
-      rtx t1, t2, t3;
-
-      t1 = gen_reg_rtx (DImode);
-      t2 = gen_reg_rtx (DImode);
-      t3 = gen_reg_rtx (DImode);
-      emit_insn (gen_extendhidi2 (t1, operands[0]));
-      emit_move_insn (t2, gen_rtx_LABEL_REF (DImode, operands[1]));
-      emit_insn (gen_adddi3 (t3, t1, t2));
-      emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
-      DONE;
-    }
-}")
+  rtx t1, t2, t3;
+
+  t1 = gen_reg_rtx (DImode);
+  t2 = gen_reg_rtx (DImode);
+  t3 = gen_reg_rtx (DImode);
+  emit_insn (gen_extendhidi2 (t1, operands[0]));
+  emit_move_insn (t2, gen_rtx_LABEL_REF (DImode, operands[1]));
+  emit_insn (gen_adddi3 (t3, t1, t2));
+  emit_jump_insn (gen_tablejump_internal2 (t3, operands[1]));
+  DONE;
+})
 
 ;; Implement a switch statement when generating embedded PIC code.
 ;; Switches are implemented by `tablejump' when not using -membedded-pic.
 
 (define_expand "casesi"
   [(set (match_dup 5)
-	(minus:SI (match_operand:SI 0 "register_operand" "d")
-		  (match_operand:SI 1 "arith_operand" "dI")))
+	(minus:SI (match_operand:SI 0 "register_operand" "")
+		  (match_operand:SI 1 "const_int_operand" "")))
    (set (cc0)
 	(compare:CC (match_dup 5)
 		    (match_operand:SI 2 "arith_operand" "")))
@@ -8558,28 +7992,25 @@ move\\t%0,%z4\\n\\
      (clobber (match_scratch:SI 6 ""))
      (clobber (reg:SI 31))])]
   "TARGET_EMBEDDED_PIC"
-  "
 {
-  if (operands[0])
-    {
-      rtx reg = gen_reg_rtx (SImode);
+  rtx index;
 
-      /* If the index is too large, go to the default label.  */
-      emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
-      emit_insn (gen_cmpsi (reg, operands[2]));
-      emit_insn (gen_bgtu (operands[4]));
+  /* If the index is too large, go to the default label.  */
+  index = expand_binop (SImode, sub_optab, operands[0],
+			operands[1], 0, 0, OPTAB_WIDEN);
+  emit_insn (gen_cmpsi (index, operands[2]));
+  emit_insn (gen_bgtu (operands[4]));
 
-      /* Do the PIC jump.  */
-      if (Pmode != DImode)
-        emit_jump_insn (gen_casesi_internal (reg, operands[3],
-					     gen_reg_rtx (SImode)));
-      else
-        emit_jump_insn (gen_casesi_internal_di (reg, operands[3],
-						gen_reg_rtx (DImode)));
+  /* Do the PIC jump.  */
+  if (Pmode != DImode)
+    emit_jump_insn (gen_casesi_internal (index, operands[3],
+					 gen_reg_rtx (SImode)));
+  else
+    emit_jump_insn (gen_casesi_internal_di (index, operands[3],
+					    gen_reg_rtx (DImode)));
 
-      DONE;
-    }
-}")
+  DONE;
+})
 
 ;; An embedded PIC switch statement looks like this:
 ;;	bal	$LS1
@@ -8602,8 +8033,8 @@ move\\t%0,%z4\\n\\
    (clobber (match_operand:SI 2 "register_operand" "=d"))
    (clobber (reg:SI 31))]
   "TARGET_EMBEDDED_PIC"
-  "%(bal\\t%S1\;sll\\t%2,%0,2\\n%~%S1:\;addu\\t%2,%2,$31%)\;\\
-lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
+  "%(bal\t%S1\;sll\t%2,%0,2\n%~%S1:\;addu\t%2,%2,$31%)\;\
+lw\t%2,%1-%S1(%2)\;addu\t%2,%2,$31\;%*j\t%2%/"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"24")])
@@ -8619,8 +8050,8 @@ lw\\t%2,%1-%S1(%2)\;addu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    (clobber (match_operand:DI 2 "register_operand" "=d"))
    (clobber (reg:DI 31))]
   "TARGET_EMBEDDED_PIC"
-  "%(bal\\t%S1\;sll\\t%2,%0,3\\n%~%S1:\;daddu\\t%2,%2,$31%)\;\\
-ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
+  "%(bal\t%S1\;sll\t%2,%0,3\n%~%S1:\;daddu\t%2,%2,$31%)\;\
+ld\t%2,%1-%S1(%2)\;daddu\t%2,%2,$31\;%*j\t%2%/"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"24")])
@@ -8633,22 +8064,21 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 (define_expand "builtin_setjmp_setup"
   [(use (match_operand 0 "register_operand" ""))]
   "TARGET_ABICALLS"
-  {
-    rtx addr;
+{
+  rtx addr;
 
-    addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
-    emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
-    DONE;
-  })
+  addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
+  emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
+  DONE;
+})
 
-;; Restore the gp that we saved above.  Despite the comment, it seems that
-;; older code did recalculate the gp from $25.  Continue to jump through
+;; Restore the gp that we saved above.  Despite the earlier comment, it seems
+;; that older code did recalculate the gp from $25.  Continue to jump through
 ;; $25 for compatibility (we lose nothing by doing so).
 
 (define_expand "builtin_longjmp"
   [(use (match_operand 0 "register_operand" "r"))]
   "TARGET_ABICALLS"
-  "
 {
   /* The elements of the buffer are, in order:  */
   int W = GET_MODE_SIZE (Pmode);
@@ -8673,7 +8103,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   emit_insn (gen_rtx_USE (VOIDmode, gp));
   emit_indirect_jump (pv);
   DONE;
-}")
+})
 
 ;;
 ;;  ....................
@@ -8686,14 +8116,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 (define_expand "prologue"
   [(const_int 1)]
   ""
-  "
 {
-  if (mips_isa >= 0)		/* avoid unused code warnings */
-    {
-      mips_expand_prologue ();
-      DONE;
-    }
-}")
+  mips_expand_prologue ();
+  DONE;
+})
 
 ;; Block any insns from being moved before this point, since the
 ;; profiling call to mcount can use various registers that aren't
@@ -8724,7 +8150,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 })
 
 ;; Trivial return.  Make it look like a normal return insn as that
-;; allows jump optimizations to work better .
+;; allows jump optimizations to work better.
+
 (define_insn "return"
   [(return)]
   "mips_can_use_return_insn ()"
@@ -8751,7 +8178,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    (clobber (reg:SI 31))]
   "TARGET_EMBEDDED_PIC
    && GET_CODE (operands[1]) == SYMBOL_REF"
-  "%($LF%= = . + 8\;bal\\t$LF%=\;nop;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
+  "%($LF%= = . + 8\;bal\t$LF%=\;nop;la\t%0,%1-$LF%=%)\;addu\t%0,%0,$31"
   [(set_attr "type"	"call")
    (set_attr "mode"	"none")
    (set_attr "length"	"20")])
@@ -8760,7 +8187,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 (define_expand "eh_return"
   [(use (match_operand 0 "general_operand" ""))]
   ""
-  "
 {
   enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
 
@@ -8772,7 +8198,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
     emit_insn (gen_eh_set_lr_si (operands[0]));
 
   DONE;
-}")
+})
 
 ;; Clobber the return address on the stack.  We can't expand this
 ;; until we know where it will be put in the stack frame.
@@ -8794,15 +8220,14 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    (clobber (match_scratch 1 ""))]
   "reload_completed && !TARGET_DEBUG_D_MODE"
   [(const_int 0)]
-  "
 {
   mips_set_return_address (operands[0], operands[1]);
   DONE;
-}")
+})
 
 (define_insn "exception_receiver"
   [(set (reg:SI 28)
-	(unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER))]
+	(unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
   "TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
   { return mips_restore_gp (operands); }
   [(set_attr "type"   "load")
@@ -8815,11 +8240,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 ;;
 ;;  ....................
 
-;; Sibling calls.  All these patterns use direct jumps.
+;; Sibling calls.  All these patterns use jump instructions.
 
-;; call_insn_operand will only accepts constant addresses if a direct
-;; jump is acceptable.  Since the 'S' constraint is defined in terms of
-;; call_insn_operand, the same is true of the constraints.
+;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
+;; addresses if a direct jump is acceptable.  Since the 'S' constraint
+;; is defined in terms of call_insn_operand, the same is true of the
+;; constraints.
 
 ;; When we use an indirect jump, we need a register that will be
 ;; preserved by the epilogue.  Since TARGET_ABICALLS forces us to
@@ -8900,11 +8326,11 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   "%*jal\t%0%/"
   "reload_completed && TARGET_SPLIT_CALLS"
   [(const_int 0)]
-  {
-    emit_call_insn (gen_call_split (operands[0], operands[1]));
-    emit_insn (gen_exception_receiver ());
-    DONE;
-  }
+{
+  emit_call_insn (gen_call_split (operands[0], operands[1]));
+  emit_insn (gen_exception_receiver ());
+  DONE;
+}
   [(set_attr "jal" "indirect,direct")
    (set_attr "extended_mips16" "no,yes")])
 
@@ -8938,12 +8364,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   "%*jal\t%1%/"
   "reload_completed && TARGET_SPLIT_CALLS"
   [(const_int 0)]
-  {
-    emit_call_insn (gen_call_value_split (operands[0], operands[1],
-					  operands[2]));
-    emit_insn (gen_exception_receiver ());
-    DONE;
-  }
+{
+  emit_call_insn (gen_call_value_split (operands[0], operands[1],
+					operands[2]));
+  emit_insn (gen_exception_receiver ());
+  DONE;
+}
   [(set_attr "jal" "indirect,direct")
    (set_attr "extended_mips16" "no,yes")])
 
@@ -8969,12 +8395,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   "%*jal\t%1%/"
   "reload_completed && TARGET_SPLIT_CALLS"
   [(const_int 0)]
-  {
-    emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
-						   operands[2], operands[3]));
-    emit_insn (gen_exception_receiver ());
-    DONE;
-  }
+{
+  emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
+						 operands[2], operands[3]));
+  emit_insn (gen_exception_receiver ());
+  DONE;
+}
   [(set_attr "jal" "indirect,direct")
    (set_attr "extended_mips16" "no,yes")])
 
@@ -8999,7 +8425,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	      (match_operand 1 "" "")
 	      (match_operand 2 "" "")])]
   ""
-  "
 {
   int i;
 
@@ -9013,7 +8438,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 
   emit_insn (gen_blockage ());
   DONE;
-}")
+})
 
 ;;
 ;;  ....................
@@ -9040,7 +8465,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (match_operand:SI 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && Pmode == SImode"
-  "* return mips_emit_prefetch (operands);"
+  { return mips_emit_prefetch (operands); }
   [(set_attr "type" "prefetch")])
 
 (define_insn "prefetch_si"
@@ -9048,7 +8473,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (match_operand:SI 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && Pmode == SImode"
-  "* return mips_emit_prefetch (operands);"
+  { return mips_emit_prefetch (operands); }
   [(set_attr "type" "prefetch")])
 
 (define_insn "prefetch_di_address"
@@ -9057,7 +8482,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	     (match_operand:DI 1 "const_int_operand" "n")
 	     (match_operand:DI 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && Pmode == DImode"
-  "* return mips_emit_prefetch (operands);"
+  { return mips_emit_prefetch (operands); }
   [(set_attr "type" "prefetch")])
 
 (define_insn "prefetch_di"
@@ -9065,7 +8490,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	     (match_operand:DI 1 "const_int_operand" "n")
 	     (match_operand:DI 2 "const_int_operand" "n"))]
   "ISA_HAS_PREFETCH && Pmode == DImode"
-  "* return mips_emit_prefetch (operands);"
+  { return mips_emit_prefetch (operands); }
   [(set_attr "type" "prefetch")])
 
 (define_insn "nop"
@@ -9086,24 +8511,7 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
       return "#nop";
   }
   [(set_attr "type"	"arith")])
-
-;; The MIPS chip does not seem to require stack probes.
-;;
-;; (define_expand "probe"
-;;   [(set (match_dup 0)
-;; 	(match_dup 1))]
-;;   ""
-;;   "
-;; {
-;;   operands[0] = gen_reg_rtx (SImode);
-;;   operands[1] = gen_rtx_MEM (SImode, stack_pointer_rtx);
-;;   MEM_VOLATILE_P (operands[1]) = TRUE;
-;;
-;;   /* fall through and generate default code */
-;; }")
-;;
 
-;;
 ;; MIPS4 Conditional move instructions.
 
 (define_insn ""
@@ -9116,9 +8524,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
+    mov%B4\t%0,%z2,%1
+    mov%b4\t%0,%z3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SI")])
 
 (define_insn ""
@@ -9131,9 +8539,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
   "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
+    mov%B4\t%0,%z2,%1
+    mov%b4\t%0,%z3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SI")])
 
 (define_insn ""
@@ -9147,9 +8555,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
   "@
-    mov%T3\\t%0,%z1,%4
-    mov%t3\\t%0,%z2,%4"
-  [(set_attr "type" "move")
+    mov%T3\t%0,%z1,%4
+    mov%t3\t%0,%z2,%4"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SI")])
 
 (define_insn ""
@@ -9162,9 +8570,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
   "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
+    mov%B4\t%0,%z2,%1
+    mov%b4\t%0,%z3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DI")])
 
 (define_insn ""
@@ -9177,9 +8585,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
   "@
-    mov%B4\\t%0,%z2,%1
-    mov%b4\\t%0,%z3,%1"
-  [(set_attr "type" "move")
+    mov%B4\t%0,%z2,%1
+    mov%b4\t%0,%z3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DI")])
 
 (define_insn ""
@@ -9193,9 +8601,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
   "@
-    mov%T3\\t%0,%z1,%4
-    mov%t3\\t%0,%z2,%4"
-  [(set_attr "type" "move")
+    mov%T3\t%0,%z1,%4
+    mov%t3\t%0,%z2,%4"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DI")])
 
 (define_insn ""
@@ -9208,9 +8616,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
   "@
-    mov%B4.s\\t%0,%2,%1
-    mov%b4.s\\t%0,%3,%1"
-  [(set_attr "type" "move")
+    mov%B4.s\t%0,%2,%1
+    mov%b4.s\t%0,%3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SF")])
 
 (define_insn ""
@@ -9223,9 +8631,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
   "@
-    mov%B4.s\\t%0,%2,%1
-    mov%b4.s\\t%0,%3,%1"
-  [(set_attr "type" "move")
+    mov%B4.s\t%0,%2,%1
+    mov%b4.s\t%0,%3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SF")])
 
 (define_insn ""
@@ -9239,9 +8647,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:SF 2 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
   "@
-    mov%T3.s\\t%0,%1,%4
-    mov%t3.s\\t%0,%2,%4"
-  [(set_attr "type" "move")
+    mov%T3.s\t%0,%1,%4
+    mov%t3.s\t%0,%2,%4"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "SF")])
 
 (define_insn ""
@@ -9254,9 +8662,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "@
-    mov%B4.d\\t%0,%2,%1
-    mov%b4.d\\t%0,%3,%1"
-  [(set_attr "type" "move")
+    mov%B4.d\t%0,%2,%1
+    mov%b4.d\t%0,%3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DF")])
 
 (define_insn ""
@@ -9269,9 +8677,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DF 3 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "@
-    mov%B4.d\\t%0,%2,%1
-    mov%b4.d\\t%0,%3,%1"
-  [(set_attr "type" "move")
+    mov%B4.d\t%0,%2,%1
+    mov%b4.d\t%0,%3,%1"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DF")])
 
 (define_insn ""
@@ -9285,9 +8693,9 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 	 (match_operand:DF 2 "register_operand" "0,f")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "@
-    mov%T3.d\\t%0,%1,%4
-    mov%t3.d\\t%0,%2,%4"
-  [(set_attr "type" "move")
+    mov%T3.d\t%0,%1,%4
+    mov%t3.d\t%0,%2,%4"
+  [(set_attr "type" "condmove")
    (set_attr "mode" "DF")])
 
 ;; These are the main define_expand's used to make conditional moves.
@@ -9299,11 +8707,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 			 (match_operand:SI 2 "reg_or_0_operand" "")
 			 (match_operand:SI 3 "reg_or_0_operand" "")))]
   "ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
-  "
 {
   gen_conditional_move (operands);
   DONE;
-}")
+})
 
 (define_expand "movdicc"
   [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
@@ -9312,11 +8719,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 			 (match_operand:DI 2 "reg_or_0_operand" "")
 			 (match_operand:DI 3 "reg_or_0_operand" "")))]
   "(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
-  "
 {
   gen_conditional_move (operands);
   DONE;
-}")
+})
 
 (define_expand "movsfcc"
   [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
@@ -9325,11 +8731,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 			 (match_operand:SF 2 "register_operand" "")
 			 (match_operand:SF 3 "register_operand" "")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
-  "
 {
   gen_conditional_move (operands);
   DONE;
-}")
+})
 
 (define_expand "movdfcc"
   [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
@@ -9338,11 +8743,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
 			 (match_operand:DF 2 "register_operand" "")
 			 (match_operand:DF 3 "register_operand" "")))]
   "ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "
 {
   gen_conditional_move (operands);
   DONE;
-}")
+})
 
 ;;
 ;;  ....................
@@ -9356,11 +8760,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_QI)]
   "TARGET_MIPS16"
-  "*
 {
   assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"QI")
    (set_attr "length"	"8")])
@@ -9369,11 +8772,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_HI)]
   "TARGET_MIPS16"
-  "*
 {
   assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"HI")
    (set_attr "length"	"8")])
@@ -9382,11 +8784,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_SI)]
   "TARGET_MIPS16"
-  "*
 {
   assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"SI")
    (set_attr "length"	"8")])
@@ -9395,11 +8796,10 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_DI)]
   "TARGET_MIPS16"
-  "*
 {
   assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"DI")
    (set_attr "length"	"16")])
@@ -9408,7 +8808,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_SF)]
   "TARGET_MIPS16"
-  "*
 {
   REAL_VALUE_TYPE d;
 
@@ -9416,8 +8815,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
     abort ();
   REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
   assemble_real (d, SFmode, GET_MODE_ALIGNMENT (SFmode));
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"SF")
    (set_attr "length"	"8")])
@@ -9426,7 +8825,6 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
   [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "=g")]
 		    UNSPEC_CONSTTABLE_DF)]
   "TARGET_MIPS16"
-  "*
 {
   REAL_VALUE_TYPE d;
 
@@ -9434,8 +8832,8 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
     abort ();
   REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
   assemble_real (d, DFmode, GET_MODE_ALIGNMENT (DFmode));
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"unknown")
    (set_attr "mode"	"DF")
    (set_attr "length"	"16")])
@@ -9493,13 +8891,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    && dead_or_set_p (insn, operands[0])
    && GET_CODE (operands[1]) == REG
    && M16_REG_P (REGNO (operands[1]))"
-  "*
 {
   if (operands[3] != pc_rtx)
-    return \"b%C2z\\t%1,%3\";
+    return "b%C2z\t%1,%3";
   else
-    return \"b%N2z\\t%1,%4\";
-}"
+    return "b%N2z\t%1,%4";
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -9518,13 +8915,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    && dead_or_set_p (insn, operands[0])
    && GET_CODE (operands[1]) == REG
    && M16_REG_P (REGNO (operands[1]))"
-  "*
 {
   if (operands[3] != pc_rtx)
-    return \"b%C2z\\t%1,%3\";
+    return "b%C2z\t%1,%3";
   else
-    return \"b%N2z\\t%1,%4\";
-}"
+    return "b%N2z\t%1,%4";
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -9547,13 +8943,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    && GET_CODE (operands[0]) == REG
    && M16_REG_P (REGNO (operands[0]))
    && dead_or_set_p (insn, operands[0])"
-  "*
 {
   if (operands[3] != pc_rtx)
-    return \"bt%C2z\\t%3\";
+    return "bt%C2z\t%3";
   else
-    return \"bt%N2z\\t%4\";
-}"
+    return "bt%N2z\t%4";
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
@@ -9572,13 +8967,12 @@ ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n\\t%*j\\t%2%/"
    && GET_CODE (operands[0]) == REG
    && M16_REG_P (REGNO (operands[0]))
    && dead_or_set_p (insn, operands[0])"
-  "*
 {
   if (operands[3] != pc_rtx)
-    return \"bt%C2z\\t%3\";
+    return "bt%C2z\t%3";
   else
-    return \"bt%N2z\\t%4\";
-}"
+    return "bt%N2z\t%4";
+}
   [(set_attr "type"	"branch")
    (set_attr "mode"	"none")
    (set_attr "length"	"8")])
diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h
index 3e6d2a7f459..4bdc8aad692 100644
--- a/gcc/config/mips/netbsd.h
+++ b/gcc/config/mips/netbsd.h
@@ -128,21 +128,10 @@ Boston, MA 02111-1307, USA.  */
   while (0)
 
 
-/* Include the generic MIPS ELF configuration.  */
-#include <mips/elf.h>
-
-/* Now clean up after it.  */
+/* Clean up after the generic MIPS/ELF configuration.  */
 #undef MD_EXEC_PREFIX
 #undef MD_STARTFILE_PREFIX
 
-/* Get generic NetBSD definitions.  */
-#include <netbsd.h>
-
-
-/* Get generic NetBSD ELF definitions.  */
-#include <netbsd-elf.h>
-
-
 /* Extra specs we need.  */
 #undef SUBTARGET_EXTRA_SPECS
 #define SUBTARGET_EXTRA_SPECS						\
diff --git a/gcc/config/mips/openbsd-be.h b/gcc/config/mips/openbsd-be.h
deleted file mode 100644
index 2f07c8fe110..00000000000
--- a/gcc/config/mips/openbsd-be.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* Configuration fragment for a mips big-endian OpenBSD target
-   Copyright (C) 1999 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
diff --git a/gcc/config/mips/openbsd.h b/gcc/config/mips/openbsd.h
index a61aac0d438..6ca833bb372 100644
--- a/gcc/config/mips/openbsd.h
+++ b/gcc/config/mips/openbsd.h
@@ -1,5 +1,5 @@
 /* Configuration for  a Mips ABI32 OpenBSD target.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2003 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -21,35 +21,24 @@ Boston, MA 02111-1307, USA.  */
 /* Definitions needed for OpenBSD, to avoid picking mips 'defaults'.  */
 
 /* GAS must know this.  */
+#undef SUBTARGET_ASM_SPEC
 #define SUBTARGET_ASM_SPEC "%{fPIC|fPIE:-KPIC}"
 
 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
 
 /* CPP specific OpenBSD specs.  */
+#undef SUBTARGET_CPP_SPEC
 #define SUBTARGET_CPP_SPEC OBSD_CPP_SPEC
 
 /* Needed for ELF (inspired by netbsd-elf).  */
 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
+#undef LOCAL_LABEL_PREFIX
 #define LOCAL_LABEL_PREFIX	"."
 
 /* The profiling lib spec here is not really correct but we leave
    it as it is until we have some kind of profiling working.  */
 #define LIB_SPEC OBSD_LIB_SPEC
 
-/* By default, OpenBSD mips is little endian.  This is important to set
-   here as mips/mips.h defaults to big endian.  */
-#ifndef TARGET_ENDIAN_DEFAULT
-#define TARGET_ENDIAN_DEFAULT 0
-#endif
-
-#include <mips/mips.h>
-
-/* Get generic OpenBSD definitions.  */
-#define OBSD_HAS_DECLARE_FUNCTION_NAME
-#define OBSD_HAS_DECLARE_OBJECT
-#define OBSD_HAS_CORRECT_SPECS
-#include <openbsd.h>
-
 /* mips assembler uses .set for arcane purposes.  __attribute__((alias))
    and friends won't work until we get recent binutils with .weakext
 	support.  */
@@ -109,9 +98,3 @@ Boston, MA 02111-1307, USA.  */
 /* Switch into a generic section.  */
 #undef TARGET_ASM_NAMED_SECTION
 #define TARGET_ASM_NAMED_SECTION  default_elf_asm_named_section
-
-/* collect2 support (Macros for initialization).  */
-
-/* Mips default configuration is COFF-only, and confuses collect2.  */
-#undef OBJECT_FORMAT_COFF
-#undef EXTENDED_COFF
diff --git a/gcc/config/mips/sdb.h b/gcc/config/mips/sdb.h
new file mode 100644
index 00000000000..6ac4c214e45
--- /dev/null
+++ b/gcc/config/mips/sdb.h
@@ -0,0 +1,89 @@
+/* Generate SDB debugging info.
+   Copyright (C) 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
+
+/* Note that no configuration uses sdb as its preferred format.  */
+
+#define SDB_DEBUGGING_INFO 1
+
+/* Forward references to tags are allowed.  */
+#define SDB_ALLOW_FORWARD_REFERENCES
+
+/* Unknown tags are also allowed.  */
+#define SDB_ALLOW_UNKNOWN_REFERENCES
+
+/* Block start/end next label #.  */
+extern int sdb_label_count;
+
+/* Starting line of current function.  */
+extern int sdb_begin_function_line;
+
+#define PUT_SDB_DEF(a)					\
+do {							\
+  fprintf (asm_out_file, "\t%s.def\t",			\
+	   (TARGET_GAS) ? "" : "#");			\
+  ASM_OUTPUT_LABELREF (asm_out_file, a); 		\
+  fputc (';', asm_out_file);				\
+} while (0)
+
+#define PUT_SDB_PLAIN_DEF(a)				\
+do {							\
+  fprintf (asm_out_file, "\t%s.def\t.%s;",		\
+	   (TARGET_GAS) ? "" : "#", (a));		\
+} while (0)
+
+/* For block start and end, we create labels, so that
+   later we can figure out where the correct offset is.
+   The normal .ent/.end serve well enough for functions,
+   so those are just commented out.  */
+
+#define PUT_SDB_BLOCK_START(LINE)			\
+do {							\
+  fprintf (asm_out_file,				\
+	   "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n",		\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (TARGET_GAS) ? "" : "#",			\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (LINE));					\
+  sdb_label_count++;					\
+} while (0)
+
+#define PUT_SDB_BLOCK_END(LINE)				\
+do {							\
+  fprintf (asm_out_file,				\
+	   "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n",		\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (TARGET_GAS) ? "" : "#",			\
+	   LOCAL_LABEL_PREFIX,				\
+	   sdb_label_count,				\
+	   (LINE));					\
+  sdb_label_count++;					\
+} while (0)
+
+#define PUT_SDB_FUNCTION_START(LINE)
+
+#define PUT_SDB_FUNCTION_END(LINE)			\
+do {							\
+  ASM_OUTPUT_SOURCE_LINE (asm_out_file, LINE + sdb_begin_function_line, 0); \
+} while (0)
+
+#define PUT_SDB_EPILOGUE_END(NAME)
diff --git a/gcc/config/mips/sr71k.md b/gcc/config/mips/sr71k.md
index d6c7cafa083..51731893dbf 100644
--- a/gcc/config/mips/sr71k.md
+++ b/gcc/config/mips/sr71k.md
@@ -172,12 +172,11 @@
 
 
 ;; This reservation is for conditional move based on integer
-;; or floating point CC.  This could probably use some refinement
-;; as "move" type attr seems to be overloaded in rtl.
-(define_insn_reservation "ir_sr70_move"
+;; or floating point CC.
+(define_insn_reservation "ir_sr70_condmove"
                                4
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "move"))
+                               (eq_attr "type" "condmove"))
                          "ri_insns")
 
 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
@@ -206,7 +205,7 @@
 (define_insn_reservation "ir_sr70_arith"
                                1
                           (and (eq_attr "cpu" "sr71000")
-                               (eq_attr "type" "arith,darith,const"))
+                               (eq_attr "type" "move,arith,darith,const"))
                          "ri_insns")
 
 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in
diff --git a/gcc/config/mips/t-rtems b/gcc/config/mips/t-rtems
new file mode 100644
index 00000000000..bd7b7adf467
--- /dev/null
+++ b/gcc/config/mips/t-rtems
@@ -0,0 +1,5 @@
+# Custom multilibs for RTEMS
+
+MULTILIB_OPTIONS = mips1/mips3 msoft-float/msingle-float EL/EB
+MULTILIB_DIRNAMES = mips1 mips3 soft-float single el eb
+MULTILIB_MATCHES = msingle-float=m4650
diff --git a/gcc/config/mmix/mmix-protos.h b/gcc/config/mmix/mmix-protos.h
index 7e04d6aa998..a5ae7c8ae2f 100644
--- a/gcc/config/mmix/mmix-protos.h
+++ b/gcc/config/mmix/mmix-protos.h
@@ -1,5 +1,5 @@
 /* Prototypes for exported functions defined in mmix.c
-   Copyright (C) 2000, 2001, 2002  Free Software Foundation, Inc.
+   Copyright (C) 2000, 2001, 2002, 2003  Free Software Foundation, Inc.
    Contributed by Hans-Peter Nilsson (hp@bitrange.com)
 
 This file is part of GCC.
@@ -19,94 +19,89 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-extern void mmix_override_options PARAMS ((void));
-extern void mmix_init_expanders PARAMS ((void));
-extern int mmix_eh_return_data_regno PARAMS ((int));
-extern int mmix_initial_elimination_offset PARAMS ((int, int));
-extern int mmix_starting_frame_offset PARAMS ((void));
-extern int mmix_function_arg_regno_p PARAMS ((int, int));
-extern void mmix_function_profiler PARAMS ((FILE *, int));
-extern void mmix_trampoline_template PARAMS ((FILE *));
+extern void mmix_override_options (void);
+extern void mmix_init_expanders (void);
+extern int mmix_eh_return_data_regno (int);
+extern int mmix_initial_elimination_offset (int, int);
+extern int mmix_starting_frame_offset (void);
+extern int mmix_function_arg_regno_p (int, int);
+extern void mmix_function_profiler (FILE *, int);
+extern void mmix_trampoline_template (FILE *);
 extern int mmix_trampoline_size;
-extern int mmix_reversible_cc_mode PARAMS ((enum machine_mode));
+extern int mmix_reversible_cc_mode (enum machine_mode);
 extern int mmix_register_move_cost
-  PARAMS ((enum machine_mode, enum reg_class, enum reg_class));
-extern const char *mmix_text_section_asm_op PARAMS ((void));
-extern const char *mmix_data_section_asm_op PARAMS ((void));
-extern void mmix_asm_output_source_filename PARAMS ((FILE *, const char *));
-extern void mmix_output_quoted_string PARAMS ((FILE *, const char *, int));
-extern void mmix_asm_output_source_line  PARAMS ((FILE *, int));
-extern void mmix_asm_output_ascii PARAMS ((FILE *, const char *, int));
-extern void mmix_asm_output_label PARAMS ((FILE *, const char *));
-extern void mmix_asm_weaken_label PARAMS ((FILE *, const char *));
-extern void mmix_asm_output_labelref PARAMS ((FILE *, const char *));
-extern void mmix_asm_output_def PARAMS ((FILE *, const char *, const char *));
-extern int mmix_print_operand_punct_valid_p PARAMS ((int));
-extern void mmix_asm_output_reg_push PARAMS ((FILE *, int));
-extern void mmix_asm_output_reg_pop PARAMS ((FILE *, int));
-extern void mmix_asm_output_skip PARAMS ((FILE *, int));
-extern void mmix_asm_output_align PARAMS ((FILE *, int));
-extern int mmix_shiftable_wyde_value PARAMS ((unsigned HOST_WIDEST_INT));
-extern void mmix_output_register_setting
-  PARAMS ((FILE *, int, HOST_WIDEST_INT, int));
-extern void mmix_conditional_register_usage PARAMS ((void));
-extern int mmix_local_regno PARAMS ((int));
-extern int mmix_dbx_register_number PARAMS ((int));
-extern int mmix_use_simple_return PARAMS ((void));
-extern void mmix_make_decl_one_only PARAMS ((tree));
+  (enum machine_mode, enum reg_class, enum reg_class);
+extern const char *mmix_text_section_asm_op (void);
+extern const char *mmix_data_section_asm_op (void);
+extern void mmix_asm_output_source_filename (FILE *, const char *);
+extern void mmix_output_quoted_string (FILE *, const char *, int);
+extern void mmix_asm_output_source_line  (FILE *, int);
+extern void mmix_asm_output_ascii (FILE *, const char *, int);
+extern void mmix_asm_output_label (FILE *, const char *);
+extern void mmix_asm_weaken_label (FILE *, const char *);
+extern void mmix_asm_output_labelref (FILE *, const char *);
+extern void mmix_asm_output_def (FILE *, const char *, const char *);
+extern int mmix_print_operand_punct_valid_p (int);
+extern void mmix_asm_output_reg_push (FILE *, int);
+extern void mmix_asm_output_reg_pop (FILE *, int);
+extern void mmix_asm_output_skip (FILE *, int);
+extern void mmix_asm_output_align (FILE *, int);
+extern int mmix_shiftable_wyde_value (unsigned HOST_WIDEST_INT);
+extern void mmix_output_register_setting (FILE *, int, HOST_WIDEST_INT, int);
+extern void mmix_conditional_register_usage (void);
+extern int mmix_local_regno (int);
+extern int mmix_dbx_register_number (int);
+extern int mmix_use_simple_return (void);
+extern void mmix_make_decl_one_only (tree);
 extern int mmix_function_arg_pass_by_reference
-  PARAMS ((const CUMULATIVE_ARGS *, enum machine_mode, tree, int));
-extern rtx mmix_function_outgoing_value PARAMS ((tree, tree));
-extern int mmix_function_value_regno_p PARAMS ((int));
-extern int mmix_data_alignment PARAMS ((tree, int));
-extern int mmix_constant_alignment PARAMS ((tree, int));
-extern int mmix_local_alignment PARAMS ((tree, int));
+  (const CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern rtx mmix_function_outgoing_value (tree, tree);
+extern int mmix_function_value_regno_p (int);
+extern int mmix_data_alignment (tree, int);
+extern int mmix_constant_alignment (tree, int);
+extern int mmix_local_alignment (tree, int);
 extern void mmix_setup_incoming_varargs
-  PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int));
-extern void mmix_asm_output_pool_prologue
-  PARAMS ((FILE *, const char *, tree, int));
-extern void mmix_asm_output_aligned_common
-  PARAMS ((FILE *, const char *, int, int));
-extern void mmix_asm_output_aligned_local
-  PARAMS ((FILE *, const char *, int, int));
+  (CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int);
+extern void mmix_asm_output_pool_prologue (FILE *, const char *, tree, int);
+extern void mmix_asm_output_aligned_common (FILE *, const char *, int, int);
+extern void mmix_asm_output_aligned_local (FILE *, const char *, int, int);
 extern void mmix_asm_declare_register_global
-  PARAMS ((FILE *, tree, int, const char *));
+  (FILE *, tree, int, const char *);
 extern rtx mmix_function_arg
-  PARAMS ((const CUMULATIVE_ARGS *, enum machine_mode, tree, int, int));
-extern rtx mmix_expand_builtin_va_arg PARAMS ((tree, tree));
-extern void mmix_asm_output_addr_diff_elt PARAMS ((FILE *, rtx, int, int));
-extern void mmix_asm_output_addr_vec_elt PARAMS ((FILE *, int));
-extern enum reg_class mmix_preferred_reload_class
-  PARAMS ((rtx, enum reg_class));
+  (const CUMULATIVE_ARGS *, enum machine_mode, tree, int, int);
+extern rtx mmix_expand_builtin_va_arg (tree, tree);
+extern void mmix_asm_output_addr_diff_elt (FILE *, rtx, int, int);
+extern void mmix_asm_output_addr_vec_elt (FILE *, int);
+extern enum reg_class mmix_preferred_reload_class (rtx, enum reg_class);
 extern enum reg_class mmix_preferred_output_reload_class
-  PARAMS ((rtx, enum reg_class));
+  (rtx, enum reg_class);
 extern enum reg_class mmix_secondary_reload_class
-  PARAMS ((enum reg_class, enum machine_mode, rtx, int));
-extern int mmix_const_ok_for_letter_p PARAMS ((HOST_WIDE_INT, int));
-extern int mmix_const_double_ok_for_letter_p PARAMS ((rtx, int));
-extern int mmix_extra_constraint PARAMS ((rtx, int, int));
-extern rtx mmix_dynamic_chain_address PARAMS ((rtx));
-extern rtx mmix_return_addr_rtx PARAMS ((int, rtx));
-extern rtx mmix_eh_return_stackadj_rtx PARAMS ((void));
-extern rtx mmix_eh_return_handler_rtx PARAMS ((void));
-extern void mmix_initialize_trampoline PARAMS ((rtx, rtx, rtx));
-extern int mmix_constant_address_p PARAMS ((rtx));
-extern int mmix_legitimate_address PARAMS ((enum machine_mode, rtx, int));
-extern int mmix_legitimate_constant_p PARAMS ((rtx));
-extern void mmix_print_operand PARAMS ((FILE *, rtx, int));
-extern void mmix_print_operand_address PARAMS ((FILE *, rtx));
-extern void mmix_expand_prologue PARAMS ((void));
-extern void mmix_expand_epilogue PARAMS ((void));
-extern rtx mmix_get_hard_reg_initial_val PARAMS ((enum machine_mode, int));
-extern int mmix_asm_preferred_eh_data_format PARAMS ((int, int));
-extern void mmix_setup_frame_addresses PARAMS ((void));
+  (enum reg_class, enum machine_mode, rtx, int);
+extern int mmix_const_ok_for_letter_p (HOST_WIDE_INT, int);
+extern int mmix_const_double_ok_for_letter_p (rtx, int);
+extern int mmix_extra_constraint (rtx, int, int);
+extern rtx mmix_dynamic_chain_address (rtx);
+extern rtx mmix_return_addr_rtx (int, rtx);
+extern rtx mmix_eh_return_stackadj_rtx (void);
+extern rtx mmix_eh_return_handler_rtx (void);
+extern void mmix_initialize_trampoline (rtx, rtx, rtx);
+extern int mmix_constant_address_p (rtx);
+extern int mmix_legitimate_address (enum machine_mode, rtx, int);
+extern int mmix_legitimate_constant_p (rtx);
+extern void mmix_print_operand (FILE *, rtx, int);
+extern void mmix_print_operand_address (FILE *, rtx);
+extern void mmix_expand_prologue (void);
+extern void mmix_expand_epilogue (void);
+extern rtx mmix_get_hard_reg_initial_val (enum machine_mode, int);
+extern int mmix_asm_preferred_eh_data_format (int, int);
+extern void mmix_setup_frame_addresses (void);
 
 #ifdef RTX_CODE
 /* Needs to be ifdef:d for sake of enum rtx_code.  */
-extern enum machine_mode mmix_select_cc_mode PARAMS ((enum rtx_code, rtx, rtx));
-extern void mmix_canonicalize_comparison PARAMS ((enum rtx_code *, rtx *, rtx *));
-extern int mmix_valid_comparison PARAMS ((enum rtx_code, enum machine_mode, rtx));
-extern rtx mmix_gen_compare_reg PARAMS ((enum rtx_code, rtx, rtx));
+extern enum machine_mode mmix_select_cc_mode (enum rtx_code, rtx, rtx);
+extern void mmix_canonicalize_comparison (enum rtx_code *, rtx *, rtx *);
+extern int mmix_valid_comparison (enum rtx_code, enum machine_mode, rtx);
+extern rtx mmix_gen_compare_reg (enum rtx_code, rtx, rtx);
 #endif
 
 /*
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 290b5d83e07..1feebdd9ae9 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1,5 +1,5 @@
 /* Definitions of target machine for GNU compiler, for MMIX.
-   Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright (C) 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Hans-Peter Nilsson (hp@bitrange.com)
 
 This file is part of GCC.
@@ -117,28 +117,25 @@ const char *mmix_cc1_ignored_option;
 static int mmix_output_destination_register;
 
 static void mmix_output_shiftvalue_op_from_str
-  PARAMS ((FILE *, const char *, HOST_WIDEST_INT));
-static void mmix_output_shifted_value PARAMS ((FILE *, HOST_WIDEST_INT));
-static void mmix_output_condition PARAMS ((FILE *, rtx, int));
-static HOST_WIDEST_INT mmix_intval PARAMS ((rtx));
-static void mmix_output_octa PARAMS ((FILE *, HOST_WIDEST_INT, int));
-static bool mmix_assemble_integer PARAMS ((rtx, unsigned int, int));
-static struct machine_function * mmix_init_machine_status PARAMS ((void));
-static void mmix_encode_section_info PARAMS ((tree, rtx, int));
-static const char *mmix_strip_name_encoding PARAMS ((const char *));
-static void mmix_emit_sp_add PARAMS ((HOST_WIDE_INT offset));
-static void mmix_target_asm_function_prologue
-  PARAMS ((FILE *, HOST_WIDE_INT));
-static void mmix_target_asm_function_end_prologue PARAMS ((FILE *));
-static void mmix_target_asm_function_epilogue
-  PARAMS ((FILE *, HOST_WIDE_INT));
-static void mmix_reorg PARAMS ((void));
+  (FILE *, const char *, HOST_WIDEST_INT);
+static void mmix_output_shifted_value (FILE *, HOST_WIDEST_INT);
+static void mmix_output_condition (FILE *, rtx, int);
+static HOST_WIDEST_INT mmix_intval (rtx);
+static void mmix_output_octa (FILE *, HOST_WIDEST_INT, int);
+static bool mmix_assemble_integer (rtx, unsigned int, int);
+static struct machine_function *mmix_init_machine_status (void);
+static void mmix_encode_section_info (tree, rtx, int);
+static const char *mmix_strip_name_encoding (const char *);
+static void mmix_emit_sp_add (HOST_WIDE_INT offset);
+static void mmix_target_asm_function_prologue (FILE *, HOST_WIDE_INT);
+static void mmix_target_asm_function_end_prologue (FILE *);
+static void mmix_target_asm_function_epilogue (FILE *, HOST_WIDE_INT);
+static void mmix_reorg (void);
 static void mmix_asm_output_mi_thunk
-  PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree));
-static void mmix_file_start PARAMS ((void));
-static void mmix_file_end PARAMS ((void));
-static bool mmix_rtx_costs
-  PARAMS ((rtx, int, int, int *));
+  (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
+static void mmix_file_start (void);
+static void mmix_file_end (void);
+static bool mmix_rtx_costs (rtx, int, int, int *);
 
 
 /* Target structure macros.  Listed by node.  See `Using and Porting GCC'
@@ -198,7 +195,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
 /* OVERRIDE_OPTIONS.  */
 
 void
-mmix_override_options ()
+mmix_override_options (void)
 {
   /* Should we err or should we warn?  Hmm.  At least we must neutralize
      it.  For example the wrong kind of case-tables will be generated with
@@ -215,7 +212,7 @@ mmix_override_options ()
 /* INIT_EXPANDERS.  */
 
 void
-mmix_init_expanders ()
+mmix_init_expanders (void)
 {
   init_machine_status = mmix_init_machine_status;
 }
@@ -223,7 +220,7 @@ mmix_init_expanders ()
 /* Set the per-function data.  */
 
 static struct machine_function *
-mmix_init_machine_status ()
+mmix_init_machine_status (void)
 {
   return ggc_alloc_cleared (sizeof (struct machine_function));
 }
@@ -234,9 +231,7 @@ mmix_init_machine_status ()
    at least 32-bit alignment. */
 
 int
-mmix_data_alignment (type, basic_align)
-     tree type ATTRIBUTE_UNUSED;
-     int basic_align;
+mmix_data_alignment (tree type ATTRIBUTE_UNUSED, int basic_align)
 {
   if (basic_align < 32)
     return 32;
@@ -247,9 +242,7 @@ mmix_data_alignment (type, basic_align)
 /* CONSTANT_ALIGNMENT.  */
 
 int
-mmix_constant_alignment (constant, basic_align)
-     tree constant ATTRIBUTE_UNUSED;
-     int basic_align;
+mmix_constant_alignment (tree constant ATTRIBUTE_UNUSED, int basic_align)
 {
   if (basic_align < 32)
     return 32;
@@ -260,9 +253,7 @@ mmix_constant_alignment (constant, basic_align)
 /* LOCAL_ALIGNMENT.  */
 
 int
-mmix_local_alignment (type, basic_align)
-     tree type ATTRIBUTE_UNUSED;
-     int basic_align;
+mmix_local_alignment (tree type ATTRIBUTE_UNUSED, int basic_align)
 {
   if (basic_align < 32)
     return 32;
@@ -273,7 +264,7 @@ mmix_local_alignment (type, basic_align)
 /* CONDITIONAL_REGISTER_USAGE.  */
 
 void
-mmix_conditional_register_usage ()
+mmix_conditional_register_usage (void)
 {
   int i;
 
@@ -314,8 +305,7 @@ mmix_conditional_register_usage ()
    saved are local.  */
 
 int
-mmix_local_regno (regno)
-     int regno;
+mmix_local_regno (int regno)
 {
   return regno <= MMIX_LAST_STACK_REGISTER_REGNUM && !call_used_regs[regno];
 }
@@ -324,9 +314,7 @@ mmix_local_regno (regno)
    We need to extend the reload class of REMAINDER_REG and HIMULT_REG.  */
 
 enum reg_class
-mmix_preferred_reload_class (x, class)
-     rtx x ATTRIBUTE_UNUSED;
-     enum reg_class class;
+mmix_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, enum reg_class class)
 {
   /* FIXME: Revisit.  */
   return GET_CODE (x) == MOD && GET_MODE (x) == DImode
@@ -337,9 +325,8 @@ mmix_preferred_reload_class (x, class)
    We need to extend the reload class of REMAINDER_REG and HIMULT_REG.  */
 
 enum reg_class
-mmix_preferred_output_reload_class (x, class)
-     rtx x ATTRIBUTE_UNUSED;
-     enum reg_class class;
+mmix_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED,
+				    enum reg_class class)
 {
   /* FIXME: Revisit.  */
   return GET_CODE (x) == MOD && GET_MODE (x) == DImode
@@ -350,11 +337,10 @@ mmix_preferred_output_reload_class (x, class)
    We need to reload regs of REMAINDER_REG and HIMULT_REG elsewhere.  */
 
 enum reg_class
-mmix_secondary_reload_class (class, mode, x, in_p)
-     enum reg_class class;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx x ATTRIBUTE_UNUSED;
-     int in_p ATTRIBUTE_UNUSED;
+mmix_secondary_reload_class (enum reg_class class,
+			     enum machine_mode mode ATTRIBUTE_UNUSED,
+			     rtx x ATTRIBUTE_UNUSED,
+			     int in_p ATTRIBUTE_UNUSED)
 {
   if (class == REMAINDER_REG
       || class == HIMULT_REG
@@ -367,9 +353,7 @@ mmix_secondary_reload_class (class, mode, x, in_p)
 /* CONST_OK_FOR_LETTER_P.  */
 
 int
-mmix_const_ok_for_letter_p (value, c)
-     HOST_WIDE_INT value;
-     int c;
+mmix_const_ok_for_letter_p (HOST_WIDE_INT value, int c)
 {
   return
     (c == 'I' ? value >= 0 && value <= 255
@@ -386,9 +370,7 @@ mmix_const_ok_for_letter_p (value, c)
 /* CONST_DOUBLE_OK_FOR_LETTER_P.  */
 
 int
-mmix_const_double_ok_for_letter_p (value, c)
-     rtx value;
-     int c;
+mmix_const_double_ok_for_letter_p (rtx value, int c)
 {
   return
     (c == 'G' ? value == CONST0_RTX (GET_MODE (value))
@@ -400,10 +382,7 @@ mmix_const_double_ok_for_letter_p (value, c)
    CONST_INT:s, but rather often as CONST_DOUBLE:s.  */
 
 int
-mmix_extra_constraint (x, c, strict)
-     rtx x;
-     int c;
-     int strict;
+mmix_extra_constraint (rtx x, int c, int strict)
 {
   HOST_WIDEST_INT value;
 
@@ -455,8 +434,7 @@ mmix_extra_constraint (x, c, strict)
 /* DYNAMIC_CHAIN_ADDRESS.  */
 
 rtx
-mmix_dynamic_chain_address (frame)
-     rtx frame;
+mmix_dynamic_chain_address (rtx frame)
 {
   /* FIXME: the frame-pointer is stored at offset -8 from the current
      frame-pointer.  Unfortunately, the caller assumes that a
@@ -468,7 +446,7 @@ mmix_dynamic_chain_address (frame)
 /* STARTING_FRAME_OFFSET.  */
 
 int
-mmix_starting_frame_offset ()
+mmix_starting_frame_offset (void)
 {
   /* The old frame pointer is in the slot below the new one, so
      FIRST_PARM_OFFSET does not need to depend on whether the
@@ -485,9 +463,7 @@ mmix_starting_frame_offset ()
 /* RETURN_ADDR_RTX.  */
 
 rtx
-mmix_return_addr_rtx (count, frame)
-     int count;
-     rtx frame ATTRIBUTE_UNUSED;
+mmix_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
 {
   return count == 0
     ? (MMIX_CFUN_NEEDS_SAVED_EH_RETURN_ADDRESS
@@ -503,7 +479,7 @@ mmix_return_addr_rtx (count, frame)
 /* SETUP_FRAME_ADDRESSES.  */
 
 void
-mmix_setup_frame_addresses ()
+mmix_setup_frame_addresses (void)
 {
   /* Nothing needed at the moment.  */
 }
@@ -512,9 +488,7 @@ mmix_setup_frame_addresses ()
    pointer.  Used to eliminate the frame pointer.  */
 
 int
-mmix_initial_elimination_offset (fromreg, toreg)
-     int fromreg;
-     int toreg;
+mmix_initial_elimination_offset (int fromreg, int toreg)
 {
   int regno;
   int fp_sp_offset
@@ -567,12 +541,11 @@ mmix_initial_elimination_offset (fromreg, toreg)
    one that must go on stack.  */
 
 rtx
-mmix_function_arg (argsp, mode, type, named, incoming)
-     const CUMULATIVE_ARGS * argsp;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
-     int incoming;
+mmix_function_arg (const CUMULATIVE_ARGS *argsp,
+		   enum machine_mode mode,
+		   tree type,
+		   int named ATTRIBUTE_UNUSED,
+		   int incoming)
 {
   /* Last-argument marker.  */
   if (type == void_type_node)
@@ -600,11 +573,10 @@ mmix_function_arg (argsp, mode, type, named, incoming)
    everything that goes by value.  */
 
 int
-mmix_function_arg_pass_by_reference (argsp, mode, type, named)
-     const CUMULATIVE_ARGS * argsp;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+mmix_function_arg_pass_by_reference (const CUMULATIVE_ARGS *argsp,
+				     enum machine_mode mode,
+				     tree type,
+				     int named ATTRIBUTE_UNUSED)
 {
   /* FIXME: Check: I'm not sure the MUST_PASS_IN_STACK check is
      necessary.  */
@@ -619,9 +591,7 @@ mmix_function_arg_pass_by_reference (argsp, mode, type, named)
    passed, and 0 otherwise.  */
 
 int
-mmix_function_arg_regno_p (regno, incoming)
-     int regno;
-     int incoming;
+mmix_function_arg_regno_p (int regno, int incoming)
 {
   int first_arg_regnum
     = incoming ? MMIX_FIRST_INCOMING_ARG_REGNUM : MMIX_FIRST_ARG_REGNUM;
@@ -633,9 +603,7 @@ mmix_function_arg_regno_p (regno, incoming)
 /* FUNCTION_OUTGOING_VALUE.  */
 
 rtx
-mmix_function_outgoing_value (valtype, func)
-     tree valtype;
-     tree func ATTRIBUTE_UNUSED;
+mmix_function_outgoing_value (tree valtype, tree func ATTRIBUTE_UNUSED)
 {
   enum machine_mode mode = TYPE_MODE (valtype);
   enum machine_mode cmode;
@@ -684,8 +652,7 @@ mmix_function_outgoing_value (valtype, func)
 /* FUNCTION_VALUE_REGNO_P.  */
 
 int
-mmix_function_value_regno_p (regno)
-     int regno;
+mmix_function_value_regno_p (int regno)
 {
   return regno == MMIX_RETURN_VALUE_REGNUM;
 }
@@ -693,8 +660,7 @@ mmix_function_value_regno_p (regno)
 /* EH_RETURN_DATA_REGNO. */
 
 int
-mmix_eh_return_data_regno (n)
-     int n ATTRIBUTE_UNUSED;
+mmix_eh_return_data_regno (int n)
 {
   if (n >= 0 && n < 4)
     return MMIX_EH_RETURN_DATA_REGNO_START + n;
@@ -705,7 +671,7 @@ mmix_eh_return_data_regno (n)
 /* EH_RETURN_STACKADJ_RTX. */
 
 rtx
-mmix_eh_return_stackadj_rtx ()
+mmix_eh_return_stackadj_rtx (void)
 {
   return gen_rtx_REG (Pmode, MMIX_EH_RETURN_STACKADJ_REGNUM);
 }
@@ -713,18 +679,16 @@ mmix_eh_return_stackadj_rtx ()
 /* EH_RETURN_HANDLER_RTX.  */
 
 rtx
-mmix_eh_return_handler_rtx ()
+mmix_eh_return_handler_rtx (void)
 {
-  return
-    gen_rtx_REG (Pmode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
+  return gen_rtx_REG (Pmode, MMIX_INCOMING_RETURN_ADDRESS_REGNUM);
 }
 
 /* ASM_PREFERRED_EH_DATA_FORMAT. */
 
 int
-mmix_asm_preferred_eh_data_format (code, global)
-     int code ATTRIBUTE_UNUSED;
-     int global ATTRIBUTE_UNUSED;
+mmix_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED,
+				   int global ATTRIBUTE_UNUSED)
 {
   /* This is the default (was at 2001-07-20).  Revisit when needed.  */
   return DW_EH_PE_absptr;
@@ -735,9 +699,8 @@ mmix_asm_preferred_eh_data_format (code, global)
    mmix_reorg.  */
 
 static void
-mmix_target_asm_function_prologue (stream, framesize)
-     FILE *stream ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT framesize ATTRIBUTE_UNUSED;
+mmix_target_asm_function_prologue (FILE *stream ATTRIBUTE_UNUSED,
+				   HOST_WIDE_INT framesize ATTRIBUTE_UNUSED)
 {
   cfun->machine->in_prologue = 1;
 }
@@ -745,8 +708,7 @@ mmix_target_asm_function_prologue (stream, framesize)
 /* Make a note that we've seen the end of the prologue.  */
 
 static void
-mmix_target_asm_function_end_prologue (stream)
-     FILE *stream ATTRIBUTE_UNUSED;
+mmix_target_asm_function_end_prologue (FILE *stream ATTRIBUTE_UNUSED)
 {
   cfun->machine->in_prologue = 0;
 }
@@ -756,7 +718,7 @@ mmix_target_asm_function_end_prologue (stream)
    register number used to modify the register numbers at output time.  */
 
 static void
-mmix_reorg ()
+mmix_reorg (void)
 {
   int regno;
 
@@ -796,10 +758,8 @@ mmix_reorg ()
 /* TARGET_ASM_FUNCTION_EPILOGUE.  */
 
 static void
-mmix_target_asm_function_epilogue (stream, locals_size)
-     FILE *stream;
-     HOST_WIDE_INT locals_size ATTRIBUTE_UNUSED;
-
+mmix_target_asm_function_epilogue (FILE *stream,
+				   HOST_WIDE_INT locals_size ATTRIBUTE_UNUSED)
 {
   /* Emit an \n for readability of the generated assembly.  */
   fputc ('\n', stream);
@@ -808,12 +768,11 @@ mmix_target_asm_function_epilogue (stream, locals_size)
 /* TARGET_ASM_OUTPUT_MI_THUNK.  */
 
 static void
-mmix_asm_output_mi_thunk (stream, fndecl, delta, vcall_offset, func)
-     FILE * stream;
-     tree fndecl ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
-     tree func;
+mmix_asm_output_mi_thunk (FILE *stream,
+			  tree fndecl ATTRIBUTE_UNUSED,
+			  HOST_WIDE_INT delta,
+			  HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+			  tree func)
 {
   /* If you define STRUCT_VALUE to 0, rather than use STRUCT_VALUE_REGNUM,
      (i.e. pass location of structure to return as invisible first
@@ -838,9 +797,8 @@ mmix_asm_output_mi_thunk (stream, fndecl, delta, vcall_offset, func)
 /* FUNCTION_PROFILER.  */
 
 void
-mmix_function_profiler (stream, labelno)
-     FILE *stream ATTRIBUTE_UNUSED;
-     int labelno ATTRIBUTE_UNUSED;
+mmix_function_profiler (FILE *stream ATTRIBUTE_UNUSED,
+			int labelno ATTRIBUTE_UNUSED)
 {
   sorry ("function_profiler support for MMIX");
 }
@@ -848,13 +806,11 @@ mmix_function_profiler (stream, labelno)
 /* SETUP_INCOMING_VARARGS.  */
 
 void
-mmix_setup_incoming_varargs (args_so_farp, mode, vartype, pretend_sizep,
-			     second_time)
-     CUMULATIVE_ARGS * args_so_farp;
-     enum machine_mode mode;
-     tree vartype;
-     int * pretend_sizep;
-     int second_time ATTRIBUTE_UNUSED;
+mmix_setup_incoming_varargs (CUMULATIVE_ARGS *args_so_farp,
+			     enum machine_mode mode,
+			     tree vartype,
+			     int *pretend_sizep,
+			     int second_time ATTRIBUTE_UNUSED)
 {
   /* The last named variable has been handled, but
      args_so_farp has not been advanced for it.  */
@@ -875,9 +831,7 @@ mmix_setup_incoming_varargs (args_so_farp, mode, vartype, pretend_sizep,
    pass-by-reference, then perform an indirection.  */
 
 rtx
-mmix_expand_builtin_va_arg (valist, type)
-     tree valist;
-     tree type;
+mmix_expand_builtin_va_arg (tree valist, tree type)
 {
   tree ptr_size = size_int (BITS_PER_WORD / BITS_PER_UNIT);
   tree addr_tree, type_size = NULL;
@@ -982,8 +936,7 @@ int mmix_trampoline_size = 32;
 /* TRAMPOLINE_TEMPLATE.  */
 
 void
-mmix_trampoline_template (stream)
-     FILE * stream;
+mmix_trampoline_template (FILE *stream)
 {
   /* Read a value into the static-chain register and jump somewhere.  The
      static chain is stored at offset 16, and the function address is
@@ -1005,10 +958,7 @@ mmix_trampoline_template (stream)
    some day it will).  */
 
 void
-mmix_initialize_trampoline (trampaddr, fnaddr, static_chain)
-     rtx trampaddr;
-     rtx fnaddr;
-     rtx static_chain;
+mmix_initialize_trampoline (rtx trampaddr, rtx fnaddr, rtx static_chain)
 {
   emit_move_insn (gen_rtx_MEM (DImode, plus_constant (trampaddr, 16)),
 		  static_chain);
@@ -1025,8 +975,7 @@ mmix_initialize_trampoline (trampaddr, fnaddr, static_chain)
    instruction, unless TARGET_BASE_ADDRESSES.  */
 
 int
-mmix_constant_address_p (x)
-     rtx x;
+mmix_constant_address_p (rtx x)
 {
   RTX_CODE code = GET_CODE (x);
   int addend = 0;
@@ -1089,10 +1038,9 @@ mmix_constant_address_p (x)
    Used by GO_IF_LEGITIMATE_ADDRESS.  */
 
 int
-mmix_legitimate_address (mode, x, strict_checking)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx x;
-     int strict_checking;
+mmix_legitimate_address (enum machine_mode mode ATTRIBUTE_UNUSED,
+			 rtx x,
+			 int strict_checking)
 {
 #define MMIX_REG_OK(X)							\
   ((strict_checking							\
@@ -1151,8 +1099,7 @@ mmix_legitimate_address (mode, x, strict_checking)
 /* LEGITIMATE_CONSTANT_P.  */
 
 int
-mmix_legitimate_constant_p (x)
-     rtx x;
+mmix_legitimate_constant_p (rtx x)
 {
   RTX_CODE code = GET_CODE (x);
 
@@ -1168,10 +1115,7 @@ mmix_legitimate_constant_p (x)
 /* SELECT_CC_MODE.  */
 
 enum machine_mode
-mmix_select_cc_mode (op, x, y)
-     RTX_CODE op;
-     rtx x;
-     rtx y ATTRIBUTE_UNUSED;
+mmix_select_cc_mode (RTX_CODE op, rtx x, rtx y ATTRIBUTE_UNUSED)
 {
   /* We use CCmode, CC_UNSmode, CC_FPmode, CC_FPEQmode and CC_FUNmode to
      output different compare insns.  Note that we do not check the
@@ -1198,8 +1142,7 @@ mmix_select_cc_mode (op, x, y)
 /* REVERSIBLE_CC_MODE.  */
 
 int
-mmix_reversible_cc_mode (mode)
-     enum machine_mode mode;
+mmix_reversible_cc_mode (enum machine_mode mode)
 {
   /* That is, all integer and the EQ, NE, ORDERED and UNORDERED float
      compares.  */
@@ -1209,11 +1152,10 @@ mmix_reversible_cc_mode (mode)
 /* TARGET_RTX_COSTS.  */
 
 static bool
-mmix_rtx_costs (x, code, outer_code, total)
-     rtx x ATTRIBUTE_UNUSED;
-     int code ATTRIBUTE_UNUSED;
-     int outer_code ATTRIBUTE_UNUSED;
-     int *total ATTRIBUTE_UNUSED;
+mmix_rtx_costs (rtx x ATTRIBUTE_UNUSED,
+		int code ATTRIBUTE_UNUSED,
+		int outer_code ATTRIBUTE_UNUSED,
+		int *total ATTRIBUTE_UNUSED)
 {
   /* For the time being, this is just a stub and we'll accept the
      generic calculations, until we can do measurements, at least.
@@ -1224,10 +1166,9 @@ mmix_rtx_costs (x, code, outer_code, total)
 /* REGISTER_MOVE_COST.  */
 
 int
-mmix_register_move_cost (mode, from, to)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     enum reg_class from;
-     enum reg_class to;
+mmix_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
+			 enum reg_class from,
+			 enum reg_class to)
 {
   return (from == GENERAL_REGS && from == to) ? 2 : 3;
 }
@@ -1239,16 +1180,13 @@ mmix_register_move_cost (mode, from, to)
 /* DATA_SECTION_ASM_OP.  */
 
 const char *
-mmix_data_section_asm_op ()
+mmix_data_section_asm_op (void)
 {
   return "\t.data ! mmixal:= 8H LOC 9B";
 }
 
 static void
-mmix_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+mmix_encode_section_info (tree decl, rtx rtl, int first)
 {
   /* Test for an external declaration, and do nothing if it is one.  */
   if ((TREE_CODE (decl) == VAR_DECL
@@ -1293,8 +1231,7 @@ mmix_encode_section_info (decl, rtl, first)
 }
 
 static const char *
-mmix_strip_name_encoding (name)
-     const char *name;
+mmix_strip_name_encoding (const char *name)
 {
   for (; (*name == '@' || *name == '*'); name++)
     ;
@@ -1306,7 +1243,7 @@ mmix_strip_name_encoding (name)
    We just emit a little comment for the time being.  */
 
 static void
-mmix_file_start ()
+mmix_file_start (void)
 {
   default_file_start ();
 
@@ -1319,7 +1256,7 @@ mmix_file_start ()
 /* TARGET_ASM_FILE_END.  */
 
 static void
-mmix_file_end ()
+mmix_file_end (void)
 {
   /* Make sure each file ends with the data section. */
   data_section ();
@@ -1328,9 +1265,7 @@ mmix_file_end ()
 /* ASM_OUTPUT_SOURCE_FILENAME.  */
 
 void
-mmix_asm_output_source_filename (stream, name)
-     FILE * stream;
-     const char * name;
+mmix_asm_output_source_filename (FILE *stream, const char *name)
 {
   fprintf (stream, "# 1 ");
   OUTPUT_QUOTED_STRING (stream, name);
@@ -1340,10 +1275,7 @@ mmix_asm_output_source_filename (stream, name)
 /* OUTPUT_QUOTED_STRING.  */
 
 void
-mmix_output_quoted_string (stream, string, length)
-     FILE * stream;
-     const char * string;
-     int length;
+mmix_output_quoted_string (FILE *stream, const char *string, int length)
 {
   const char * string_end = string + length;
   static const char *const unwanted_chars = "\"[]\\";
@@ -1387,9 +1319,7 @@ mmix_output_quoted_string (stream, string, length)
 /* ASM_OUTPUT_SOURCE_LINE.  */
 
 void
-mmix_asm_output_source_line  (stream, lineno)
-     FILE * stream;
-     int lineno;
+mmix_asm_output_source_line  (FILE *stream, int lineno)
 {
   fprintf (stream, "# %d ", lineno);
   OUTPUT_QUOTED_STRING (stream, main_input_filename);
@@ -1401,10 +1331,7 @@ mmix_asm_output_source_line  (stream, lineno)
    CONST_DOUBLEs.  */
 
 static bool
-mmix_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if (aligned_p)
     switch (size)
@@ -1465,10 +1392,7 @@ mmix_assemble_integer (x, size, aligned_p)
 /* ASM_OUTPUT_ASCII.  */
 
 void
-mmix_asm_output_ascii (stream, string, length)
-     FILE *stream;
-     const char *string;
-     int length;
+mmix_asm_output_ascii (FILE *stream, const char *string, int length)
 {
   while (length > 0)
     {
@@ -1484,11 +1408,10 @@ mmix_asm_output_ascii (stream, string, length)
 /* ASM_OUTPUT_ALIGNED_COMMON.  */
 
 void
-mmix_asm_output_aligned_common (stream, name, size, align)
-     FILE *stream;
-     const char *name;
-     int size;
-     int align;
+mmix_asm_output_aligned_common (FILE *stream,
+				const char *name,
+				int size,
+				int align)
 {
   /* This is mostly the elfos.h one.  There doesn't seem to be a way to
      express this in a mmixal-compatible way.  */
@@ -1501,11 +1424,10 @@ mmix_asm_output_aligned_common (stream, name, size, align)
 /* ASM_OUTPUT_ALIGNED_LOCAL.  */
 
 void
-mmix_asm_output_aligned_local (stream, name, size, align)
-     FILE * stream;
-     const char * name;
-     int size;
-     int align;
+mmix_asm_output_aligned_local (FILE *stream,
+			       const char *name,
+			       int size,
+			       int align)
 {
   data_section ();
 
@@ -1517,9 +1439,7 @@ mmix_asm_output_aligned_local (stream, name, size, align)
 /* ASM_OUTPUT_LABEL.  */
 
 void
-mmix_asm_output_label (stream, name)
-     FILE *stream;
-     const char * name;
+mmix_asm_output_label (FILE *stream, const char *name)
 {
   assemble_name (stream, name);
   fprintf (stream, "\tIS @\n");
@@ -1528,11 +1448,10 @@ mmix_asm_output_label (stream, name)
 /* ASM_DECLARE_REGISTER_GLOBAL.  */
 
 void
-mmix_asm_declare_register_global (stream, decl, regno, name)
-     FILE *stream ATTRIBUTE_UNUSED;
-     tree decl ATTRIBUTE_UNUSED;
-     int regno ATTRIBUTE_UNUSED;
-     const char *name ATTRIBUTE_UNUSED;
+mmix_asm_declare_register_global (FILE *stream ATTRIBUTE_UNUSED,
+				  tree decl ATTRIBUTE_UNUSED,
+				  int regno ATTRIBUTE_UNUSED,
+				  const char *name ATTRIBUTE_UNUSED)
 {
   /* Nothing to do here, but there *will* be, therefore the framework is
      here.  */
@@ -1541,9 +1460,8 @@ mmix_asm_declare_register_global (stream, decl, regno, name)
 /* ASM_WEAKEN_LABEL.  */
 
 void
-mmix_asm_weaken_label (stream, name)
-     FILE * stream ATTRIBUTE_UNUSED;
-     const char * name ATTRIBUTE_UNUSED;
+mmix_asm_weaken_label (FILE *stream ATTRIBUTE_UNUSED,
+		       const char *name ATTRIBUTE_UNUSED)
 {
   fprintf (stream, "\t.weak ");
   assemble_name (stream, name);
@@ -1553,8 +1471,7 @@ mmix_asm_weaken_label (stream, name)
 /* MAKE_DECL_ONE_ONLY.  */
 
 void
-mmix_make_decl_one_only (decl)
-     tree decl;
+mmix_make_decl_one_only (tree decl)
 {
   DECL_WEAK (decl) = 1;
 }
@@ -1563,9 +1480,7 @@ mmix_make_decl_one_only (decl)
    Strip GCC's '*' and our own '@'.  No order is assumed.  */
 
 void
-mmix_asm_output_labelref (stream, name)
-     FILE *stream;
-     const char *name;
+mmix_asm_output_labelref (FILE *stream, const char *name)
 {
   int is_extern = 1;
 
@@ -1581,10 +1496,7 @@ mmix_asm_output_labelref (stream, name)
 /* ASM_OUTPUT_DEF.  */
 
 void
-mmix_asm_output_def (stream, name, value)
-     FILE * stream;
-     const char * name;
-     const char * value;
+mmix_asm_output_def (FILE *stream, const char *name, const char *value)
 {
   assemble_name (stream, name);
   fprintf (stream, "\tIS ");
@@ -1595,10 +1507,7 @@ mmix_asm_output_def (stream, name, value)
 /* PRINT_OPERAND.  */
 
 void
-mmix_print_operand (stream, x, code)
-     FILE * stream;
-     rtx x;
-     int code;
+mmix_print_operand (FILE *stream, rtx x, int code)
 {
   /* When we add support for different codes later, we can, when needed,
      drop through to the main handler with a modified operand.  */
@@ -1825,8 +1734,7 @@ mmix_print_operand (stream, x, code)
 /* PRINT_OPERAND_PUNCT_VALID_P.  */
 
 int
-mmix_print_operand_punct_valid_p (code)
-     int code ATTRIBUTE_UNUSED;
+mmix_print_operand_punct_valid_p (int code ATTRIBUTE_UNUSED)
 {
   /* A '+' is used for branch prediction, similar to other ports.  */
   return code == '+'
@@ -1837,9 +1745,7 @@ mmix_print_operand_punct_valid_p (code)
 /* PRINT_OPERAND_ADDRESS.  */
 
 void
-mmix_print_operand_address (stream, x)
-     FILE *stream;
-     rtx x;
+mmix_print_operand_address (FILE *stream, rtx x)
 {
   if (REG_P (x))
     {
@@ -1884,9 +1790,7 @@ mmix_print_operand_address (stream, x)
 /* ASM_OUTPUT_REG_PUSH.  */
 
 void
-mmix_asm_output_reg_push (stream, regno)
-     FILE * stream;
-     int regno;
+mmix_asm_output_reg_push (FILE *stream, int regno)
 {
   fprintf (stream, "\tSUBU %s,%s,8\n\tSTOU %s,%s,0\n",
 	   reg_names[MMIX_STACK_POINTER_REGNUM],
@@ -1898,9 +1802,7 @@ mmix_asm_output_reg_push (stream, regno)
 /* ASM_OUTPUT_REG_POP.  */
 
 void
-mmix_asm_output_reg_pop (stream, regno)
-     FILE * stream;
-     int regno;
+mmix_asm_output_reg_pop (FILE *stream, int regno)
 {
   fprintf (stream, "\tLDOU %s,%s,0\n\tINCL %s,8\n",
 	   reg_names[MMIX_OUTPUT_REGNO (regno)],
@@ -1911,11 +1813,10 @@ mmix_asm_output_reg_pop (stream, regno)
 /* ASM_OUTPUT_ADDR_DIFF_ELT.  */
 
 void
-mmix_asm_output_addr_diff_elt (stream, body, value, rel)
-     FILE *stream;
-     rtx body ATTRIBUTE_UNUSED;
-     int value;
-     int rel;
+mmix_asm_output_addr_diff_elt (FILE *stream,
+			       rtx body ATTRIBUTE_UNUSED,
+			       int value,
+			       int rel)
 {
   fprintf (stream, "\tTETRA L%d-L%d\n", value, rel);
 }
@@ -1923,9 +1824,7 @@ mmix_asm_output_addr_diff_elt (stream, body, value, rel)
 /* ASM_OUTPUT_ADDR_VEC_ELT.  */
 
 void
-mmix_asm_output_addr_vec_elt (stream, value)
-     FILE *stream;
-     int value;
+mmix_asm_output_addr_vec_elt (FILE *stream, int value)
 {
   fprintf (stream, "\tOCTA L:%d\n", value);
 }
@@ -1933,9 +1832,7 @@ mmix_asm_output_addr_vec_elt (stream, value)
 /* ASM_OUTPUT_SKIP.  */
 
 void
-mmix_asm_output_skip (stream, nbytes)
-     FILE *stream;
-     int nbytes;
+mmix_asm_output_skip (FILE *stream, int nbytes)
 {
   fprintf (stream, "\tLOC @+%d\n", nbytes);
 }
@@ -1943,9 +1840,7 @@ mmix_asm_output_skip (stream, nbytes)
 /* ASM_OUTPUT_ALIGN.  */
 
 void
-mmix_asm_output_align (stream, power)
-     FILE *stream;
-     int power;
+mmix_asm_output_align (FILE *stream, int power)
 {
   /* We need to record the needed alignment of this section in the object,
      so we have to output an alignment directive.  Use a .p2align (not
@@ -1960,8 +1855,7 @@ mmix_asm_output_align (stream, power)
 /* DBX_REGISTER_NUMBER.  */
 
 int
-mmix_dbx_register_number (regno)
-     int regno;
+mmix_dbx_register_number (int regno)
 {
   /* Adjust the register number to the one it will be output as, dammit.
      It'd be nice if we could check the assumption that we're filling a
@@ -1979,15 +1873,13 @@ mmix_dbx_register_number (regno)
 
 /* End of target macro support functions.
 
-   Now MMIX's own functions.  First the exported ones.  */
+   Now the MMIX port's own functions.  First the exported ones.  */
 
 /* Wrapper for get_hard_reg_initial_val since integrate.h isn't included
    from insn-emit.c.  */
 
 rtx
-mmix_get_hard_reg_initial_val (mode, regno)
-     enum machine_mode mode;
-     int regno;
+mmix_get_hard_reg_initial_val (enum machine_mode mode, int regno)
 {
   return get_hard_reg_initial_val (mode, regno);
 }
@@ -1996,7 +1888,7 @@ mmix_get_hard_reg_initial_val (mode, regno)
    "POP %d,0" should be used even within the function.  */
 
 int
-mmix_use_simple_return ()
+mmix_use_simple_return (void)
 {
   int regno;
 
@@ -2033,7 +1925,7 @@ mmix_use_simple_return ()
 /* Expands the function prologue into RTX.  */
 
 void
-mmix_expand_prologue ()
+mmix_expand_prologue (void)
 {
   HOST_WIDE_INT locals_size = get_frame_size ();
   int regno;
@@ -2268,7 +2160,7 @@ mmix_expand_prologue ()
 /* Expands the function epilogue into RTX.  */
 
 void
-mmix_expand_epilogue ()
+mmix_expand_epilogue (void)
 {
   HOST_WIDE_INT locals_size = get_frame_size ();
   int regno;
@@ -2391,11 +2283,10 @@ mmix_expand_epilogue ()
    first insn and after the last insn is wanted.  */
 
 void
-mmix_output_register_setting (stream, regno, value, do_begin_end)
-     FILE *stream;
-     int regno;
-     HOST_WIDEST_INT value;
-     int do_begin_end;
+mmix_output_register_setting (FILE *stream,
+			      int regno,
+			      HOST_WIDEST_INT value,
+			      int do_begin_end)
 {
   if (do_begin_end)
     fprintf (stream, "\t");
@@ -2503,8 +2394,7 @@ mmix_output_register_setting (stream, regno, value, do_begin_end)
    else return 0.  */
 
 int
-mmix_shiftable_wyde_value (value)
-     unsigned HOST_WIDEST_INT value;
+mmix_shiftable_wyde_value (unsigned HOST_WIDEST_INT value)
 {
   /* Shift by 16 bits per group, stop when we've found two groups with
      nonzero bits.  */
@@ -2530,9 +2420,7 @@ mmix_shiftable_wyde_value (value)
 /* True if this is an address_operand or a symbolic operand.  */
 
 int
-mmix_symbolic_or_address_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_symbolic_or_address_operand (rtx op, enum machine_mode mode)
 {
   switch (GET_CODE (op))
     {
@@ -2558,9 +2446,7 @@ mmix_symbolic_or_address_operand (op, mode)
    doesn't seem to be worth it at the moment.  */
 
 int
-mmix_reg_or_constant_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_reg_or_constant_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode)
     || (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == VOIDmode)
@@ -2570,9 +2456,7 @@ mmix_reg_or_constant_operand (op, mode)
 /* True if this is a register with a condition-code mode.  */
 
 int
-mmix_reg_cc_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_reg_cc_operand (rtx op, enum machine_mode mode)
 {
   if (mode == VOIDmode)
     mode = GET_MODE (op);
@@ -2587,9 +2471,7 @@ mmix_reg_cc_operand (op, mode)
    replaced by (reg).  */
 
 int
-mmix_foldable_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_foldable_comparison_operator (rtx op, enum machine_mode mode)
 {
   RTX_CODE code = GET_CODE (op);
 
@@ -2614,9 +2496,7 @@ mmix_foldable_comparison_operator (op, mode)
    code with -ffast-math (gcc.dg/20001228-1.c).  */
 
 int
-mmix_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_comparison_operator (rtx op, enum machine_mode mode)
 {
   RTX_CODE code = GET_CODE (op);
 
@@ -2652,9 +2532,7 @@ mmix_comparison_operator (op, mode)
 /* True if this is a register or 0 (int or float).  */
 
 int
-mmix_reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_reg_or_0_operand (rtx op, enum machine_mode mode)
 {
   /* FIXME: Is mode calculation necessary and correct?  */
   return
@@ -2665,9 +2543,7 @@ mmix_reg_or_0_operand (op, mode)
 /* True if this is a register or an int 0..255.  */
 
 int
-mmix_reg_or_8bit_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mmix_reg_or_8bit_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode)
     || (GET_CODE (op) == CONST_INT
@@ -2679,10 +2555,7 @@ mmix_reg_or_8bit_operand (op, mode)
    is the comparison of mode is CC-somethingmode.  */
 
 int
-mmix_valid_comparison (code, mode, op)
-     RTX_CODE code;
-     enum machine_mode mode;
-     rtx op;
+mmix_valid_comparison (RTX_CODE code, enum machine_mode mode, rtx op)
 {
   if (mode == VOIDmode && op != NULL_RTX)
     mode = GET_MODE (op);
@@ -2711,9 +2584,7 @@ mmix_valid_comparison (code, mode, op)
    NULL_RTX if this is not a valid comparison.  */
 
 rtx
-mmix_gen_compare_reg (code, x, y)
-     RTX_CODE code;
-     rtx x, y;
+mmix_gen_compare_reg (RTX_CODE code, rtx x, rtx y)
 {
   enum machine_mode ccmode = SELECT_CC_MODE (code, x, y);
   rtx cc_reg;
@@ -2748,8 +2619,7 @@ mmix_gen_compare_reg (code, x, y)
 /* Local (static) helper functions.  */
 
 static void
-mmix_emit_sp_add (offset)
-     HOST_WIDE_INT offset;
+mmix_emit_sp_add (HOST_WIDE_INT offset)
 {
   rtx insn;
 
@@ -2793,10 +2663,9 @@ mmix_emit_sp_add (offset)
    wyde.  The type of operator is passed as an asm output modifier.  */
 
 static void
-mmix_output_shiftvalue_op_from_str (stream, mainop, value)
-     FILE *stream;
-     const char *mainop;
-     HOST_WIDEST_INT value;
+mmix_output_shiftvalue_op_from_str (FILE *stream,
+				    const char *mainop,
+				    HOST_WIDEST_INT value)
 {
   static const char *const op_part[] = {"L", "ML", "MH", "H"};
   int i;
@@ -2827,10 +2696,7 @@ mmix_output_shiftvalue_op_from_str (stream, mainop, value)
 /* Print a 64-bit value, optionally prefixed by assembly pseudo.  */
 
 static void
-mmix_output_octa (stream, value, do_begin_end)
-     FILE *stream;
-     HOST_WIDEST_INT value;
-     int do_begin_end;
+mmix_output_octa (FILE *stream, HOST_WIDEST_INT value, int do_begin_end)
 {
   /* Snipped from final.c:output_addr_const.  We need to avoid the
      presumed universal "0x" prefix.  We can do it by replacing "0x" with
@@ -2864,9 +2730,7 @@ mmix_output_octa (stream, value, do_begin_end)
    be output with an operand).  */
 
 static void
-mmix_output_shifted_value (stream, value)
-     FILE * stream;
-     HOST_WIDEST_INT value;
+mmix_output_shifted_value (FILE *stream, HOST_WIDEST_INT value)
 {
   int i;
 
@@ -2878,13 +2742,13 @@ mmix_output_shifted_value (stream, value)
     }
 
   for (i = 0; i < 4; i++)
-  {
-    /* We know we're through when we find one-bits in the low 16 bits.  */
-    if (value & 0xffff)
     {
-      fprintf (stream, "#%x", (int) (value & 0xffff));
-      return;
-    }
+      /* We know we're through when we find one-bits in the low 16 bits.  */
+      if (value & 0xffff)
+	{
+	  fprintf (stream, "#%x", (int) (value & 0xffff));
+	  return;
+	}
 
     value >>= 16;
   }
@@ -2902,10 +2766,7 @@ mmix_output_shifted_value (stream, value)
    same as swapping the arguments).  */
 
 static void
-mmix_output_condition (stream, x, reversed)
-     FILE *stream;
-     rtx x;
-     int reversed;
+mmix_output_condition (FILE *stream, rtx x, int reversed)
 {
   struct cc_conv
   {
@@ -3010,8 +2871,7 @@ mmix_output_condition (stream, x, reversed)
 /* Return the bit-value for a const_int or const_double.  */
 
 static HOST_WIDEST_INT
-mmix_intval (x)
-     rtx x;
+mmix_intval (rtx x)
 {
   unsigned HOST_WIDEST_INT retval;
 
diff --git a/gcc/config/mn10300/linux.h b/gcc/config/mn10300/linux.h
new file mode 100644
index 00000000000..1ae5b013110
--- /dev/null
+++ b/gcc/config/mn10300/linux.h
@@ -0,0 +1,116 @@
+/* Definitions of taret machine for GNU compiler.
+   Matsushita AM33/2.0
+   Copyright 2001, 2002 Free Software Foundation, Inc.
+   Contributed by Alexandre Oliva <aoliva@redhat.com>
+
+   This file is part of GNU CC.
+
+   GNU CC is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GNU CC is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GNU CC; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+   
+#undef  PREFERRED_DEBUGGING_TYPE
+#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
+
+#define TARGET_OS_CPP_BUILTINS()		\
+    do						\
+      {						\
+	builtin_define_std ("unix");		\
+	builtin_define_std ("linux");		\
+	builtin_define ("__gnu_linux__");	\
+	builtin_assert ("system=unix");		\
+	builtin_assert ("system=posix");	\
+      }						\
+    while (0)
+
+#undef  CPP_SPEC
+#define CPP_SPEC "%{mam33:-D__AM33__} %{!mam33:-D__AM33__=2 -D__AM33_2__} \
+  %{posix:-D_POSIX_SOURCE} \
+  %{pthread:-D_REENTRANT -D_PTHREADS}"
+
+#undef  ASM_SPEC
+#define ASM_SPEC "%{Wa,*:%*}"
+
+#undef  LINK_SPEC
+#define LINK_SPEC "%{mrelax:--relax} %{shared:-shared} \
+   %{!static: \
+     %{rdynamic:-export-dynamic} \
+     %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}} \
+   %{static:-static}"
+
+#undef  LIB_SPEC
+#define LIB_SPEC \
+  "%{shared: -lc} \
+   %{!static:-rpath-link %R/lib:%R/usr/lib} \
+   %{!shared: %{pthread:-lpthread} \
+     %{profile:-lc_p} %{!profile: -lc}}"
+
+#undef  STARTFILE_SPEC
+#define STARTFILE_SPEC \
+  "%{!shared: \
+     %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \
+		       %{!p:%{profile:gcrt1.o%s} \
+			 %{!profile:crt1.o%s}}}} \
+   crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
+
+#undef  TARGET_SWITCHES
+#define TARGET_SWITCHES	\
+  {{ "am33",		-0x4,	N_("Target the AM33 processor") }, \
+   { "am33-2",		6,	N_("Target the AM33/2.0 processor") }, \
+   { "relax",		0,	N_("Enable linker relaxations") }, \
+   { "", TARGET_DEFAULT, NULL }}
+
+#undef  TARGET_DEFAULT
+#define TARGET_DEFAULT 6
+
+#undef  TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (AM33/2.0 GNU/Linux)");
+
+#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
+
+extern int mn10300_protect_label;
+
+#undef  PRINT_OPERAND
+#define PRINT_OPERAND(FILE, X, CODE)		\
+  do						\
+    {						\
+      mn10300_protect_label = 1;		\
+      print_operand ((FILE), (X), (CODE));	\
+      mn10300_protect_label = 0;		\
+    }						\
+  while (0)
+
+#undef  PRINT_OPERAND_ADDRESS
+#define PRINT_OPERAND_ADDRESS(FILE, X)		\
+  do						\
+    {						\
+      mn10300_protect_label = 1;		\
+      print_operand_address ((FILE), (X));	\
+      mn10300_protect_label = 0;		\
+    }						\
+   while (0)
+
+#undef  ASM_OUTPUT_LABELREF
+#define ASM_OUTPUT_LABELREF(FILE, NAME)		\
+  do						\
+    {						\
+      const char * real_name;			\
+						\
+      real_name = (*targetm.strip_name_encoding) (NAME);	\
+      if (mn10300_protect_label)		\
+        asm_fprintf (FILE, "+");		\
+      asm_fprintf (FILE, "%U%s", real_name);	\
+    }						\
+  while (0)           
+
diff --git a/gcc/config/mn10300/mn10300-protos.h b/gcc/config/mn10300/mn10300-protos.h
index 209a7e6c891..74154d92494 100644
--- a/gcc/config/mn10300/mn10300-protos.h
+++ b/gcc/config/mn10300/mn10300-protos.h
@@ -26,6 +26,8 @@ extern void mn10300_va_start PARAMS ((tree, rtx));
 #endif /* TREE_CODE */
 
 extern struct rtx_def *legitimize_address PARAMS ((rtx, rtx, enum machine_mode));
+extern rtx legitimize_pic_address   (rtx, rtx);
+extern int legitimate_pic_operand_p (rtx);
 extern void print_operand PARAMS ((FILE *, rtx, int));
 extern void print_operand_address PARAMS ((FILE *, rtx));
 extern void mn10300_print_reg_list PARAMS ((FILE *, int));
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index df5d35fb770..3e14de37643 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -44,6 +44,16 @@ Boston, MA 02111-1307, USA.  */
 #include "target.h"
 #include "target-def.h"
 
+/* This is used by GOTaddr2picreg to uniquely identify
+   UNSPEC_INT_LABELs.  */
+int mn10300_unspec_int_label_counter;
+
+/* This is used in the am33_2.0-linux-gnu port, in which global symbol
+   names are not prefixed by underscores, to tell whether to prefix a
+   label with a plus sign or not, so that the assembler can tell
+   symbol names from register names.  */
+int mn10300_protect_label;
+
 /* The size of the callee register save area.  Right now we save everything
    on entry since it costs us nothing in code size.  It does cost us from a
    speed standpoint, so we want to optimize this sooner or later.  */
@@ -75,6 +85,10 @@ static void mn10300_file_start PARAMS ((void));
 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
 
+#undef  TARGET_ENCODE_SECTION_INFO
+#define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
+
+static void mn10300_encode_section_info (tree, rtx, int);
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 static void
@@ -82,7 +96,9 @@ mn10300_file_start ()
 {
   default_file_start ();
 
-  if (TARGET_AM33)
+  if (TARGET_AM33_2)
+    fprintf (asm_out_file, "\t.am33_2\n");
+  else if (TARGET_AM33)
     fprintf (asm_out_file, "\t.am33\n");
 }
 
@@ -100,6 +116,58 @@ print_operand (file, x, code)
     {
       case 'b':
       case 'B':
+	if (cc_status.mdep.fpCC)
+	  {
+	    switch (code == 'b' ? GET_CODE (x)
+		    : reverse_condition_maybe_unordered (GET_CODE (x)))
+	      {
+	      case NE:
+		fprintf (file, "ne");
+		break;
+	      case EQ:
+		fprintf (file, "eq");
+		break;
+	      case GE:
+		fprintf (file, "ge");
+		break;
+	      case GT:
+		fprintf (file, "gt");
+		break;
+	      case LE:
+		fprintf (file, "le");
+		break;
+	      case LT:
+		fprintf (file, "lt");
+		break;
+	      case ORDERED:
+		fprintf (file, "lge");
+		break;
+	      case UNORDERED:
+		fprintf (file, "uo");
+		break;
+	      case LTGT:
+		fprintf (file, "lg");
+		break;
+	      case UNEQ:
+		fprintf (file, "ue");
+		break;
+	      case UNGE:
+		fprintf (file, "uge");
+		break;
+	      case UNGT:
+		fprintf (file, "ug");
+		break;
+	      case UNLE:
+		fprintf (file, "ule");
+		break;
+	      case UNLT:
+		fprintf (file, "ul");
+		break;
+	      default:
+		abort ();
+	      }
+	    break;
+	  }
 	/* These are normal and reversed branches.  */
 	switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
 	  {
@@ -151,6 +219,24 @@ print_operand (file, x, code)
 	  print_operand (file, x, 0);
 	break;
      
+      case 'D':
+	switch (GET_CODE (x))
+	  {
+	  case MEM:
+	    fputc ('(', file);
+	    output_address (XEXP (x, 0));
+	    fputc (')', file);
+	    break;
+
+	  case REG:
+	    fprintf (file, "fd%d", REGNO (x) - 18);
+	    break;
+
+	  default:
+	    abort ();
+	  }
+	break;
+
       /* These are the least significant word in a 64bit value.  */
       case 'L':
 	switch (GET_CODE (x))
@@ -338,6 +424,7 @@ print_operand (file, x, code)
 	  case CONST:
 	  case LABEL_REF:
 	  case CODE_LABEL:
+	  case UNSPEC:
 	    print_operand_address (file, x);
 	    break;
 	  default:
@@ -388,6 +475,22 @@ print_operand_address (file, addr)
     }
 }
 
+/* Count the number of FP registers that have to be saved.  */
+static int
+fp_regs_to_save ()
+{
+  int i, n = 0;
+
+  if (! TARGET_AM33_2)
+    return 0;
+
+  for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
+    if (regs_ever_live[i] && ! call_used_regs[i])
+      ++n;
+
+  return n;
+}
+
 /* Print a set of registers in the format required by "movm" and "ret".
    Register K is saved if bit K of MASK is set.  The data and address
    registers can be stored individually, but the extended registers cannot.
@@ -446,6 +549,7 @@ can_use_return_insn ()
 	  && !regs_ever_live[15]
 	  && !regs_ever_live[16]
 	  && !regs_ever_live[17]
+	  && fp_regs_to_save () == 0
 	  && !frame_pointer_needed);
 }
 
@@ -460,7 +564,7 @@ mn10300_get_live_callee_saved_regs ()
   int i;
 
   mask = 0;
-  for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+  for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
     if (regs_ever_live[i] && ! call_used_regs[i])
       mask |= (1 << i);
   if ((mask & 0x3c000) != 0)
@@ -501,7 +605,7 @@ mn10300_gen_multiple_store (mask)
 
       /* Count how many registers need to be saved. */
       count = 0;
-      for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+      for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
 	if ((mask & (1 << i)) != 0)
 	  count += 1;
 
@@ -519,7 +623,7 @@ mn10300_gen_multiple_store (mask)
 
       /* Create each store. */
       pari = 1;
-      for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+      for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
 	if ((mask & (1 << i)) != 0)
 	  {
 	    rtx address = gen_rtx_PLUS (SImode,
@@ -549,6 +653,240 @@ expand_prologue ()
   /* If we use any of the callee-saved registers, save them now. */
   mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
 
+  if (TARGET_AM33_2 && fp_regs_to_save ())
+    {
+      int num_regs_to_save = fp_regs_to_save (), i;
+      HOST_WIDE_INT xsize;
+      enum { save_sp_merge,
+	     save_sp_no_merge,
+	     save_sp_partial_merge,
+	     save_a0_merge,
+	     save_a0_no_merge } strategy;
+      unsigned int strategy_size = (unsigned)-1, this_strategy_size;
+      rtx reg;
+      rtx insn;
+
+      /* We have several different strategies to save FP registers.
+	 We can store them using SP offsets, which is beneficial if
+	 there are just a few registers to save, or we can use `a0' in
+	 post-increment mode (`a0' is the only call-clobbered address
+	 register that is never used to pass information to a
+	 function).  Furthermore, if we don't need a frame pointer, we
+	 can merge the two SP adds into a single one, but this isn't
+	 always beneficial; sometimes we can just split the two adds
+	 so that we don't exceed a 16-bit constant size.  The code
+	 below will select which strategy to use, so as to generate
+	 smallest code.  Ties are broken in favor or shorter sequences
+	 (in terms of number of instructions).  */
+
+#define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
+			: (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
+#define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
+			: (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
+#define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
+  (((S) >= (L)) ? (SIZE1) * (N) \
+   : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
+			       + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
+   : (ELSE))
+#define SIZE_FMOV_SP_(S,N) \
+  (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
+                   SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
+				    (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
+#define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
+
+      /* Consider alternative save_sp_merge only if we don't need the
+	 frame pointer and size is nonzero.  */
+      if (! frame_pointer_needed && size)
+	{
+	  /* Insn: add -(size + 4 * num_regs_to_save), sp.  */
+	  this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
+	  /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
+	  this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = save_sp_merge;
+	      strategy_size = this_strategy_size;
+	    }
+	}
+
+      /* Consider alternative save_sp_no_merge unconditionally.  */
+      /* Insn: add -4 * num_regs_to_save, sp.  */
+      this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
+      /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
+      this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
+      if (size)
+	{
+	  /* Insn: add -size, sp.  */
+	  this_strategy_size += SIZE_ADD_SP (-size);
+	}
+
+      if (this_strategy_size < strategy_size)
+	{
+	  strategy = save_sp_no_merge;
+	  strategy_size = this_strategy_size;
+	}
+
+      /* Consider alternative save_sp_partial_merge only if we don't
+	 need a frame pointer and size is reasonably large.  */
+      if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
+	{
+	  /* Insn: add -128, sp.  */
+	  this_strategy_size = SIZE_ADD_SP (-128);
+	  /* Insn: fmov fs#, (##, sp), for each fs# to be saved.  */
+	  this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
+					      num_regs_to_save);
+	  if (size)
+	    {
+	      /* Insn: add 128-size, sp.  */
+	      this_strategy_size += SIZE_ADD_SP (128 - size);
+	    }
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = save_sp_partial_merge;
+	      strategy_size = this_strategy_size;
+	    }
+	}
+
+      /* Consider alternative save_a0_merge only if we don't need a
+	 frame pointer, size is nonzero and the user hasn't
+	 changed the calling conventions of a0.  */
+      if (! frame_pointer_needed && size
+	  && call_used_regs[FIRST_ADDRESS_REGNUM]
+	  && ! fixed_regs[FIRST_ADDRESS_REGNUM])
+	{
+	  /* Insn: add -(size + 4 * num_regs_to_save), sp.  */
+	  this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
+	  /* Insn: mov sp, a0.  */
+	  this_strategy_size++;
+	  if (size)
+	    {
+	      /* Insn: add size, a0.  */
+	      this_strategy_size += SIZE_ADD_AX (size);
+	    }
+	  /* Insn: fmov fs#, (a0+), for each fs# to be saved.  */
+	  this_strategy_size += 3 * num_regs_to_save;
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = save_a0_merge;
+	      strategy_size = this_strategy_size;
+	    }
+	}
+
+      /* Consider alternative save_a0_no_merge if the user hasn't
+	 changed the calling conventions of a0. */
+      if (call_used_regs[FIRST_ADDRESS_REGNUM]
+	  && ! fixed_regs[FIRST_ADDRESS_REGNUM])
+	{
+	  /* Insn: add -4 * num_regs_to_save, sp.  */
+	  this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
+	  /* Insn: mov sp, a0.  */
+	  this_strategy_size++;
+	  /* Insn: fmov fs#, (a0+), for each fs# to be saved.  */
+	  this_strategy_size += 3 * num_regs_to_save;
+	  if (size)
+	    {
+	      /* Insn: add -size, sp.  */
+	      this_strategy_size += SIZE_ADD_SP (-size);
+	    }
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = save_a0_no_merge;
+	      strategy_size = this_strategy_size;
+	    }
+	}
+
+      /* Emit the initial SP add, common to all strategies.  */
+      switch (strategy)
+	{
+	case save_sp_no_merge:
+	case save_a0_no_merge:
+	  emit_insn (gen_addsi3 (stack_pointer_rtx,
+				 stack_pointer_rtx,
+				 GEN_INT (-4 * num_regs_to_save)));
+	  xsize = 0;
+	  break;
+
+	case save_sp_partial_merge:
+	  emit_insn (gen_addsi3 (stack_pointer_rtx,
+				 stack_pointer_rtx,
+				 GEN_INT (-128)));
+	  xsize = 128 - 4 * num_regs_to_save;
+	  size -= xsize;
+	  break;
+
+	case save_sp_merge:
+	case save_a0_merge:
+	  emit_insn (gen_addsi3 (stack_pointer_rtx,
+				 stack_pointer_rtx,
+				 GEN_INT (-(size + 4 * num_regs_to_save))));
+	  /* We'll have to adjust FP register saves according to the
+	     frame size. */
+	  xsize = size;
+	  /* Since we've already created the stack frame, don't do it
+	     again at the end of the function. */
+	  size = 0;
+	  break;
+
+	default:
+	  abort ();
+	}
+	  
+      /* Now prepare register a0, if we have decided to use it.  */
+      switch (strategy)
+	{
+	case save_sp_merge:
+	case save_sp_no_merge:
+	case save_sp_partial_merge:
+	  reg = 0;
+	  break;
+
+	case save_a0_merge:
+	case save_a0_no_merge:
+	  reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
+	  emit_insn (gen_movsi (reg, stack_pointer_rtx));
+	  if (xsize)
+	    emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
+	  reg = gen_rtx_POST_INC (SImode, reg);
+	  break;
+	  
+	default:
+	  abort ();
+	}
+      
+      /* Now actually save the FP registers.  */
+      for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
+	if (regs_ever_live[i] && ! call_used_regs[i])
+	  {
+	    rtx addr;
+
+	    if (reg)
+	      addr = reg;
+	    else
+	      {
+		/* If we aren't using `a0', use an SP offset.  */
+		if (xsize)
+		  {
+		    addr = gen_rtx_PLUS (SImode,
+					 stack_pointer_rtx,
+					 GEN_INT (xsize));
+		  }
+		else
+		  addr = stack_pointer_rtx;
+		
+		xsize += 4;
+	      }
+
+	    insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
+					 gen_rtx_REG (SImode, i)));
+
+	    RTX_FRAME_RELATED_P (insn) = 1;
+	  }
+    }
+
   /* Now put the frame pointer into the frame pointer register.  */
   if (frame_pointer_needed)
     emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
@@ -558,6 +896,24 @@ expand_prologue ()
     emit_insn (gen_addsi3 (stack_pointer_rtx,
 			   stack_pointer_rtx,
 			   GEN_INT (-size)));
+  if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+    {
+      rtx insn = get_last_insn ();
+      rtx last = emit_insn (gen_GOTaddr2picreg ());
+
+      /* Mark these insns as possibly dead.  Sometimes, flow2 may
+	 delete all uses of the PIC register.  In this case, let it
+	 delete the initialization too.  */
+      do
+	{
+	  insn = NEXT_INSN (insn);
+
+	  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
+						const0_rtx,
+						REG_NOTES (insn));
+	}
+      while (insn != last);
+    }
 }
 
 void
@@ -569,6 +925,193 @@ expand_epilogue ()
   size = get_frame_size () + current_function_outgoing_args_size;
   size += (current_function_outgoing_args_size ? 4 : 0);
 
+  if (TARGET_AM33_2 && fp_regs_to_save ())
+    {
+      int num_regs_to_save = fp_regs_to_save (), i;
+      rtx reg = 0;
+
+      /* We have several options to restore FP registers.  We could
+	 load them from SP offsets, but, if there are enough FP
+	 registers to restore, we win if we use a post-increment
+	 addressing mode.  */
+
+      /* If we have a frame pointer, it's the best option, because we
+	 already know it has the value we want.  */
+      if (frame_pointer_needed)
+	reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
+      /* Otherwise, we may use `a1', since it's call-clobbered and
+	 it's never used for return values.  But only do so if it's
+	 smaller than using SP offsets.  */
+      else
+	{
+	  enum { restore_sp_post_adjust,
+		 restore_sp_pre_adjust,
+		 restore_sp_partial_adjust,
+		 restore_a1 } strategy;
+	  unsigned int this_strategy_size, strategy_size = (unsigned)-1;
+
+	  /* Consider using sp offsets before adjusting sp.  */
+	  /* Insn: fmov (##,sp),fs#, for each fs# to be restored.  */
+	  this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
+	  /* If size is too large, we'll have to adjust SP with an
+		 add.  */
+	  if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+	    {
+	      /* Insn: add size + 4 * num_regs_to_save, sp.  */
+	      this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
+	    }
+	  /* If we don't have to restore any non-FP registers,
+		 we'll be able to save one byte by using rets.  */
+	  if (! REG_SAVE_BYTES)
+	    this_strategy_size--;
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = restore_sp_post_adjust;
+	      strategy_size = this_strategy_size;
+	    }
+
+	  /* Consider using sp offsets after adjusting sp.  */
+	  /* Insn: add size, sp.  */
+	  this_strategy_size = SIZE_ADD_SP (size);
+	  /* Insn: fmov (##,sp),fs#, for each fs# to be restored.  */
+	  this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
+	  /* We're going to use ret to release the FP registers
+		 save area, so, no savings. */
+
+	  if (this_strategy_size < strategy_size)
+	    {
+	      strategy = restore_sp_pre_adjust;
+	      strategy_size = this_strategy_size;
+	    }
+
+	  /* Consider using sp offsets after partially adjusting sp.
+	     When size is close to 32Kb, we may be able to adjust SP
+	     with an imm16 add instruction while still using fmov
+	     (d8,sp).  */
+	  if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+	    {
+	      /* Insn: add size + 4 * num_regs_to_save
+				+ REG_SAVE_BYTES - 252,sp.  */
+	      this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
+						+ REG_SAVE_BYTES - 252);
+	      /* Insn: fmov (##,sp),fs#, fo each fs# to be restored.  */
+	      this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
+						  - 4 * num_regs_to_save,
+						  num_regs_to_save);
+	      /* We're going to use ret to release the FP registers
+		 save area, so, no savings. */
+
+	      if (this_strategy_size < strategy_size)
+		{
+		  strategy = restore_sp_partial_adjust;
+		  strategy_size = this_strategy_size;
+		}
+	    }
+
+	  /* Consider using a1 in post-increment mode, as long as the
+	     user hasn't changed the calling conventions of a1.  */
+	  if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
+	      && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
+	    {
+	      /* Insn: mov sp,a1.  */
+	      this_strategy_size = 1;
+	      if (size)
+		{
+		  /* Insn: add size,a1.  */
+		  this_strategy_size += SIZE_ADD_AX (size);
+		}
+	      /* Insn: fmov (a1+),fs#, for each fs# to be restored.  */
+	      this_strategy_size += 3 * num_regs_to_save;
+	      /* If size is large enough, we may be able to save a
+		 couple of bytes.  */
+	      if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
+		{
+		  /* Insn: mov a1,sp.  */
+		  this_strategy_size += 2;
+		}
+	      /* If we don't have to restore any non-FP registers,
+		 we'll be able to save one byte by using rets.  */
+	      if (! REG_SAVE_BYTES)
+		this_strategy_size--;
+
+	      if (this_strategy_size < strategy_size)
+		{
+		  strategy = restore_a1;
+		  strategy_size = this_strategy_size;
+		}
+	    }
+
+	  switch (strategy)
+	    {
+	    case restore_sp_post_adjust:
+	      break;
+
+	    case restore_sp_pre_adjust:
+	      emit_insn (gen_addsi3 (stack_pointer_rtx,
+				     stack_pointer_rtx,
+				     GEN_INT (size)));
+	      size = 0;
+	      break;
+
+	    case restore_sp_partial_adjust:
+	      emit_insn (gen_addsi3 (stack_pointer_rtx,
+				     stack_pointer_rtx,
+				     GEN_INT (size + 4 * num_regs_to_save
+					      + REG_SAVE_BYTES - 252)));
+	      size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
+	      break;
+	      
+	    case restore_a1:
+	      reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
+	      emit_insn (gen_movsi (reg, stack_pointer_rtx));
+	      if (size)
+		emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
+	      break;
+
+	    default:
+	      abort ();
+	    }
+	}
+
+      /* Adjust the selected register, if any, for post-increment.  */
+      if (reg)
+	reg = gen_rtx_POST_INC (SImode, reg);
+
+      for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
+	if (regs_ever_live[i] && ! call_used_regs[i])
+	  {
+	    rtx addr;
+	    
+	    if (reg)
+	      addr = reg;
+	    else if (size)
+	      {
+		/* If we aren't using a post-increment register, use an
+		   SP offset. */
+		addr = gen_rtx_PLUS (SImode,
+				     stack_pointer_rtx,
+				     GEN_INT (size));
+	      }
+	    else
+	      addr = stack_pointer_rtx;
+
+	    size += 4;
+
+	    emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
+				  gen_rtx_MEM (SImode, addr)));
+	  }
+
+      /* If we were using the restore_a1 strategy and the number of
+	 bytes to be released won't fit in the `ret' byte, copy `a1'
+	 to `sp', to avoid having to use `add' to adjust it.  */
+      if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
+	{
+	  emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
+	  size = 0;
+	}
+    }
+
   /* Maybe cut back the stack, except for the register save area.
 
      If the frame pointer exists, then use the frame pointer to
@@ -649,6 +1192,9 @@ notice_update_cc (body, insn)
       /* The insn is a compare instruction.  */
       CC_STATUS_INIT;
       cc_status.value1 = SET_SRC (body);
+      if (GET_CODE (cc_status.value1) == COMPARE
+	  && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
+	cc_status.mdep.fpCC = 1;
       break;
 
     case CC_INVERT:
@@ -714,7 +1260,7 @@ store_multiple_operation (op, mode)
 
      LAST keeps track of the smallest-numbered register stored so far.
      MASK is the set of stored registers. */
-  last = FIRST_PSEUDO_REGISTER;
+  last = LAST_EXTENDED_REGNUM + 1;
   mask = 0;
   for (i = 1; i < count; i++)
     {
@@ -756,6 +1302,9 @@ call_address_operand (op, mode)
      rtx op;
      enum machine_mode mode ATTRIBUTE_UNUSED;
 {
+  if (flag_pic)
+    return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
+
   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
 }
 
@@ -810,6 +1359,14 @@ secondary_reload_class (class, mode, in)
       return DATA_REGS;
     }
  
+  if (TARGET_AM33_2 && class == FP_REGS
+      && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
+    {
+      if (TARGET_AM33)
+	return DATA_OR_EXTENDED_REGS;
+      return DATA_REGS;
+    }
+
   /* Otherwise assume no secondary reloads are needed.  */
   return NO_REGS;
 }
@@ -826,8 +1383,10 @@ initial_offset (from, to)
 	  || regs_ever_live[6] || regs_ever_live[7]
 	  || regs_ever_live[14] || regs_ever_live[15]
 	  || regs_ever_live[16] || regs_ever_live[17]
+	  || fp_regs_to_save ()
 	  || frame_pointer_needed)
-	return REG_SAVE_BYTES;
+	return REG_SAVE_BYTES
+	  + 4 * fp_regs_to_save ();
       else
 	return 0;
     }
@@ -841,8 +1400,10 @@ initial_offset (from, to)
 	  || regs_ever_live[6] || regs_ever_live[7]
 	  || regs_ever_live[14] || regs_ever_live[15]
 	  || regs_ever_live[16] || regs_ever_live[17]
+	  || fp_regs_to_save ()
 	  || frame_pointer_needed)
 	return (get_frame_size () + REG_SAVE_BYTES
+		+ 4 * fp_regs_to_save ()
 		+ (current_function_outgoing_args_size
 		   ? current_function_outgoing_args_size + 4 : 0)); 
       else
@@ -1155,6 +1716,15 @@ const_8bit_operand (op, mode)
 	  && INTVAL (op) < 256);
 }
 
+/* Return true if the operand is the 1.0f constant.  */
+int
+const_1f_operand (op, mode)
+    register rtx op;
+    enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return (op == CONST1_RTX (SFmode));
+}
+
 /* Similarly, but when using a zero_extract pattern for a btst where
    the source operand might end up in memory.  */
 int
@@ -1222,6 +1792,9 @@ legitimize_address (x, oldx, mode)
      rtx oldx ATTRIBUTE_UNUSED;
      enum machine_mode mode ATTRIBUTE_UNUSED;
 {
+  if (flag_pic && ! legitimate_pic_operand_p (x))
+    x = legitimize_pic_address (oldx, NULL_RTX);
+
   /* Uh-oh.  We might have an address for x[n-100000].  This needs
      special handling to avoid creating an indexed memory address
      with x-100000 as the base.  */
@@ -1252,6 +1825,75 @@ legitimize_address (x, oldx, mode)
   return x;
 }
 
+/* Convert a non-PIC address in `orig' to a PIC address using @GOT or
+   @GOTOFF in `reg'. */
+rtx
+legitimize_pic_address (orig, reg)
+     rtx orig;
+     rtx reg;
+{
+  if (GET_CODE (orig) == LABEL_REF
+      || (GET_CODE (orig) == SYMBOL_REF
+	  && (CONSTANT_POOL_ADDRESS_P (orig)
+	      || ! MN10300_GLOBAL_P (orig))))
+    {
+      if (reg == 0)
+	reg = gen_reg_rtx (Pmode);
+
+      emit_insn (gen_symGOTOFF2reg (reg, orig));
+      return reg;
+    }
+  else if (GET_CODE (orig) == SYMBOL_REF)
+    {
+      if (reg == 0)
+	reg = gen_reg_rtx (Pmode);
+
+      emit_insn (gen_symGOT2reg (reg, orig));
+      return reg;
+    }
+  return orig;
+}
+
+/* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
+   isn't protected by a PIC unspec; nonzero otherwise.  */
+int
+legitimate_pic_operand_p (x)
+     rtx x;
+{
+  register const char *fmt;
+  register int i;
+
+  if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+    return 0;
+
+  if (GET_CODE (x) == UNSPEC
+      && (XINT (x, 1) == UNSPEC_PIC
+	  || XINT (x, 1) == UNSPEC_GOT
+	  || XINT (x, 1) == UNSPEC_GOTOFF
+	  || XINT (x, 1) == UNSPEC_PLT))
+      return 1;
+
+  if (GET_CODE (x) == QUEUED)
+    return legitimate_pic_operand_p (QUEUED_VAR (x));
+
+  fmt = GET_RTX_FORMAT (GET_CODE (x));
+  for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
+    {
+      if (fmt[i] == 'E')
+	{
+	  register int j;
+
+	  for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+	    if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
+	      return 0;
+	}
+      else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
+	return 0;
+    }
+
+  return 1;
+}
+
 static int
 mn10300_address_cost_1 (x, unsig)
      rtx x;
@@ -1271,6 +1913,7 @@ mn10300_address_cost_1 (x, unsig)
 
 	case DATA_REGS:
 	case EXTENDED_REGS:
+	case FP_REGS:
 	  return 3;
 
 	case NO_REGS:
@@ -1438,3 +2081,23 @@ mn10300_wide_const_load_uses_clr (operands)
 
   return val[0] == 0 || val[1] == 0;
 }
+/* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
+   may access it using GOTOFF instead of GOT.  */
+
+static void
+mn10300_encode_section_info (decl, rtl, first)
+     tree decl;
+     rtx rtl;
+     int first;
+{
+  rtx symbol;
+
+  if (GET_CODE (rtl) != MEM)
+    return;
+  symbol = XEXP (rtl, 0);
+  if (GET_CODE (symbol) != SYMBOL_REF)
+    return;
+
+  if (flag_pic)
+    SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
+}
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index cae8f2a3f81..2432a38a1ce 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler.
    Matsushita MN10300 series
-   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002
+   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Jeff Law (law@cygnus.com).
 
@@ -40,12 +40,14 @@ Boston, MA 02111-1307, USA.  */
     }						\
   while (0)
 
-#define CPP_SPEC "%{mam33:-D__AM33__}"
+#define CPP_SPEC "%{mam33:-D__AM33__} %{mam33-2:-D__AM33__=2 -D__AM33_2__}"
 
 /* Run-time compilation parameters selecting different hardware subsets.  */
 
 extern int target_flags;
 
+extern GTY(()) int mn10300_unspec_int_label_counter;
+
 /* Macros used in the machine description to test the flags.  */
 
 /* Macro to define tables used to set the flags.
@@ -60,6 +62,9 @@ extern int target_flags;
 /* Generate code for the AM33 processor.  */
 #define TARGET_AM33			(target_flags & 0x2)
 
+/* Generate code for the AM33/2.0 processor.  */
+#define TARGET_AM33_2			(target_flags & 0x4)
+
 #define TARGET_SWITCHES  \
   {{ "mult-bug",	0x1,  N_("Work around hardware multiply bug")},	\
    { "no-mult-bug", 	-0x1, N_("Do not work around hardware multiply bug")},\
@@ -67,6 +72,9 @@ extern int target_flags;
    { "am33", 		-(0x1), ""},\
    { "no-am33", 	-0x2, ""},	\
    { "no-crt0",		0,    N_("No default crt0.o") }, \
+   { "am33-2",		0x6,  N_("Target the AM33/2.0 processor")},   \
+   { "am33-2",		-(0x1), ""},\
+   { "no-am33-2",	-0x4,   ""},  \
    { "relax",		0,    N_("Enable linker relaxations") }, \
    { "", TARGET_DEFAULT, NULL}}
 
@@ -131,7 +139,7 @@ extern int target_flags;
    All registers that the compiler knows about must be given numbers,
    even those that are not normally considered general registers.  */
 
-#define FIRST_PSEUDO_REGISTER 18
+#define FIRST_PSEUDO_REGISTER 50
 
 /* Specify machine-specific register numbers.  */
 #define FIRST_DATA_REGNUM 0
@@ -140,6 +148,8 @@ extern int target_flags;
 #define LAST_ADDRESS_REGNUM 8
 #define FIRST_EXTENDED_REGNUM 10
 #define LAST_EXTENDED_REGNUM 17
+#define FIRST_FP_REGNUM 18
+#define LAST_FP_REGNUM 49
 
 /* Specify the registers used for certain standard purposes.
    The values of these macros are register numbers.  */
@@ -162,7 +172,10 @@ extern int target_flags;
    and are not available for the register allocator.  */
 
 #define FIXED_REGISTERS \
-  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}
+  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 \
+  , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+  , 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+  }
 
 /* 1 for registers not available across function calls.
    These must include the FIXED_REGISTERS and also any
@@ -173,10 +186,16 @@ extern int target_flags;
    like.  */
 
 #define CALL_USED_REGISTERS \
-  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0}
+  { 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0 \
+  , 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
+  , 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
+  }
 
 #define REG_ALLOC_ORDER \
-  { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9}
+  { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
+  , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
+  , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 \
+  }
 
 #define CONDITIONAL_REGISTER_USAGE \
 {						\
@@ -188,6 +207,15 @@ extern int target_flags;
 	   i <= LAST_EXTENDED_REGNUM; i++) 	\
 	fixed_regs[i] = call_used_regs[i] = 1; 	\
     }						\
+  if (!TARGET_AM33_2)				\
+    {						\
+      for (i = FIRST_FP_REGNUM;			\
+	   i <= LAST_FP_REGNUM; 		\
+           i++) 				\
+	fixed_regs[i] = call_used_regs[i] = 1;	\
+    }						\
+  if (flag_pic)					\
+    fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;	\
 }
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
@@ -247,6 +275,7 @@ enum reg_class {
   DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, 
   EXTENDED_REGS, DATA_OR_EXTENDED_REGS, ADDRESS_OR_EXTENDED_REGS,
   SP_OR_EXTENDED_REGS, SP_OR_ADDRESS_OR_EXTENDED_REGS, 
+  FP_REGS, FP_ACC_REGS,
   GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
 };
 
@@ -260,6 +289,7 @@ enum reg_class {
   "EXTENDED_REGS", \
   "DATA_OR_EXTENDED_REGS", "ADDRESS_OR_EXTENDED_REGS", \
   "SP_OR_EXTENDED_REGS", "SP_OR_ADDRESS_OR_EXTENDED_REGS", \
+  "FP_REGS", "FP_ACC_REGS", \
   "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
 
 /* Define which registers fit in which classes.
@@ -267,19 +297,21 @@ enum reg_class {
    of length N_REG_CLASSES.  */
 
 #define REG_CLASS_CONTENTS  			\
-{      {0},		/* No regs      */	\
-   {0x0000f},		/* DATA_REGS */		\
-   {0x001f0},		/* ADDRESS_REGS */	\
-   {0x00200},		/* SP_REGS */		\
-   {0x001ff},		/* DATA_OR_ADDRESS_REGS */\
-   {0x003f0},		/* SP_OR_ADDRESS_REGS */\
-   {0x3fc00},		/* EXTENDED_REGS */	\
-   {0x3fc0f},		/* DATA_OR_EXTENDED_REGS */	\
-   {0x3fdf0},		/* ADDRESS_OR_EXTENDED_REGS */	\
-   {0x3fe00},		/* SP_OR_EXTENDED_REGS */	\
-   {0x3fff0},		/* SP_OR_ADDRESS_OR_EXTENDED_REGS */	\
-   {0x3fdff},		/* GENERAL_REGS */    	\
-   {0x3ffff},		/* ALL_REGS 	*/	\
+{  { 0,	0 },		/* No regs      */	\
+ { 0x0000f, 0 },	/* DATA_REGS */		\
+ { 0x001f0, 0 },	/* ADDRESS_REGS */	\
+ { 0x00200, 0 },	/* SP_REGS */		\
+ { 0x001ff, 0 },	/* DATA_OR_ADDRESS_REGS */\
+ { 0x003f0, 0 },	/* SP_OR_ADDRESS_REGS */\
+ { 0x3fc00, 0 },	/* EXTENDED_REGS */	\
+ { 0x3fc0f, 0 },	/* DATA_OR_EXTENDED_REGS */	\
+ { 0x3fdf0, 0 },	/* ADDRESS_OR_EXTENDED_REGS */	\
+ { 0x3fe00, 0 },	/* SP_OR_EXTENDED_REGS */	\
+ { 0x3fff0, 0 },	/* SP_OR_ADDRESS_OR_EXTENDED_REGS */	\
+ { 0xfffc0000, 0x3ffff }, /* FP_REGS */		\
+ { 0x03fc0000, 0 },	/* FP_ACC_REGS */	\
+ { 0x3fdff, 0 }, 	/* GENERAL_REGS */	\
+ { 0xffffffff, 0x3ffff } /* ALL_REGS 	*/	\
 }
 
 /* The same information, inverted:
@@ -292,6 +324,7 @@ enum reg_class {
    (REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \
    (REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
    (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
+   (REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
    NO_REGS)
 
 /* The class value for index registers, and the one for base regs.  */
@@ -306,6 +339,9 @@ enum reg_class {
    (C) == 'y' ? SP_REGS : \
    ! TARGET_AM33 ? NO_REGS : \
    (C) == 'x' ? EXTENDED_REGS : \
+   ! TARGET_AM33_2 ? NO_REGS : \
+   (C) == 'f' ? FP_REGS : \
+   (C) == 'A' ? FP_ACC_REGS : \
    NO_REGS)
 
 /* Macros to check register numbers against specific register classes.  */
@@ -350,6 +386,8 @@ enum reg_class {
 #define REGNO_AM33_P(regno) \
   (REGNO_DATA_P ((regno)) || REGNO_ADDRESS_P ((regno)) \
    || REGNO_EXTENDED_P ((regno)))
+#define REGNO_FP_P(regno) \
+  REGNO_IN_RANGE_P ((regno), FIRST_FP_REGNUM, LAST_FP_REGNUM)
 
 #define REGNO_OK_FOR_BASE_P(regno) \
   (REGNO_SP_P ((regno)) \
@@ -397,6 +435,11 @@ enum reg_class {
 #define CLASS_MAX_NREGS(CLASS, MODE)	\
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 
+/* A class that contains registers which the compiler must always
+   access in a mode that is the same size as the mode in which it
+   loaded the register.  */
+#define CLASS_CANNOT_CHANGE_SIZE FP_REGS
+
 /* The letters I, J, K, L, M, N, O, P in a register constraint string
    can be used to stand for particular ranges of immediate operands.
    This macro defines what the ranges are.
@@ -669,6 +712,9 @@ struct cum_arg {int nbytes; };
 
 /* Extra constraints.  */
  
+#define OK_FOR_Q(OP) \
+   (GET_CODE (OP) == MEM && ! CONSTANT_ADDRESS_P (XEXP (OP, 0)))
+
 #define OK_FOR_R(OP) \
    (GET_CODE (OP) == MEM					\
     && GET_MODE (OP) == QImode					\
@@ -692,6 +738,10 @@ struct cum_arg {int nbytes; };
 
 #define EXTRA_CONSTRAINT(OP, C) \
  ((C) == 'R' ? OK_FOR_R (OP) \
+  : (C) == 'Q' ? OK_FOR_Q (OP) \
+  : (C) == 'S' && flag_pic \
+  ? GET_CODE (OP) == UNSPEC && (XINT (OP, 1) == UNSPEC_PLT \
+				|| XINT (OP, 1) == UNSPEC_PIC) \
   : (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF \
   : (C) == 'T' ? OK_FOR_T (OP) \
   : 0)
@@ -732,7 +782,8 @@ struct cum_arg {int nbytes; };
 
 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)    	\
 {							\
-  if (CONSTANT_ADDRESS_P (X))				\
+  if (CONSTANT_ADDRESS_P (X)				\
+      && (! flag_pic || legitimate_pic_operand_p (X)))	\
     goto ADDR;						\
   if (RTX_OK_FOR_BASE_P (X))				\
     goto ADDR;						\
@@ -754,6 +805,8 @@ struct cum_arg {int nbytes; };
 	{						\
 	  if (GET_CODE (index) == CONST_INT)		\
 	    goto ADDR;					\
+	  if (GET_CODE (index) == CONST)		\
+	    goto ADDR;					\
 	}						\
     }							\
 }
@@ -790,6 +843,60 @@ struct cum_arg {int nbytes; };
 
 #define LEGITIMATE_CONSTANT_P(X) 1
 
+/* Zero if this needs fixing up to become PIC.  */
+
+#define LEGITIMATE_PIC_OPERAND_P(X) (legitimate_pic_operand_p (X))
+
+/* Register to hold the addressing base for
+   position independent code access to data items.  */
+#define PIC_OFFSET_TABLE_REGNUM	PIC_REG
+
+/* The name of the pseudo-symbol representing the Global Offset Table.  */
+#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
+
+#define SYMBOLIC_CONST_P(X)	\
+((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)	\
+  && ! LEGITIMATE_PIC_OPERAND_P (X))
+
+/* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled.  */
+#define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X))
+
+/* Recognize machine-specific patterns that may appear within
+   constants.  Used for PIC-specific UNSPECs.  */
+#define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
+  do									\
+    if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1)	\
+      {									\
+	switch (XINT ((X), 1))						\
+	  {								\
+	  case UNSPEC_INT_LABEL:					\
+	    asm_fprintf ((STREAM), ".%LLIL%d",				\
+ 			 INTVAL (XVECEXP ((X), 0, 0)));			\
+	    break;							\
+	  case UNSPEC_PIC:						\
+	    /* GLOBAL_OFFSET_TABLE or local symbols, no suffix.  */	\
+	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
+	    break;							\
+	  case UNSPEC_GOT:						\
+	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
+	    fputs ("@GOT", (STREAM));					\
+	    break;							\
+	  case UNSPEC_GOTOFF:						\
+	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
+	    fputs ("@GOTOFF", (STREAM));				\
+	    break;							\
+	  case UNSPEC_PLT:						\
+	    output_addr_const ((STREAM), XVECEXP ((X), 0, 0));		\
+	    fputs ("@PLT", (STREAM));					\
+	    break;							\
+	  default:							\
+	    goto FAIL;							\
+	  }								\
+	break;								\
+      }									\
+    else								\
+      goto FAIL;							\
+  while (0)
 
 /* Tell final.c how to eliminate redundant test instructions.  */
 
@@ -814,6 +921,7 @@ struct cum_arg {int nbytes; };
    ! TARGET_AM33 ? 6 : \
    (CLASS1 == SP_REGS || CLASS2 == SP_REGS) ? 6 : \
    (CLASS1 == CLASS2 && CLASS1 == EXTENDED_REGS) ? 6 : \
+   (CLASS1 == FP_REGS || CLASS2 == FP_REGS) ? 6 : \
    (CLASS1 == EXTENDED_REGS || CLASS2 == EXTENDED_REGS) ? 4 : \
    4)
 
@@ -885,6 +993,10 @@ struct cum_arg {int nbytes; };
 #define REGISTER_NAMES \
 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \
+, "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \
+, "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \
+, "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \
+, "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \
 }
 
 #define ADDITIONAL_REGISTER_NAMES \
@@ -892,6 +1004,10 @@ struct cum_arg {int nbytes; };
   {"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \
   {"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \
   {"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \
+, {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \
+, {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \
+, {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \
+, {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \
 }
 
 /* Print an instruction operand X on file FILE.
@@ -994,3 +1110,15 @@ struct cum_arg {int nbytes; };
 
 #define FILE_ASM_OP "\t.file\n"
 
+#define PREDICATE_CODES \
+  {"const_1f_operand", {CONST_INT, CONST_DOUBLE}},
+
+typedef struct mn10300_cc_status_mdep
+  {
+    int fpCC;
+  }
+cc_status_mdep;
+
+#define CC_STATUS_MDEP cc_status_mdep
+
+#define CC_STATUS_MDEP_INIT (cc_status.mdep.fpCC = 0)
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index f889aa61cdd..46a8ff125cd 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -37,6 +37,17 @@
 ;; clobber - value of cc is unknown
 (define_attr "cc" "none,none_0hit,set_znv,set_zn,compare,clobber,invert"
   (const_string "clobber"))
+
+(define_constants [
+  (PIC_REG	6)
+  (SP_REG	9)
+
+  (UNSPEC_INT_LABEL	0)
+  (UNSPEC_PIC		1)
+  (UNSPEC_GOT		2)
+  (UNSPEC_GOTOFF	3)
+  (UNSPEC_PLT		4)
+])
 
 ;; ----------------------------------------------------------------------
 ;; MOVE INSTRUCTIONS
@@ -57,8 +68,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
-	(match_operand:QI 1 "general_operand" "0,I,d*xai,m,d*xa"))]
+  [(set (match_operand:QI 0 "nonimmediate_operand" "=d*x*a*f,d*x,d*x*a,d*x*a,m,*f,d*x*a")
+	(match_operand:QI 1 "general_operand" "0,I,d*xai,m,d*xa,d*xa*f,*f"))]
   "TARGET_AM33
    && (register_operand (operands[0], QImode)
        || register_operand (operands[1], QImode))"
@@ -93,11 +104,14 @@
     case 3:
     case 4:
       return \"movbu %1,%0\";
+    case 5:
+    case 6:
+      return \"fmov %1,%0\";
     default:
       abort ();
     }
 }"
-  [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
+  [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
@@ -147,8 +161,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a,d*x,d*x*a,d*x*a,m")
-	(match_operand:HI 1 "general_operand" "0,I,d*x*ai,m,d*x*a"))]
+  [(set (match_operand:HI 0 "nonimmediate_operand" "=d*x*a*f,d*x,d*x*a,d*x*a,m,*f,d*x*a")
+	(match_operand:HI 1 "general_operand" "0,I,d*x*ai,m,d*x*a,d*x*a*f,*f"))]
   "TARGET_AM33
    && (register_operand (operands[0], HImode)
        || register_operand (operands[1], HImode))"
@@ -183,11 +197,14 @@
     case 3:
     case 4:
       return \"movhu %1,%0\";
+    case 5:
+    case 6:
+      return \"fmov %1,%0\";
     default:
       abort ();
     }
 }"
-  [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit")])
+  [(set_attr "cc" "none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d*a,d,d*a,d,m")
@@ -263,6 +280,12 @@
   DONE;
 }")
 
+(define_insn "pop_pic_reg"
+  [(set (reg:SI PIC_REG)
+	(mem:SI (post_inc:SI (reg:SI SP_REG))))]
+  "reload_completed"
+  "movm (sp),[a2]")
+
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
@@ -273,13 +296,40 @@
   if (!register_operand (operand1, SImode)
       && !register_operand (operand0, SImode))
     operands[1] = copy_to_mode_reg (SImode, operand1);
+  if (flag_pic)
+    {
+      rtx temp;
+      if (SYMBOLIC_CONST_P (operands[1]))
+	{
+	  if (GET_CODE (operands[0]) == MEM)
+	    operands[1] = force_reg (Pmode, operands[1]);
+	  else
+	    {
+	      temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+	      operands[1] = legitimize_pic_address (operands[1], temp);
+	    }
+	}
+      else if (GET_CODE (operands[1]) == CONST
+	       && GET_CODE (XEXP (operands[1], 0)) == PLUS
+	       && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
+	{
+	  temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
+	  temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
+					 temp);
+	  operands[1] = expand_binop (SImode, add_optab, temp,
+				      XEXP (XEXP (operands[1], 0), 1),
+				      no_new_pseudos ? temp
+				      : gen_reg_rtx (Pmode),
+				      0, OPTAB_LIB_WIDEN);
+	}
+    }
 }")
 
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y")
+				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,!*y,*f,*f,dxaQ")
 	(match_operand:SI 1 "general_operand"
-				"0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR"))]
+				"0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,!*y,axR,0,dxaQi*f,*f"))]
   "register_operand (operands[0], SImode)
    || register_operand (operands[1], SImode)"
   "*
@@ -321,11 +371,16 @@
 	    return \"movu %1,%0\";
 	}
       return \"mov %1,%0\";
+    case 14:
+      return \"nop\";
+    case 15:
+    case 16:
+      return \"fmov %1,%0\";
     default:
       abort ();
     }
 }"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
+  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none,none_0hit,none_0hit")])
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
@@ -340,8 +395,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=dx,ax,dx,a,daxm,dax")
-	(match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxFm"))]
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,dx,ax,dx,a,f,dxaQ,daxm,dax")
+	(match_operand:SF 1 "general_operand" "0,0,0,G,G,fdxaQF,f,dax,daxFm"))]
   "register_operand (operands[0], SFmode)
    || register_operand (operands[1], SFmode)"
   "*
@@ -350,12 +405,17 @@
     {
     case 0:
     case 1:
-      return \"nop\";
     case 2:
-      return \"clr %0\";
+      return \"nop\";
     case 3:
-    case 4:
+      return \"clr %0\";
+    /* case 4: below */
     case 5:
+    case 6:
+      return \"fmov %1, %0\";
+    case 4:
+    case 7:
+    case 8:
       if (REGNO_REG_CLASS (true_regnum (operands[0])) == EXTENDED_REGS
 	  && GET_CODE (operands[1]) == CONST_INT)
 	{
@@ -370,7 +430,7 @@
       abort ();
     }
 }"
-  [(set_attr "cc" "none,none,clobber,none_0hit,none_0hit,none_0hit")])
+  [(set_attr "cc" "none,none,none,clobber,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
@@ -386,9 +446,9 @@
 
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
+				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax,*f,*f,*f,dxa,*f,Q")
 	(match_operand:DI 1 "general_operand"
-				"0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
+				"0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim,0,*f,dxai,*f,Q,*f"))]
   "register_operand (operands[0], DImode)
    || register_operand (operands[1], DImode)"
   "*
@@ -516,6 +576,26 @@
 	      output_asm_insn (\"mov %H1,%H0\", operands);
 	    return \"\";
 	  }
+      case 12:
+        return \"nop\";
+      case 13:
+      case 14:
+      case 15:
+        return \"fmov %L1, %L0\;fmov %H1, %H0\";
+      case 16:
+	if (GET_CODE (operands[1]) == MEM
+	    && GET_CODE (XEXP (operands[1], 0)) == CONST_INT
+	    && (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
+	  return \"fmov %D1, %D0\";
+	else
+          return \"fmov %L1, %L0\;fmov %H1, %H0\";
+      case 17:
+	if (GET_CODE (operands[0]) == MEM
+	    && GET_CODE (XEXP (operands[0], 0)) == CONST_INT
+	    && (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
+	  return \"fmov %D1, %D0\";
+	else
+          return \"fmov %L1, %L0\;fmov %H1, %H0\";
     default:
       abort ();
     }
@@ -523,8 +603,9 @@
   [(set (attr "cc")
 	(cond
 	 [
-	 (lt (symbol_ref "which_alternative") (const_int 2)
-	     ) (const_string "none")
+	 (ior (lt (symbol_ref "which_alternative") (const_int 2))
+	      (eq (symbol_ref "which_alternative") (const_int 12))
+	      ) (const_string "none")
 	 (eq (symbol_ref "which_alternative") (const_int 2)
 	     ) (const_string "clobber")
 	 (eq (symbol_ref "which_alternative") (const_int 3)
@@ -555,9 +636,9 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "nonimmediate_operand"
-				"=dx,ax,dx,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
+				"=f,dx,ax,dx,f,f,dxa,f,Q,a,dxm,dxm,axm,axm,dx,dx,ax,ax")
 	(match_operand:DF 1 "general_operand"
-				"0,0,G,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
+				"0,0,0,G,f,dxaF,f,Q,f,G,dx,ax,dx,ax,dxFm,axFm,dxFm,axFm"))]
   "register_operand (operands[0], DFmode)
    || register_operand (operands[1], DFmode)"
   "*
@@ -569,24 +650,46 @@
     {
       case 0:
       case 1:
+      case 2:
 	return \"nop\";
 
-      case 2:
+      case 3:
 	return \"clr %L0\;clr %H0\";
 
-      case 3:
-	 if (rtx_equal_p (operands[0], operands[1]))
-	   return \"sub %L1,%L0\;mov %L0,%H0\";
-	 else
-	   return \"mov %1,%L0\;mov %L0,%H0\";
       case 4:
       case 5:
       case 6:
+        return \"fmov %L1, %L0\;fmov %H1, %H0\";
+
       case 7:
+	if (GET_CODE (operands[1]) == MEM
+	    && GET_CODE (XEXP (operands[1], 0)) == CONST_INT
+	    && (INTVAL (XEXP (operands[1], 0)) & 7) == 0)
+	  return \"fmov %D1, %D0\";
+	else
+          return \"fmov %L1, %L0\;fmov %H1, %H0\";
+
       case 8:
+	if (GET_CODE (operands[0]) == MEM
+	    && GET_CODE (XEXP (operands[0], 0)) == CONST_INT
+	    && (INTVAL (XEXP (operands[0], 0)) & 7) == 0)
+	  return \"fmov %D1, %D0\";
+	else
+          return \"fmov %L1, %L0\;fmov %H1, %H0\";
+
       case 9:
+	 if (rtx_equal_p (operands[0], operands[1]))
+	   return \"sub %L1,%L0\;mov %L0,%H0\";
+	 else
+	   return \"mov %1,%L0\;mov %L0,%H0\";
       case 10:
       case 11:
+      case 12:
+      case 13:
+      case 14:
+      case 15:
+      case 16:
+      case 17:
 	if (GET_CODE (operands[1]) == CONST_INT)
 	  {
 	    rtx low, high;
@@ -692,17 +795,17 @@
   [(set (attr "cc")
 	(cond
 	 [
-	 (lt (symbol_ref "which_alternative") (const_int 2)
+	 (lt (symbol_ref "which_alternative") (const_int 3)
 	     ) (const_string "none")
-	 (eq (symbol_ref "which_alternative") (const_int 2)
-	     ) (const_string "clobber")
 	 (eq (symbol_ref "which_alternative") (const_int 3)
+	     ) (const_string "clobber")
+	 (eq (symbol_ref "which_alternative") (const_int 9)
 	     ) (if_then_else
 		(ne (symbol_ref "rtx_equal_p (operands[0], operands[1])")
 		    (const_int 0)) (const_string "clobber")
 		    (const_string "none_0hit"))
-	 (ior (eq (symbol_ref "which_alternative") (const_int 8))
-	      (eq (symbol_ref "which_alternative") (const_int 9))
+	 (ior (eq (symbol_ref "which_alternative") (const_int 14))
+	      (eq (symbol_ref "which_alternative") (const_int 15))
 	      ) (if_then_else
 		 (ne (symbol_ref "mn10300_wide_const_load_uses_clr
 				  (operands)")
@@ -773,6 +876,14 @@
   btst 0,d0
   cmp %1,%0"
   [(set_attr "cc" "compare,compare")])
+
+(define_insn "cmpsf"
+  [(set (cc0)
+	(compare (match_operand:SF 0 "register_operand" "f,f")
+		 (match_operand:SF 1 "nonmemory_operand" "f,F")))]
+  "TARGET_AM33_2"
+  "fcmp %1,%0"
+  [(set_attr "cc" "compare,compare")])
 
 ;; ----------------------------------------------------------------------
 ;; ADD INSTRUCTIONS
@@ -1113,7 +1224,7 @@
     return \"and %1,%0\";
   return \"and %2,%0\";
 }"
-  [(set_attr "cc" "none_0hit,set_znv,set_znv")])
+  [(set_attr "cc" "none_0hit,set_zn,set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx,dx")
@@ -1144,7 +1255,7 @@
     return \"lsr 4,%0\;asl2 %0\;asl2 %0\";
   return \"and %2,%0\";
 }"
-  [(set_attr "cc" "none_0hit,set_znv")])
+  [(set_attr "cc" "none_0hit,set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; OR INSTRUCTIONS
@@ -1180,7 +1291,7 @@
     return \"or %1,%0\";
   return \"or %2,%0\";
 }"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
@@ -1188,7 +1299,7 @@
 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
   ""
   "or %2,%0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; XOR INSTRUCTIONS
@@ -1224,7 +1335,7 @@
     return \"xor %1,%0\";
   return \"xor %2,%0\";
 }"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
@@ -1232,7 +1343,7 @@
 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
   ""
   "xor %2,%0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 ;; ----------------------------------------------------------------------
 ;; NOT INSTRUCTIONS
@@ -1249,14 +1360,14 @@
 	(not:SI (match_operand:SI 1 "register_operand" "0,0")))]
   "TARGET_AM33"
   "not %0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=dx")
 	(not:SI (match_operand:SI 1 "register_operand" "0")))]
   ""
   "not %0"
-  [(set_attr "cc" "set_znv")])
+  [(set_attr "cc" "set_zn")])
 
 ;; -----------------------------------------------------------------
 ;; BIT FIELDS
@@ -1293,7 +1404,7 @@
   "@
   bclr %N1,%A0
   and %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
+  [(set_attr "cc" "clobber,set_zn")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "memory_operand" "=R,T")
@@ -1315,7 +1426,7 @@
   "@
   bset %U1,%A0
   or %1,%0"
-  [(set_attr "cc" "clobber,set_znv")])
+  [(set_attr "cc" "clobber,set_zn")])
 
 (define_expand "iorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -1338,7 +1449,7 @@
   bset %U2,%A0
   bset %2,%0
   or %2,%0"
-  [(set_attr "cc" "clobber,clobber,set_znv")])
+  [(set_attr "cc" "clobber,clobber,set_zn")])
 
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=R,T,d")
@@ -1353,7 +1464,7 @@
   bset %U2,%A0
   bset %2,%0
   or %2,%0"
-  [(set_attr "cc" "clobber,clobber,set_znv")])
+  [(set_attr "cc" "clobber,clobber,set_zn")])
 
 (define_insn ""
   [(set (cc0)
@@ -1551,6 +1662,8 @@
   ""
   "*
 {
+  if (cc_status.mdep.fpCC)
+    return \"fb%b1 %0\";
   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
       && (GET_CODE (operands[1]) == GT
 	  || GET_CODE (operands[1]) == GE
@@ -1570,6 +1683,8 @@
   ""
   "*
 {
+  if (cc_status.mdep.fpCC)
+    return \"fb%B1 %0\";
   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
       && (GET_CODE (operands[1]) == GT
 	  || GET_CODE (operands[1]) == GE
@@ -1595,6 +1710,43 @@
   "jmp (%0)"
   [(set_attr "cc" "none")])
 
+(define_expand "builtin_setjmp_receiver"
+  [(match_operand 0 "" "")]
+  "flag_pic"
+  "
+{
+  if (flag_pic)
+    emit_insn (gen_GOTaddr2picreg ());
+
+  DONE;
+}")
+
+(define_expand "casesi"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:SI 1 "immediate_operand" "")
+   (match_operand:SI 2 "immediate_operand" "")
+   (match_operand 3 "" "") (match_operand 4 "" "")]
+  ""
+  "
+{
+  rtx table = gen_reg_rtx (SImode);
+  rtx index = gen_reg_rtx (SImode);
+  rtx addr = gen_reg_rtx (Pmode);
+
+  emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
+  emit_move_insn (index, plus_constant (operands[0], - INTVAL (operands[1])));
+  emit_insn (gen_cmpsi (index, operands[2]));
+  emit_jump_insn (gen_bgtu (operands[4]));
+  emit_move_insn (index, gen_rtx_ASHIFT (SImode, index, GEN_INT (2)));
+  emit_move_insn (addr, gen_rtx_MEM (SImode,
+				     gen_rtx_PLUS (SImode, table, index)));
+  if (flag_pic)
+    emit_move_insn (addr, gen_rtx_PLUS (SImode, addr, table));
+
+  emit_jump_insn (gen_tablejump (addr, operands[3]));
+  DONE;
+}")
+
 (define_insn "tablejump"
   [(set (pc) (match_operand:SI 0 "register_operand" "a"))
    (use (label_ref (match_operand 1 "" "")))]
@@ -1610,6 +1762,20 @@
   ""
   "
 {
+  if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+    {
+      if (MN10300_GLOBAL_P (XEXP (operands[0], 0)))
+	{
+	  /* The PLT code won't run on AM30, but then, there's no
+	     shared library support for AM30 either, so we just assume
+	     the linker is going to adjust all @PLT relocs to the
+	     actual symbols.  */
+	  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
+	  XEXP (operands[0], 0) = gen_sym2PLT (XEXP (operands[0], 0));
+	}
+      else
+	XEXP (operands[0], 0) = gen_sym2PIC (XEXP (operands[0], 0));
+    }
   if (! call_address_operand (XEXP (operands[0], 0), VOIDmode))
     XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
   emit_call_insn (gen_call_internal (XEXP (operands[0], 0), operands[1]));
@@ -1639,6 +1805,20 @@
   ""
   "
 {
+  if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+    {
+      if (MN10300_GLOBAL_P (XEXP (operands[1], 0)))
+	{
+	  /* The PLT code won't run on AM30, but then, there's no
+	     shared library support for AM30 either, so we just assume
+	     the linker is going to adjust all @PLT relocs to the
+	     actual symbols.  */
+	  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
+	  XEXP (operands[1], 0) = gen_sym2PLT (XEXP (operands[1], 0));
+	}
+      else
+	XEXP (operands[1], 0) = gen_sym2PIC (XEXP (operands[1], 0));
+    }
   if (! call_address_operand (XEXP (operands[1], 0), VOIDmode))
     XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
   emit_call_insn (gen_call_value_internal (operands[0],
@@ -1996,6 +2176,12 @@
   rtx result;
   rtx target;
 
+  if (TARGET_AM33_2)
+    {
+      emit_insn (gen_abssf2_am33_2 (operands[0], operands[1]));
+      DONE;
+    }
+
   target = operand_subword_force (operands[0], 0, SFmode);
   result = expand_binop (SImode, and_optab,
 			 operand_subword_force (operands[1], 0, SFmode),
@@ -2012,6 +2198,15 @@
 }")
 
 
+(define_insn "abssf2_am33_2"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
+  "TARGET_AM33_2"
+  "@
+   fabs %0
+   fabs %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
 (define_expand "negdf2"
   [(set (match_operand:DF 0 "register_operand" "")
         (neg:DF (match_operand:DF 1 "register_operand" "")))]
@@ -2052,6 +2247,12 @@
   rtx result;
   rtx target;
 
+  if (TARGET_AM33_2)
+    {
+      emit_insn (gen_negsf2_am33_2 (operands[0], operands[1]));
+      DONE;
+    }
+
   target = operand_subword_force (operands[0], 0, SFmode);
   result = expand_binop (SImode, xor_optab,
 			 operand_subword_force (operands[1], 0, SFmode),
@@ -2068,6 +2269,114 @@
   DONE;
 }")
 
+(define_insn "negsf2_am33_2"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
+  "TARGET_AM33_2"
+  "@
+   fneg %0
+   fneg %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_expand "sqrtsf2"
+  [(set (match_operand:SF 0 "register_operand" "")
+	(sqrt:SF (match_operand:SF 1 "register_operand" "")))]
+  "TARGET_AM33_2 && flag_unsafe_math_optimizations"
+  "
+{
+  rtx scratch = gen_reg_rtx (SFmode);
+  emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
+  emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
+			 scratch));
+  DONE;
+}")
+
+(define_insn "rsqrtsf2"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
+		(sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))]
+  "TARGET_AM33_2"
+  "@
+   frsqrt %0
+   frsqrt %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "addsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(plus:SF (match_operand:SF 1 "register_operand" "%0,f")
+		 (match_operand:SF 2 "general_operand" "f,?fF")))]
+  "TARGET_AM33_2"
+  "@
+   fadd %2, %0
+   fadd %2, %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "subsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(minus:SF (match_operand:SF 1 "register_operand" "0,f")
+		  (match_operand:SF 2 "general_operand" "f,?fF")))]
+  "TARGET_AM33_2"
+  "@
+   fsub %2, %0
+   fsub %2, %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "mulsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(mult:SF (match_operand:SF 1 "register_operand" "%0,f")
+		 (match_operand:SF 2 "general_operand" "f,?fF")))]
+  "TARGET_AM33_2"
+  "@
+   fmul %2, %0
+   fmul %2, %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "divsf3"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(div:SF (match_operand:SF 1 "register_operand" "0,f")
+		(match_operand:SF 2 "general_operand" "f,?fF")))]
+  "TARGET_AM33_2"
+  "@
+   fdiv %2, %0
+   fdiv %2, %1, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "fmaddsf4"
+  [(set (match_operand:SF 0 "register_operand" "=A")
+	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
+			  (match_operand:SF 2 "register_operand" "f"))
+		 (match_operand:SF 3 "register_operand" "f")))]
+  "TARGET_AM33_2"
+  "fmadd %1, %2, %3, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "fmsubsf4"
+  [(set (match_operand:SF 0 "register_operand" "=A")
+	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
+			   (match_operand:SF 2 "register_operand" "f"))
+		  (match_operand:SF 3 "register_operand" "f")))]
+  "TARGET_AM33_2"
+  "fmsub %1, %2, %3, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "fnmaddsf4"
+  [(set (match_operand:SF 0 "register_operand" "=A")
+	(minus:SF (match_operand:SF 3 "register_operand" "f")
+		  (mult:SF (match_operand:SF 1 "register_operand" "%f")
+			   (match_operand:SF 2 "register_operand" "f"))))]
+  "TARGET_AM33_2"
+  "fnmadd %1, %2, %3, %0"
+  [(set_attr "cc" "none_0hit")])
+
+(define_insn "fnmsubsf4"
+  [(set (match_operand:SF 0 "register_operand" "=A")
+	(minus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
+				   (match_operand:SF 2 "register_operand" "f")))
+		  (match_operand:SF 3 "register_operand" "f")))]
+  "TARGET_AM33_2"
+  "fnmsub %1, %2, %3, %0"
+  [(set_attr "cc" "none_0hit")])
+
 
 ;; ----------------------------------------------------------------------
 ;; PROLOGUE/EPILOGUE
@@ -2202,3 +2511,134 @@
   "add %0,%0\;bcc %1"
   [(set_attr "cc" "clobber")])
 
+(define_expand "int_label"
+  [(unspec [(match_operand:SI 0 "" "")] UNSPEC_INT_LABEL)]
+  "" "")
+
+(define_expand "GOTaddr2picreg"
+  [(match_dup 0)]
+  "" "
+{
+  /* It would be nice to be able to have int_label keep track of the
+     counter and all, but if we add C code to it, we'll get an insn
+     back, and we just want the pattern.  */
+  operands[0] = gen_int_label (GEN_INT (mn10300_unspec_int_label_counter++));
+  if (TARGET_AM33)
+    emit_insn (gen_am33_loadPC (operands[0]));
+  else
+    emit_insn (gen_mn10300_loadPC (operands[0]));
+  emit_insn (gen_add_GOT_to_pic_reg (operands[0]));
+  DONE;
+}
+")
+
+(define_insn "am33_loadPC"
+  [(parallel
+    [(set (reg:SI PIC_REG) (pc))
+     (use (match_operand 0 "" ""))])]
+  "TARGET_AM33"
+  "%0:\;mov pc,a2")
+
+
+(define_insn_and_split "mn10300_loadPC"
+  [(parallel
+    [(set (reg:SI PIC_REG) (pc))
+     (use (match_operand 0 "" ""))])]
+  ""
+  "#"
+  "reload_completed"
+  [(match_operand 0 "" "")]
+  "
+{
+  rtx sp_reg = gen_rtx_REG (SImode, SP_REG);
+  int need_stack_space = (get_frame_size () == 0
+			  && current_function_outgoing_args_size == 0);
+
+  if (need_stack_space)
+    emit_move_insn (sp_reg, plus_constant (sp_reg, -4));
+
+  emit_insn (gen_call_next_insn (operands[0]));
+
+  if (need_stack_space)
+    emit_insn (gen_pop_pic_reg ());
+  else
+    emit_move_insn (pic_offset_table_rtx, gen_rtx_MEM (SImode, sp_reg));
+
+  DONE;
+}")
+
+(define_insn "call_next_insn"
+  [(parallel
+    [(set (mem:SI (reg:SI SP_REG)) (pc))
+     (use (match_operand 0 "" ""))])]
+  "reload_completed"
+  "calls %0\;%0:")
+
+(define_expand "add_GOT_to_pic_reg"
+  [(set (reg:SI PIC_REG)
+	(plus:SI
+	 (reg:SI PIC_REG)
+	 (const
+	  (unspec [(minus:SI
+		    (match_dup 1)
+		    (const (minus:SI
+			    (const (match_operand:SI 0 "" ""))
+			    (pc))))
+		  ] UNSPEC_PIC))))]
+  ""
+  "
+{
+  operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
+}")
+
+(define_expand "symGOT2reg"
+  [(match_operand:SI 0 "" "")
+   (match_operand:SI 1 "" "")]
+  ""
+  "
+{
+  rtx insn = emit_insn (gen_symGOT2reg_i (operands[0], operands[1]));
+
+  RTX_UNCHANGING_P (SET_SRC (PATTERN (insn))) = 1;
+
+  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
+					REG_NOTES (insn));
+
+  DONE;
+}")
+
+(define_expand "symGOT2reg_i"
+  [(set (match_operand:SI 0 "" "")
+	(mem:SI (plus:SI (reg:SI PIC_REG)
+			 (const (unspec [(match_operand:SI 1 "" "")]
+					UNSPEC_GOT)))))]
+  ""
+  "")
+
+(define_expand "symGOTOFF2reg"
+  [(match_operand:SI 0 "" "") (match_operand:SI 1 "" "")]
+  ""
+  "
+{
+  rtx insn = emit_insn (gen_symGOTOFF2reg_i (operands[0], operands[1]));
+
+  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
+					REG_NOTES (insn));
+
+  DONE;
+}")
+
+(define_expand "symGOTOFF2reg_i"
+  [(set (match_operand:SI 0 "" "")
+	(const (unspec [(match_operand:SI 1 "" "")] UNSPEC_GOTOFF)))
+  (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI PIC_REG)))]
+  ""
+  "")
+
+(define_expand "sym2PIC"
+  [(unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC)]
+  "" "")
+
+(define_expand "sym2PLT"
+  [(unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT)]
+  "" "")
diff --git a/gcc/config/mn10300/t-linux b/gcc/config/mn10300/t-linux
new file mode 100644
index 00000000000..a80c1cf4eec
--- /dev/null
+++ b/gcc/config/mn10300/t-linux
@@ -0,0 +1,11 @@
+# We want fine grained libraries, so use the new code to build the
+# floating point emulation libraries.
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	cat $(srcdir)/config/fp-bit.c > dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
diff --git a/gcc/config/mn10300/t-mn10300 b/gcc/config/mn10300/t-mn10300
index 2e26e229acc..a35b2c50185 100644
--- a/gcc/config/mn10300/t-mn10300
+++ b/gcc/config/mn10300/t-mn10300
@@ -10,8 +10,8 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
 	echo '#define FLOAT' > fp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
 
-MULTILIB_OPTIONS = mam33
-MULTILIB_DIRNAMES = am33
+MULTILIB_OPTIONS = mam33/mam33-2
+MULTILIB_DIRNAMES = am33 am33-2
 
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/pa/elf.h b/gcc/config/pa/elf.h
index 5b35178ea91..0752e7b5b29 100644
--- a/gcc/config/pa/elf.h
+++ b/gcc/config/pa/elf.h
@@ -1,20 +1,20 @@
 /* Definitions for ELF assembler support.
-   Copyright (C) 1999 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/fptr.c b/gcc/config/pa/fptr.c
index 680cb20c3a4..fe48edf765b 100644
--- a/gcc/config/pa/fptr.c
+++ b/gcc/config/pa/fptr.c
@@ -1,21 +1,21 @@
 /* Subroutine for function pointer canonicalization on PA-RISC with ELF32.
-   Copyright 2002 Free Software Foundation, Inc.
+   Copyright 2002, 2003 Free Software Foundation, Inc.
    Contributed by John David Anglin (dave.anglin@nrc.ca).
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/lib2funcs.asm b/gcc/config/pa/lib2funcs.asm
index abd69d5e130..8f5278baedb 100644
--- a/gcc/config/pa/lib2funcs.asm
+++ b/gcc/config/pa/lib2funcs.asm
@@ -2,14 +2,14 @@
 ;  Subroutines for out of line prologues and epilogues on for the HPPA
 ;  Copyright (C) 1994, 1995, 1996 Free Software Foundation, Inc.
 
-;  This file is part of GNU CC.
+;  This file is part of GCC.
 
-;  GNU CC is free software; you can redistribute it and/or modify
+;  GCC is free software; you can redistribute it and/or modify
 ;  it under the terms of the GNU General Public License as published by
 ;  the Free Software Foundation; either version 2, or (at your option)
 ;  any later version.
 
-;  GNU CC is distributed in the hope that it will be useful,
+;  GCC is distributed in the hope that it will be useful,
 ;  but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;  GNU General Public License for more details.
@@ -24,7 +24,7 @@
 ;  executable.)
 
 ;  You should have received a copy of the GNU General Public License
-;  along with GNU CC; see the file COPYING.  If not, write to
+;  along with GCC; see the file COPYING.  If not, write to
 ;  the Free Software Foundation, 59 Temple Place - Suite 330,
 ;  Boston, MA 02111-1307, USA.
 
diff --git a/gcc/config/pa/long_double.h b/gcc/config/pa/long_double.h
index 5d2c6199bc8..11504cac54a 100644
--- a/gcc/config/pa/long_double.h
+++ b/gcc/config/pa/long_double.h
@@ -1,20 +1,20 @@
 /* Definitions of long double support for GNU compiler.
-   Copyright (C) 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 2000, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/milli64.S b/gcc/config/pa/milli64.S
index 99d2d2e12a3..60eb5d210f7 100644
--- a/gcc/config/pa/milli64.S
+++ b/gcc/config/pa/milli64.S
@@ -2,12 +2,12 @@
    adapted for gcc by Paul Bame <bame@debian.org>
    and Alan Modra <alan@linuxcare.com.au>.
 
-   Copyright 2001, 2002 Free Software Foundation, Inc.
+   Copyright 2001, 2002, 2003 Free Software Foundation, Inc.
 
-   This file is part of GNU CC and is released under the terms of
+   This file is part of GCC and is released under the terms of
    of the GNU General Public License as published by the Free Software
    Foundation; either version 2, or (at your option) any later version.
-   See the file COPYING in the top-level GNU CC source directory for a copy
+   See the file COPYING in the top-level GCC source directory for a copy
    of the license.  */
 
 
diff --git a/gcc/config/pa/pa-64.h b/gcc/config/pa/pa-64.h
index 6cb289e3b41..a76a8aab8e1 100644
--- a/gcc/config/pa/pa-64.h
+++ b/gcc/config/pa/pa-64.h
@@ -1,21 +1,21 @@
 /* Definitions of target machine for GNU compiler, for HPs using the
    64bit runtime model.
-   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h
index 5b99ee5aadc..bea7331d676 100644
--- a/gcc/config/pa/pa-hpux.h
+++ b/gcc/config/pa/pa-hpux.h
@@ -1,20 +1,20 @@
 /* Definitions of target machine for GNU compiler, for HP-UX.
-   Copyright (C) 1991, 1995, 1996, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1991, 1995, 1996, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
@@ -28,6 +28,12 @@ Boston, MA 02111-1307, USA.  */
 #define SIZE_TYPE "unsigned int"
 #define PTRDIFF_TYPE "int"
 
+/* GCC always defines __STDC__.  HP C++ compilers don't define it.  This
+   causes trouble when sys/stdsyms.h is included.  As a work around,
+   we define __STDC_EXT__.  A similar situation exists with respect to
+   the definition of __cplusplus.  We define _INCLUDE_LONGLONG
+   to prevent nlist.h from defining __STDC_32_MODE__ (no longlong
+   support).  */
 #undef TARGET_OS_CPP_BUILTINS
 #define TARGET_OS_CPP_BUILTINS()				\
   do								\
@@ -46,6 +52,7 @@ Boston, MA 02111-1307, USA.  */
 	  {							\
 	    builtin_define ("_HPUX_SOURCE");			\
 	    builtin_define ("_INCLUDE_LONGLONG");		\
+	    builtin_define ("__STDC_EXT__");			\
 	  }							\
 	else if (!flag_iso)					\
 	  {							\
diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h
index 78ac2afef0d..b9d06d5f642 100644
--- a/gcc/config/pa/pa-hpux10.h
+++ b/gcc/config/pa/pa-hpux10.h
@@ -1,25 +1,31 @@
 /* Definitions of target machine for GNU compiler, for HP PA-RISC
-   Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002
+   Copyright (C) 1995, 1996, 1997, 2000, 2001, 2002, 2003
    Free Software Foundation, Inc.
    Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* GCC always defines __STDC__.  HP C++ compilers don't define it.  This
+   causes trouble when sys/stdsyms.h is included.  As a work around,
+   we define __STDC_EXT__.  A similar situation exists with respect to
+   the definition of __cplusplus.  We define _INCLUDE_LONGLONG
+   to prevent nlist.h from defining __STDC_32_MODE__ (no longlong
+   support).  */
 #undef TARGET_OS_CPP_BUILTINS
 #define TARGET_OS_CPP_BUILTINS()				\
   do								\
@@ -36,6 +42,7 @@ Boston, MA 02111-1307, USA.  */
 	  {							\
 	    builtin_define ("_HPUX_SOURCE");			\
 	    builtin_define ("_INCLUDE_LONGLONG");		\
+	    builtin_define ("__STDC_EXT__");			\
 	  }							\
 	else if (!flag_iso)					\
 	  {							\
diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h
index 5a35ace408b..e8865dfff7f 100644
--- a/gcc/config/pa/pa-hpux11.h
+++ b/gcc/config/pa/pa-hpux11.h
@@ -1,23 +1,29 @@
 /* Definitions of target machine for GNU compiler, for HP PA-RISC
    Copyright (C) 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
+/* GCC always defines __STDC__.  HP C++ compilers don't define it.  This
+   causes trouble when sys/stdsyms.h is included.  As a work around,
+   we define __STDC_EXT__.  A similar situation exists with respect to
+   the definition of __cplusplus.  We define _INCLUDE_LONGLONG
+   to prevent nlist.h from defining __STDC_32_MODE__ (no longlong
+   support).  */
 #undef TARGET_OS_CPP_BUILTINS
 #define TARGET_OS_CPP_BUILTINS()				\
   do								\
@@ -34,6 +40,7 @@ Boston, MA 02111-1307, USA.  */
 	  {							\
 	    builtin_define ("_HPUX_SOURCE");			\
 	    builtin_define ("_INCLUDE_LONGLONG");		\
+	    builtin_define ("__STDC_EXT__");			\
 	  }							\
 	else							\
 	  {							\
@@ -67,6 +74,13 @@ Boston, MA 02111-1307, USA.  */
     }								\
   while (0)
 
+#undef CPP_SPEC
+#define CPP_SPEC \
+  "%{mt|pthread:-D_REENTRANT -D_THREAD_SAFE -D_POSIX_C_SOURCE=199506L}"
+/* aCC defines also -DRWSTD_MULTI_THREAD, -DRW_MULTI_THREAD.  These
+   affect only aCC's C++ library (Rogue Wave-derived) which we do not
+   use, and they violate the user's name space.  */
+
 /* We can debug dynamically linked executables on hpux11; we also
    want dereferencing of a NULL pointer to cause a SEGV.  */
 #undef LINK_SPEC
@@ -93,15 +107,12 @@ Boston, MA 02111-1307, USA.  */
    %{static:-a archive} %{shared:-b}"
 #endif
 
-/* Like the default, except no -lg.  */
+/* hpux 11 has posix threads.  */
 #undef LIB_SPEC
 #define LIB_SPEC \
   "%{!shared:\
-     %{!p:%{!pg:\
-       %{!threads:-lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\
-       %{threads:-lcma -lc_r}}}\
-     %{p:%{!pg:-lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\
-     %{pg:-lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}"
+     %{mt|pthread:-lpthread} -lc \
+     %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}"
 
 /* Under hpux11, the normal location of the `ld' and `as' programs is the
    /usr/ccs/bin directory.  */
diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h
index ed7c82bf846..027c946dba3 100644
--- a/gcc/config/pa/pa-linux.h
+++ b/gcc/config/pa/pa-linux.h
@@ -1,20 +1,20 @@
 /* Definitions for PA_RISC with ELF format
-   Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+   Copyright 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa-modes.def b/gcc/config/pa/pa-modes.def
index 75fba097ee0..c57c9bc4bc9 100644
--- a/gcc/config/pa/pa-modes.def
+++ b/gcc/config/pa/pa-modes.def
@@ -1,23 +1,23 @@
 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
    Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
    and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
    Software Science at the University of Utah.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa-osf.h b/gcc/config/pa/pa-osf.h
index 74a6e588505..a824da6128d 100644
--- a/gcc/config/pa/pa-osf.h
+++ b/gcc/config/pa/pa-osf.h
@@ -1,21 +1,21 @@
 /* Definitions of target machine for GNU compiler, for HP PA-RISC 1.1
-   Copyright (C) 1991, 1995, 1996, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1991, 1995, 1996, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Tim Moore (moore@defmacro.cs.utah.edu)
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa-pro-end.h b/gcc/config/pa/pa-pro-end.h
index 927f424bc50..5fc06e23e28 100644
--- a/gcc/config/pa/pa-pro-end.h
+++ b/gcc/config/pa/pa-pro-end.h
@@ -1,20 +1,20 @@
 /* Definitions of target machine for GNU compiler, for PRO.
-   Copyright (C) 1996, 1997, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1996, 1997, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h
index cff08c2ba1d..f5f15cb3fd3 100644
--- a/gcc/config/pa/pa-protos.h
+++ b/gcc/config/pa/pa-protos.h
@@ -1,165 +1,165 @@
 /* Prototypes for pa.c functions used in the md file & elsewhere.
    Copyright (C) 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
 #ifdef RTX_CODE
 /* Prototype function used in various macros.  */
-extern int symbolic_operand PARAMS ((rtx, enum machine_mode));
+extern int symbolic_operand (rtx, enum machine_mode);
 
 /* Used in insn-*.c.  */
-extern int following_call PARAMS ((rtx));
-extern int function_label_operand PARAMS ((rtx, enum machine_mode));
-extern int lhs_lshift_cint_operand PARAMS ((rtx, enum machine_mode));
+extern int following_call (rtx);
+extern int function_label_operand (rtx, enum machine_mode);
+extern int lhs_lshift_cint_operand (rtx, enum machine_mode);
 
 #ifdef TREE_CODE
-extern void hppa_va_start PARAMS ((tree, rtx));
-extern rtx hppa_va_arg PARAMS ((tree, tree));
+extern void hppa_va_start (tree, rtx);
+extern rtx hppa_va_arg (tree, tree);
 #endif /* TREE_CODE */
-extern rtx hppa_legitimize_address PARAMS ((rtx, rtx, enum machine_mode));
+extern rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
 
 /* Define functions in pa.c and used in insn-output.c.  */
 
-extern const char *output_and PARAMS ((rtx *));
-extern const char *output_ior PARAMS ((rtx *));
-extern const char *output_move_double PARAMS ((rtx *));
-extern const char *output_fp_move_double PARAMS ((rtx *));
-extern const char *output_block_move PARAMS ((rtx *, int));
-extern const char *output_cbranch PARAMS ((rtx *, int, int, int, rtx));
-extern const char *output_lbranch PARAMS ((rtx, rtx));
-extern const char *output_bb PARAMS ((rtx *, int, int, int, rtx, int));
-extern const char *output_bvb PARAMS ((rtx *, int, int, int, rtx, int));
-extern const char *output_dbra PARAMS ((rtx *, rtx, int));
-extern const char *output_movb PARAMS ((rtx *, rtx, int, int));
-extern const char *output_parallel_movb PARAMS ((rtx *, int));
-extern const char *output_parallel_addb PARAMS ((rtx *, int));
-extern const char *output_call PARAMS ((rtx, rtx, int));
-extern const char *output_indirect_call PARAMS ((rtx, rtx));
-extern const char *output_millicode_call PARAMS ((rtx, rtx));
-extern const char *output_mul_insn PARAMS ((int, rtx));
-extern const char *output_div_insn PARAMS ((rtx *, int, rtx));
-extern const char *output_mod_insn PARAMS ((int, rtx));
-extern const char *singlemove_string PARAMS ((rtx *));
-extern void output_arg_descriptor PARAMS ((rtx));
-extern void output_global_address PARAMS ((FILE *, rtx, int));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern rtx legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx));
-extern struct rtx_def *gen_cmp_fp PARAMS ((enum rtx_code, rtx, rtx));
-extern void hppa_encode_label PARAMS ((rtx));
-extern int arith11_operand PARAMS ((rtx, enum machine_mode));
-extern int adddi3_operand PARAMS ((rtx, enum machine_mode));
-extern int symbolic_expression_p PARAMS ((rtx));
-extern int symbolic_memory_operand PARAMS ((rtx, enum machine_mode));
-extern int pa_adjust_insn_length PARAMS ((rtx, int));
-extern int int11_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_cint_move_operand PARAMS ((rtx, enum machine_mode));
-extern int arith5_operand PARAMS ((rtx, enum machine_mode));
-extern int uint5_operand PARAMS ((rtx, enum machine_mode));
-extern int pic_label_operand PARAMS ((rtx, enum machine_mode));
-extern int plus_xor_ior_operator PARAMS ((rtx, enum machine_mode));
-extern int basereg_operand PARAMS ((rtx, enum machine_mode));
-extern int shadd_operand PARAMS ((rtx, enum machine_mode));
-extern int arith_operand PARAMS ((rtx, enum machine_mode));
-extern int read_only_operand PARAMS ((rtx, enum machine_mode));
-extern int move_operand PARAMS ((rtx, enum machine_mode));
-extern int and_operand PARAMS ((rtx, enum machine_mode));
-extern int ior_operand PARAMS ((rtx, enum machine_mode));
-extern int arith32_operand PARAMS ((rtx, enum machine_mode));
-extern int uint32_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_nonsymb_mem_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_before_reload_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_0_or_nonsymb_mem_operand PARAMS ((rtx, enum machine_mode));
-extern int pre_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int post_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int div_operand PARAMS ((rtx, enum machine_mode));
-extern int int5_operand PARAMS ((rtx, enum machine_mode));
-extern int movb_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int ireg_or_int5_operand PARAMS ((rtx, enum machine_mode));
-extern int fmpyaddoperands PARAMS ((rtx *));
-extern int fmpysuboperands PARAMS ((rtx *));
-extern int call_operand_address PARAMS ((rtx, enum machine_mode));
-extern int ior_operand PARAMS ((rtx, enum machine_mode));
-extern void emit_bcond_fp PARAMS ((enum rtx_code, rtx));
-extern int emit_move_sequence PARAMS ((rtx *, enum machine_mode, rtx));
-extern int emit_hpdiv_const PARAMS ((rtx *, int));
-extern int is_function_label_plus_const PARAMS ((rtx));
-extern int jump_in_call_delay PARAMS ((rtx));
-extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
-						      enum machine_mode, rtx));
-extern int hppa_fpstore_bypass_p PARAMS ((rtx, rtx));
-extern int attr_length_millicode_call PARAMS ((rtx));
-extern int attr_length_call PARAMS ((rtx, int));
-extern int attr_length_indirect_call PARAMS ((rtx));
-extern int attr_length_save_restore_dltp PARAMS ((rtx));
+extern const char *output_and (rtx *);
+extern const char *output_ior (rtx *);
+extern const char *output_move_double (rtx *);
+extern const char *output_fp_move_double (rtx *);
+extern const char *output_block_move (rtx *, int);
+extern const char *output_cbranch (rtx *, int, int, int, rtx);
+extern const char *output_lbranch (rtx, rtx);
+extern const char *output_bb (rtx *, int, int, int, rtx, int);
+extern const char *output_bvb (rtx *, int, int, int, rtx, int);
+extern const char *output_dbra (rtx *, rtx, int);
+extern const char *output_movb (rtx *, rtx, int, int);
+extern const char *output_parallel_movb (rtx *, int);
+extern const char *output_parallel_addb (rtx *, int);
+extern const char *output_call (rtx, rtx, int);
+extern const char *output_indirect_call (rtx, rtx);
+extern const char *output_millicode_call (rtx, rtx);
+extern const char *output_mul_insn (int, rtx);
+extern const char *output_div_insn (rtx *, int, rtx);
+extern const char *output_mod_insn (int, rtx);
+extern const char *singlemove_string (rtx *);
+extern void output_arg_descriptor (rtx);
+extern void output_global_address (FILE *, rtx, int);
+extern void print_operand (FILE *, rtx, int);
+extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
+extern struct rtx_def *gen_cmp_fp (enum rtx_code, rtx, rtx);
+extern void hppa_encode_label (rtx);
+extern int arith11_operand (rtx, enum machine_mode);
+extern int adddi3_operand (rtx, enum machine_mode);
+extern int symbolic_expression_p (rtx);
+extern int symbolic_memory_operand (rtx, enum machine_mode);
+extern int pa_adjust_insn_length (rtx, int);
+extern int int11_operand (rtx, enum machine_mode);
+extern int reg_or_cint_move_operand (rtx, enum machine_mode);
+extern int arith5_operand (rtx, enum machine_mode);
+extern int uint5_operand (rtx, enum machine_mode);
+extern int pic_label_operand (rtx, enum machine_mode);
+extern int plus_xor_ior_operator (rtx, enum machine_mode);
+extern int basereg_operand (rtx, enum machine_mode);
+extern int shadd_operand (rtx, enum machine_mode);
+extern int arith_operand (rtx, enum machine_mode);
+extern int read_only_operand (rtx, enum machine_mode);
+extern int move_operand (rtx, enum machine_mode);
+extern int and_operand (rtx, enum machine_mode);
+extern int ior_operand (rtx, enum machine_mode);
+extern int arith32_operand (rtx, enum machine_mode);
+extern int uint32_operand (rtx, enum machine_mode);
+extern int reg_or_nonsymb_mem_operand (rtx, enum machine_mode);
+extern int reg_before_reload_operand (rtx, enum machine_mode);
+extern int reg_or_0_operand (rtx, enum machine_mode);
+extern int reg_or_0_or_nonsymb_mem_operand (rtx, enum machine_mode);
+extern int pre_cint_operand (rtx, enum machine_mode);
+extern int post_cint_operand (rtx, enum machine_mode);
+extern int div_operand (rtx, enum machine_mode);
+extern int int5_operand (rtx, enum machine_mode);
+extern int movb_comparison_operator (rtx, enum machine_mode);
+extern int ireg_or_int5_operand (rtx, enum machine_mode);
+extern int fmpyaddoperands (rtx *);
+extern int fmpysuboperands (rtx *);
+extern int call_operand_address (rtx, enum machine_mode);
+extern int ior_operand (rtx, enum machine_mode);
+extern void emit_bcond_fp (enum rtx_code, rtx);
+extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
+extern int emit_hpdiv_const (rtx *, int);
+extern int is_function_label_plus_const (rtx);
+extern int jump_in_call_delay (rtx);
+extern enum reg_class secondary_reload_class (enum reg_class,
+					      enum machine_mode, rtx);
+extern int hppa_fpstore_bypass_p (rtx, rtx);
+extern int attr_length_millicode_call (rtx);
+extern int attr_length_call (rtx, int);
+extern int attr_length_indirect_call (rtx);
+extern int attr_length_save_restore_dltp (rtx);
 
 /* Declare functions defined in pa.c and used in templates.  */
 
-extern struct rtx_def *return_addr_rtx PARAMS ((int, rtx));
+extern struct rtx_def *return_addr_rtx (int, rtx);
 
-extern int fp_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int arith_double_operand PARAMS ((rtx, enum machine_mode));
-extern int ireg_operand PARAMS ((rtx, enum machine_mode));
-extern int lhs_lshift_operand PARAMS ((rtx, enum machine_mode));
-extern int pc_or_label_operand PARAMS ((rtx, enum machine_mode));
+extern int fp_reg_operand (rtx, enum machine_mode);
+extern int arith_double_operand (rtx, enum machine_mode);
+extern int ireg_operand (rtx, enum machine_mode);
+extern int lhs_lshift_operand (rtx, enum machine_mode);
+extern int pc_or_label_operand (rtx, enum machine_mode);
 #ifdef ARGS_SIZE_RTX
 /* expr.h defines ARGS_SIZE_RTX and `enum direction' */
 #ifdef TREE_CODE
-extern enum direction function_arg_padding PARAMS ((enum machine_mode, tree));
+extern enum direction function_arg_padding (enum machine_mode, tree);
 #endif
 #endif /* ARGS_SIZE_RTX */
-extern int non_hard_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int eq_neq_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int insn_refs_are_delayed PARAMS ((rtx));
+extern int non_hard_reg_operand (rtx, enum machine_mode);
+extern int eq_neq_comparison_operator (rtx, enum machine_mode);
+extern int insn_refs_are_delayed (rtx);
 #endif /* RTX_CODE */
 
 /* Prototype function used in macro CONST_OK_FOR_LETTER_P.  */
-extern int zdepi_cint_p PARAMS ((unsigned HOST_WIDE_INT));
-
-extern struct rtx_def *hppa_builtin_saveregs PARAMS ((void));
-
-extern void override_options PARAMS ((void));
-extern void output_ascii PARAMS ((FILE *, const char *, int));
-extern int compute_frame_size PARAMS ((int, int *));
-extern int and_mask_p PARAMS ((unsigned HOST_WIDE_INT));
-extern int cint_ok_for_move PARAMS ((HOST_WIDE_INT));
-extern void hppa_expand_prologue PARAMS ((void));
-extern void hppa_expand_epilogue PARAMS ((void));
-extern int hppa_can_use_return_insn_p PARAMS ((void));
-extern int ior_mask_p PARAMS ((unsigned HOST_WIDE_INT));
-extern void compute_zdepdi_operands PARAMS ((unsigned HOST_WIDE_INT,
-					     unsigned *));
+extern int zdepi_cint_p (unsigned HOST_WIDE_INT);
+
+extern struct rtx_def *hppa_builtin_saveregs (void);
+
+extern void override_options (void);
+extern void output_ascii (FILE *, const char *, int);
+extern int compute_frame_size (int, int *);
+extern int and_mask_p (unsigned HOST_WIDE_INT);
+extern int cint_ok_for_move (HOST_WIDE_INT);
+extern void hppa_expand_prologue (void);
+extern void hppa_expand_epilogue (void);
+extern int hppa_can_use_return_insn_p (void);
+extern int ior_mask_p (unsigned HOST_WIDE_INT);
+extern void compute_zdepdi_operands (unsigned HOST_WIDE_INT,
+				     unsigned *);
 #ifdef RTX_CODE
-extern const char * output_64bit_and PARAMS ((rtx *));
-extern const char * output_64bit_ior PARAMS ((rtx *));
-extern int cmpib_comparison_operator PARAMS ((rtx, enum machine_mode));
+extern const char * output_64bit_and (rtx *);
+extern const char * output_64bit_ior (rtx *);
+extern int cmpib_comparison_operator (rtx, enum machine_mode);
 #endif
 
 
 
 #ifdef TREE_CODE
-extern int reloc_needed PARAMS ((tree));
+extern int reloc_needed (tree);
 #ifdef RTX_CODE
-extern rtx function_arg PARAMS ((CUMULATIVE_ARGS *, enum machine_mode,
-				 tree, int));
-extern rtx function_value PARAMS ((tree, tree));
+extern rtx function_arg (CUMULATIVE_ARGS *, enum machine_mode,
+			 tree, int);
+extern rtx function_value (tree, tree);
 #endif
-extern int function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *,
-					       enum machine_mode,
-					       tree, int));
+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *,
+				       enum machine_mode,
+				       tree, int);
 #endif /* TREE_CODE */
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 9287583bd7d..9c207d6d591 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -3,20 +3,20 @@
    2002, 2003 Free Software Foundation, Inc.
    Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
@@ -50,13 +50,13 @@ Boston, MA 02111-1307, USA.  */
 #include "target.h"
 #include "target-def.h"
 
-static int hppa_use_dfa_pipeline_interface PARAMS ((void));
+static int hppa_use_dfa_pipeline_interface (void);
 
 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE 
 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
 
 static int
-hppa_use_dfa_pipeline_interface ()
+hppa_use_dfa_pipeline_interface (void)
 {
   return 1;
 }
@@ -64,8 +64,7 @@ hppa_use_dfa_pipeline_interface ()
 /* Return nonzero if there is a bypass for the output of 
    OUT_INSN and the fp store IN_INSN.  */
 int
-hppa_fpstore_bypass_p (out_insn, in_insn)
-     rtx out_insn, in_insn;
+hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
 {
   enum machine_mode store_mode;
   enum machine_mode other_mode;
@@ -96,56 +95,56 @@ hppa_fpstore_bypass_p (out_insn, in_insn)
 #endif
 #endif
 
-static int hppa_address_cost PARAMS ((rtx));
-static bool hppa_rtx_costs PARAMS ((rtx, int, int, int *));
-static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
-static void pa_reorg PARAMS ((void));
-static void pa_combine_instructions PARAMS ((void));
-static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
-static int forward_branch_p PARAMS ((rtx));
-static int shadd_constant_p PARAMS ((int));
-static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
-static int compute_movstrsi_length PARAMS ((rtx));
-static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
-static void remove_useless_addtr_insns PARAMS ((int));
-static void store_reg PARAMS ((int, int, int));
-static void store_reg_modify PARAMS ((int, int, int));
-static void load_reg PARAMS ((int, int, int));
-static void set_reg_plus_d PARAMS ((int, int, int, int));
-static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void update_total_code_bytes PARAMS ((int));
-static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int pa_adjust_priority PARAMS ((rtx, int));
-static int pa_issue_rate PARAMS ((void));
-static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
+static int hppa_address_cost (rtx);
+static bool hppa_rtx_costs (rtx, int, int, int *);
+static inline rtx force_mode (enum machine_mode, rtx);
+static void pa_reorg (void);
+static void pa_combine_instructions (void);
+static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
+static int forward_branch_p (rtx);
+static int shadd_constant_p (int);
+static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
+static int compute_movstrsi_length (rtx);
+static bool pa_assemble_integer (rtx, unsigned int, int);
+static void remove_useless_addtr_insns (int);
+static void store_reg (int, int, int);
+static void store_reg_modify (int, int, int);
+static void load_reg (int, int, int);
+static void set_reg_plus_d (int, int, int, int);
+static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void update_total_code_bytes (int);
+static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
+static int pa_adjust_cost (rtx, rtx, rtx, int);
+static int pa_adjust_priority (rtx, int);
+static int pa_issue_rate (void);
+static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
      ATTRIBUTE_UNUSED;
-static void pa_encode_section_info PARAMS ((tree, rtx, int));
-static const char *pa_strip_name_encoding PARAMS ((const char *));
-static bool pa_function_ok_for_sibcall PARAMS ((tree, tree));
-static void pa_globalize_label PARAMS ((FILE *, const char *))
+static void pa_encode_section_info (tree, rtx, int);
+static const char *pa_strip_name_encoding (const char *);
+static bool pa_function_ok_for_sibcall (tree, tree);
+static void pa_globalize_label (FILE *, const char *)
      ATTRIBUTE_UNUSED;
-static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					    HOST_WIDE_INT, tree));
+static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+				    HOST_WIDE_INT, tree);
 #if !defined(USE_COLLECT2)
-static void pa_asm_out_constructor PARAMS ((rtx, int));
-static void pa_asm_out_destructor PARAMS ((rtx, int));
+static void pa_asm_out_constructor (rtx, int);
+static void pa_asm_out_destructor (rtx, int);
 #endif
-static void pa_init_builtins PARAMS ((void));
-static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
-static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
-static struct deferred_plabel *get_plabel PARAMS ((const char *))
+static void pa_init_builtins (void);
+static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
+static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
+static struct deferred_plabel *get_plabel (const char *)
      ATTRIBUTE_UNUSED;
-static inline void pa_file_start_level PARAMS ((void)) ATTRIBUTE_UNUSED;
-static inline void pa_file_start_space PARAMS ((int)) ATTRIBUTE_UNUSED;
-static inline void pa_file_start_file PARAMS ((int)) ATTRIBUTE_UNUSED;
-static inline void pa_file_start_mcount PARAMS ((const char*)) ATTRIBUTE_UNUSED;
-static void pa_elf_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
-static void pa_som_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
-static void pa_linux_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
-static void pa_hpux64_gas_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
-static void pa_hpux64_hpas_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
-static void output_deferred_plabels PARAMS ((void));
+static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
+static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
+static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
+static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
+static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
+static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
+static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
+static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
+static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
+static void output_deferred_plabels (void);
 
 /* Save the operands last given to a compare for use when we
    generate a scc or bcc insn.  */
@@ -168,7 +167,7 @@ const char *pa_arch_string;
    registers which were saved by the current function's prologue.  */
 static int gr_saved, fr_saved;
 
-static rtx find_addr_reg PARAMS ((rtx));
+static rtx find_addr_reg (rtx);
 
 /* Keep track of the number of bytes we have output in the CODE subspace
    during this compilation so we'll know when to emit inline long-calls.  */
@@ -257,7 +256,7 @@ static size_t n_deferred_plabels = 0;
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 void
-override_options ()
+override_options (void)
 {
   if (pa_cpu_string == NULL)
     pa_cpu_string = TARGET_SCHED_DEFAULT;
@@ -366,7 +365,7 @@ override_options ()
 }
 
 static void
-pa_init_builtins ()
+pa_init_builtins (void)
 {
 #ifdef DONT_HAVE_FPUTC_UNLOCKED
   built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
@@ -377,9 +376,7 @@ pa_init_builtins ()
 /* Return nonzero only if OP is a register of mode MODE,
    or CONST0_RTX.  */
 int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_0_operand (rtx op, enum machine_mode mode)
 {
   return (op == CONST0_RTX (mode) || register_operand (op, mode));
 }
@@ -390,9 +387,7 @@ reg_or_0_operand (op, mode)
    For 2.5 try to eliminate either call_operand_address or
    function_label_operand, they perform very similar functions.  */
 int
-call_operand_address (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_MODE (op) == word_mode
 	  && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
@@ -402,8 +397,7 @@ call_operand_address (op, mode)
    expressions will have one of a few well defined forms, so
    we need only check those forms.  */
 int
-symbolic_expression_p (x)
-     register rtx x;
+symbolic_expression_p (rtx x)
 {
 
   /* Strip off any HIGH.  */
@@ -414,9 +408,7 @@ symbolic_expression_p (x)
 }
 
 int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -437,9 +429,7 @@ symbolic_operand (op, mode)
    operand of mode MODE.  */
 
 int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
@@ -454,9 +444,7 @@ symbolic_memory_operand (op, mode)
    not symbolic.  */
 
 int
-reg_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+reg_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -471,9 +459,7 @@ reg_or_nonsymb_mem_operand (op, mode)
    that is not symbolic.  */
 
 int
-reg_or_0_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -494,9 +480,7 @@ reg_or_0_or_nonsymb_mem_operand (op, mode)
    if reload didn't find a hard register for the operand.  */
 
 int
-reg_before_reload_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+reg_before_reload_operand (rtx op, enum machine_mode mode)
 {
   /* Don't accept a SUBREG since it will need a reload.  */
   if (GET_CODE (op) == SUBREG)
@@ -516,8 +500,7 @@ reg_before_reload_operand (op, mode)
 /* Accept any constant that can be moved in one instruction into a
    general register.  */
 int
-cint_ok_for_move (intval)
-     HOST_WIDE_INT intval;
+cint_ok_for_move (HOST_WIDE_INT intval)
 {
   /* OK if ldo, ldil, or zdepi, can be used.  */
   return (CONST_OK_FOR_LETTER_P (intval, 'J')
@@ -528,9 +511,7 @@ cint_ok_for_move (intval)
 /* Accept anything that can be moved in one instruction into a general
    register.  */
 int
-move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+move_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -581,9 +562,7 @@ move_operand (op, mode)
 /* Accept REG and any CONST_INT that can be moved in one instruction into a
    general register.  */
 int
-reg_or_cint_move_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_cint_move_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -595,9 +574,7 @@ reg_or_cint_move_operand (op, mode)
 }
 
 int
-pic_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (!flag_pic)
     return 0;
@@ -616,9 +593,7 @@ pic_label_operand (op, mode)
 }
 
 int
-fp_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return reg_renumber && FP_REG_P (op);
 }
@@ -629,9 +604,7 @@ fp_reg_operand (op, mode)
    three operand arithmetic insn that accepts registers of mode MODE
    or 14-bit signed integers.  */
 int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
@@ -641,9 +614,7 @@ arith_operand (op, mode)
    three operand arithmetic insn that accepts registers of mode MODE
    or 11-bit signed integers.  */
 int
-arith11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith11_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
@@ -652,9 +623,7 @@ arith11_operand (op, mode)
 /* Return truth value of whether OP can be used as an operand in a
    adddi3 insn.  */
 int
-adddi3_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+adddi3_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT
@@ -664,9 +633,7 @@ adddi3_operand (op, mode)
 /* A constant integer suitable for use in a PRE_MODIFY memory
    reference.  */
 int
-pre_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
@@ -675,18 +642,14 @@ pre_cint_operand (op, mode)
 /* A constant integer suitable for use in a POST_MODIFY memory
    reference.  */
 int
-post_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
 }
 
 int
-arith_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_double_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_DOUBLE
@@ -701,9 +664,7 @@ arith_double_operand (op, mode)
    is an integer register.  */
 
 int
-ireg_or_int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
 	  || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
@@ -711,9 +672,7 @@ ireg_or_int5_operand (op, mode)
 
 /* Return nonzero if OP is an integer register, else return zero.  */
 int
-ireg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
 }
@@ -722,33 +681,25 @@ ireg_operand (op, mode)
    range constraining immediate operands in three-address insns.  */
 
 int
-int5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
 }
 
 int
-uint5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
 }
 
 int
-int11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
 }
 
 int
-uint32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
 #if HOST_BITS_PER_WIDE_INT > 32
   /* All allowed constants will fit a CONST_INT.  */
@@ -762,9 +713,7 @@ uint32_operand (op, mode)
 }
 
 int
-arith5_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith5_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode) || int5_operand (op, mode);
 }
@@ -773,8 +722,7 @@ arith5_operand (op, mode)
    zdepi first sign extends a 5 bit signed number to a given field
    length, then places this field anywhere in a zero.  */
 int
-zdepi_cint_p (x)
-     unsigned HOST_WIDE_INT x;
+zdepi_cint_p (unsigned HOST_WIDE_INT x)
 {
   unsigned HOST_WIDE_INT lsb_mask, t;
 
@@ -792,8 +740,7 @@ zdepi_cint_p (x)
    1....10....0
    1..10..01..1  */
 int
-and_mask_p (mask)
-     unsigned HOST_WIDE_INT mask;
+and_mask_p (unsigned HOST_WIDE_INT mask)
 {
   mask = ~mask;
   mask += mask & -mask;
@@ -802,9 +749,7 @@ and_mask_p (mask)
 
 /* True iff depi or extru can be used to compute (reg & OP).  */
 int
-and_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+and_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
@@ -812,8 +757,7 @@ and_operand (op, mode)
 
 /* True iff depi can be used to compute (reg | MASK).  */
 int
-ior_mask_p (mask)
-     unsigned HOST_WIDE_INT mask;
+ior_mask_p (unsigned HOST_WIDE_INT mask)
 {
   mask += mask & -mask;
   return (mask & (mask - 1)) == 0;
@@ -821,17 +765,13 @@ ior_mask_p (mask)
 
 /* True iff depi can be used to compute (reg | OP).  */
 int
-ior_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
 }
 
 int
-lhs_lshift_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+lhs_lshift_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
 }
@@ -840,9 +780,7 @@ lhs_lshift_operand (op, mode)
    Such values can be the left hand side x in (x << r), using the zvdepi
    instruction.  */
 int
-lhs_lshift_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   unsigned HOST_WIDE_INT x;
   if (GET_CODE (op) != CONST_INT)
@@ -852,17 +790,13 @@ lhs_lshift_cint_operand (op, mode)
 }
 
 int
-arith32_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith32_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
 }
 
 int
-pc_or_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
 }
@@ -873,9 +807,7 @@ pc_or_label_operand (op, mode)
    than one register, we lose.  */
 
 rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig, reg;
-     enum machine_mode mode;
+legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
 {
   rtx pic_ref = orig;
 
@@ -997,9 +929,8 @@ legitimize_pic_address (orig, mode, reg)
    a register.  */
 
 rtx
-hppa_legitimize_address (x, oldx, mode)
-     rtx x, oldx ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
+hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
+			 enum machine_mode mode)
 {
   rtx orig = x;
 
@@ -1347,8 +1278,7 @@ hppa_legitimize_address (x, oldx, mode)
    as GO_IF_LEGITIMATE_ADDRESS.  */
 
 static int
-hppa_address_cost (X)
-     rtx X;
+hppa_address_cost (rtx X)
 {
   switch (GET_CODE (X))
     {
@@ -1368,10 +1298,7 @@ hppa_address_cost (X)
    scanned.  In either case, *TOTAL contains the cost result.  */
 
 static bool
-hppa_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code;
-     int *total;
+hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   switch (code)
     {
@@ -1447,9 +1374,7 @@ hppa_rtx_costs (x, code, outer_code, total)
 /* Ensure mode of ORIG, a REG rtx, is MODE.  Returns either ORIG or a
    new rtx with the correct mode.  */
 static inline rtx
-force_mode (mode, orig)
-     enum machine_mode mode;
-     rtx orig;
+force_mode (enum machine_mode mode, rtx orig)
 {
   if (mode == GET_MODE (orig))
     return orig;
@@ -1471,10 +1396,7 @@ force_mode (mode, orig)
    of SCRATCH_REG in the proper mode.  */
 
 int
-emit_move_sequence (operands, mode, scratch_reg)
-     rtx *operands;
-     enum machine_mode mode;
-     rtx scratch_reg;
+emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
 {
   register rtx operand0 = operands[0];
   register rtx operand1 = operands[1];
@@ -1966,8 +1888,7 @@ emit_move_sequence (operands, mode, scratch_reg)
    it will need a link/runtime reloc).  */
 
 int
-reloc_needed (exp)
-     tree exp;
+reloc_needed (tree exp)
 {
   int reloc = 0;
 
@@ -2011,9 +1932,7 @@ reloc_needed (exp)
    will be true.  */
 
 int
-read_only_operand (operand, mode)
-     rtx operand;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (operand) == CONST)
     operand = XEXP (XEXP (operand, 0), 0);
@@ -2034,8 +1953,7 @@ read_only_operand (operand, mode)
 /* Return the best assembler insn template
    for moving operands[1] into operands[0] as a fullword.   */
 const char *
-singlemove_string (operands)
-     rtx *operands;
+singlemove_string (rtx *operands)
 {
   HOST_WIDE_INT intval;
 
@@ -2080,9 +1998,7 @@ singlemove_string (operands)
    useful for copying IMM to a register using the zdepi
    instructions.  Store the immediate value to insert in OP[0].  */
 static void
-compute_zdepwi_operands (imm, op)
-     unsigned HOST_WIDE_INT imm;
-     unsigned *op;
+compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
 {
   int lsb, len;
 
@@ -2119,9 +2035,7 @@ compute_zdepwi_operands (imm, op)
    useful for copying IMM to a register using the depdi,z
    instructions.  Store the immediate value to insert in OP[0].  */
 void
-compute_zdepdi_operands (imm, op)
-     unsigned HOST_WIDE_INT imm;
-     unsigned *op;
+compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
 {
   HOST_WIDE_INT lsb, len;
 
@@ -2159,8 +2073,7 @@ compute_zdepdi_operands (imm, op)
    with operands OPERANDS.  */
 
 const char *
-output_move_double (operands)
-     rtx *operands;
+output_move_double (rtx *operands)
 {
   enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
   rtx latehalf[2];
@@ -2435,8 +2348,7 @@ output_move_double (operands)
 }
 
 const char *
-output_fp_move_double (operands)
-     rtx *operands;
+output_fp_move_double (rtx *operands)
 {
   if (FP_REG_P (operands[0]))
     {
@@ -2474,8 +2386,7 @@ output_fp_move_double (operands)
    ADDR can be effectively incremented by incrementing REG.  */
 
 static rtx
-find_addr_reg (addr)
-     rtx addr;
+find_addr_reg (rtx addr)
 {
   while (GET_CODE (addr) == PLUS)
     {
@@ -2506,9 +2417,7 @@ find_addr_reg (addr)
    OPERANDS[6] is another temporary register.   */
 
 const char *
-output_block_move (operands, size_is_constant)
-     rtx *operands;
-     int size_is_constant ATTRIBUTE_UNUSED;
+output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
 {
   int align = INTVAL (operands[5]);
   unsigned long n_bytes = INTVAL (operands[4]);
@@ -2607,8 +2516,7 @@ output_block_move (operands, size_is_constant)
    count insns rather than emit them.  */
 
 static int
-compute_movstrsi_length (insn)
-     rtx insn;
+compute_movstrsi_length (rtx insn)
 {
   rtx pat = PATTERN (insn);
   unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
@@ -2639,8 +2547,7 @@ compute_movstrsi_length (insn)
 
 
 const char *
-output_and (operands)
-     rtx *operands;
+output_and (rtx *operands)
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
     {
@@ -2692,8 +2599,7 @@ output_and (operands)
 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
    storing the result in operands[0].  */
 const char *
-output_64bit_and (operands)
-     rtx *operands;
+output_64bit_and (rtx *operands)
 {
   if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
     {
@@ -2743,8 +2649,7 @@ output_64bit_and (operands)
 }
 
 const char *
-output_ior (operands)
-     rtx *operands;
+output_ior (rtx *operands)
 {
   unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
   int bs0, bs1, p, len;
@@ -2774,8 +2679,7 @@ output_ior (operands)
 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
    storing the result in operands[0].  */
 const char *
-output_64bit_ior (operands)
-     rtx *operands;
+output_64bit_ior (rtx *operands)
 {
   unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
   int bs0, bs1, p, len;
@@ -2808,10 +2712,7 @@ output_64bit_ior (operands)
    be preceded by P%.  */
 
 static bool
-pa_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if (size == UNITS_PER_WORD && aligned_p
       && function_label_operand (x, VOIDmode))
@@ -2826,10 +2727,7 @@ pa_assemble_integer (x, size, aligned_p)
 
 /* Output an ascii string.  */
 void
-output_ascii (file, p, size)
-     FILE *file;
-     const char *p;
-     int size;
+output_ascii (FILE *file, const char *p, int size)
 {
   int i;
   int chars_output;
@@ -2896,8 +2794,7 @@ output_ascii (file, p, size)
    when there's a 1:1 correspondence between fcmp and ftest/fbranch
    instructions.  */
 static void
-remove_useless_addtr_insns (check_notes)
-     int check_notes;
+remove_useless_addtr_insns (int check_notes)
 {
   rtx insn;
   static int pass = 0;
@@ -3108,8 +3005,7 @@ static int local_fsize, save_fregs;
    in %r1.  There is code in expand_hppa_{prologue,epilogue} that knows this.*/
 
 static void
-store_reg (reg, disp, base)
-     int reg, disp, base;
+store_reg (int reg, int disp, int base)
 {
   rtx insn, dest, src, basereg;
 
@@ -3149,8 +3045,7 @@ store_reg (reg, disp, base)
    add MOD to BASE.  MOD must be <= 8k.  */
 
 static void
-store_reg_modify (base, reg, mod)
-     int base, reg, mod;
+store_reg_modify (int base, int reg, int mod)
 {
   rtx insn, basereg, srcreg, delta;
 
@@ -3197,8 +3092,7 @@ store_reg_modify (base, reg, mod)
    There is code in expand_hppa_{prologue,epilogue} that knows about this.  */
 
 static void
-set_reg_plus_d (reg, base, disp, note)
-     int reg, base, disp, note;
+set_reg_plus_d (int reg, int base, int disp, int note)
 {
   rtx insn;
 
@@ -3225,9 +3119,7 @@ set_reg_plus_d (reg, base, disp, note)
 }
 
 int
-compute_frame_size (size, fregs_live)
-     int size;
-     int *fregs_live;
+compute_frame_size (int size, int *fregs_live)
 {
   int freg_saved = 0;
   int i, j;
@@ -3320,9 +3212,7 @@ compute_frame_size (size, fregs_live)
    to do this is made in regclass.c.  */
 
 static void
-pa_output_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   /* The function's label and associated .PROC must never be
      separated and must be output *after* any profiling declarations
@@ -3371,7 +3261,7 @@ pa_output_function_prologue (file, size)
 }
 
 void
-hppa_expand_prologue ()
+hppa_expand_prologue (void)
 {
   int merge_sp_adjust_with_store = 0;
   int size = get_frame_size ();
@@ -3664,8 +3554,7 @@ hppa_expand_prologue ()
    Handle case where DISP > 8k by using the add_high_const patterns.  */
 
 static void
-load_reg (reg, disp, base)
-     int reg, disp, base;
+load_reg (int reg, int disp, int base)
 {
   rtx src, dest, basereg;
 
@@ -3690,11 +3579,10 @@ load_reg (reg, disp, base)
 /* Update the total code bytes output to the text section.  */
 
 static void
-update_total_code_bytes (nbytes)
-     int nbytes;
+update_total_code_bytes (int nbytes)
 {
   if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
-      && in_text_section ())
+      && !IN_NAMED_SECTION_P (cfun->decl))
     {
       if (INSN_ADDRESSES_SET_P ())
 	{
@@ -3720,9 +3608,7 @@ update_total_code_bytes (nbytes)
    adjustments before returning.  */
 
 static void
-pa_output_function_epilogue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   rtx insn = get_last_insn ();
 
@@ -3770,7 +3656,7 @@ pa_output_function_epilogue (file, size)
 }
 
 void
-hppa_expand_epilogue ()
+hppa_expand_epilogue (void)
 {
   rtx tmpreg;
   int offset, i;
@@ -3946,14 +3832,13 @@ hppa_expand_epilogue ()
 }
 
 rtx
-hppa_pic_save_rtx ()
+hppa_pic_save_rtx (void)
 {
   return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
 }
 
 void
-hppa_profile_hook (label_no)
-     int label_no;
+hppa_profile_hook (int label_no)
 {
   rtx begin_label_rtx, call_insn;
   char begin_label_name[16];
@@ -4039,9 +3924,7 @@ hppa_profile_hook (label_no)
    return location is in a shared library.  */
 
 rtx
-return_addr_rtx (count, frameaddr)
-     int count;
-     rtx frameaddr;
+return_addr_rtx (int count, rtx frameaddr)
 {
   rtx label;
   rtx rp;
@@ -4120,7 +4003,7 @@ return_addr_rtx (count, frameaddr)
    It's only valid if %r2 hasn't been saved into the caller's frame
    (we're not profiling and %r2 isn't live anywhere).  */
 int
-hppa_can_use_return_insn_p ()
+hppa_can_use_return_insn_p (void)
 {
   return (reload_completed
 	  && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
@@ -4129,9 +4012,7 @@ hppa_can_use_return_insn_p ()
 }
 
 void
-emit_bcond_fp (code, operand0)
-     enum rtx_code code;
-     rtx operand0;
+emit_bcond_fp (enum rtx_code code, rtx operand0)
 {
   emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
 			       gen_rtx_IF_THEN_ELSE (VOIDmode,
@@ -4145,9 +4026,7 @@ emit_bcond_fp (code, operand0)
 }
 
 rtx
-gen_cmp_fp (code, operand0, operand1)
-     enum rtx_code code;
-     rtx operand0, operand1;
+gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
 {
   return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
 		      gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
@@ -4157,11 +4036,7 @@ gen_cmp_fp (code, operand0, operand1)
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
 static int
-pa_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
+pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 {
   enum attr_type attr_type;
 
@@ -4349,9 +4224,7 @@ pa_adjust_cost (insn, link, dep_insn, cost)
 /* Adjust scheduling priorities.  We use this to try and keep addil
    and the next use of %r1 close together.  */
 static int
-pa_adjust_priority (insn, priority)
-     rtx insn;
-     int priority;
+pa_adjust_priority (rtx insn, int priority)
 {
   rtx set = single_set (insn);
   rtx src, dest;
@@ -4383,7 +4256,7 @@ pa_adjust_priority (insn, priority)
    The 7XXX processors can issue two insns at a time.
    The 8000 can issue 4 insns at a time.  */
 static int
-pa_issue_rate ()
+pa_issue_rate (void)
 {
   switch (pa_cpu)
     {
@@ -4411,29 +4284,13 @@ pa_issue_rate ()
    Also compute the length of an inline block move here as it is too
    complicated to express as a length attribute in pa.md.  */
 int
-pa_adjust_insn_length (insn, length)
-    rtx insn;
-    int length;
+pa_adjust_insn_length (rtx insn, int length)
 {
   rtx pat = PATTERN (insn);
 
-  /* Call insns which are *not* indirect and have unfilled delay slots.  */
-  if (GET_CODE (insn) == CALL_INSN)
-    {
-
-      if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
-	  && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
-	return 4;
-      else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
-	       && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
-		  == SYMBOL_REF)
-	return 4;
-      else
-	return 0;
-    }
-  /* Jumps inside switch tables which have unfilled delay slots
-     also need adjustment.  */
-  else if (GET_CODE (insn) == JUMP_INSN
+  /* Jumps inside switch tables which have unfilled delay slots need
+     adjustment.  */
+  if (GET_CODE (insn) == JUMP_INSN
 	   && simplejump_p (insn)
 	   && GET_MODE (insn) == SImode)
     return 4;
@@ -4486,10 +4343,7 @@ pa_adjust_insn_length (insn, length)
    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
 
 void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
+print_operand (FILE *file, rtx x, int code)
 {
   switch (code)
     {
@@ -4854,10 +4708,7 @@ print_operand (file, x, code)
 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF.  */
 
 void
-output_global_address (file, x, round_constant)
-     FILE *file;
-     rtx x;
-     int round_constant;
+output_global_address (FILE *file, rtx x, int round_constant)
 {
 
   /* Imagine  (high (const (plus ...))).  */
@@ -4935,7 +4786,7 @@ output_global_address (file, x, round_constant)
    There are several possible versions.  */
 #define aputs(x) fputs(x, asm_out_file)
 static inline void
-pa_file_start_level ()
+pa_file_start_level (void)
 {
   if (TARGET_64BIT)
     aputs ("\t.LEVEL 2.0w\n");
@@ -4948,8 +4799,7 @@ pa_file_start_level ()
 }
 
 static inline void
-pa_file_start_space (sortspace)
-     int sortspace;
+pa_file_start_space (int sortspace)
 {
   aputs ("\t.SPACE $PRIVATE$");
   if (sortspace)
@@ -4964,8 +4814,7 @@ pa_file_start_space (sortspace)
 }
 
 static inline void
-pa_file_start_file (want_version)
-     int want_version;
+pa_file_start_file (int want_version)
 {
   if (write_symbols != NO_DEBUG)
     {
@@ -4976,15 +4825,14 @@ pa_file_start_file (want_version)
 }
 
 static inline void
-pa_file_start_mcount (aswhat)
-     const char *aswhat;
+pa_file_start_mcount (const char *aswhat)
 {
   if (profile_flag)
     fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
 }
   
 static void
-pa_elf_file_start ()
+pa_elf_file_start (void)
 {
   pa_file_start_level ();
   pa_file_start_mcount ("ENTRY");
@@ -4992,7 +4840,7 @@ pa_elf_file_start ()
 }
 
 static void
-pa_som_file_start ()
+pa_som_file_start (void)
 {
   pa_file_start_level ();
   pa_file_start_space (0);
@@ -5003,7 +4851,7 @@ pa_som_file_start ()
 }
 
 static void
-pa_linux_file_start ()
+pa_linux_file_start (void)
 {
   pa_file_start_file (1);
   pa_file_start_level ();
@@ -5011,7 +4859,7 @@ pa_linux_file_start ()
 }
 
 static void
-pa_hpux64_gas_file_start ()
+pa_hpux64_gas_file_start (void)
 {
   pa_file_start_level ();
 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
@@ -5022,7 +4870,7 @@ pa_hpux64_gas_file_start ()
 }
 
 static void
-pa_hpux64_hpas_file_start ()
+pa_hpux64_hpas_file_start (void)
 {
   pa_file_start_level ();
   pa_file_start_space (1);
@@ -5032,8 +4880,7 @@ pa_hpux64_hpas_file_start ()
 #undef aputs
 
 static struct deferred_plabel *
-get_plabel (fname)
-     const char *fname;
+get_plabel (const char *fname)
 {
   size_t i;
 
@@ -5073,7 +4920,7 @@ get_plabel (fname)
 }
 
 static void
-output_deferred_plabels ()
+output_deferred_plabels (void)
 {
   size_t i;
   /* If we have deferred plabels, then we need to switch into the data
@@ -5099,15 +4946,14 @@ output_deferred_plabels ()
    Keep track of which ones we have used.  */
 
 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
-static void import_milli			PARAMS ((enum millicodes));
+static void import_milli (enum millicodes);
 static char imported[(int) end1000];
 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
 static const char import_string[] = ".IMPORT $$....,MILLICODE";
 #define MILLI_START 10
 
 static void
-import_milli (code)
-     enum millicodes code;
+import_milli (enum millicodes code)
 {
   char str[sizeof (import_string)];
 
@@ -5124,9 +4970,7 @@ import_milli (code)
    the proper registers.  */
 
 const char *
-output_mul_insn (unsignedp, insn)
-     int unsignedp ATTRIBUTE_UNUSED;
-     rtx insn;
+output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
 {
   import_milli (mulI);
   return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
@@ -5145,9 +4989,7 @@ static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
 static int div_milli[16][2];
 
 int
-div_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+div_operand (rtx op, enum machine_mode mode)
 {
   return (mode == SImode
 	  && ((GET_CODE (op) == REG && REGNO (op) == 25)
@@ -5156,9 +4998,7 @@ div_operand (op, mode)
 }
 
 int
-emit_hpdiv_const (operands, unsignedp)
-     rtx *operands;
-     int unsignedp;
+emit_hpdiv_const (rtx *operands, int unsignedp)
 {
   if (GET_CODE (operands[2]) == CONST_INT
       && INTVAL (operands[2]) > 0
@@ -5188,10 +5028,7 @@ emit_hpdiv_const (operands, unsignedp)
 }
 
 const char *
-output_div_insn (operands, unsignedp, insn)
-     rtx *operands;
-     int unsignedp;
-     rtx insn;
+output_div_insn (rtx *operands, int unsignedp, rtx insn)
 {
   int divisor;
 
@@ -5245,9 +5082,7 @@ output_div_insn (operands, unsignedp, insn)
 /* Output a $$rem millicode to do mod.  */
 
 const char *
-output_mod_insn (unsignedp, insn)
-     int unsignedp;
-     rtx insn;
+output_mod_insn (int unsignedp, rtx insn)
 {
   if (unsignedp)
     {
@@ -5264,8 +5099,7 @@ output_mod_insn (unsignedp, insn)
 }
 
 void
-output_arg_descriptor (call_insn)
-     rtx call_insn;
+output_arg_descriptor (rtx call_insn)
 {
   const char *arg_regs[4];
   enum machine_mode arg_mode;
@@ -5349,10 +5183,7 @@ output_arg_descriptor (call_insn)
    It might be worthwhile to try and make this a leaf function too.  */
 
 enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx in;
+secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
 {
   int regno, is_symbolic;
 
@@ -5440,9 +5271,7 @@ secondary_reload_class (class, mode, in)
 }
 
 enum direction
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
+function_arg_padding (enum machine_mode mode, tree type)
 {
   if (mode == BLKmode
       || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
@@ -5481,7 +5310,7 @@ function_arg_padding (mode, type)
    va_list.  A pointer to this constructor is returned.  */
 
 struct rtx_def *
-hppa_builtin_saveregs ()
+hppa_builtin_saveregs (void)
 {
   rtx offset, dest;
   tree fntype = TREE_TYPE (current_function_decl);
@@ -5550,17 +5379,14 @@ hppa_builtin_saveregs ()
 }
 
 void
-hppa_va_start (valist, nextarg)
-     tree valist;
-     rtx nextarg;
+hppa_va_start (tree valist, rtx nextarg)
 {
   nextarg = expand_builtin_saveregs ();
   std_expand_builtin_va_start (valist, nextarg);
 }
 
 rtx
-hppa_va_arg (valist, type)
-     tree valist, type;
+hppa_va_arg (tree valist, tree type)
 {
   HOST_WIDE_INT size = int_size_in_bytes (type);
   HOST_WIDE_INT ofs;
@@ -5668,10 +5494,7 @@ hppa_va_arg (valist, type)
    parameters.  */
 
 const char *
-output_cbranch (operands, nullify, length, negated, insn)
-     rtx *operands;
-     int nullify, length, negated;
-     rtx insn;
+output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
 {
   static char buf[100];
   int useskip = 0;
@@ -5856,8 +5679,7 @@ output_cbranch (operands, nullify, length, negated, insn)
    maximum range of a simple branch instruction.  */
 
 const char *
-output_lbranch (dest, insn)
-     rtx dest, insn;
+output_lbranch (rtx dest, rtx insn)
 {
   rtx xoperands[2];
  
@@ -5975,11 +5797,8 @@ output_lbranch (dest, insn)
    above.  it returns the appropriate output template to emit the branch.  */
 
 const char *
-output_bb (operands, nullify, length, negated, insn, which)
-     rtx *operands ATTRIBUTE_UNUSED;
-     int nullify, length, negated;
-     rtx insn;
-     int which;
+output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
+	   int negated, rtx insn, int which)
 {
   static char buf[100];
   int useskip = 0;
@@ -6123,11 +5942,8 @@ output_bb (operands, nullify, length, negated, insn, which)
    branch.  */
 
 const char *
-output_bvb (operands, nullify, length, negated, insn, which)
-     rtx *operands ATTRIBUTE_UNUSED;
-     int nullify, length, negated;
-     rtx insn;
-     int which;
+output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
+	    int negated, rtx insn, int which)
 {
   static char buf[100];
   int useskip = 0;
@@ -6269,10 +6085,7 @@ output_bvb (operands, nullify, length, negated, insn, which)
    Note it may perform some output operations on its own before
    returning the final output string.  */
 const char *
-output_dbra (operands, insn, which_alternative)
-     rtx *operands;
-     rtx insn;
-     int which_alternative;
+output_dbra (rtx *operands, rtx insn, int which_alternative)
 {
 
   /* A conditional branch to the following instruction (eg the delay slot) is
@@ -6375,11 +6188,8 @@ output_dbra (operands, insn, which_alternative)
    Note it may perform some output operations on its own before
    returning the final output string.  */
 const char *
-output_movb (operands, insn, which_alternative, reverse_comparison)
-     rtx *operands;
-     rtx insn;
-     int which_alternative;
-     int reverse_comparison;
+output_movb (rtx *operands, rtx insn, int which_alternative,
+	     int reverse_comparison)
 {
 
   /* A conditional branch to the following instruction (eg the delay slot) is
@@ -6485,8 +6295,7 @@ output_movb (operands, insn, which_alternative, reverse_comparison)
 
 /* Copy any FP arguments in INSN into integer registers.  */
 static void
-copy_fp_args (insn)
-     rtx insn;
+copy_fp_args (rtx insn)
 {
   rtx link;
   rtx xoperands[2];
@@ -6529,8 +6338,7 @@ copy_fp_args (insn)
 
 /* Compute length of the FP argument copy sequence for INSN.  */
 static int
-length_fp_args (insn)
-     rtx insn;
+length_fp_args (rtx insn)
 {
   int length = 0;
   rtx link;
@@ -6567,11 +6375,10 @@ length_fp_args (insn)
    over estimate the length than to under estimate it.  */
 
 int
-attr_length_millicode_call (insn)
-     rtx insn;
+attr_length_millicode_call (rtx insn)
 {
   unsigned long distance = -1;
-  unsigned long total = in_text_section () ? total_code_bytes : 0;
+  unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
 
   if (INSN_ADDRESSES_SET_P ())
     {
@@ -6607,9 +6414,7 @@ attr_length_millicode_call (insn)
    CALL_DEST is the routine we are calling.  */
 
 const char *
-output_millicode_call (insn, call_dest)
-     rtx insn;
-     rtx call_dest;
+output_millicode_call (rtx insn, rtx call_dest)
 {
   int attr_length = get_attr_length (insn);
   int seq_length = dbr_sequence_length ();
@@ -6758,73 +6563,93 @@ output_millicode_call (insn, call_dest)
 
 /* Return the attribute length of the call instruction INSN.  The SIBCALL
    flag indicates whether INSN is a regular call or a sibling call.  The
-   length must match the code generated by output_call.  We include the delay
-   slot in the returned length as it is better to over estimate the length
-   than to under estimate it.  */
+   length returned must be longer than the code actually generated by
+   output_call.  Since branch shortening is done before delay branch
+   sequencing, there is no way to determine whether or not the delay
+   slot will be filled during branch shortening.  Even when the delay
+   slot is filled, we may have to add a nop if the delay slot contains
+   a branch that can't reach its target.  Thus, we always have to include
+   the delay slot in the length estimate.  This used to be done in
+   pa_adjust_insn_length but we do it here now as some sequences always
+   fill the delay slot and we can save four bytes in the estimate for
+   these sequences.  */
 
 int
-attr_length_call (insn, sibcall)
-     rtx insn;
-     int sibcall;
+attr_length_call (rtx insn, int sibcall)
 {
+  int local_call;
+  rtx call_dest;
+  tree call_decl;
+  int length = 0;
+  rtx pat = PATTERN (insn);
   unsigned long distance = -1;
-  unsigned long total = in_text_section ()? total_code_bytes : 0;
 
   if (INSN_ADDRESSES_SET_P ())
     {
+      unsigned long total;
+
+      total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
       distance = (total + insn_current_reference_address (insn));
       if (distance < total)
 	distance = -1;
     }
 
-  if (TARGET_64BIT)
-    {
-      if (!TARGET_LONG_CALLS
-	  && ((!sibcall && distance < 7600000) || distance < 240000))
-	return 8;
-
-      return (sibcall ? 28 : 24);
-    }
+  /* Determine if this is a local call.  */
+  if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
+    call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
   else
-    {
-      if (!TARGET_LONG_CALLS
-	  && ((TARGET_PA_20 && !sibcall && distance < 7600000)
-	      || distance < 240000))
-	return 8;
+    call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
 
-      if (TARGET_LONG_ABS_CALL && !flag_pic)
-	return 12;
+  call_decl = SYMBOL_REF_DECL (call_dest);
+  local_call = call_decl && (*targetm.binds_local_p) (call_decl);
 
-      if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
-	  || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
-	{
-	  if (TARGET_PA_20)
-	    return 20;
+  /* pc-relative branch.  */
+  if (!TARGET_LONG_CALLS
+      && ((TARGET_PA_20 && !sibcall && distance < 7600000)
+	  || distance < 240000))
+    length += 8;
 
-	  return 28;
-	}
-      else
-	{
-	  int length = 0;
+  /* 64-bit plabel sequence.  */
+  else if (TARGET_64BIT && !local_call)
+    length += sibcall ? 28 : 24;
 
-	  if (TARGET_SOM)
-	    length += length_fp_args (insn);
+  /* non-pic long absolute branch sequence.  */
+  else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
+    length += 12;
 
-	  if (flag_pic)
-	    length += 4;
+  /* long pc-relative branch sequence.  */
+  else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
+	   || (TARGET_64BIT && !TARGET_GAS)
+	   || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
+    {
+      length += 20;
 
-	  if (TARGET_PA_20)
-	    return (length + 32);
+      if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
+	length += 8;
+    }
 
-	  if (!TARGET_NO_SPACE_REGS)
-	    length += 8;
+  /* 32-bit plabel sequence.  */
+  else
+    {
+      length += 32;
+
+      if (TARGET_SOM)
+	length += length_fp_args (insn);
+
+      if (flag_pic)
+	length += 4;
 
+      if (!TARGET_PA_20)
+	{
 	  if (!sibcall)
 	    length += 8;
 
-	  return (length + 32);
+	  if (!TARGET_NO_SPACE_REGS)
+	    length += 8;
 	}
     }
+
+  return length;
 }
 
 /* INSN is a function call.  It may have an unconditional jump
@@ -6833,16 +6658,13 @@ attr_length_call (insn, sibcall)
    CALL_DEST is the routine we are calling.  */
 
 const char *
-output_call (insn, call_dest, sibcall)
-     rtx insn;
-     rtx call_dest;
-     int sibcall;
+output_call (rtx insn, rtx call_dest, int sibcall)
 {
   int delay_insn_deleted = 0;
   int delay_slot_filled = 0;
   int seq_length = dbr_sequence_length ();
   tree call_decl = SYMBOL_REF_DECL (call_dest);
-  int local_call = call_decl && !TREE_PUBLIC (call_decl);
+  int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
   rtx xoperands[2];
 
   xoperands[0] = call_dest;
@@ -7077,7 +6899,7 @@ output_call (insn, call_dest, sibcall)
 	}
     }
 
-  if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
+  if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
     output_asm_insn ("nop", xoperands);
 
   /* We are done if there isn't a jump in the delay slot.  */
@@ -7129,11 +6951,10 @@ output_call (insn, call_dest, sibcall)
    the sequence itself.  */
 
 int
-attr_length_indirect_call (insn)
-     rtx insn;
+attr_length_indirect_call (rtx insn)
 {
   unsigned long distance = -1;
-  unsigned long total = in_text_section () ? total_code_bytes : 0;
+  unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
 
   if (INSN_ADDRESSES_SET_P ())
     {
@@ -7161,9 +6982,7 @@ attr_length_indirect_call (insn)
 }
 
 const char *
-output_indirect_call (insn, call_dest)
-     rtx insn;
-     rtx call_dest;
+output_indirect_call (rtx insn, rtx call_dest)
 {
   rtx xoperands[1];
 
@@ -7225,8 +7044,7 @@ output_indirect_call (insn, call_dest)
    within the same translation unit.  */
 
 int
-attr_length_save_restore_dltp (insn)
-     rtx insn;
+attr_length_save_restore_dltp (rtx insn)
 {
   if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
     return 0;
@@ -7240,8 +7058,7 @@ attr_length_save_restore_dltp (insn)
    space), and special magic is needed to construct their address.  */
 
 void
-hppa_encode_label (sym)
-     rtx sym;
+hppa_encode_label (rtx sym)
 {
   const char *str = XSTR (sym, 0);
   int len = strlen (str) + 1;
@@ -7255,10 +7072,7 @@ hppa_encode_label (sym)
 }
 
 static void
-pa_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+pa_encode_section_info (tree decl, rtx rtl, int first)
 {
   if (first && TEXT_SPACE_P (decl))
     {
@@ -7271,8 +7085,7 @@ pa_encode_section_info (decl, rtl, first)
 /* This is sort of inverse to pa_encode_section_info.  */
 
 static const char *
-pa_strip_name_encoding (str)
-     const char *str;
+pa_strip_name_encoding (const char *str)
 {
   str += (*str == '@');
   str += (*str == '*');
@@ -7280,9 +7093,7 @@ pa_strip_name_encoding (str)
 }
 
 int
-function_label_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
 }
@@ -7291,8 +7102,7 @@ function_label_operand (op, mode)
    with a constant.  Used to keep certain patterns from matching
    during instruction combination.  */
 int
-is_function_label_plus_const (op)
-     rtx op;
+is_function_label_plus_const (rtx op)
 {
   /* Strip off any CONST.  */
   if (GET_CODE (op) == CONST)
@@ -7306,12 +7116,9 @@ is_function_label_plus_const (op)
 /* Output assembly code for a thunk to FUNCTION.  */
 
 static void
-pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk_fndecl;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
-     tree function;
+pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
+			HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+			tree function)
 {
   const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
   const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
@@ -7465,7 +7272,7 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
 	    }
 	  else
 	    {
-	      fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
+	      fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
 	      fprintf (file, "\tmtsp %%r21,%%sr0\n");
 	      fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
 	      nbytes += 44;
@@ -7572,9 +7379,7 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
    It is safe to perform a sibcall optimization when the target function
    will never return.  */
 static bool
-pa_function_ok_for_sibcall (decl, exp)
-     tree decl;
-     tree exp ATTRIBUTE_UNUSED;
+pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
   /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
      single subspace mode and the call is not indirect.  As far as I know,
@@ -7601,8 +7406,7 @@ pa_function_ok_for_sibcall (decl, exp)
 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
    use in fmpyadd instructions.  */
 int
-fmpyaddoperands (operands)
-     rtx *operands;
+fmpyaddoperands (rtx *operands)
 {
   enum machine_mode mode = GET_MODE (operands[0]);
 
@@ -7659,9 +7463,7 @@ fmpyaddoperands (operands)
 
 #if !defined(USE_COLLECT2)
 static void
-pa_asm_out_constructor (symbol, priority)
-     rtx symbol;
-     int priority;
+pa_asm_out_constructor (rtx symbol, int priority)
 {
   if (!function_label_operand (symbol, VOIDmode))
     hppa_encode_label (symbol);
@@ -7678,9 +7480,7 @@ pa_asm_out_constructor (symbol, priority)
 }
 
 static void
-pa_asm_out_destructor (symbol, priority)
-     rtx symbol;
-     int priority;
+pa_asm_out_destructor (rtx symbol, int priority)
 {
   if (!function_label_operand (symbol, VOIDmode))
     hppa_encode_label (symbol);
@@ -7700,8 +7500,7 @@ pa_asm_out_destructor (symbol, priority)
 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
    use in fmpysub instructions.  */
 int
-fmpysuboperands (operands)
-     rtx *operands;
+fmpysuboperands (rtx *operands)
 {
   enum machine_mode mode = GET_MODE (operands[0]);
 
@@ -7755,9 +7554,7 @@ fmpysuboperands (operands)
 }
 
 int
-plus_xor_ior_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
 	  || GET_CODE (op) == IOR);
@@ -7766,8 +7563,7 @@ plus_xor_ior_operator (op, mode)
 /* Return 1 if the given constant is 2, 4, or 8.  These are the valid
    constants for shadd instructions.  */
 static int
-shadd_constant_p (val)
-     int val;
+shadd_constant_p (int val)
 {
   if (val == 2 || val == 4 || val == 8)
     return 1;
@@ -7778,9 +7574,7 @@ shadd_constant_p (val)
 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8.  These are
    the valid constant for shadd instructions.  */
 int
-shadd_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
 }
@@ -7788,9 +7582,7 @@ shadd_operand (op, mode)
 /* Return 1 if OP is valid as a base register in a reg + reg address.  */
 
 int
-basereg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+basereg_operand (rtx op, enum machine_mode mode)
 {
   /* cse will create some unscaled indexed addresses, however; it
      generally isn't a win on the PA, so avoid creating unscaled
@@ -7818,9 +7610,7 @@ basereg_operand (op, mode)
 /* Return 1 if this operand is anything other than a hard register.  */
 
 int
-non_hard_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
 }
@@ -7828,8 +7618,7 @@ non_hard_reg_operand (op, mode)
 /* Return 1 if INSN branches forward.  Should be using insn_addresses
    to avoid walking through all the insns...  */
 static int
-forward_branch_p (insn)
-     rtx insn;
+forward_branch_p (rtx insn)
 {
   rtx label = JUMP_LABEL (insn);
 
@@ -7846,18 +7635,14 @@ forward_branch_p (insn)
 
 /* Return 1 if OP is an equality comparison, else return 0.  */
 int
-eq_neq_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
 }
 
 /* Return 1 if OP is an operator suitable for use in a movb instruction.  */
 int
-movb_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == EQ || GET_CODE (op) == NE
 	  || GET_CODE (op) == LT || GET_CODE (op) == GE);
@@ -7865,8 +7650,7 @@ movb_comparison_operator (op, mode)
 
 /* Return 1 if INSN is in the delay slot of a call instruction.  */
 int
-jump_in_call_delay (insn)
-     rtx insn;
+jump_in_call_delay (rtx insn)
 {
 
   if (GET_CODE (insn) != JUMP_INSN)
@@ -7889,9 +7673,7 @@ jump_in_call_delay (insn)
 /* Output an unconditional move and branch insn.  */
 
 const char *
-output_parallel_movb (operands, length)
-     rtx *operands;
-     int length;
+output_parallel_movb (rtx *operands, int length)
 {
   /* These are the cases in which we win.  */
   if (length == 4)
@@ -7920,9 +7702,7 @@ output_parallel_movb (operands, length)
 /* Output an unconditional add and branch insn.  */
 
 const char *
-output_parallel_addb (operands, length)
-     rtx *operands;
-     int length;
+output_parallel_addb (rtx *operands, int length)
 {
   /* To make life easy we want operand0 to be the shared input/output
      operand and operand1 to be the readonly operand.  */
@@ -7953,8 +7733,7 @@ output_parallel_addb (operands, length)
    the delay slot of the call.  */
 
 int
-following_call (insn)
-     rtx insn;
+following_call (rtx insn)
 {
   if (! TARGET_JUMP_IN_DELAY)
     return 0;
@@ -8012,7 +7791,7 @@ following_call (insn)
    when using GAS (allows for better link time optimizations).  */
 
 static void
-pa_reorg ()
+pa_reorg (void)
 {
   rtx insn;
 
@@ -8183,7 +7962,7 @@ pa_reorg ()
       branch length restrictions.  */
 
 static void
-pa_combine_instructions ()
+pa_combine_instructions (void)
 {
   rtx anchor, new;
 
@@ -8379,10 +8158,8 @@ pa_combine_instructions ()
 }
 
 static int
-pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
-     rtx new, anchor, floater;
-     int reversed;
-     rtx dest, src1, src2;
+pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
+		  rtx src1, rtx src2)
 {
   int insn_code_number;
   rtx start, end;
@@ -8457,8 +8234,7 @@ pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
    filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
    in particular.  */
 int
-insn_refs_are_delayed (insn)
-     rtx insn;
+insn_refs_are_delayed (rtx insn)
 {
   return ((GET_CODE (insn) == INSN
 	   && GET_CODE (PATTERN (insn)) != SEQUENCE
@@ -8477,9 +8253,7 @@ insn_refs_are_delayed (insn)
    to match the HP Compiler ABI.  */
 
 rtx
-function_value (valtype, func)
-    tree valtype;
-    tree func ATTRIBUTE_UNUSED;
+function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
 {
   enum machine_mode valmode;
 
@@ -8527,11 +8301,8 @@ function_value (valtype, func)
    ??? We might want to restructure this so that it looks more like other
    ports.  */
 rtx
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
+	      int named ATTRIBUTE_UNUSED)
 {
   int max_arg_words = (TARGET_64BIT ? 8 : 4);
   int alignment = 0;
@@ -8730,11 +8501,8 @@ function_arg (cum, mode, type, named)
    then this routine should return zero. It is currently called only for
    the 64-bit target.  */
 int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+			    tree type, int named ATTRIBUTE_UNUSED)
 {
   unsigned int max_arg_words = 8;
   unsigned int offset = 0;
@@ -8758,9 +8526,7 @@ function_arg_partial_nregs (cum, mode, type, named)
    MATCH_OPERATOR to recognize all the branch insns.  */
 
 int
-cmpib_comparison_operator (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+cmpib_comparison_operator (rtx op, enum machine_mode mode)
 {
   return ((mode == VOIDmode || GET_MODE (op) == mode)
           && (GET_CODE (op) == EQ
@@ -8801,9 +8567,7 @@ pa_select_section (exp, reloc, align)
 }
 
 static void
-pa_globalize_label (stream, name)
-     FILE *stream;
-     const char *name;
+pa_globalize_label (FILE *stream, const char *name)
 {
   /* We only handle DATA objects here, functions are globalized in
      ASM_DECLARE_FUNCTION_NAME.  */
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 3f61074e632..ce69b3bc19b 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -5,20 +5,20 @@
    and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
    Software Science at the University of Utah.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
@@ -325,9 +325,7 @@ extern int target_flags;
 
 #define OVERRIDE_OPTIONS override_options ()
 
-/* stabs-in-som is nearly identical to stabs-in-elf.  To avoid useless
-   code duplication we simply include this file and override as needed.  */
-#include "dbxelf.h"
+/* Override some settings from dbxelf.h.  */
 
 /* We do not have to be compatible with dbx, so we enable gdb extensions
    by default.  */
@@ -552,7 +550,7 @@ do {								\
 
 /* Function to return the rtx used to save the pic offset table register
    across function calls.  */
-extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void));
+extern struct rtx_def *hppa_pic_save_rtx (void);
 
 #define DEFAULT_PCC_STRUCT_RETURN 0
 
@@ -654,10 +652,14 @@ extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void));
     && REGNO (IN) < FIRST_PSEUDO_REGISTER)			\
    ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
 
+#define MAYBE_FP_REG_CLASS_P(CLASS) \
+  reg_classes_intersect_p ((CLASS), FP_REGS)
+
 /* On the PA it is not possible to directly move data between
    GENERAL_REGS and FP_REGS.  */
-#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)  \
-  (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
+#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE)		\
+  (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)	\
+   || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
 
 /* Return the stack location to use for secondary memory needed reloads.  */
 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
@@ -960,7 +962,7 @@ extern enum cmp_type hppa_branch_type;
   (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
 
 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
-void hppa_profile_hook PARAMS ((int label_no));
+void hppa_profile_hook (int label_no);
 
 /* The profile counter if emitted must come before the prologue.  */
 #define PROFILE_BEFORE_PROLOGUE 1
@@ -1515,6 +1517,11 @@ do { 									\
 
 #define TARGET_ASM_SELECT_SECTION  pa_select_section
    
+/* Return a nonzero value if DECL has a section attribute.  */
+#define IN_NAMED_SECTION_P(DECL) \
+  ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
+   && DECL_SECTION_NAME (DECL) != NULL_TREE)
+
 /* Define this macro if references to a symbol must be treated
    differently depending on something about the variable or
    function named by the symbol (such as what section it is in).
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 35369966d59..b5c994017ba 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -1,23 +1,23 @@
-;;- Machine description for HP PA-RISC architecture for GNU C compiler
+;;- Machine description for HP PA-RISC architecture for GCC compiler
 ;;   Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
 ;;   2002, 2003 Free Software Foundation, Inc.
 ;;   Contributed by the Center for Software Science at the University
 ;;   of Utah.
 
-;; This file is part of GNU CC.
+;; This file is part of GCC.
 
-;; GNU CC is free software; you can redistribute it and/or modify
+;; GCC is free software; you can redistribute it and/or modify
 ;; it under the terms of the GNU General Public License as published by
 ;; the Free Software Foundation; either version 2, or (at your option)
 ;; any later version.
 
-;; GNU CC is distributed in the hope that it will be useful,
+;; GCC is distributed in the hope that it will be useful,
 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ;; GNU General Public License for more details.
 
 ;; You should have received a copy of the GNU General Public License
-;; along with GNU CC; see the file COPYING.  If not, write to
+;; along with GCC; see the file COPYING.  If not, write to
 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
 ;; Boston, MA 02111-1307, USA.
 
@@ -7145,6 +7145,7 @@
   [(set_attr "type" "branch")
    (set_attr "length" "4")])
 
+;;; Operands 2 and 3 are assumed to be CONST_INTs.
 (define_expand "extzv"
   [(set (match_operand 0 "register_operand" "")
 	(zero_extract (match_operand 1 "register_operand" "")
@@ -7153,34 +7154,34 @@
   ""
   "
 {
-  /* PA extraction insns don't support zero length bitfields.  */
-  if (INTVAL (operands[2]) == 0)
+  HOST_WIDE_INT len = INTVAL (operands[2]);
+  HOST_WIDE_INT pos = INTVAL (operands[3]);
+
+  /* PA extraction insns don't support zero length bitfields or fields
+     extending beyond the left or right-most bits.  Also, we reject lengths
+     equal to a word as they are better handled by the move patterns.  */
+  if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
+    FAIL;
+
+  /* From mips.md: extract_bit_field doesn't verify that our source
+     matches the predicate, so check it again here.  */
+  if (!register_operand (operands[1], VOIDmode))
     FAIL;
 
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-	FAIL;
-      emit_insn (gen_extzv_64 (operands[0], operands[1],
-			       operands[2], operands[3]));
-    }
+    emit_insn (gen_extzv_64 (operands[0], operands[1],
+			     operands[2], operands[3]));
   else
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
-	FAIL;
-      emit_insn (gen_extzv_32 (operands[0], operands[1],
-			       operands[2], operands[3]));
-    }
+    emit_insn (gen_extzv_32 (operands[0], operands[1],
+			     operands[2], operands[3]));
   DONE;
 }")
 
 (define_insn "extzv_32"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "uint32_operand" "")
-			 (match_operand:SI 3 "uint32_operand" "")))]
+			 (match_operand:SI 2 "uint5_operand" "")
+			 (match_operand:SI 3 "uint5_operand" "")))]
   ""
   "{extru|extrw,u} %1,%3+%2-1,%2,%0"
   [(set_attr "type" "shift")
@@ -7216,6 +7217,7 @@
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
+;;; Operands 2 and 3 are assumed to be CONST_INTs.
 (define_expand "extv"
   [(set (match_operand 0 "register_operand" "")
 	(sign_extract (match_operand 1 "register_operand" "")
@@ -7224,34 +7226,34 @@
   ""
   "
 {
-  /* PA extraction insns don't support zero length bitfields.  */
-  if (INTVAL (operands[2]) == 0)
+  HOST_WIDE_INT len = INTVAL (operands[2]);
+  HOST_WIDE_INT pos = INTVAL (operands[3]);
+
+  /* PA extraction insns don't support zero length bitfields or fields
+     extending beyond the left or right-most bits.  Also, we reject lengths
+     equal to a word as they are better handled by the move patterns.  */
+  if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
+    FAIL;
+
+  /* From mips.md: extract_bit_field doesn't verify that our source
+     matches the predicate, so check it again here.  */
+  if (!register_operand (operands[1], VOIDmode))
     FAIL;
 
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-	FAIL;
-      emit_insn (gen_extv_64 (operands[0], operands[1],
-			      operands[2], operands[3]));
-    }
+    emit_insn (gen_extv_64 (operands[0], operands[1],
+			    operands[2], operands[3]));
   else
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
-	FAIL;
-      emit_insn (gen_extv_32 (operands[0], operands[1],
-			      operands[2], operands[3]));
-    }
+    emit_insn (gen_extv_32 (operands[0], operands[1],
+			    operands[2], operands[3]));
   DONE;
 }")
 
 (define_insn "extv_32"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
-			 (match_operand:SI 2 "uint32_operand" "")
-			 (match_operand:SI 3 "uint32_operand" "")))]
+			 (match_operand:SI 2 "uint5_operand" "")
+			 (match_operand:SI 3 "uint5_operand" "")))]
   ""
   "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
   [(set_attr "type" "shift")
@@ -7287,7 +7289,7 @@
   [(set_attr "type" "shift")
    (set_attr "length" "4")])
 
-;; Only specify the mode operands 0, the rest are assumed to be word_mode.
+;;; Operands 1 and 2 are assumed to be CONST_INTs.
 (define_expand "insv"
   [(set (zero_extract (match_operand 0 "register_operand" "")
                       (match_operand 1 "uint32_operand" "")
@@ -7296,29 +7298,33 @@
   ""
   "
 {
+  HOST_WIDE_INT len = INTVAL (operands[1]);
+  HOST_WIDE_INT pos = INTVAL (operands[2]);
+
+  /* PA insertion insns don't support zero length bitfields or fields
+     extending beyond the left or right-most bits.  Also, we reject lengths
+     equal to a word as they are better handled by the move patterns.  */
+  if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
+    FAIL;
+
+  /* From mips.md: insert_bit_field doesn't verify that our destination
+     matches the predicate, so check it again here.  */
+  if (!register_operand (operands[0], VOIDmode))
+    FAIL;
+
   if (TARGET_64BIT)
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
-	FAIL;
-      emit_insn (gen_insv_64 (operands[0], operands[1],
-			      operands[2], operands[3]));
-    }
+    emit_insn (gen_insv_64 (operands[0], operands[1],
+			    operands[2], operands[3]));
   else
-    {
-      if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
-          || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
-	FAIL;
-      emit_insn (gen_insv_32 (operands[0], operands[1],
-			      operands[2], operands[3]));
-    }
+    emit_insn (gen_insv_32 (operands[0], operands[1],
+			    operands[2], operands[3]));
   DONE;
 }")
 
 (define_insn "insv_32"
   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
-			 (match_operand:SI 1 "uint32_operand" "")
-			 (match_operand:SI 2 "uint32_operand" ""))
+			 (match_operand:SI 1 "uint5_operand" "")
+			 (match_operand:SI 2 "uint5_operand" ""))
 	(match_operand:SI 3 "arith5_operand" "r,L"))]
   ""
   "@
diff --git a/gcc/config/pa/pa32-linux.h b/gcc/config/pa/pa32-linux.h
index c8e7b37012b..49439594920 100644
--- a/gcc/config/pa/pa32-linux.h
+++ b/gcc/config/pa/pa32-linux.h
@@ -1,20 +1,20 @@
 /* Definitions for PA_RISC with ELF-32 format
    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa64-hpux.h b/gcc/config/pa/pa64-hpux.h
index d16d741e2d1..a29583b561b 100644
--- a/gcc/config/pa/pa64-hpux.h
+++ b/gcc/config/pa/pa64-hpux.h
@@ -2,20 +2,20 @@
    HPUX using the 64bit runtime model.
    Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
@@ -383,3 +383,7 @@ PA_INIT_FINI_HACK
    and returns 0.  /bin/true cannot be used because it is a script without
    an interpreter.  */
 #define INIT_ENVIRONMENT "LD_PXDB=/usr/ccs/bin/size"
+
+/* The HPUX dynamic linker objects to weak symbols with no
+   definitions, so do not use them in gthr-posix.h.  */
+#define GTHREAD_USE_WEAK 0
diff --git a/gcc/config/pa/pa64-linux.h b/gcc/config/pa/pa64-linux.h
index 82a2b05005b..5d7fdbee181 100644
--- a/gcc/config/pa/pa64-linux.h
+++ b/gcc/config/pa/pa64-linux.h
@@ -1,20 +1,20 @@
 /* Definitions for PA_RISC with ELF format on 64-bit Linux
    Copyright (C) 1999, 2000, 2002 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h
index ced7df737e7..29cc230c79b 100644
--- a/gcc/config/pa/pa64-regs.h
+++ b/gcc/config/pa/pa64-regs.h
@@ -1,20 +1,20 @@
-/* Configuration for GNU C-compiler for PA-RISC.
-   Copyright (C) 1999, 2000 Free Software Foundation, Inc.
+/* Configuration for GCC-compiler for PA-RISC.
+   Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/quadlib.c b/gcc/config/pa/quadlib.c
index 05d632a25c6..cfec5e9723c 100644
--- a/gcc/config/pa/quadlib.c
+++ b/gcc/config/pa/quadlib.c
@@ -1,9 +1,9 @@
 /* Subroutines for long double support.
    Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
@@ -17,13 +17,13 @@ do apply in other respects; for example, they cover modification of
 the file, and distribution when not linked into a combine
 executable.)
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/rtems.h b/gcc/config/pa/rtems.h
index 14a8b2a6d6c..5450cfb2fb1 100644
--- a/gcc/config/pa/rtems.h
+++ b/gcc/config/pa/rtems.h
@@ -2,20 +2,20 @@
    Copyright (C) 1997, 2000, 2002, 2003 Free Software Foundation, Inc.
    Contributed by Joel Sherrill (joel@OARcorp.com).
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
diff --git a/gcc/config/pa/som.h b/gcc/config/pa/som.h
index 6d34bf93fd3..fae73922a98 100644
--- a/gcc/config/pa/som.h
+++ b/gcc/config/pa/som.h
@@ -1,20 +1,20 @@
 /* Definitions for SOM assembler support.
    Copyright (C) 1999, 2001, 2002, 2003 Free Software Foundation, Inc.
 
-This file is part of GNU CC.
+This file is part of GCC.
 
-GNU CC is free software; you can redistribute it and/or modify
+GCC is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 2, or (at your option)
 any later version.
 
-GNU CC is distributed in the hope that it will be useful,
+GCC is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
+along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
@@ -232,7 +232,7 @@ do {								\
 #define EXTRA_SECTIONS in_readonly_data
 
 #define EXTRA_SECTION_FUNCTIONS						\
-extern void readonly_data PARAMS ((void));				\
+extern void readonly_data (void);					\
 void									\
 readonly_data ()							\
 {									\
diff --git a/gcc/config/rs6000/aix.h b/gcc/config/rs6000/aix.h
index d40221513aa..991d2c31153 100644
--- a/gcc/config/rs6000/aix.h
+++ b/gcc/config/rs6000/aix.h
@@ -149,6 +149,29 @@
    ? MAX (MAX ((COMPUTED), (SPECIFIED)), 64)		\
    : MAX ((COMPUTED), (SPECIFIED)))
 
+/* The AIX ABI isn't explicit on whether aggregates smaller than a
+   word/doubleword should be padded upward or downward.  One could
+   reasonably assume that they follow the normal rules for structure
+   layout treating the parameter area as any other block of memory,
+   then map the reg param area to registers, i.e., pad upward, which
+   is the way IBM Compilers for AIX behave.
+   Setting both of the following defines results in this behaviour.  */
+#define AGGREGATE_PADDING_FIXED 1
+#define AGGREGATES_PAD_UPWARD_ALWAYS 1
+
+/* We don't want anything in the reg parm area being passed on the
+   stack.  */
+#define MUST_PASS_IN_STACK(MODE, TYPE)				\
+   ((TYPE) != 0							\
+    && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST		\
+	|| TREE_ADDRESSABLE (TYPE)))
+
+/* Specify padding for the last element of a block move between
+   registers and memory.  FIRST is nonzero if this is the only
+   element.  */
+#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
+  (!(FIRST) ? upward : FUNCTION_ARG_PADDING (MODE, TYPE))
+
 /* Indicate that jump tables go in the text section.  */
 
 #define JUMP_TABLES_IN_TEXT_SECTION 1
@@ -209,6 +232,38 @@
    So we have to squirrel it away with this.  */
 #define SETUP_FRAME_ADDRESSES() rs6000_aix_emit_builtin_unwind_init ()
 
+/* If the current unwind info (FS) does not contain explicit info
+   saving R2, then we have to do a minor amount of code reading to
+   figure out if it was saved.  The big problem here is that the
+   code that does the save/restore is generated by the linker, so
+   we have no good way to determine at compile time what to do.  */
+
+#ifdef __powerpc64__
+#define MD_FROB_UPDATE_CONTEXT(CTX, FS)					\
+  do {									\
+    if ((FS)->regs.reg[2].how == REG_UNSAVED)				\
+      {									\
+	unsigned int *insn						\
+	  = (unsigned int *)						\
+	    _Unwind_GetGR ((CTX), LINK_REGISTER_REGNUM);		\
+	if (*insn == 0xE8410028)					\
+	  _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40);			\
+      }									\
+  } while (0)
+#else
+#define MD_FROB_UPDATE_CONTEXT(CTX, FS)					\
+  do {									\
+    if ((FS)->regs.reg[2].how == REG_UNSAVED)				\
+      {									\
+	unsigned int *insn						\
+	  = (unsigned int *)						\
+	    _Unwind_GetGR ((CTX), LINK_REGISTER_REGNUM);		\
+	if (*insn == 0x80410014)					\
+	  _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 20);			\
+      }									\
+  } while (0)
+#endif
+
 #define PROFILE_HOOK(LABEL)   output_profile_hook (LABEL)
 
 /* Print subsidiary information on the compiler version in use.  */
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 736d4fd6b1f..d7718fee98b 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -1198,7 +1198,7 @@ vec_dss (const char a1)
 /* vec_dssall */
 
 inline void
-vec_dssall ()
+vec_dssall (void)
 {
   __builtin_altivec_dssall ();
 }
@@ -2419,7 +2419,7 @@ vec_vmrglb (vector unsigned char a1, vector unsigned char a2)
 /* vec_mfvscr */
 
 inline vector unsigned short
-vec_mfvscr ()
+vec_mfvscr (void)
 {
   return (vector unsigned short) __builtin_altivec_mfvscr ();
 }
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index b28544ade3b..4722826d691 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -97,6 +97,14 @@ do {									\
 %{static: %{Zdynamic: %e conflicting code gen style switches are used}}\
 %{!static:%{!mdynamic-no-pic:-fPIC}}"
 
+#define ASM_SPEC "-arch ppc \
+  %{Zforce_cpusubtype_ALL:-force_cpusubtype_ALL} \
+  %{!Zforce_cpusubtype_ALL:%{faltivec:-force_cpusubtype_ALL}}"
+
+#undef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS			\
+  { "darwin_arch", "ppc" },
+
 /* Make both r2 and r3 available for allocation.  */
 #define FIXED_R2 0
 #define FIXED_R13 0
@@ -237,16 +245,17 @@ do {									\
    a SYMBOL_REF.  */
 
 #undef PREFERRED_RELOAD_CLASS
-#define PREFERRED_RELOAD_CLASS(X,CLASS)			\
-  (((GET_CODE (X) == CONST_DOUBLE			\
-    && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)	\
-   ? NO_REGS						\
-   : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT 	\
-      && (CLASS) == NON_SPECIAL_REGS)			\
-   ? GENERAL_REGS					\
-   : (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == HIGH)	\
-   ? BASE_REGS						\
-   : (CLASS)))
+#define PREFERRED_RELOAD_CLASS(X,CLASS)				\
+  ((GET_CODE (X) == CONST_DOUBLE				\
+    && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT)		\
+   ? NO_REGS							\
+   : ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == HIGH)	\
+      && reg_class_subset_p (BASE_REGS, (CLASS)))		\
+   ? BASE_REGS							\
+   : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT			\
+      && (CLASS) == NON_SPECIAL_REGS)				\
+   ? GENERAL_REGS						\
+   : (CLASS))
 
 /* Fix for emit_group_load (): force large constants to be pushed via regs.  */
 #define ALWAYS_PUSH_CONSTS_USING_REGS_P		1
diff --git a/gcc/config/rs6000/host-darwin.c b/gcc/config/rs6000/host-darwin.c
index 294a6544910..7e8055690e4 100644
--- a/gcc/config/rs6000/host-darwin.c
+++ b/gcc/config/rs6000/host-darwin.c
@@ -23,17 +23,19 @@
 #include "coretypes.h"
 #include <signal.h>
 #include <sys/ucontext.h>
+#include <sys/mman.h>
 #include "hosthooks.h"
 #include "hosthooks-def.h"
 #include "toplev.h"
 #include "diagnostic.h"
 
-static void segv_crash_handler PARAMS ((int));
-static void segv_handler PARAMS ((int, siginfo_t *, void *));
-static void darwin_rs6000_extra_signals PARAMS ((void));
+static void segv_crash_handler (int);
+static void segv_handler (int, siginfo_t *, void *);
+static void darwin_rs6000_extra_signals (void);
 
-/* No prototype for this, filed as Radar 3150910.  */
-extern int sigaltstack(const stack_t *, stack_t *);
+/* This doesn't have a prototype in signal.h in 10.2.x and earlier,
+   fixed in later releases.  */
+extern int sigaltstack(const struct sigaltstack *, struct sigaltstack *);
 
 #undef HOST_HOOKS_EXTRA_SIGNALS
 #define HOST_HOOKS_EXTRA_SIGNALS darwin_rs6000_extra_signals
@@ -45,17 +47,15 @@ extern int sigaltstack(const stack_t *, stack_t *);
    the previous bottom of the stack.  */
 
 static void
-segv_crash_handler (sig)
-     int sig ATTRIBUTE_UNUSED;
+segv_crash_handler (int sig ATTRIBUTE_UNUSED)
 {
   internal_error ("Segmentation Fault (code)");
 }
 
 static void
-segv_handler (sig, sip, scp)
-     int sig ATTRIBUTE_UNUSED;
-     siginfo_t *sip ATTRIBUTE_UNUSED;
-     void *scp;
+segv_handler (int sig ATTRIBUTE_UNUSED,
+	      siginfo_t *sip ATTRIBUTE_UNUSED,
+	      void *scp)
 {
   ucontext_t *uc = (ucontext_t *)scp;
   unsigned faulting_insn;
@@ -119,7 +119,7 @@ segv_handler (sig, sip, scp)
 }
 
 static void
-darwin_rs6000_extra_signals ()
+darwin_rs6000_extra_signals (void)
 {
   struct sigaction sact;
   stack_t sigstk;
@@ -136,5 +136,54 @@ darwin_rs6000_extra_signals ()
   if (sigaction (SIGSEGV, &sact, 0) < 0) 
     fatal_error ("While setting up signal handler: %m");
 }
+
+static void * darwin_rs6000_gt_pch_get_address (size_t);
+static bool darwin_rs6000_gt_pch_use_address (void *, size_t);
+
+#undef HOST_HOOKS_GT_PCH_GET_ADDRESS
+#define HOST_HOOKS_GT_PCH_GET_ADDRESS darwin_rs6000_gt_pch_get_address
+#undef HOST_HOOKS_GT_PCH_USE_ADDRESS
+#define HOST_HOOKS_GT_PCH_USE_ADDRESS darwin_rs6000_gt_pch_use_address
+
+
+/* Yes, this is really supposed to work.  */
+static char pch_address_space[1024*1024*1024] __attribute__((aligned (4096)));
+
+/* Return the address of the PCH address space, if the PCH will fit in it.  */
+
+static void *
+darwin_rs6000_gt_pch_get_address (size_t sz)
+{
+  if (sz <= sizeof (pch_address_space))
+    return pch_address_space;
+  else
+    return NULL;
+}
+
+/* Check ADDR and SZ for validity, and deallocate (using munmap) that part of
+   pch_address_space beyond SZ.  */
+
+static bool
+darwin_rs6000_gt_pch_use_address (void *addr, size_t sz)
+{
+  const size_t pagesize = getpagesize();
+  bool result;
+
+  if ((size_t)pch_address_space % pagesize != 0
+      || sizeof (pch_address_space) % pagesize != 0)
+    abort ();
+  
+  result = (addr == pch_address_space && sz <= sizeof (pch_address_space));
+  if (! result)
+    sz = 0;
+
+  /* Round the size to a whole page size.  Normally this is a no-op.  */
+  sz = (sz + pagesize - 1) / pagesize * pagesize;
+
+  if (munmap (pch_address_space + sz, sizeof (pch_address_space) - sz) != 0)
+    fatal_error ("couldn't unmap pch_address_space: %m\n");
+
+  return result;
+}
 
 const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
index c3e4a586570..1ef484e629d 100644
--- a/gcc/config/rs6000/linux.h
+++ b/gcc/config/rs6000/linux.h
@@ -63,6 +63,9 @@
 #undef	LINK_OS_DEFAULT_SPEC
 #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)"
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 #undef  TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (PowerPC GNU/Linux)");
 
diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
index c1c1edb4d30..cbe18645066 100644
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
@@ -160,6 +160,10 @@
 
 #ifndef RS6000_BI_ARCH
 
+/* 64-bit PowerPC Linux is always big-endian.  */
+#undef	TARGET_LITTLE_ENDIAN
+#define TARGET_LITTLE_ENDIAN	0
+
 /* 64-bit PowerPC Linux always has a TOC.  */
 #undef  TARGET_TOC
 #define	TARGET_TOC		1
@@ -232,6 +236,35 @@
 #undef  JUMP_TABLES_IN_TEXT_SECTION
 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_64BIT
 
+/* The linux ppc64 ABI isn't explicit on whether aggregates smaller
+   than a doubleword should be padded upward or downward.  You could
+   reasonably assume that they follow the normal rules for structure
+   layout treating the parameter area as any other block of memory,
+   then map the reg param area to registers.  ie. pad updard.
+   Setting both of the following defines results in this behaviour.
+   Setting just the first one will result in aggregates that fit in a
+   doubleword being padded downward, and others being padded upward.
+   Not a bad idea as this results in struct { int x; } being passed
+   the same way as an int.  */
+#define AGGREGATE_PADDING_FIXED TARGET_64BIT
+#define AGGREGATES_PAD_UPWARD_ALWAYS 0
+
+/* We don't want anything in the reg parm area being passed on the
+   stack.  */
+#define MUST_PASS_IN_STACK(MODE, TYPE)				\
+  ((TARGET_64BIT						\
+    && (TYPE) != 0						\
+    && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST		\
+	|| TREE_ADDRESSABLE (TYPE)))				\
+   || (!TARGET_64BIT						\
+       && default_must_pass_in_stack ((MODE), (TYPE))))
+
+/* Specify padding for the last element of a block move between
+   registers and memory.  FIRST is nonzero if this is the only
+   element.  */
+#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
+  (!(FIRST) ? upward : FUNCTION_ARG_PADDING (MODE, TYPE))
+
 /* __throw will restore its own return address to be the same as the
    return address of the function that the throw is being made to.
    This is unfortunate, because we want to check the original
@@ -504,6 +537,9 @@ while (0)
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Do code reading to identify a signal frame, and set the frame
    state data appropriately.  See unwind-dw2.c for the structs.  */
 
@@ -520,6 +556,24 @@ enum { SIGNAL_FRAMESIZE = 64 };
 
 #ifdef __powerpc64__
 
+/* If the current unwind info (FS) does not contain explicit info
+   saving R2, then we have to do a minor amount of code reading to
+   figure out if it was saved.  The big problem here is that the
+   code that does the save/restore is generated by the linker, so
+   we have no good way to determine at compile time what to do.  */
+
+#define MD_FROB_UPDATE_CONTEXT(CTX, FS)					\
+  do {									\
+    if ((FS)->regs.reg[2].how == REG_UNSAVED)				\
+      {									\
+	unsigned int *insn						\
+	  = (unsigned int *)						\
+	    _Unwind_GetGR ((CTX), LINK_REGISTER_REGNUM);		\
+	if (*insn == 0xE8410028)					\
+	  _Unwind_SetGRPtr ((CTX), 2, (CTX)->cfa + 40);			\
+      }									\
+  } while (0)
+
 #define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS)		\
   do {									\
     unsigned char *pc_ = (CONTEXT)->ra;					\
diff --git a/gcc/config/rs6000/lynx.h b/gcc/config/rs6000/lynx.h
index 04ed1219aab..b32b07890ae 100644
--- a/gcc/config/rs6000/lynx.h
+++ b/gcc/config/rs6000/lynx.h
@@ -19,31 +19,6 @@
    Free Software Foundation, 59 Temple Place - Suite 330, Boston,
    MA 02111-1307, USA.  */
 
-/* Definitions we want to override with those from rs6000.h:  */
-#undef LIB_SPEC
-#undef PTRDIFF_TYPE
-#undef WCHAR_TYPE
-#undef WCHAR_TYPE_SIZE
-#undef EXTRA_SECTIONS
-#undef READONLY_DATA_SECTION
-#undef READONLY_DATA_SECTION_ASM_OP
-#undef EXTRA_SECTION_FUNCTIONS
-#undef TARGET_ASM_SELECT_RTX_SECTION
-#undef TARGET_ASM_SELECT_SECTION
-#undef USER_LABEL_PREFIX
-#undef ASM_OUTPUT_LABELREF
-#undef ASM_GENERATE_INTERNAL_LABEL
-#undef ASM_OUTPUT_COMMON
-#undef ASM_OUTPUT_LOCAL
-
-#undef SDB_DEBUGGING_INFO
-#undef DBX_DEBUGGING_INFO
-#undef PREFERRED_DEBUGGING_TYPE
-
-#undef FUNCTION_PROFILER
-
-#include <rs6000/rs6000.h>
-
 /* Print subsidiary information on the compiler version in use.  */
 #define TARGET_VERSION fprintf (stderr, " (LynxOS-RS/6000)");
 
diff --git a/gcc/config/rs6000/lynxbase.h b/gcc/config/rs6000/lynxbase.h
new file mode 100644
index 00000000000..02a255254a5
--- /dev/null
+++ b/gcc/config/rs6000/lynxbase.h
@@ -0,0 +1,45 @@
+/* Definitions for Rs6000 running LynxOS.
+   Copyright (C) 2003 Free Software Foundation, Inc.
+   Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com)
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 2, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GCC; see the file COPYING.  If not, write to the
+   Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+   MA 02111-1307, USA.  */
+
+/* Definitions we want to override with those from rs6000.h:  */
+#undef LIB_SPEC
+#undef PTRDIFF_TYPE
+#undef SIZE_TYPE
+#undef WCHAR_TYPE
+#undef WCHAR_TYPE_SIZE
+#undef EXTRA_SECTIONS
+#undef READONLY_DATA_SECTION
+#undef READONLY_DATA_SECTION_ASM_OP
+#undef EXTRA_SECTION_FUNCTIONS
+#undef TARGET_ASM_SELECT_RTX_SECTION
+#undef TARGET_ASM_SELECT_SECTION
+#undef USER_LABEL_PREFIX
+#undef ASM_OUTPUT_LABELREF
+#undef ASM_GENERATE_INTERNAL_LABEL
+#undef ASM_OUTPUT_COMMON
+#undef ASM_OUTPUT_LOCAL
+
+#undef SDB_DEBUGGING_INFO
+#undef DBX_DEBUGGING_INFO
+#undef PREFERRED_DEBUGGING_TYPE
+
+#undef FUNCTION_PROFILER
+#undef SUBTARGET_SWITCHES
diff --git a/gcc/config/rs6000/ppc64-fp.c b/gcc/config/rs6000/ppc64-fp.c
index 3f6d7cd1bb0..755827fb0b4 100644
--- a/gcc/config/rs6000/ppc64-fp.c
+++ b/gcc/config/rs6000/ppc64-fp.c
@@ -31,7 +31,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 02111-1307, USA.  */
 
 #if defined(__powerpc64__)
-#include "fp-bit.h"
+#include "config/fp-bit.h"
 
 extern DItype __fixdfdi (DFtype);
 extern DItype __fixsfdi (SFtype);
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index a7e8dd3a7c2..a47afee59b3 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -48,8 +48,7 @@
 } while (0)
 
 void
-rs6000_pragma_longcall (pfile)
-     cpp_reader *pfile ATTRIBUTE_UNUSED;
+rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED)
 {
   tree x, n;
 
@@ -80,8 +79,7 @@ rs6000_pragma_longcall (pfile)
 #define builtin_assert(TXT) cpp_assert (pfile, TXT)
 
 void
-rs6000_cpu_cpp_builtins (pfile)
-     cpp_reader *pfile;
+rs6000_cpu_cpp_builtins (cpp_reader *pfile)
 {
   if (TARGET_POWER2)
     builtin_define ("_ARCH_PWR2");
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index fc7e9cb96d8..8340c2b5931 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -27,186 +27,182 @@
 #ifdef RTX_CODE
 
 #ifdef TREE_CODE
-extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, int, int));
-extern void rs6000_va_start PARAMS ((tree, rtx));
+extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int);
+extern void rs6000_va_start (tree, rtx);
 #endif /* TREE_CODE */
 
-extern struct rtx_def *rs6000_got_register PARAMS ((rtx));
-extern struct rtx_def *find_addr_reg PARAMS ((rtx));
-extern int any_operand PARAMS ((rtx, enum machine_mode));
-extern int short_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int u_short_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int non_short_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int exact_log2_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int gpc_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int cc_reg_operand PARAMS ((rtx, enum machine_mode));
-extern int cc_reg_not_cr0_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_short_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_neg_short_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_aligned_short_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_u_short_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_arith_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_add_cint64_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_sub_cint64_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_logical_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int got_operand PARAMS ((rtx, enum machine_mode));
-extern int got_no_const_operand PARAMS ((rtx, enum machine_mode));
-extern int num_insns_constant PARAMS ((rtx, enum machine_mode));
-extern int easy_fp_constant PARAMS ((rtx, enum machine_mode));
-extern int easy_vector_constant PARAMS ((rtx, enum machine_mode));
-extern const char *output_vec_const_move PARAMS ((rtx *));
-extern int zero_fp_constant PARAMS ((rtx, enum machine_mode));
-extern int zero_constant PARAMS ((rtx, enum machine_mode));
-extern int volatile_mem_operand PARAMS ((rtx, enum machine_mode));
-extern int offsettable_mem_operand PARAMS ((rtx, enum machine_mode));
-extern int mem_or_easy_const_operand PARAMS ((rtx, enum machine_mode));
-extern int add_operand PARAMS ((rtx, enum machine_mode));
-extern int non_add_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode));
-extern int logical_operand PARAMS ((rtx, enum machine_mode));
-extern int mask_operand PARAMS ((rtx, enum machine_mode));
-extern int mask_operand_wrap PARAMS ((rtx, enum machine_mode));
-extern int mask64_operand PARAMS ((rtx, enum machine_mode));
-extern int mask64_2_operand PARAMS ((rtx, enum machine_mode));
-extern void build_mask64_2_operands PARAMS ((rtx, rtx *));
-extern int and64_operand PARAMS ((rtx, enum machine_mode));
-extern int and64_2_operand PARAMS ((rtx, enum machine_mode));
-extern int and_operand PARAMS ((rtx, enum machine_mode));
-extern int count_register_operand PARAMS ((rtx, enum machine_mode));
-extern int xer_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_mem_operand PARAMS ((rtx, enum machine_mode));
-extern int lwa_operand PARAMS ((rtx, enum machine_mode));
-extern int call_operand PARAMS ((rtx, enum machine_mode));
-extern int current_file_function_operand PARAMS ((rtx, enum machine_mode));
-extern int input_operand PARAMS ((rtx, enum machine_mode));
-extern int small_data_operand PARAMS ((rtx, enum machine_mode));
-extern int s8bit_cint_operand PARAMS ((rtx, enum machine_mode));
-extern bool legitimate_constant_pool_address_p PARAMS ((rtx));
-extern int expand_block_move PARAMS ((rtx[]));
-extern int load_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern const char * rs6000_output_load_multiple PARAMS ((rtx[]));
-extern int store_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern int branch_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int branch_positive_comparison_operator 
-  PARAMS ((rtx, enum machine_mode));
-extern int scc_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int trap_comparison_operator PARAMS ((rtx, enum machine_mode));
-extern int boolean_operator PARAMS ((rtx, enum machine_mode));
-extern int boolean_or_operator PARAMS ((rtx, enum machine_mode));
-extern int min_max_operator PARAMS ((rtx, enum machine_mode));
-extern int includes_lshift_p PARAMS ((rtx, rtx));
-extern int includes_rshift_p PARAMS ((rtx, rtx));
-extern int includes_rldic_lshift_p PARAMS ((rtx, rtx));
-extern int includes_rldicr_lshift_p PARAMS ((rtx, rtx));
-extern int registers_ok_for_quad_peep PARAMS ((rtx, rtx));
-extern int addrs_ok_for_quad_peep PARAMS ((rtx, rtx));
+extern struct rtx_def *rs6000_got_register (rtx);
+extern struct rtx_def *find_addr_reg (rtx);
+extern int any_operand (rtx, enum machine_mode);
+extern int short_cint_operand (rtx, enum machine_mode);
+extern int u_short_cint_operand (rtx, enum machine_mode);
+extern int non_short_cint_operand (rtx, enum machine_mode);
+extern int exact_log2_cint_operand (rtx, enum machine_mode);
+extern int gpc_reg_operand (rtx, enum machine_mode);
+extern int cc_reg_operand (rtx, enum machine_mode);
+extern int cc_reg_not_cr0_operand (rtx, enum machine_mode);
+extern int reg_or_short_operand (rtx, enum machine_mode);
+extern int reg_or_neg_short_operand (rtx, enum machine_mode);
+extern int reg_or_aligned_short_operand (rtx, enum machine_mode);
+extern int reg_or_u_short_operand (rtx, enum machine_mode);
+extern int reg_or_cint_operand (rtx, enum machine_mode);
+extern int reg_or_arith_cint_operand (rtx, enum machine_mode);
+extern int reg_or_add_cint64_operand (rtx, enum machine_mode);
+extern int reg_or_sub_cint64_operand (rtx, enum machine_mode);
+extern int reg_or_logical_cint_operand (rtx, enum machine_mode);
+extern int got_operand (rtx, enum machine_mode);
+extern int got_no_const_operand (rtx, enum machine_mode);
+extern int num_insns_constant (rtx, enum machine_mode);
+extern int easy_fp_constant (rtx, enum machine_mode);
+extern int easy_vector_constant (rtx, enum machine_mode);
+extern const char *output_vec_const_move (rtx *);
+extern int zero_fp_constant (rtx, enum machine_mode);
+extern int zero_constant (rtx, enum machine_mode);
+extern int volatile_mem_operand (rtx, enum machine_mode);
+extern int offsettable_mem_operand (rtx, enum machine_mode);
+extern int mem_or_easy_const_operand (rtx, enum machine_mode);
+extern int add_operand (rtx, enum machine_mode);
+extern int non_add_cint_operand (rtx, enum machine_mode);
+extern int non_logical_cint_operand (rtx, enum machine_mode);
+extern int logical_operand (rtx, enum machine_mode);
+extern int mask_operand (rtx, enum machine_mode);
+extern int mask_operand_wrap (rtx, enum machine_mode);
+extern int mask64_operand (rtx, enum machine_mode);
+extern int mask64_2_operand (rtx, enum machine_mode);
+extern void build_mask64_2_operands (rtx, rtx *);
+extern int and64_operand (rtx, enum machine_mode);
+extern int and64_2_operand (rtx, enum machine_mode);
+extern int and_operand (rtx, enum machine_mode);
+extern int count_register_operand (rtx, enum machine_mode);
+extern int xer_operand (rtx, enum machine_mode);
+extern int reg_or_mem_operand (rtx, enum machine_mode);
+extern int lwa_operand (rtx, enum machine_mode);
+extern int call_operand (rtx, enum machine_mode);
+extern int current_file_function_operand (rtx, enum machine_mode);
+extern int input_operand (rtx, enum machine_mode);
+extern int small_data_operand (rtx, enum machine_mode);
+extern int s8bit_cint_operand (rtx, enum machine_mode);
+extern bool legitimate_constant_pool_address_p (rtx);
+extern int expand_block_move (rtx[]);
+extern int load_multiple_operation (rtx, enum machine_mode);
+extern const char * rs6000_output_load_multiple (rtx[]);
+extern int store_multiple_operation (rtx, enum machine_mode);
+extern int branch_comparison_operator (rtx, enum machine_mode);
+extern int branch_positive_comparison_operator (rtx, enum machine_mode);
+extern int scc_comparison_operator (rtx, enum machine_mode);
+extern int trap_comparison_operator (rtx, enum machine_mode);
+extern int boolean_operator (rtx, enum machine_mode);
+extern int boolean_or_operator (rtx, enum machine_mode);
+extern int min_max_operator (rtx, enum machine_mode);
+extern int includes_lshift_p (rtx, rtx);
+extern int includes_rshift_p (rtx, rtx);
+extern int includes_rldic_lshift_p (rtx, rtx);
+extern int includes_rldicr_lshift_p (rtx, rtx);
+extern int registers_ok_for_quad_peep (rtx, rtx);
+extern int addrs_ok_for_quad_peep (rtx, rtx);
 extern int altivec_in_gprs_p (rtx, rtx);
-extern enum reg_class secondary_reload_class PARAMS ((enum reg_class,
-						      enum machine_mode, rtx));
-extern int ccr_bit PARAMS ((rtx, int));
-extern int extract_MB PARAMS ((rtx));
-extern int extract_ME PARAMS ((rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern enum rtx_code rs6000_reverse_condition PARAMS ((enum machine_mode,
-						       enum rtx_code));
-extern void rs6000_emit_sCOND PARAMS ((enum rtx_code, rtx));
-extern void rs6000_emit_cbranch PARAMS ((enum rtx_code, rtx));
-extern char * output_cbranch PARAMS ((rtx, const char *, int, rtx));
-extern rtx rs6000_emit_set_const PARAMS ((rtx, enum machine_mode, rtx, int));
-extern int rs6000_emit_cmove PARAMS ((rtx, rtx, rtx, rtx));
-extern void rs6000_emit_minmax PARAMS ((rtx, enum rtx_code, rtx, rtx));
-extern void output_toc PARAMS ((FILE *, rtx, int, enum machine_mode));
-extern void rs6000_initialize_trampoline PARAMS ((rtx, rtx, rtx));
-extern struct rtx_def *rs6000_longcall_ref PARAMS ((rtx));
-extern void rs6000_fatal_bad_address PARAMS ((rtx));
-extern int stmw_operation PARAMS ((rtx, enum machine_mode));
-extern int mfcr_operation PARAMS ((rtx, enum machine_mode));
-extern int mtcrf_operation PARAMS ((rtx, enum machine_mode));
-extern int lmw_operation PARAMS ((rtx, enum machine_mode));
-extern struct rtx_def *create_TOC_reference PARAMS ((rtx));
-extern void rs6000_emit_eh_toc_restore PARAMS ((rtx));
+extern enum reg_class secondary_reload_class (enum reg_class,
+						      enum machine_mode, rtx);
+extern int ccr_bit (rtx, int);
+extern int extract_MB (rtx);
+extern int extract_ME (rtx);
+extern void print_operand (FILE *, rtx, int);
+extern void print_operand_address (FILE *, rtx);
+extern enum rtx_code rs6000_reverse_condition (enum machine_mode,
+						       enum rtx_code);
+extern void rs6000_emit_sCOND (enum rtx_code, rtx);
+extern void rs6000_emit_cbranch (enum rtx_code, rtx);
+extern char * output_cbranch (rtx, const char *, int, rtx);
+extern rtx rs6000_emit_set_const (rtx, enum machine_mode, rtx, int);
+extern int rs6000_emit_cmove (rtx, rtx, rtx, rtx);
+extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
+extern void output_toc (FILE *, rtx, int, enum machine_mode);
+extern void rs6000_initialize_trampoline (rtx, rtx, rtx);
+extern struct rtx_def *rs6000_longcall_ref (rtx);
+extern void rs6000_fatal_bad_address (rtx);
+extern int stmw_operation (rtx, enum machine_mode);
+extern int mfcr_operation (rtx, enum machine_mode);
+extern int mtcrf_operation (rtx, enum machine_mode);
+extern int lmw_operation (rtx, enum machine_mode);
+extern struct rtx_def *create_TOC_reference (rtx);
 extern void rs6000_split_altivec_in_gprs (rtx *);
-extern void rs6000_emit_move PARAMS ((rtx, rtx, enum machine_mode));
-extern rtx rs6000_legitimize_address PARAMS ((rtx, rtx, enum machine_mode));
-extern rtx rs6000_legitimize_reload_address PARAMS ((rtx, enum machine_mode,
-			    int, int, int, int *));
-extern int rs6000_legitimate_address PARAMS ((enum machine_mode, rtx, int));
-extern bool rs6000_mode_dependent_address PARAMS ((rtx));
-extern rtx rs6000_return_addr PARAMS ((int, rtx));
-extern void rs6000_output_symbol_ref PARAMS ((FILE*, rtx));
-
-extern rtx rs6000_machopic_legitimize_pic_address PARAMS ((rtx orig, enum machine_mode mode, rtx reg));
+extern void rs6000_emit_move (rtx, rtx, enum machine_mode);
+extern rtx rs6000_legitimize_address (rtx, rtx, enum machine_mode);
+extern rtx rs6000_legitimize_reload_address (rtx, enum machine_mode,
+			    int, int, int, int *);
+extern int rs6000_legitimate_address (enum machine_mode, rtx, int);
+extern bool rs6000_mode_dependent_address (rtx);
+extern rtx rs6000_return_addr (int, rtx);
+extern void rs6000_output_symbol_ref (FILE*, rtx);
+
+extern rtx rs6000_machopic_legitimize_pic_address (rtx orig, 
+                            enum machine_mode mode, rtx reg);
 
 #endif /* RTX_CODE */
 
 #ifdef TREE_CODE
-extern void function_arg_advance PARAMS ((CUMULATIVE_ARGS *, enum machine_mode,
-					  tree, int));
-extern int function_arg_boundary PARAMS ((enum machine_mode, tree));
-extern struct rtx_def *function_arg PARAMS ((CUMULATIVE_ARGS *,
-					     enum machine_mode, tree, int));
-extern int function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *,
-					       enum machine_mode, tree, int));
-extern int function_arg_pass_by_reference PARAMS ((CUMULATIVE_ARGS *,
+extern void function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
+					  tree, int);
+extern int function_arg_boundary (enum machine_mode, tree);
+extern struct rtx_def *function_arg (CUMULATIVE_ARGS *,
+					     enum machine_mode, tree, int);
+extern int function_arg_partial_nregs (CUMULATIVE_ARGS *,
+					       enum machine_mode, tree, int);
+extern int function_arg_pass_by_reference (CUMULATIVE_ARGS *,
 						   enum machine_mode,
-						   tree, int));
-extern void setup_incoming_varargs PARAMS ((CUMULATIVE_ARGS *,
+						   tree, int);
+extern void setup_incoming_varargs (CUMULATIVE_ARGS *,
 					    enum machine_mode, tree,
-					    int *, int));
+					    int *, int);
 extern rtx rs6000_function_value (tree, tree);
 extern rtx rs6000_libcall_value (enum machine_mode);
-extern struct rtx_def *rs6000_va_arg PARAMS ((tree, tree));
-extern int function_ok_for_sibcall PARAMS ((tree));
-extern void rs6000_elf_declare_function_name
-  PARAMS ((FILE *, const char *, tree));
+extern struct rtx_def *rs6000_va_arg (tree, tree);
+extern int function_ok_for_sibcall (tree);
+extern void rs6000_elf_declare_function_name (FILE *, const char *, tree);
 #ifdef ARGS_SIZE_RTX
 /* expr.h defines ARGS_SIZE_RTX and `enum direction' */
-extern enum direction function_arg_padding PARAMS ((enum machine_mode, tree));
+extern enum direction function_arg_padding (enum machine_mode, tree);
 #endif /* ARGS_SIZE_RTX */
 
 #endif /* TREE_CODE */
 
-extern void optimization_options PARAMS ((int, int));
-extern void rs6000_override_options PARAMS ((const char *));
-extern int direct_return PARAMS ((void));
-extern union tree_node *rs6000_build_va_list PARAMS ((void));
-extern int first_reg_to_save PARAMS ((void));
-extern int first_fp_reg_to_save PARAMS ((void));
-extern rs6000_stack_t *rs6000_stack_info PARAMS ((void));
-extern void output_ascii PARAMS ((FILE *, const char *, int));
-extern void rs6000_gen_section_name PARAMS ((char **, const char *,
-					     const char *));
-extern void output_function_profiler PARAMS ((FILE *, int));
-extern void output_profile_hook  PARAMS ((int));
-extern int rs6000_trampoline_size PARAMS ((void));
-extern void toc_section PARAMS ((void));
-extern void sdata_section PARAMS ((void));
-extern void sdata2_section PARAMS ((void));
-extern void sbss_section PARAMS ((void));
-extern void private_data_section PARAMS ((void));
-extern void read_only_data_section PARAMS ((void));
-extern void read_only_private_data_section PARAMS ((void));
-extern int get_TOC_alias_set PARAMS ((void));
-extern int uses_TOC PARAMS ((void));
-extern void rs6000_emit_prologue PARAMS ((void));
-extern void rs6000_emit_load_toc_table PARAMS ((int));
-extern void rs6000_aix_emit_builtin_unwind_init PARAMS ((void));
-extern void rs6000_emit_epilogue PARAMS ((int));
-extern void debug_stack_info PARAMS ((rs6000_stack_t *));
-extern const char * output_isel PARAMS ((rtx *));
-extern int vrsave_operation PARAMS ((rtx, enum machine_mode));
-extern int rs6000_register_move_cost PARAMS ((enum machine_mode,
-					      enum reg_class, enum reg_class));
-extern int rs6000_memory_move_cost PARAMS ((enum machine_mode,
-					    enum reg_class, int));
-extern bool rs6000_tls_referenced_p PARAMS ((rtx));
-extern int rs6000_tls_symbol_ref PARAMS ((rtx, enum machine_mode));
+extern void optimization_options (int, int);
+extern void rs6000_override_options (const char *);
+extern int direct_return (void);
+extern union tree_node *rs6000_build_va_list (void);
+extern int first_reg_to_save (void);
+extern int first_fp_reg_to_save (void);
+extern rs6000_stack_t *rs6000_stack_info (void);
+extern void output_ascii (FILE *, const char *, int);
+extern void rs6000_gen_section_name (char **, const char *, const char *);
+extern void output_function_profiler (FILE *, int);
+extern void output_profile_hook  (int);
+extern int rs6000_trampoline_size (void);
+extern void toc_section (void);
+extern void sdata_section (void);
+extern void sdata2_section (void);
+extern void sbss_section (void);
+extern void private_data_section (void);
+extern void read_only_data_section (void);
+extern void read_only_private_data_section (void);
+extern int get_TOC_alias_set (void);
+extern int uses_TOC (void);
+extern void rs6000_emit_prologue (void);
+extern void rs6000_emit_load_toc_table (int);
+extern void rs6000_aix_emit_builtin_unwind_init (void);
+extern void rs6000_emit_epilogue (int);
+extern void debug_stack_info (rs6000_stack_t *);
+extern const char * output_isel (rtx *);
+extern int vrsave_operation (rtx, enum machine_mode);
+extern int rs6000_register_move_cost (enum machine_mode,
+					      enum reg_class, enum reg_class);
+extern int rs6000_memory_move_cost (enum machine_mode, enum reg_class, int);
+extern bool rs6000_tls_referenced_p (rtx);
+extern int rs6000_tls_symbol_ref (rtx, enum machine_mode);
 
 /* Declare functions in rs6000-c.c */
 
-extern void rs6000_pragma_longcall PARAMS ((struct cpp_reader *));
-extern void rs6000_cpu_cpp_builtins PARAMS ((struct cpp_reader *));
+extern void rs6000_pragma_longcall (struct cpp_reader *);
+extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
 
 #endif  /* rs6000-protos.h */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7ff59de6b76..ae702fc012b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -198,129 +198,126 @@ struct builtin_description
   const enum rs6000_builtins code;
 };
 
-static bool rs6000_function_ok_for_sibcall PARAMS ((tree, tree));
-static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT));
-static void validate_condition_mode 
-  PARAMS ((enum rtx_code, enum machine_mode));
-static rtx rs6000_generate_compare PARAMS ((enum rtx_code));
-static void rs6000_maybe_dead PARAMS ((rtx));
-static void rs6000_emit_stack_tie PARAMS ((void));
-static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx));
-static rtx spe_synthesize_frame_save PARAMS ((rtx));
-static bool spe_func_has_64bit_regs_p PARAMS ((void));
-static void emit_frame_save PARAMS ((rtx, rtx, enum machine_mode,
-				     unsigned int, int, int));
-static rtx gen_frame_mem_offset PARAMS ((enum machine_mode, rtx, int));
-static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int));
-static unsigned rs6000_hash_constant PARAMS ((rtx));
-static unsigned toc_hash_function PARAMS ((const void *));
-static int toc_hash_eq PARAMS ((const void *, const void *));
-static int constant_pool_expr_1 PARAMS ((rtx, int *, int *));
-static bool constant_pool_expr_p PARAMS ((rtx));
-static bool toc_relative_expr_p PARAMS ((rtx));
-static bool legitimate_small_data_p PARAMS ((enum machine_mode, rtx));
-static bool legitimate_offset_address_p PARAMS ((enum machine_mode, rtx, int));
-static bool legitimate_indexed_address_p PARAMS ((rtx, int));
-static bool legitimate_indirect_address_p PARAMS ((rtx, int));
-static bool legitimate_lo_sum_address_p PARAMS ((enum machine_mode, rtx, int));
-static struct machine_function * rs6000_init_machine_status PARAMS ((void));
-static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int));
+static bool rs6000_function_ok_for_sibcall (tree, tree);
+static int num_insns_constant_wide (HOST_WIDE_INT);
+static void validate_condition_mode (enum rtx_code, enum machine_mode);
+static rtx rs6000_generate_compare (enum rtx_code);
+static void rs6000_maybe_dead (rtx);
+static void rs6000_emit_stack_tie (void);
+static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
+static rtx spe_synthesize_frame_save (rtx);
+static bool spe_func_has_64bit_regs_p (void);
+static void emit_frame_save (rtx, rtx, enum machine_mode,
+				     unsigned int, int, int);
+static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
+static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
+static unsigned rs6000_hash_constant (rtx);
+static unsigned toc_hash_function (const void *);
+static int toc_hash_eq (const void *, const void *);
+static int constant_pool_expr_1 (rtx, int *, int *);
+static bool constant_pool_expr_p (rtx);
+static bool toc_relative_expr_p (rtx);
+static bool legitimate_small_data_p (enum machine_mode, rtx);
+static bool legitimate_offset_address_p (enum machine_mode, rtx, int);
+static bool legitimate_indexed_address_p (rtx, int);
+static bool legitimate_indirect_address_p (rtx, int);
+static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
+static struct machine_function * rs6000_init_machine_status (void);
+static bool rs6000_assemble_integer (rtx, unsigned int, int);
 #ifdef HAVE_GAS_HIDDEN
-static void rs6000_assemble_visibility PARAMS ((tree, int));
+static void rs6000_assemble_visibility (tree, int);
 #endif
-static int rs6000_ra_ever_killed PARAMS ((void));
-static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *));
+static int rs6000_ra_ever_killed (void);
+static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
 extern const struct attribute_spec rs6000_attribute_table[];
-static void rs6000_set_default_type_attributes PARAMS ((tree));
-static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void rs6000_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					    HOST_WIDE_INT, tree));
-static rtx rs6000_emit_set_long_const PARAMS ((rtx,
-  HOST_WIDE_INT, HOST_WIDE_INT));
-static void rs6000_file_start PARAMS ((void));
+static void rs6000_set_default_type_attributes (tree);
+static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
+static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+					    HOST_WIDE_INT, tree);
+static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
+static void rs6000_file_start (void);
 #if TARGET_ELF
-static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *,
-							   int));
-static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int));
-static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int));
-static void rs6000_elf_select_section PARAMS ((tree, int,
-					       unsigned HOST_WIDE_INT));
-static void rs6000_elf_unique_section PARAMS ((tree, int));
-static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx,
-						   unsigned HOST_WIDE_INT));
-static void rs6000_elf_encode_section_info PARAMS ((tree, rtx, int))
+static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
+static void rs6000_elf_asm_out_constructor (rtx, int);
+static void rs6000_elf_asm_out_destructor (rtx, int);
+static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
+static void rs6000_elf_unique_section (tree, int);
+static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
+						   unsigned HOST_WIDE_INT);
+static void rs6000_elf_encode_section_info (tree, rtx, int)
      ATTRIBUTE_UNUSED;
-static bool rs6000_elf_in_small_data_p PARAMS ((tree));
+static bool rs6000_elf_in_small_data_p (tree);
 #endif
 #if TARGET_XCOFF
-static void rs6000_xcoff_asm_globalize_label PARAMS ((FILE *, const char *));
-static void rs6000_xcoff_asm_named_section PARAMS ((const char *, unsigned int));
-static void rs6000_xcoff_select_section PARAMS ((tree, int,
-						 unsigned HOST_WIDE_INT));
-static void rs6000_xcoff_unique_section PARAMS ((tree, int));
-static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx,
-						     unsigned HOST_WIDE_INT));
-static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *));
-static unsigned int rs6000_xcoff_section_type_flags PARAMS ((tree, const char *, int));
-static void rs6000_xcoff_file_start PARAMS ((void));
-static void rs6000_xcoff_file_end PARAMS ((void));
+static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
+static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
+static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
+static void rs6000_xcoff_unique_section (tree, int);
+static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
+						     unsigned HOST_WIDE_INT);
+static const char * rs6000_xcoff_strip_name_encoding (const char *);
+static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
+static void rs6000_xcoff_file_start (void);
+static void rs6000_xcoff_file_end (void);
 #endif
 #if TARGET_MACHO
-static bool rs6000_binds_local_p PARAMS ((tree));
+static bool rs6000_binds_local_p (tree);
 #endif
-static int rs6000_use_dfa_pipeline_interface PARAMS ((void));
-static int rs6000_variable_issue PARAMS ((FILE *, int, rtx, int));
-static bool rs6000_rtx_costs PARAMS ((rtx, int, int, int *));
-static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int rs6000_adjust_priority PARAMS ((rtx, int));
-static int rs6000_issue_rate PARAMS ((void));
-static int rs6000_use_sched_lookahead PARAMS ((void));
-
-static void rs6000_init_builtins PARAMS ((void));
-static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx));
-static rtx rs6000_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx));
-static rtx rs6000_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx));
-static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int));
-static void altivec_init_builtins PARAMS ((void));
-static void rs6000_common_init_builtins PARAMS ((void));
-
-static void enable_mask_for_builtins PARAMS ((struct builtin_description *,
+static int rs6000_use_dfa_pipeline_interface (void);
+static int rs6000_variable_issue (FILE *, int, rtx, int);
+static bool rs6000_rtx_costs (rtx, int, int, int *);
+static int rs6000_adjust_cost (rtx, rtx, rtx, int);
+static int rs6000_adjust_priority (rtx, int);
+static int rs6000_issue_rate (void);
+static int rs6000_use_sched_lookahead (void);
+
+static void rs6000_init_builtins (void);
+static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
+static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
+static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
+static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+static void altivec_init_builtins (void);
+static void rs6000_common_init_builtins (void);
+
+static void enable_mask_for_builtins (struct builtin_description *,
 					      int, enum rs6000_builtins,
-					      enum rs6000_builtins));
-static void spe_init_builtins PARAMS ((void));
-static rtx spe_expand_builtin PARAMS ((tree, rtx, bool *));
-static rtx spe_expand_predicate_builtin PARAMS ((enum insn_code, tree, rtx));
-static rtx spe_expand_evsel_builtin PARAMS ((enum insn_code, tree, rtx));
-static int rs6000_emit_int_cmove PARAMS ((rtx, rtx, rtx, rtx));
-
-static rtx altivec_expand_builtin PARAMS ((tree, rtx, bool *));
-static rtx altivec_expand_ld_builtin PARAMS ((tree, rtx, bool *));
-static rtx altivec_expand_st_builtin PARAMS ((tree, rtx, bool *));
-static rtx altivec_expand_dst_builtin PARAMS ((tree, rtx, bool *));
-static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx));
-static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx));
-static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree));
-static void rs6000_parse_abi_options PARAMS ((void));
-static void rs6000_parse_alignment_option PARAMS ((void));
-static void rs6000_parse_tls_size_option PARAMS ((void));
+					      enum rs6000_builtins);
+static void spe_init_builtins (void);
+static rtx spe_expand_builtin (tree, rtx, bool *);
+static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
+static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
+static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
+
+static rtx altivec_expand_builtin (tree, rtx, bool *);
+static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
+static rtx altivec_expand_st_builtin (tree, rtx, bool *);
+static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
+static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
+static rtx altivec_expand_predicate_builtin (enum insn_code, 
+					    const char *, tree, rtx);
+static rtx altivec_expand_stv_builtin (enum insn_code, tree);
+static void rs6000_parse_abi_options (void);
+static void rs6000_parse_alignment_option (void);
+static void rs6000_parse_tls_size_option (void);
 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
-static int first_altivec_reg_to_save PARAMS ((void));
-static unsigned int compute_vrsave_mask PARAMS ((void));
-static void is_altivec_return_reg PARAMS ((rtx, void *));
-static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int));
-int easy_vector_constant PARAMS ((rtx, enum machine_mode));
-static int easy_vector_same PARAMS ((rtx, enum machine_mode));
-static bool is_ev64_opaque_type PARAMS ((tree));
-static rtx rs6000_dwarf_register_span PARAMS ((rtx));
-static rtx rs6000_legitimize_tls_address PARAMS ((rtx, enum tls_model));
-static rtx rs6000_tls_get_addr PARAMS ((void));
-static rtx rs6000_got_sym PARAMS ((void));
-static inline int rs6000_tls_symbol_ref_1 PARAMS ((rtx *, void *));
-static const char *rs6000_get_some_local_dynamic_name PARAMS ((void));
-static int rs6000_get_some_local_dynamic_name_1 PARAMS ((rtx *, void *));
+static int first_altivec_reg_to_save (void);
+static unsigned int compute_vrsave_mask (void);
+static void is_altivec_return_reg (rtx, void *);
+static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
+int easy_vector_constant (rtx, enum machine_mode);
+static int easy_vector_same (rtx, enum machine_mode);
+static bool is_ev64_opaque_type (tree);
+static rtx rs6000_dwarf_register_span (rtx);
+static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
+static rtx rs6000_tls_get_addr (void);
+static rtx rs6000_got_sym (void);
+static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
+static const char *rs6000_get_some_local_dynamic_name (void);
+static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
 static rtx rs6000_complex_function_value (enum machine_mode);
-static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree);
+static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *, 
+				    enum machine_mode, tree);
 
 /* Hash table stuff for keeping track of TOC entries.  */
 
@@ -501,8 +498,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
    type and sometimes adjust other TARGET_ options.  */
 
 void
-rs6000_override_options (default_cpu)
-     const char *default_cpu;
+rs6000_override_options (const char *default_cpu)
 {
   size_t i, j;
   struct rs6000_cpu_select *ptr;
@@ -888,7 +884,7 @@ rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
 
 /* Handle -mabi= options.  */
 static void
-rs6000_parse_abi_options ()
+rs6000_parse_abi_options (void)
 {
   if (rs6000_abi_string == 0)
     return;
@@ -911,7 +907,7 @@ rs6000_parse_abi_options ()
 
 /* Handle -malign-XXXXXX options.  */
 static void
-rs6000_parse_alignment_option ()
+rs6000_parse_alignment_option (void)
 {
   if (rs6000_alignment_string == 0
       || ! strcmp (rs6000_alignment_string, "power"))
@@ -926,7 +922,7 @@ rs6000_parse_alignment_option ()
 /* Validate and record the size specified with the -mtls-size option.  */
 
 static void
-rs6000_parse_tls_size_option ()
+rs6000_parse_tls_size_option (void)
 {
   if (rs6000_tls_size_string == 0)
     return;
@@ -941,16 +937,14 @@ rs6000_parse_tls_size_option ()
 }
 
 void
-optimization_options (level, size)
-     int level ATTRIBUTE_UNUSED;
-     int size ATTRIBUTE_UNUSED;
+optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
 {
 }
 
 /* Do anything needed at the start of the asm file.  */
 
 static void
-rs6000_file_start ()
+rs6000_file_start (void)
 {
   size_t i;
   char buffer[80];
@@ -1006,7 +1000,7 @@ rs6000_file_start ()
 /* Return nonzero if this function is known to have a null epilogue.  */
 
 int
-direct_return ()
+direct_return (void)
 {
   if (reload_completed)
     {
@@ -1028,18 +1022,15 @@ direct_return ()
 /* Returns 1 always.  */
 
 int
-any_operand (op, mode)
-     rtx op ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+any_operand (rtx op ATTRIBUTE_UNUSED, 
+	     enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return 1;
 }
 
 /* Returns 1 if op is the count register.  */
 int
-count_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != REG)
     return 0;
@@ -1055,9 +1046,7 @@ count_register_operand (op, mode)
 
 /* Returns 1 if op is an altivec register.  */
 int
-altivec_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   
   return (register_operand (op, mode)
@@ -1067,9 +1056,7 @@ altivec_register_operand (op, mode)
 }
 
 int
-xer_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != REG)
     return 0;
@@ -1084,9 +1071,7 @@ xer_operand (op, mode)
    by such constants completes more quickly.  */
 
 int
-s8bit_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ( GET_CODE (op) == CONST_INT
 	  && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
@@ -1095,9 +1080,7 @@ s8bit_cint_operand (op, mode)
 /* Return 1 if OP is a constant that can fit in a D field.  */
 
 int
-short_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
@@ -1106,9 +1089,7 @@ short_cint_operand (op, mode)
 /* Similar for an unsigned D field.  */
 
 int
-u_short_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
@@ -1117,9 +1098,7 @@ u_short_cint_operand (op, mode)
 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field.  */
 
 int
-non_short_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
@@ -1129,9 +1108,7 @@ non_short_cint_operand (op, mode)
    and an exact power of 2.  */
 
 int
-exact_log2_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && INTVAL (op) > 0
@@ -1142,9 +1119,7 @@ exact_log2_cint_operand (op, mode)
    ctr, or lr).  */
 
 int
-gpc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+gpc_reg_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  && (GET_CODE (op) != REG
@@ -1157,9 +1132,7 @@ gpc_reg_operand (op, mode)
    CR field.  */
 
 int
-cc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+cc_reg_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  && (GET_CODE (op) != REG
@@ -1171,9 +1144,7 @@ cc_reg_operand (op, mode)
    CR field that isn't CR0.  */
 
 int
-cc_reg_not_cr0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  && (GET_CODE (op) != REG
@@ -1186,9 +1157,7 @@ cc_reg_not_cr0_operand (op, mode)
    mode unless MODE is VOIDmode.  */
 
 int
-reg_or_short_operand (op, mode)
-      rtx op;
-      enum machine_mode mode;
+reg_or_short_operand (rtx op, enum machine_mode mode)
 {
   return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
 }
@@ -1197,9 +1166,7 @@ reg_or_short_operand (op, mode)
    valid for a D-field.  */
 
 int
-reg_or_neg_short_operand (op, mode)
-      rtx op;
-      enum machine_mode mode;
+reg_or_neg_short_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == CONST_INT)
     return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P');
@@ -1212,9 +1179,7 @@ reg_or_neg_short_operand (op, mode)
    mode unless MODE is VOIDmode.  */
 
 int
-reg_or_aligned_short_operand (op, mode)
-      rtx op;
-      enum machine_mode mode;
+reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
 {
   if (gpc_reg_operand (op, mode))
     return 1;
@@ -1229,9 +1194,7 @@ reg_or_aligned_short_operand (op, mode)
    high-order 16 bits are zero.  */
 
 int
-reg_or_u_short_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_u_short_operand (rtx op, enum machine_mode mode)
 {
   return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
 }
@@ -1240,9 +1203,7 @@ reg_or_u_short_operand (op, mode)
    constant integer.  */
 
 int
-reg_or_cint_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+reg_or_cint_operand (rtx op, enum machine_mode mode)
 {
   return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
 }
@@ -1251,9 +1212,7 @@ reg_or_cint_operand (op, mode)
    32-bit signed constant integer.  */
 
 int
-reg_or_arith_cint_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
 {
   return (gpc_reg_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT
@@ -1268,9 +1227,7 @@ reg_or_arith_cint_operand (op, mode)
    signed constant integer valid for 64-bit addition.  */
 
 int
-reg_or_add_cint64_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
 {
   return (gpc_reg_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT
@@ -1287,9 +1244,7 @@ reg_or_add_cint64_operand (op, mode)
    signed constant integer valid for 64-bit subtraction.  */
 
 int
-reg_or_sub_cint64_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
 {
   return (gpc_reg_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT
@@ -1306,9 +1261,7 @@ reg_or_sub_cint64_operand (op, mode)
    32-bit unsigned constant integer.  */
 
 int
-reg_or_logical_cint_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -1339,9 +1292,7 @@ reg_or_logical_cint_operand (op, mode)
 /* Return 1 if the operand is an operand that can be loaded via the GOT.  */
 
 int
-got_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == SYMBOL_REF
 	  || GET_CODE (op) == CONST
@@ -1352,9 +1303,7 @@ got_operand (op, mode)
    the GOT (labels involving addition aren't allowed).  */
 
 int
-got_no_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
 }
@@ -1363,8 +1312,7 @@ got_no_const_operand (op, mode)
    integer register.  */
 
 static int
-num_insns_constant_wide (value)
-     HOST_WIDE_INT value;
+num_insns_constant_wide (HOST_WIDE_INT value)
 {
   /* signed constant loadable with {cal|addi} */
   if (CONST_OK_FOR_LETTER_P (value, 'I'))
@@ -1398,9 +1346,7 @@ num_insns_constant_wide (value)
 }
 
 int
-num_insns_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
+num_insns_constant (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -1477,9 +1423,7 @@ num_insns_constant (op, mode)
    safely read CONST_DOUBLE_{LOW,HIGH}.  */
 
 int
-easy_fp_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
+easy_fp_constant (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) != CONST_DOUBLE
       || GET_MODE (op) != mode
@@ -1553,9 +1497,7 @@ easy_fp_constant (op, mode)
 /* Return nonzero if all elements of a vector have the same value.  */
 
 static int
-easy_vector_same (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int units, i, cst;
 
@@ -1574,9 +1516,7 @@ easy_vector_same (op, mode)
    register without using memory.  */
 
 int
-easy_vector_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
+easy_vector_constant (rtx op, enum machine_mode mode)
 {
   int cst, cst2;
 
@@ -1625,9 +1565,7 @@ easy_vector_constant (op, mode)
 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.  */
 
 int
-easy_vector_constant_add_self (op, mode)
-     rtx op;
-     enum machine_mode mode;
+easy_vector_constant_add_self (rtx op, enum machine_mode mode)
 {
   int cst;
 
@@ -1640,8 +1578,7 @@ easy_vector_constant_add_self (op, mode)
 }
 
 const char *
-output_vec_const_move (operands)
-     rtx *operands;
+output_vec_const_move (rtx *operands)
 {
   int cst, cst2;
   enum machine_mode mode;
@@ -1701,18 +1638,14 @@ output_vec_const_move (operands)
 /* Return 1 if the operand is the constant 0.  This works for scalars
    as well as vectors.  */
 int
-zero_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
+zero_constant (rtx op, enum machine_mode mode)
 {
   return op == CONST0_RTX (mode);
 }
 
 /* Return 1 if the operand is 0.0.  */
 int
-zero_fp_constant (op, mode)
-     rtx op;
-     enum machine_mode mode;
+zero_fp_constant (rtx op, enum machine_mode mode)
 {
   return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
 }
@@ -1723,9 +1656,7 @@ zero_fp_constant (op, mode)
    recognize volatile references where its safe.  */
 
 int
-volatile_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+volatile_mem_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) != MEM)
     return 0;
@@ -1748,9 +1679,7 @@ volatile_mem_operand (op, mode)
 /* Return 1 if the operand is an offsettable memory operand.  */
 
 int
-offsettable_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+offsettable_mem_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == MEM)
 	  && offsettable_address_p (reload_completed || reload_in_progress,
@@ -1761,9 +1690,7 @@ offsettable_mem_operand (op, mode)
    memory.  */
 
 int
-mem_or_easy_const_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+mem_or_easy_const_operand (rtx op, enum machine_mode mode)
 {
   return memory_operand (op, mode) || easy_fp_constant (op, mode);
 }
@@ -1772,9 +1699,7 @@ mem_or_easy_const_operand (op, mode)
    that can be used as the operand of a `mode' add insn.  */
 
 int
-add_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+add_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == CONST_INT)
     return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
@@ -1786,9 +1711,7 @@ add_operand (op, mode)
 /* Return 1 if OP is a constant but not a valid add_operand.  */
 
 int
-non_add_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT
 	  && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
@@ -1799,9 +1722,7 @@ non_add_cint_operand (op, mode)
    can be used as the operand of an OR or XOR insn on the RS/6000.  */
 
 int
-logical_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+logical_operand (rtx op, enum machine_mode mode)
 {
   HOST_WIDE_INT opl, oph;
 
@@ -1838,9 +1759,7 @@ logical_operand (op, mode)
    above), but could be split into one.  */
 
 int
-non_logical_cint_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+non_logical_cint_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
 	  && ! logical_operand (op, mode)
@@ -1853,9 +1772,7 @@ non_logical_cint_operand (op, mode)
    away and confuse the making of MB and ME.  */
 
 int
-mask_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   HOST_WIDE_INT c, lsb;
 
@@ -1897,9 +1814,7 @@ mask_operand (op, mode)
 /* Return 1 for the PowerPC64 rlwinm corner case.  */
 
 int
-mask_operand_wrap (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   HOST_WIDE_INT c, lsb;
 
@@ -1928,9 +1843,7 @@ mask_operand_wrap (op, mode)
    confuses the making of MB and ME.  */
 
 int
-mask64_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -1961,9 +1874,7 @@ mask64_operand (op, mode)
    rldicr machine insns.  */
 
 int
-mask64_2_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -2010,9 +1921,7 @@ mask64_2_operand (op, mode)
 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
    implement ANDing by the mask IN.  */
 void
-build_mask64_2_operands (in, out)
-     rtx in;
-     rtx *out;
+build_mask64_2_operands (rtx in, rtx *out)
 {
 #if HOST_BITS_PER_WIDE_INT >= 64
   unsigned HOST_WIDE_INT c, lsb, m1, m2;
@@ -2083,9 +1992,7 @@ build_mask64_2_operands (in, out)
    that can be used as the operand of a PowerPC64 logical AND insn.  */
 
 int
-and64_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+and64_operand (rtx op, enum machine_mode mode)
 {
   if (fixed_regs[CR0_REGNO])	/* CR0 not available, don't do andi./andis.  */
     return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
@@ -2097,9 +2004,7 @@ and64_operand (op, mode)
    with two rldicl or rldicr insns.  */
 
 int
-and64_2_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+and64_2_operand (rtx op, enum machine_mode mode)
 {
   if (fixed_regs[CR0_REGNO])	/* CR0 not available, don't do andi./andis. */
     return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
@@ -2111,9 +2016,7 @@ and64_2_operand (op, mode)
    constant that can be used as the operand of an RS/6000 logical AND insn.  */
 
 int
-and_operand (op, mode)
-    rtx op;
-    enum machine_mode mode;
+and_operand (rtx op, enum machine_mode mode)
 {
   if (fixed_regs[CR0_REGNO])	/* CR0 not available, don't do andi./andis.  */
     return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
@@ -2124,9 +2027,7 @@ and_operand (op, mode)
 /* Return 1 if the operand is a general register or memory operand.  */
 
 int
-reg_or_mem_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_mem_operand (rtx op, enum machine_mode mode)
 {
   return (gpc_reg_operand (op, mode)
 	  || memory_operand (op, mode)
@@ -2138,9 +2039,7 @@ reg_or_mem_operand (op, mode)
    instruction.  */
 
 int
-lwa_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+lwa_operand (rtx op, enum machine_mode mode)
 {
   rtx inner = op;
 
@@ -2159,9 +2058,7 @@ lwa_operand (op, mode)
 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.  */
 
 int
-symbol_ref_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+symbol_ref_operand (rtx op, enum machine_mode mode)
 {
   if (mode != VOIDmode && GET_MODE (op) != mode)
     return 0;
@@ -2174,9 +2071,7 @@ symbol_ref_operand (op, mode)
    to CALL.  This is a SYMBOL_REF, a pseudo-register, LR or CTR.  */
 
 int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+call_operand (rtx op, enum machine_mode mode)
 {
   if (mode != VOIDmode && GET_MODE (op) != mode)
     return 0;
@@ -2192,9 +2087,8 @@ call_operand (op, mode)
    this file.  */
 
 int
-current_file_function_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+current_file_function_operand (rtx op, 
+                              enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == SYMBOL_REF
 	  && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
@@ -2205,9 +2099,7 @@ current_file_function_operand (op, mode)
 /* Return 1 if this operand is a valid input for a move insn.  */
 
 int
-input_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+input_operand (rtx op, enum machine_mode mode)
 {
   /* Memory is always valid.  */
   if (memory_operand (op, mode))
@@ -2267,9 +2159,8 @@ input_operand (op, mode)
 /* Return 1 for an operand in small memory on V.4/eabi.  */
 
 int
-small_data_operand (op, mode)
-     rtx op ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+small_data_operand (rtx op ATTRIBUTE_UNUSED, 
+		    enum machine_mode mode ATTRIBUTE_UNUSED)
 {
 #if TARGET_ELF
   rtx sym_ref;
@@ -2327,10 +2218,7 @@ altivec_in_gprs_p (rtx op0, rtx op1)
 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address.  */
 
 static int 
-constant_pool_expr_1 (op, have_sym, have_toc) 
-    rtx op;
-    int *have_sym;
-    int *have_toc;
+constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc) 
 {
   switch (GET_CODE(op)) 
     {
@@ -2368,8 +2256,7 @@ constant_pool_expr_1 (op, have_sym, have_toc)
 }
 
 static bool
-constant_pool_expr_p (op)
-    rtx op;
+constant_pool_expr_p (rtx op)
 {
   int have_sym = 0;
   int have_toc = 0;
@@ -2377,8 +2264,7 @@ constant_pool_expr_p (op)
 }
 
 static bool
-toc_relative_expr_p (op)
-    rtx op;
+toc_relative_expr_p (rtx op)
 {
   int have_sym = 0;
   int have_toc = 0;
@@ -2389,8 +2275,7 @@ toc_relative_expr_p (op)
 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
 
 bool
-legitimate_constant_pool_address_p (x)
-     rtx x;
+legitimate_constant_pool_address_p (rtx x)
 {
   return (TARGET_TOC
 	  && GET_CODE (x) == PLUS
@@ -2400,9 +2285,7 @@ legitimate_constant_pool_address_p (x)
 }
 
 static bool
-legitimate_small_data_p (mode, x)
-     enum machine_mode mode;
-     rtx x;
+legitimate_small_data_p (enum machine_mode mode, rtx x)
 {
   return (DEFAULT_ABI == ABI_V4
 	  && !flag_pic && !TARGET_TOC
@@ -2411,10 +2294,7 @@ legitimate_small_data_p (mode, x)
 }
 
 static bool
-legitimate_offset_address_p (mode, x, strict)
-     enum machine_mode mode;
-     rtx x;
-     int strict;
+legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
 {
   unsigned HOST_WIDE_INT offset, extra;
 
@@ -2473,9 +2353,7 @@ legitimate_offset_address_p (mode, x, strict)
 }
 
 static bool
-legitimate_indexed_address_p (x, strict)
-     rtx x;
-     int strict;
+legitimate_indexed_address_p (rtx x, int strict)
 {
   rtx op0, op1;
 
@@ -2494,18 +2372,13 @@ legitimate_indexed_address_p (x, strict)
 }
 
 static inline bool
-legitimate_indirect_address_p (x, strict)
-     rtx x;
-     int strict;
+legitimate_indirect_address_p (rtx x, int strict)
 {
   return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
 }
 
 static bool
-legitimate_lo_sum_address_p (mode, x, strict)
-     enum machine_mode mode;
-     rtx x;
-     int strict;
+legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
 {
   if (GET_CODE (x) != LO_SUM)
     return false;
@@ -2558,10 +2431,8 @@ legitimate_lo_sum_address_p (mode, x, strict)
    load the other things into a register and return the sum.  */
 
 rtx
-rs6000_legitimize_address (x, oldx, mode)
-     rtx x;
-     rtx oldx ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
+rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
+			   enum machine_mode mode)
 {
   if (GET_CODE (x) == SYMBOL_REF)
     {
@@ -2674,7 +2545,7 @@ rs6000_legitimize_address (x, oldx, mode)
 
 static GTY(()) rtx rs6000_tls_symbol;
 static rtx
-rs6000_tls_get_addr ()
+rs6000_tls_get_addr (void)
 {
   if (!rs6000_tls_symbol)
     rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
@@ -2686,7 +2557,7 @@ rs6000_tls_get_addr ()
 
 static GTY(()) rtx rs6000_got_symbol;
 static rtx
-rs6000_got_sym ()
+rs6000_got_sym (void)
 {
   if (!rs6000_got_symbol)
     {
@@ -2702,9 +2573,7 @@ rs6000_got_sym ()
    this (thread-local) address.  */
 
 static rtx
-rs6000_legitimize_tls_address (addr, model)
-     rtx addr;
-     enum tls_model model;
+rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
 {
   rtx dest, insn;
 
@@ -2890,9 +2759,7 @@ rs6000_legitimize_tls_address (addr, model)
    instruction definitions.  */
 
 int
-rs6000_tls_symbol_ref (x, mode)
-     rtx x;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return RS6000_SYMBOL_REF_TLS_P (x);
 }
@@ -2900,8 +2767,7 @@ rs6000_tls_symbol_ref (x, mode)
 /* Return 1 if X contains a thread-local symbol.  */
 
 bool
-rs6000_tls_referenced_p (x)
-     rtx x;
+rs6000_tls_referenced_p (rtx x)
 {
   return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
 }
@@ -2910,9 +2776,7 @@ rs6000_tls_referenced_p (x)
    rs6000_tls_symbol_ref except for the type of the unused argument.  */
 
 static inline int
-rs6000_tls_symbol_ref_1 (x, data)
-     rtx *x;
-     void *data ATTRIBUTE_UNUSED;
+rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
 {
   return RS6000_SYMBOL_REF_TLS_P (*x);
 }
@@ -2938,13 +2802,8 @@ rs6000_tls_symbol_ref_1 (x, data)
    The Darwin code is inside #if TARGET_MACHO because only then is
    machopic_function_base_name() defined.  */
 rtx
-rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
-    rtx x;
-    enum machine_mode mode;
-    int opnum;
-    int type;
-    int ind_levels ATTRIBUTE_UNUSED;
-    int *win;
+rs6000_legitimize_reload_address (rtx x, enum machine_mode mode, 
+	int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
 {
   /* We must recognize output that we have already generated ourselves.  */ 
   if (GET_CODE (x) == PLUS
@@ -3080,10 +2939,7 @@ rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win)
    adjacent memory cells are accessed by adding word-sized offsets
    during assembly output.  */
 int
-rs6000_legitimate_address (mode, x, reg_ok_strict)
-    enum machine_mode mode;
-    rtx x;
-    int reg_ok_strict;
+rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
 {
   if (RS6000_SYMBOL_REF_TLS_P (x))
     return 0;
@@ -3132,8 +2988,7 @@ rs6000_legitimate_address (mode, x, reg_ok_strict)
    sub-words of a TFmode operand, which is what we had before.  */
 
 bool
-rs6000_mode_dependent_address (addr)
-     rtx addr;
+rs6000_mode_dependent_address (rtx addr)
 {
   switch (GET_CODE (addr))
     {
@@ -3166,10 +3021,8 @@ rs6000_mode_dependent_address (addr)
    insns, zero is returned and no insns and emitted.  */
 
 rtx
-rs6000_emit_set_const (dest, mode, source, n)
-     rtx dest, source;
-     enum machine_mode mode;
-     int n ATTRIBUTE_UNUSED;
+rs6000_emit_set_const (rtx dest, enum machine_mode mode, 
+		       rtx source, int n ATTRIBUTE_UNUSED)
 {
   rtx result, insn, set;
   HOST_WIDE_INT c0, c1;
@@ -3231,9 +3084,7 @@ rs6000_emit_set_const (dest, mode, source, n)
    exponential run times encountered when looking for longer sequences
    with rs6000_emit_set_const.  */
 static rtx
-rs6000_emit_set_long_const (dest, c1, c2)
-     rtx dest;
-     HOST_WIDE_INT c1, c2;
+rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
 {
   if (!TARGET_POWERPC64)
     {
@@ -3317,10 +3168,7 @@ rs6000_emit_set_long_const (dest, c1, c2)
 
 /* Emit a move from SOURCE to DEST in mode MODE.  */
 void
-rs6000_emit_move (dest, source, mode)
-     rtx dest;
-     rtx source;
-     enum machine_mode mode;
+rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
 {
   rtx operands[2];
   operands[0] = dest;
@@ -3669,12 +3517,8 @@ rs6000_emit_move (dest, source, mode)
    so we never return a PARALLEL.  */
 
 void
-init_cumulative_args (cum, fntype, libname, incoming, libcall)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     rtx libname ATTRIBUTE_UNUSED;
-     int incoming;
-     int libcall;
+init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype, 
+	rtx libname ATTRIBUTE_UNUSED, int incoming, int libcall)
 {
   static CUMULATIVE_ARGS zero_cumulative;
 
@@ -3702,8 +3546,6 @@ init_cumulative_args (cum, fntype, libname, incoming, libcall)
   else
     cum->nargs_prototype = 0;
 
-  cum->orig_nargs = cum->nargs_prototype;
-
   /* Check for a longcall attribute.  */
   if (fntype
       && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
@@ -3738,21 +3580,52 @@ init_cumulative_args (cum, fntype, libname, incoming, libcall)
    argument slot.  */
 
 enum direction
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
+function_arg_padding (enum machine_mode mode, tree type)
 {
-  if (type != 0 && AGGREGATE_TYPE_P (type))
-    return upward;
+#ifndef AGGREGATE_PADDING_FIXED
+#define AGGREGATE_PADDING_FIXED 0
+#endif
+#ifndef AGGREGATES_PAD_UPWARD_ALWAYS
+#define AGGREGATES_PAD_UPWARD_ALWAYS 0
+#endif
+
+  if (!AGGREGATE_PADDING_FIXED)
+    {
+      /* GCC used to pass structures of the same size as integer types as
+	 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
+	 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
+	 passed padded downward, except that -mstrict-align further
+	 muddied the water in that multi-component structures of 2 and 4
+	 bytes in size were passed padded upward.
+
+	 The following arranges for best compatibility with previous
+	 versions of gcc, but removes the -mstrict-align dependency.  */
+      if (BYTES_BIG_ENDIAN)
+	{
+	  HOST_WIDE_INT size = 0;
+
+	  if (mode == BLKmode)
+	    {
+	      if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
+		size = int_size_in_bytes (type);
+	    }
+	  else
+	    size = GET_MODE_SIZE (mode);
 
-  /* This is the default definition.  */
-  return (! BYTES_BIG_ENDIAN
-	  ? upward
-	  : ((mode == BLKmode
-	      ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-		 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
-	      : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
-	     ? downward : upward));
+	  if (size == 1 || size == 2 || size == 4)
+	    return downward;
+	}
+      return upward;
+    }
+
+  if (AGGREGATES_PAD_UPWARD_ALWAYS)
+    {
+      if (type != 0 && AGGREGATE_TYPE_P (type))
+	return upward;
+    }
+
+  /* Fall back to the default.  */
+  return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
 }
 
 /* If defined, a C expression that gives the alignment boundary, in bits,
@@ -3762,9 +3635,7 @@ function_arg_padding (mode, type)
    V.4 wants long longs to be double word aligned.  */
 
 int
-function_arg_boundary (mode, type)
-     enum machine_mode mode;
-     tree type ATTRIBUTE_UNUSED;
+function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
 {
   if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode))
     return 64;
@@ -3781,11 +3652,8 @@ function_arg_boundary (mode, type)
    (TYPE is null for libcalls where that information may not be available.)  */
 
 void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
+function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, 
+		      tree type, int named)
 {
   cum->nargs_prototype--;
 
@@ -3880,7 +3748,8 @@ function_arg_advance (cum, mode, type, named)
 
 /* Determine where to put a SIMD argument on the SPE.  */
 static rtx
-rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type)
+rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, 
+			 tree type)
 {
   if (cum->stdarg)
     {
@@ -3938,11 +3807,8 @@ rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type
    doesn't support PARALLEL anyway.  */
 
 struct rtx_def *
-function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
+function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, 
+	      tree type, int named)
 {
   enum rs6000_abi abi = DEFAULT_ABI;
 
@@ -4065,11 +3931,8 @@ function_arg (cum, mode, type, named)
    For args passed entirely in registers or entirely in memory, zero.  */
 
 int
-function_arg_partial_nregs (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 
+			    tree type, int named ATTRIBUTE_UNUSED)
 {
   if (DEFAULT_ABI == ABI_V4)
     return 0;
@@ -4106,11 +3969,9 @@ function_arg_partial_nregs (cum, mode, type, named)
    reference.  */
 
 int
-function_arg_pass_by_reference (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 
+				enum machine_mode mode ATTRIBUTE_UNUSED, 
+				tree type, int named ATTRIBUTE_UNUSED)
 {
   if (DEFAULT_ABI == ABI_V4
       && ((type && AGGREGATE_TYPE_P (type))
@@ -4139,13 +4000,8 @@ function_arg_pass_by_reference (cum, mode, type, named)
    stack and set PRETEND_SIZE to the length of the registers pushed.  */
 
 void
-setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int *pretend_size ATTRIBUTE_UNUSED;
-     int no_rtl;
-
+setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, 
+		tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
 {
   CUMULATIVE_ARGS next_cum;
   int reg_size = TARGET_32BIT ? 4 : 8;
@@ -4233,7 +4089,7 @@ setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
 /* Create the va_list data type.  */
 
 tree
-rs6000_build_va_list ()
+rs6000_build_va_list (void)
 {
   tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
 
@@ -4281,9 +4137,7 @@ rs6000_build_va_list ()
 /* Implement va_start.  */
 
 void
-rs6000_va_start (valist, nextarg)
-     tree valist;
-     rtx nextarg;
+rs6000_va_start (tree valist, rtx nextarg)
 {
   HOST_WIDE_INT words, n_gpr, n_fpr;
   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
@@ -4347,8 +4201,7 @@ rs6000_va_start (valist, nextarg)
 /* Implement va_arg.  */
 
 rtx
-rs6000_va_arg (valist, type)
-     tree valist, type;
+rs6000_va_arg (tree valist, tree type)
 {
   tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
   tree gpr, fpr, ovf, sav, reg, t, u;
@@ -4973,18 +4826,13 @@ static struct builtin_description bdesc_1arg[] =
   { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
   { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
   { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
-  { 0, CODE_FOR_spe_evsplatfi, "__builtin_spe_evsplatfi", SPE_BUILTIN_EVSPLATFI },
-  { 0, CODE_FOR_spe_evsplati, "__builtin_spe_evsplati", SPE_BUILTIN_EVSPLATI },
 
   /* Place-holder.  Leave as last unary SPE builtin.  */
   { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
 };
 
 static rtx
-rs6000_expand_unop_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat;
   tree arg0 = TREE_VALUE (arglist);
@@ -5033,10 +4881,7 @@ rs6000_expand_unop_builtin (icode, arglist, target)
 }
 
 static rtx
-altivec_expand_abs_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat, scratch1, scratch2;
   tree arg0 = TREE_VALUE (arglist);
@@ -5068,10 +4913,7 @@ altivec_expand_abs_builtin (icode, arglist, target)
 }
 
 static rtx
-rs6000_expand_binop_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat;
   tree arg0 = TREE_VALUE (arglist);
@@ -5143,11 +4985,8 @@ rs6000_expand_binop_builtin (icode, arglist, target)
 }
 
 static rtx
-altivec_expand_predicate_builtin (icode, opcode, arglist, target)
-     enum insn_code icode;
-     const char *opcode;
-     tree arglist;
-     rtx target;
+altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode, 
+				  tree arglist, rtx target)
 {
   rtx pat, scratch;
   tree cr6_form = TREE_VALUE (arglist);
@@ -5224,9 +5063,7 @@ altivec_expand_predicate_builtin (icode, opcode, arglist, target)
 }
 
 static rtx
-altivec_expand_stv_builtin (icode, arglist)
-     enum insn_code icode;
-     tree arglist;
+altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
 {
   tree arg0 = TREE_VALUE (arglist);
   tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
@@ -5259,10 +5096,7 @@ altivec_expand_stv_builtin (icode, arglist)
 }
 
 static rtx
-rs6000_expand_ternop_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat;
   tree arg0 = TREE_VALUE (arglist);
@@ -5322,10 +5156,7 @@ rs6000_expand_ternop_builtin (icode, arglist, target)
 
 /* Expand the lvx builtins.  */
 static rtx
-altivec_expand_ld_builtin (exp, target, expandedp)
-     tree exp;
-     rtx target;
-     bool *expandedp;
+altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   tree arglist = TREE_OPERAND (exp, 1);
@@ -5378,10 +5209,8 @@ altivec_expand_ld_builtin (exp, target, expandedp)
 
 /* Expand the stvx builtins.  */
 static rtx
-altivec_expand_st_builtin (exp, target, expandedp)
-     tree exp;
-     rtx target ATTRIBUTE_UNUSED;
-     bool *expandedp;
+altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, 
+			   bool *expandedp)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   tree arglist = TREE_OPERAND (exp, 1);
@@ -5432,10 +5261,8 @@ altivec_expand_st_builtin (exp, target, expandedp)
 
 /* Expand the dst builtins.  */
 static rtx
-altivec_expand_dst_builtin (exp, target, expandedp)
-     tree exp;
-     rtx target ATTRIBUTE_UNUSED;
-     bool *expandedp;
+altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED, 
+			    bool *expandedp)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   tree arglist = TREE_OPERAND (exp, 1);
@@ -5495,10 +5322,7 @@ altivec_expand_dst_builtin (exp, target, expandedp)
 /* Expand the builtin in EXP and store the result in TARGET.  Store
    true in *EXPANDEDP if we found a builtin to expand.  */
 static rtx
-altivec_expand_builtin (exp, target, expandedp)
-     tree exp;
-     rtx target;
-     bool *expandedp;
+altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
 {
   struct builtin_description *d;
   struct builtin_description_predicates *dp;
@@ -5678,10 +5502,7 @@ static struct builtin_description bdesc_2arg_spe[] =
    This expands the SPE builtins that are not simple unary and binary
    operations.  */
 static rtx
-spe_expand_builtin (exp, target, expandedp)
-     tree exp;
-     rtx target;
-     bool *expandedp;
+spe_expand_builtin (tree exp, rtx target, bool *expandedp)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   tree arglist = TREE_OPERAND (exp, 1);
@@ -5717,6 +5538,19 @@ spe_expand_builtin (exp, target, expandedp)
       break;
     }
 
+  /* The evsplat*i instructions are not quite generic.  */
+  switch (fcode)
+    {
+    case SPE_BUILTIN_EVSPLATFI:
+      return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
+					 arglist, target);
+    case SPE_BUILTIN_EVSPLATI:
+      return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
+					 arglist, target);
+    default:
+      break;
+    }
+
   d = (struct builtin_description *) bdesc_2arg_spe;
   for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
     if (d->code == fcode)
@@ -5801,10 +5635,7 @@ spe_expand_builtin (exp, target, expandedp)
 }
 
 static rtx
-spe_expand_predicate_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat, scratch, tmp;
   tree form = TREE_VALUE (arglist);
@@ -5913,10 +5744,7 @@ spe_expand_predicate_builtin (icode, arglist, target)
 */
 
 static rtx
-spe_expand_evsel_builtin (icode, arglist, target)
-     enum insn_code icode;
-     tree arglist;
-     rtx target;
+spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
 {
   rtx pat, scratch;
   tree arg0 = TREE_VALUE (arglist);
@@ -5973,12 +5801,9 @@ spe_expand_evsel_builtin (icode, arglist, target)
    IGNORE is nonzero if the value is to be ignored.  */
 
 static rtx
-rs6000_expand_builtin (exp, target, subtarget, mode, ignore)
-     tree exp;
-     rtx target;
-     rtx subtarget ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     int ignore ATTRIBUTE_UNUSED;
+rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
+		      enum machine_mode mode ATTRIBUTE_UNUSED, 
+		      int ignore ATTRIBUTE_UNUSED)
 {
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
   tree arglist = TREE_OPERAND (exp, 1);
@@ -6029,7 +5854,7 @@ rs6000_expand_builtin (exp, target, subtarget, mode, ignore)
 }
 
 static void
-rs6000_init_builtins ()
+rs6000_init_builtins (void)
 {
   opaque_V2SI_type_node = copy_node (V2SI_type_node);
   opaque_V2SF_type_node = copy_node (V2SF_type_node);
@@ -6049,10 +5874,9 @@ rs6000_init_builtins ()
    START is the builtin enum at which to start.
    END is the builtin enum at which to end.  */
 static void
-enable_mask_for_builtins (desc, size, start, end)
-     struct builtin_description *desc;
-     int size;
-     enum rs6000_builtins start, end;
+enable_mask_for_builtins (struct builtin_description *desc, int size,
+			  enum rs6000_builtins start, 
+			  enum rs6000_builtins end)
 {
   int i;
 
@@ -6073,7 +5897,7 @@ enable_mask_for_builtins (desc, size, start, end)
 }
 
 static void
-spe_init_builtins ()
+spe_init_builtins (void)
 {
   tree endlink = void_list_node;
   tree puint_type_node = build_pointer_type (unsigned_type_node);
@@ -6172,6 +5996,11 @@ spe_init_builtins ()
 				      tree_cons (NULL_TREE, integer_type_node,
 						 endlink)));
 
+  tree v2si_ftype_signed_char
+    = build_function_type (opaque_V2SI_type_node,
+			   tree_cons (NULL_TREE, signed_char_type_node,
+				      endlink));
+
   /* The initialization of the simple binary and unary builtins is
      done in rs6000_common_init_builtins, but we have to enable the
      mask bits here manually because we have run out of `target_flags'
@@ -6194,6 +6023,10 @@ spe_init_builtins ()
 			    SPE_BUILTIN_EVSEL_CMPGTS,
 			    SPE_BUILTIN_EVSEL_FSTSTEQ);
 
+  (*lang_hooks.decls.pushdecl)
+    (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
+		 opaque_V2SI_type_node));
+
   /* Initialize irregular SPE builtins.  */
   
   def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
@@ -6212,6 +6045,8 @@ spe_init_builtins ()
   def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
   def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
   def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
+  def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
+  def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
 
   /* Loads.  */
   def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
@@ -6281,7 +6116,7 @@ spe_init_builtins ()
 }
 
 static void
-altivec_init_builtins ()
+altivec_init_builtins (void)
 {
   struct builtin_description *d;
   struct builtin_description_predicates *dp;
@@ -6480,7 +6315,7 @@ altivec_init_builtins ()
 }
 
 static void
-rs6000_common_init_builtins ()
+rs6000_common_init_builtins (void)
 {
   struct builtin_description *d;
   size_t i;
@@ -6950,8 +6785,7 @@ rs6000_common_init_builtins ()
 #define MAX_MOVE_REG 4
 
 int
-expand_block_move (operands)
-     rtx operands[];
+expand_block_move (rtx operands[])
 {
   rtx orig_dest = operands[0];
   rtx orig_src	= operands[1];
@@ -6987,8 +6821,8 @@ expand_block_move (operands)
   for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
     {
       union {
-	rtx (*movstrsi) PARAMS ((rtx, rtx, rtx, rtx));
-	rtx (*mov) PARAMS ((rtx, rtx));
+	rtx (*movstrsi) (rtx, rtx, rtx, rtx);
+	rtx (*mov) (rtx, rtx);
       } gen_func;
       enum machine_mode mode = BLKmode;
       rtx src, dest;
@@ -7118,9 +6952,7 @@ expand_block_move (operands)
    PARALLEL and the first section will be tested.  */
 
 int
-load_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int dest_regno;
@@ -7161,9 +6993,7 @@ load_multiple_operation (op, mode)
    is a CLOBBER.  It will be tested later.  */
 
 int
-store_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0) - 1;
   unsigned int src_regno;
@@ -7206,8 +7036,7 @@ store_multiple_operation (op, mode)
    operands[2] is the first destination register.  */
 
 const char *
-rs6000_output_load_multiple (operands)
-     rtx operands[3];
+rs6000_output_load_multiple (rtx operands[3])
 {
   /* We have to handle the case where the pseudo used to contain the address
      is assigned to one of the output registers.  */
@@ -7261,9 +7090,7 @@ rs6000_output_load_multiple (operands)
 /* Return 1 for a parallel vrsave operation.  */
 
 int
-vrsave_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int dest_regno, src_regno;
@@ -7297,9 +7124,7 @@ vrsave_operation (op, mode)
 /* Return 1 for an PARALLEL suitable for mfcr.  */
 
 int
-mfcr_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   int i;
@@ -7347,9 +7172,7 @@ mfcr_operation (op, mode)
 /* Return 1 for an PARALLEL suitable for mtcrf.  */
 
 int
-mtcrf_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   int i;
@@ -7396,9 +7219,7 @@ mtcrf_operation (op, mode)
 /* Return 1 for an PARALLEL suitable for lmw.  */
 
 int
-lmw_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int dest_regno;
@@ -7474,9 +7295,7 @@ lmw_operation (op, mode)
 /* Return 1 for an PARALLEL suitable for stmw.  */
 
 int
-stmw_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int src_regno;
@@ -7554,9 +7373,7 @@ stmw_operation (op, mode)
    never be generated.  */
 
 static void
-validate_condition_mode (code, mode)
-     enum rtx_code code;
-     enum machine_mode mode;
+validate_condition_mode (enum rtx_code code, enum machine_mode mode)
 {
   if (GET_RTX_CLASS (code) != '<' 
       || GET_MODE_CLASS (mode) != MODE_CC)
@@ -7597,9 +7414,7 @@ validate_condition_mode (code, mode)
    We only check the opcode against the mode of the CC value here.  */
 
 int
-branch_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
   enum machine_mode cc_mode;
@@ -7621,9 +7436,7 @@ branch_comparison_operator (op, mode)
    is set.  */
 
 int
-branch_positive_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
+branch_positive_comparison_operator (rtx op, enum machine_mode mode)
 {
   enum rtx_code code;
 
@@ -7641,17 +7454,13 @@ branch_positive_comparison_operator (op, mode)
    insn: it must be a positive comparison.  */
 
 int
-scc_comparison_operator (op, mode)
-     rtx op;
-     enum machine_mode mode;
+scc_comparison_operator (rtx op, enum machine_mode mode)
 {
   return branch_positive_comparison_operator (op, mode);
 }
 
 int
-trap_comparison_operator (op, mode)
-    rtx op;
-    enum machine_mode mode;
+trap_comparison_operator (rtx op, enum machine_mode mode)
 {
   if (mode != VOIDmode && mode != GET_MODE (op))
     return 0;
@@ -7659,27 +7468,21 @@ trap_comparison_operator (op, mode)
 }
 
 int
-boolean_operator (op, mode)
-    rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
+boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
   return (code == AND || code == IOR || code == XOR);
 }
 
 int
-boolean_or_operator (op, mode)
-    rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
+boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
   return (code == IOR || code == XOR);
 }
 
 int
-min_max_operator (op, mode)
-    rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
+min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
   return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
@@ -7690,9 +7493,7 @@ min_max_operator (op, mode)
    left insn of SHIFTOP bits.  Both are known to be SImode CONST_INT.  */
 
 int
-includes_lshift_p (shiftop, andop)
-     rtx shiftop;
-     rtx andop;
+includes_lshift_p (rtx shiftop, rtx andop)
 {
   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
 
@@ -7704,9 +7505,7 @@ includes_lshift_p (shiftop, andop)
 /* Similar, but for right shift.  */
 
 int
-includes_rshift_p (shiftop, andop)
-     rtx shiftop;
-     rtx andop;
+includes_rshift_p (rtx shiftop, rtx andop)
 {
   unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
 
@@ -7720,9 +7519,7 @@ includes_rshift_p (shiftop, andop)
    significant 0's, then one or more 1's, then zero or more 0's.  */
 
 int
-includes_rldic_lshift_p (shiftop, andop)
-     rtx shiftop;
-     rtx andop;
+includes_rldic_lshift_p (rtx shiftop, rtx andop)
 {
   if (GET_CODE (andop) == CONST_INT)
     {
@@ -7815,9 +7612,7 @@ includes_rldic_lshift_p (shiftop, andop)
    significant 0's, with the remainder of the word 1's.  */
 
 int
-includes_rldicr_lshift_p (shiftop, andop)
-     rtx shiftop;
-     rtx andop;
+includes_rldicr_lshift_p (rtx shiftop, rtx andop)
 {
   if (GET_CODE (andop) == CONST_INT)
     {
@@ -7889,8 +7684,7 @@ includes_rldicr_lshift_p (shiftop, andop)
    abort if we are passed pseudo registers.  */
 
 int
-registers_ok_for_quad_peep (reg1, reg2)
-     rtx reg1, reg2;
+registers_ok_for_quad_peep (rtx reg1, rtx reg2)
 {
   /* We might have been passed a SUBREG.  */
   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 
@@ -7904,9 +7698,7 @@ registers_ok_for_quad_peep (reg1, reg2)
    (addr2 == addr1 + 8).  */
 
 int
-addrs_ok_for_quad_peep (addr1, addr2)
-     rtx addr1;
-     rtx addr2;
+addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
 {
   unsigned int reg1;
   int offset1;
@@ -7935,9 +7727,9 @@ addrs_ok_for_quad_peep (addr1, addr2)
       offset1 = 0;
     }
 
-/* Make sure the second address is a (mem (plus (reg) (const_int)))
-    or if it is (mem (reg)) then make sure that offset1 is -8 and the same 
-    register as addr1.  */
+  /* Make sure the second address is a (mem (plus (reg) (const_int)))
+      or if it is (mem (reg)) then make sure that offset1 is -8 and the same 
+      register as addr1.  */
   if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
    return 1;
   if (GET_CODE (addr2) != PLUS)
@@ -7964,10 +7756,8 @@ addrs_ok_for_quad_peep (addr1, addr2)
    NO_REGS is returned.  */
 
 enum reg_class
-secondary_reload_class (class, mode, in)
-     enum reg_class class;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx in;
+secondary_reload_class (enum reg_class class, 
+		enum machine_mode mode ATTRIBUTE_UNUSED, rtx in)
 {
   int regno;
 
@@ -8045,9 +7835,7 @@ secondary_reload_class (class, mode, in)
    Return -1 if OP isn't a valid comparison for some reason.  */
 
 int
-ccr_bit (op, scc_p)
-     rtx op;
-     int scc_p;
+ccr_bit (rtx op, int scc_p)
 {
   enum rtx_code code = GET_CODE (op);
   enum machine_mode cc_mode;
@@ -8112,8 +7900,7 @@ ccr_bit (op, scc_p)
 /* Return the GOT register.  */
 
 struct rtx_def *
-rs6000_got_register (value)
-     rtx value ATTRIBUTE_UNUSED;
+rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
 {
   /* The second flow pass currently (June 1999) can't update
      regs_ever_live without disturbing other parts of the compiler, so
@@ -8131,7 +7918,7 @@ rs6000_got_register (value)
    from push_function_context.  */
 
 static struct machine_function *
-rs6000_init_machine_status ()
+rs6000_init_machine_status (void)
 {
   return ggc_alloc_cleared (sizeof (machine_function));
 }
@@ -8145,8 +7932,7 @@ rs6000_init_machine_status ()
   (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
 
 int
-extract_MB (op)
-     rtx op;
+extract_MB (rtx op)
 {
   int i;
   unsigned long val = INT_LOWPART (op);
@@ -8179,8 +7965,7 @@ extract_MB (op)
 }
 
 int
-extract_ME (op)
-     rtx op;
+extract_ME (rtx op)
 {
   int i;
   unsigned long val = INT_LOWPART (op);
@@ -8217,7 +8002,7 @@ extract_ME (op)
    so that we can print its name in some tls_ld pattern.  */
 
 static const char *
-rs6000_get_some_local_dynamic_name ()
+rs6000_get_some_local_dynamic_name (void)
 {
   rtx insn;
 
@@ -8236,9 +8021,7 @@ rs6000_get_some_local_dynamic_name ()
 /* Helper function for rs6000_get_some_local_dynamic_name.  */
 
 static int
-rs6000_get_some_local_dynamic_name_1 (px, data)
-     rtx *px;
-     void *data ATTRIBUTE_UNUSED;
+rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
 {
   rtx x = *px;
 
@@ -8266,10 +8049,7 @@ rs6000_get_some_local_dynamic_name_1 (px, data)
 #endif
 
 void
-print_operand (file, x, code)
-    FILE *file;
-    rtx x;
-    int code;
+print_operand (FILE *file, rtx x, int code)
 {
   int i;
   HOST_WIDE_INT val;
@@ -8887,9 +8667,7 @@ print_operand (file, x, code)
 /* Print the address of an operand.  */
 
 void
-print_operand_address (file, x)
-     FILE *file;
-     rtx x;
+print_operand_address (FILE *file, rtx x)
 {
   if (GET_CODE (x) == REG)
     fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
@@ -8978,16 +8756,13 @@ print_operand_address (file, x)
    targets.  */
 
 static bool
-rs6000_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
 #ifdef RELOCATABLE_NEEDS_FIXUP
   /* Special handling for SI values.  */
   if (size == 4 && aligned_p)
     {
-      extern int in_toc_section PARAMS ((void));
+      extern int in_toc_section (void);
       static int recurse = 0;
       
       /* For -mrelocatable, we mark all addresses that need to be fixed up
@@ -9041,9 +8816,7 @@ rs6000_assemble_integer (x, size, aligned_p)
    VISIBILITY_TYPE.  */
 
 static void
-rs6000_assemble_visibility (decl, vis)
-     tree decl;
-     int vis;
+rs6000_assemble_visibility (tree decl, int vis)
 {
   /* Functions need to have their entry point symbol visibility set as
      well as their descriptor symbol visibility.  */
@@ -9068,9 +8841,7 @@ rs6000_assemble_visibility (decl, vis)
 #endif
 
 enum rtx_code
-rs6000_reverse_condition (mode, code)
-     enum machine_mode mode;
-     enum rtx_code code;
+rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
 {
   /* Reversal of FP compares takes care -- an ordered compare
      becomes an unordered compare and vice versa.  */
@@ -9087,8 +8858,7 @@ rs6000_reverse_condition (mode, code)
    represents the result of the compare.  */
 
 static rtx
-rs6000_generate_compare (code)
-     enum rtx_code code;
+rs6000_generate_compare (enum rtx_code code)
 {
   enum machine_mode comp_mode;
   rtx compare_result;
@@ -9272,9 +9042,7 @@ rs6000_generate_compare (code)
 /* Emit the RTL for an sCOND pattern.  */
 
 void
-rs6000_emit_sCOND (code, result)
-     enum rtx_code code;
-     rtx result;
+rs6000_emit_sCOND (enum rtx_code code, rtx result)
 {
   rtx condition_rtx;
   enum machine_mode op_mode;
@@ -9320,9 +9088,7 @@ rs6000_emit_sCOND (code, result)
 /* Emit a branch of kind CODE to location LOC.  */
 
 void
-rs6000_emit_cbranch (code, loc)
-     enum rtx_code code;
-     rtx loc;
+rs6000_emit_cbranch (enum rtx_code code, rtx loc)
 {
   rtx condition_rtx, loc_ref;
 
@@ -9346,11 +9112,7 @@ rs6000_emit_cbranch (code, loc)
    INSN is the insn.  */
 
 char *
-output_cbranch (op, label, reversed, insn)
-     rtx op;
-     const char * label;
-     int reversed;
-     rtx insn;
+output_cbranch (rtx op, const char *label, int reversed, rtx insn)
 {
   static char string[64];
   enum rtx_code code = GET_CODE (op);
@@ -9472,11 +9234,7 @@ output_cbranch (op, label, reversed, insn)
    is zero/false.  Return 0 if the hardware has no such operation.  */
 
 int
-rs6000_emit_cmove (dest, op, true_cond, false_cond)
-     rtx dest;
-     rtx op;
-     rtx true_cond;
-     rtx false_cond;
+rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
 {
   enum rtx_code code = GET_CODE (op);
   rtx op0 = rs6000_compare_op0;
@@ -9641,11 +9399,7 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond)
 /* Same as above, but for ints (isel).  */
 
 static int
-rs6000_emit_int_cmove (dest, op, true_cond, false_cond)
-     rtx dest;
-     rtx op;
-     rtx true_cond;
-     rtx false_cond;
+rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
 {
   rtx condition_rtx, cr;
 
@@ -9670,8 +9424,7 @@ rs6000_emit_int_cmove (dest, op, true_cond, false_cond)
 }
 
 const char *
-output_isel (operands)
-     rtx *operands;
+output_isel (rtx *operands)
 {
   enum rtx_code code;
 
@@ -9686,11 +9439,7 @@ output_isel (operands)
 }
 
 void
-rs6000_emit_minmax (dest, code, op0, op1)
-     rtx dest;
-     enum rtx_code code;
-     rtx op0;
-     rtx op1;
+rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
 {
   enum machine_mode mode = GET_MODE (op0);
   enum rtx_code c;
@@ -9797,7 +9546,7 @@ rs6000_split_altivec_in_gprs (rtx *operands)
    saved. 32 if none.  */
 
 int
-first_reg_to_save ()
+first_reg_to_save (void)
 {
   int first_reg;
 
@@ -9823,7 +9572,7 @@ first_reg_to_save ()
 /* Similar, for FP regs.  */
 
 int
-first_fp_reg_to_save ()
+first_fp_reg_to_save (void)
 {
   int first_reg;
 
@@ -9838,7 +9587,7 @@ first_fp_reg_to_save ()
 /* Similar, for AltiVec regs.  */
 
 static int
-first_altivec_reg_to_save ()
+first_altivec_reg_to_save (void)
 {
   int i;
 
@@ -9859,7 +9608,7 @@ first_altivec_reg_to_save ()
    the 32-bit word is 0.  */
 
 static unsigned int
-compute_vrsave_mask ()
+compute_vrsave_mask (void)
 {
   unsigned int i, mask = 0;
 
@@ -9891,9 +9640,7 @@ compute_vrsave_mask ()
 }
 
 static void
-is_altivec_return_reg (reg, xyes)
-     rtx reg;
-     void *xyes;
+is_altivec_return_reg (rtx reg, void *xyes)
 {
   bool *yes = (bool *) xyes;
   if (REGNO (reg) == ALTIVEC_ARG_RETURN)
@@ -9999,7 +9746,7 @@ is_altivec_return_reg (reg, xyes)
 #endif
 
 rs6000_stack_t *
-rs6000_stack_info ()
+rs6000_stack_info (void)
 {
   static rs6000_stack_t info, zero_info;
   rs6000_stack_t *info_ptr = &info;
@@ -10308,7 +10055,7 @@ rs6000_stack_info ()
    mode.  */
 
 static bool
-spe_func_has_64bit_regs_p ()
+spe_func_has_64bit_regs_p (void)
 {
   rtx insns, insn;
 
@@ -10338,8 +10085,7 @@ spe_func_has_64bit_regs_p ()
 }
 
 void
-debug_stack_info (info)
-     rs6000_stack_t *info;
+debug_stack_info (rs6000_stack_t *info)
 {
   const char *abi_string;
 
@@ -10483,9 +10229,7 @@ debug_stack_info (info)
 }
 
 rtx
-rs6000_return_addr (count, frame)
-     int count;
-     rtx frame;
+rs6000_return_addr (int count, rtx frame)
 {
   /* Currently we don't optimize very well between prolog and body
      code and for PIC code the code can be actually quite bad, so
@@ -10505,6 +10249,7 @@ rs6000_return_addr (count, frame)
 			   RETURN_ADDRESS_OFFSET)));
     }
 
+  cfun->machine->ra_need_lr = 1;
   return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
 }
 
@@ -10516,9 +10261,7 @@ rs6000_return_addr (count, frame)
    type info must be available here.  (The tail recursion case can work
    with vector parameters, but there's no way to distinguish here.) */
 static bool
-rs6000_function_ok_for_sibcall (decl, exp)
-    tree decl;
-    tree exp ATTRIBUTE_UNUSED;
+rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
   tree type;
   if (decl)
@@ -10546,7 +10289,7 @@ rs6000_function_ok_for_sibcall (decl, exp)
 }
 
 static int
-rs6000_ra_ever_killed ()
+rs6000_ra_ever_killed (void)
 {
   rtx top;
   rtx reg;
@@ -10599,8 +10342,7 @@ rs6000_ra_ever_killed ()
 
 /* Add a REG_MAYBE_DEAD note to the insn.  */
 static void
-rs6000_maybe_dead (insn)
-     rtx insn;
+rs6000_maybe_dead (rtx insn)
 {
   REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
 					const0_rtx,
@@ -10612,8 +10354,7 @@ rs6000_maybe_dead (insn)
    a constant pool; or for SVR4 -fpic.  */
 
 void
-rs6000_emit_load_toc_table (fromprolog)
-     int fromprolog;
+rs6000_emit_load_toc_table (int fromprolog)
 {
   rtx dest, insn;
   dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
@@ -10712,7 +10453,7 @@ rs6000_emit_load_toc_table (fromprolog)
 }
 
 int   
-get_TOC_alias_set ()
+get_TOC_alias_set (void)
 {
     static int set = -1;
     if (set == -1)
@@ -10753,8 +10494,7 @@ uses_TOC ()
 }
 
 rtx
-create_TOC_reference (symbol) 
-    rtx symbol;
+create_TOC_reference (rtx symbol) 
 {
   return gen_rtx_PLUS (Pmode, 
 	   gen_rtx_REG (Pmode, TOC_REGISTER),
@@ -10763,139 +10503,47 @@ create_TOC_reference (symbol)
 		 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
 }
 
-/* __throw will restore its own return address to be the same as the
-   return address of the function that the throw is being made to.
-   This is unfortunate, because we want to check the original
-   return address to see if we need to restore the TOC.
-   So we have to squirrel it away here.  
-   This is used only in compiling __throw and __rethrow. 
-
-   Most of this code should be removed by CSE.  */
-static rtx insn_after_throw;
+/* If _Unwind_* has been called from within the same module,
+   toc register is not guaranteed to be saved to 40(1) on function
+   entry.  Save it there in that case.  */
 
-/* This does the saving...  */
 void
-rs6000_aix_emit_builtin_unwind_init ()
+rs6000_aix_emit_builtin_unwind_init (void)
 {
   rtx mem;
   rtx stack_top = gen_reg_rtx (Pmode);
   rtx opcode_addr = gen_reg_rtx (Pmode);
-
-  insn_after_throw = gen_reg_rtx (SImode);
+  rtx opcode = gen_reg_rtx (SImode);
+  rtx tocompare = gen_reg_rtx (SImode);
+  rtx no_toc_save_needed = gen_label_rtx ();
 
   mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
   emit_move_insn (stack_top, mem);
 
-  mem = gen_rtx_MEM (Pmode, 
-		     gen_rtx_PLUS (Pmode, stack_top, 
+  mem = gen_rtx_MEM (Pmode,
+		     gen_rtx_PLUS (Pmode, stack_top,
 				   GEN_INT (2 * GET_MODE_SIZE (Pmode))));
   emit_move_insn (opcode_addr, mem);
-  emit_move_insn (insn_after_throw, gen_rtx_MEM (SImode, opcode_addr));
-}
-
-/* Emit insns to _restore_ the TOC register, at runtime (specifically
-   in _eh.o).  Only used on AIX.
-
-   The idea is that on AIX, function calls look like this:
-	bl  somefunction-trampoline
-	lwz r2,20(sp)
-
-   and later,
-	somefunction-trampoline:
-	stw r2,20(sp)
-	 ... load function address in the count register ...
-	bctr
-   or like this, if the linker determines that this is not a cross-module call
-   and so the TOC need not be restored:
-	bl  somefunction
-	nop
-   or like this, if the compiler could determine that this is not a
-   cross-module call:
-	bl  somefunction
-   now, the tricky bit here is that register 2 is saved and restored
-   by the _linker_, so we can't readily generate debugging information
-   for it.  So we need to go back up the call chain looking at the
-   insns at return addresses to see which calls saved the TOC register
-   and so see where it gets restored from.
-
-   Oh, and all this gets done in RTL inside the eh_epilogue pattern,
-   just before the actual epilogue.
-
-   On the bright side, this incurs no space or time overhead unless an
-   exception is thrown, except for the extra code in libgcc.a.  
-
-   The parameter STACKSIZE is a register containing (at runtime)
-   the amount to be popped off the stack in addition to the stack frame
-   of this routine (which will be __throw or __rethrow, and so is
-   guaranteed to have a stack frame).  */
-
-void
-rs6000_emit_eh_toc_restore (stacksize)
-     rtx stacksize;
-{
-  rtx top_of_stack;
-  rtx bottom_of_stack = gen_reg_rtx (Pmode);
-  rtx tocompare = gen_reg_rtx (SImode);
-  rtx opcode = gen_reg_rtx (SImode);
-  rtx opcode_addr = gen_reg_rtx (Pmode);
-  rtx mem;
-  rtx loop_start = gen_label_rtx ();
-  rtx no_toc_restore_needed = gen_label_rtx ();
-  rtx loop_exit = gen_label_rtx ();
-  
-  mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
-  set_mem_alias_set (mem, rs6000_sr_alias_set);
-  emit_move_insn (bottom_of_stack, mem);
-
-  top_of_stack = expand_binop (Pmode, add_optab, 
-			       bottom_of_stack, stacksize,
-			       NULL_RTX, 1, OPTAB_WIDEN);
-
-  emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 
+  emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
+  emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
 					   : 0xE8410028, SImode));
 
-  if (insn_after_throw == NULL_RTX)
-    abort ();
-  emit_move_insn (opcode, insn_after_throw);
-  
-  emit_note (NOTE_INSN_LOOP_BEG);
-  emit_label (loop_start);
-  
-  do_compare_rtx_and_jump (opcode, tocompare, NE, 1,
+  do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
 			   SImode, NULL_RTX, NULL_RTX,
-			   no_toc_restore_needed);
-  
-  mem = gen_rtx_MEM (Pmode, 
-		     gen_rtx_PLUS (Pmode, bottom_of_stack, 
-				   GEN_INT (5 * GET_MODE_SIZE (Pmode))));
-  emit_move_insn (gen_rtx_REG (Pmode, 2), mem);
-
-  emit_label (no_toc_restore_needed);
-  do_compare_rtx_and_jump (top_of_stack, bottom_of_stack, EQ, 1,
-			   Pmode, NULL_RTX, NULL_RTX,
-			   loop_exit);
-
-  mem = gen_rtx_MEM (Pmode, bottom_of_stack);
-  set_mem_alias_set (mem, rs6000_sr_alias_set);
-  emit_move_insn (bottom_of_stack, mem);
-  
-  mem = gen_rtx_MEM (Pmode, 
-		     gen_rtx_PLUS (Pmode, bottom_of_stack, 
-				   GEN_INT (2 * GET_MODE_SIZE (Pmode))));
-  emit_move_insn (opcode_addr, mem);
-  emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
+			   no_toc_save_needed);
 
-  emit_note (NOTE_INSN_LOOP_CONT);
-  emit_jump (loop_start);
-  emit_note (NOTE_INSN_LOOP_END);
-  emit_label (loop_exit);
+  mem = gen_rtx_MEM (Pmode,
+		     gen_rtx_PLUS (Pmode, stack_top,
+				   GEN_INT (5 * GET_MODE_SIZE (Pmode))));
+  emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
+  emit_label (no_toc_save_needed);
 }
 
 /* This ties together stack memory (MEM with an alias set of
    rs6000_sr_alias_set) and the change to the stack pointer.  */
 
 static void
-rs6000_emit_stack_tie ()
+rs6000_emit_stack_tie (void)
 {
   rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
 
@@ -10908,9 +10556,7 @@ rs6000_emit_stack_tie ()
    The generated code may use hard register 0 as a temporary.  */
 
 static void
-rs6000_emit_allocate_stack (size, copy_r12)
-     HOST_WIDE_INT size;
-     int copy_r12;
+rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
 {
   rtx insn;
   rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
@@ -10998,12 +10644,8 @@ rs6000_emit_allocate_stack (size, copy_r12)
    its hand so much.  */
 
 static void
-rs6000_frame_related (insn, reg, val, reg2, rreg)
-     rtx insn;
-     rtx reg;
-     HOST_WIDE_INT val;
-     rtx reg2;
-     rtx rreg;
+rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, 
+		      rtx reg2, rtx rreg)
 {
   rtx real, temp;
 
@@ -11085,8 +10727,7 @@ rs6000_frame_related (insn, reg, val, reg2, rreg)
    original note, plus a synthetic register save.  */
 
 static rtx
-spe_synthesize_frame_save (real)
-     rtx real;
+spe_synthesize_frame_save (rtx real)
 {
   rtx synth, offset, reg, real2;
 
@@ -11149,10 +10790,7 @@ spe_synthesize_frame_save (real)
    appropriate CLOBBERs.  */
 
 static rtx
-generate_set_vrsave (reg, info, epiloguep)
-     rtx reg;
-     rs6000_stack_t *info;
-     int epiloguep;
+generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
 {
   int nclobs, i;
   rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
@@ -11211,13 +10849,8 @@ generate_set_vrsave (reg, info, epiloguep)
    Save REGNO into [FRAME_REG + OFFSET] in mode MODE.  */
 
 static void
-emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size)
-     rtx frame_reg;
-     rtx frame_ptr;
-     enum machine_mode mode;
-     unsigned int regno;
-     int offset;
-     int total_size;
+emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode, 
+		 unsigned int regno, int offset, int total_size)
 {
   rtx reg, offset_rtx, insn, mem, addr, int_rtx;
   rtx replacea, replaceb;
@@ -11259,10 +10892,7 @@ emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size)
    converting to a valid addressing mode.  */
 
 static rtx
-gen_frame_mem_offset (mode, reg, offset)
-     enum machine_mode mode;
-     rtx reg;
-     int offset;
+gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
 {
   rtx int_rtx, offset_rtx;
 
@@ -11282,7 +10912,7 @@ gen_frame_mem_offset (mode, reg, offset)
 /* Emit function prologue as insns.  */
 
 void
-rs6000_emit_prologue ()
+rs6000_emit_prologue (void)
 {
   rs6000_stack_t *info = rs6000_stack_info ();
   enum machine_mode reg_mode = TARGET_POWERPC64 ? DImode : SImode;
@@ -11307,10 +10937,14 @@ rs6000_emit_prologue ()
 			      || info->spe_64bit_regs_used == 0)
 			  && info->first_gp_reg_save < 31);
   saving_FPRs_inline = (info->first_fp_reg_save == 64
-			|| FP_SAVE_INLINE (info->first_fp_reg_save));
+			|| FP_SAVE_INLINE (info->first_fp_reg_save)
+			|| current_function_calls_eh_return
+			|| cfun->machine->ra_need_lr);
 
   /* For V.4, update stack before we do any saving and set back pointer.  */
-  if (info->push_p && DEFAULT_ABI == ABI_V4)
+  if (info->push_p
+      && (DEFAULT_ABI == ABI_V4
+	  || current_function_calls_eh_return))
     {
       if (info->total_size < 32767)
 	sp_offset = info->total_size;
@@ -11538,6 +11172,23 @@ rs6000_emit_prologue ()
     {
       unsigned int i, regno;
 
+      /* In AIX ABI we need to pretend we save r2 here.  */
+      if (TARGET_AIX)
+	{
+	  rtx addr, reg, mem;
+
+	  reg = gen_rtx_REG (reg_mode, 2);
+	  addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
+			       GEN_INT (sp_offset + 5 * reg_size));
+	  mem = gen_rtx_MEM (reg_mode, addr);
+	  set_mem_alias_set (mem, rs6000_sr_alias_set);
+
+	  insn = emit_move_insn (mem, reg);
+	  rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, 
+				NULL_RTX, NULL_RTX);
+	  PATTERN (insn) = gen_blockage ();
+	}
+
       for (i = 0; ; ++i)
 	{
 	  regno = EH_RETURN_DATA_REGNO (i);
@@ -11596,7 +11247,8 @@ rs6000_emit_prologue ()
 
   /* Update stack and set back pointer unless this is V.4, 
      for which it was done previously.  */
-  if (info->push_p && DEFAULT_ABI != ABI_V4)
+  if (info->push_p
+      && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
     rs6000_emit_allocate_stack (info->total_size, FALSE);
 
   /* Set frame pointer, if needed.  */
@@ -11652,9 +11304,8 @@ rs6000_emit_prologue ()
 /* Write function prologue.  */
 
 static void
-rs6000_output_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+rs6000_output_function_prologue (FILE *file, 
+				 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   rs6000_stack_t *info = rs6000_stack_info ();
 
@@ -11720,8 +11371,7 @@ rs6000_output_function_prologue (file, size)
    need special notes to explain where r11 is in relation to the stack.  */
 
 void
-rs6000_emit_epilogue (sibcall)
-     int sibcall;
+rs6000_emit_epilogue (int sibcall)
 {
   rs6000_stack_t *info;
   int restoring_FPRs_inline;
@@ -11775,7 +11425,8 @@ rs6000_emit_epilogue (sibcall)
     }
   else if (info->push_p)
     {
-      if (DEFAULT_ABI == ABI_V4)
+      if (DEFAULT_ABI == ABI_V4
+	  || current_function_calls_eh_return)
 	sp_offset = info->total_size;
       else
 	{
@@ -11860,6 +11511,17 @@ rs6000_emit_epilogue (sibcall)
     {
       unsigned int i, regno;
 
+      if (TARGET_AIX)
+	{
+	  rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
+				   GEN_INT (sp_offset + 5 * reg_size));
+	  rtx mem = gen_rtx_MEM (reg_mode, addr);
+
+	  set_mem_alias_set (mem, rs6000_sr_alias_set);
+
+	  emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
+	}
+
       for (i = 0; ; ++i)
 	{
 	  rtx mem;
@@ -12011,7 +11673,8 @@ rs6000_emit_epilogue (sibcall)
      (which may not have any obvious dependency on the stack).  This
      doesn't hurt performance, because there is no scheduling that can
      be done after this point.  */
-  if (DEFAULT_ABI == ABI_V4)
+  if (DEFAULT_ABI == ABI_V4
+      || current_function_calls_eh_return)
     {
       if (frame_reg_rtx != sp_reg_rtx)
 	  rs6000_emit_stack_tie ();
@@ -12088,9 +11751,8 @@ rs6000_emit_epilogue (sibcall)
 /* Write function epilogue.  */
 
 static void
-rs6000_output_function_epilogue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
+rs6000_output_function_epilogue (FILE *file, 
+				 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
 {
   rs6000_stack_t *info = rs6000_stack_info ();
 
@@ -12131,6 +11793,23 @@ rs6000_output_function_epilogue (file, size)
 	}
     }
 
+#if TARGET_OBJECT_FORMAT == OBJECT_MACHO
+  /* Mach-O doesn't support labels at the end of objects, so if
+     it looks like we might want one, insert a NOP.  */
+  {
+    rtx insn = get_last_insn ();
+    while (insn
+	   && NOTE_P (insn)
+	   && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
+      insn = PREV_INSN (insn);
+    if (insn 
+	&& (LABEL_P (insn) 
+	    || (NOTE_P (insn)
+		&& NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
+      fputs ("\tnop\n", file);
+  }
+#endif
+
   /* Output a traceback table here.  See /usr/include/sys/debug.h for info
      on its format.
 
@@ -12392,12 +12071,9 @@ rs6000_output_function_epilogue (file, size)
    not support varargs.  */
 
 static void
-rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk_fndecl ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset;
-     tree function;
+rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 
+			HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 
+			tree function)
 {
   rtx this, insn, funexp;
 
@@ -12410,7 +12086,7 @@ rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
 
   /* Find the "this" pointer.  If the function returns a structure,
      the structure return pointer is in r3.  */
-  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     this = gen_rtx_REG (Pmode, 4);
   else
     this = gen_rtx_REG (Pmode, 3);
@@ -12524,8 +12200,7 @@ rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
 /* Hash functions for the hash table.  */
 
 static unsigned
-rs6000_hash_constant (k)
-     rtx k;
+rs6000_hash_constant (rtx k)
 {
   enum rtx_code code = GET_CODE (k);
   enum machine_mode mode = GET_MODE (k);
@@ -12598,8 +12273,7 @@ rs6000_hash_constant (k)
 }
 
 static unsigned
-toc_hash_function (hash_entry)
-     const void * hash_entry;
+toc_hash_function (const void *hash_entry)
 {
   const struct toc_hash_struct *thc = 
     (const struct toc_hash_struct *) hash_entry;
@@ -12609,9 +12283,7 @@ toc_hash_function (hash_entry)
 /* Compare H1 and H2 for equivalence.  */
 
 static int
-toc_hash_eq (h1, h2)
-     const void * h1;
-     const void * h2;
+toc_hash_eq (const void *h1, const void *h2)
 {
   rtx r1 = ((const struct toc_hash_struct *) h1)->key;
   rtx r2 = ((const struct toc_hash_struct *) h2)->key;
@@ -12635,9 +12307,7 @@ toc_hash_eq (h1, h2)
   || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0) 
 
 void
-rs6000_output_symbol_ref (file, x)
-     FILE *file;
-     rtx x;
+rs6000_output_symbol_ref (FILE *file, rtx x)
 {
   /* Currently C++ toc references to vtables can be emitted before it
      is decided whether the vtable is public or private.  If this is
@@ -12659,11 +12329,7 @@ rs6000_output_symbol_ref (file, x)
    written.  */
 
 void
-output_toc (file, x, labelno, mode)
-     FILE *file;
-     rtx x;
-     int labelno;
-     enum machine_mode mode;
+output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
 {
   char buf[256];
   const char *name = buf;
@@ -12963,10 +12629,7 @@ output_toc (file, x, labelno, mode)
    so we must artificially break them up early.  */
 
 void
-output_ascii (file, p, n)
-     FILE *file;
-     const char *p;
-     int n;
+output_ascii (FILE *file, const char *p, int n)
 {
   char c;
   int i, count_string;
@@ -13037,10 +12700,8 @@ output_ascii (file, p, n)
    the name.  */
 
 void
-rs6000_gen_section_name (buf, filename, section_desc)
-     char **buf;
-     const char *filename;
-     const char *section_desc;
+rs6000_gen_section_name (char **buf, const char *filename, 
+		         const char *section_desc)
 {
   const char *q, *after_last_slash, *last_period = 0;
   char *p;
@@ -13083,8 +12744,7 @@ rs6000_gen_section_name (buf, filename, section_desc)
 /* Emit profile function.  */
 
 void
-output_profile_hook (labelno)
-     int labelno ATTRIBUTE_UNUSED;
+output_profile_hook (int labelno ATTRIBUTE_UNUSED)
 {
   if (TARGET_PROFILE_KERNEL)
     return;
@@ -13137,9 +12797,7 @@ output_profile_hook (labelno)
 /* Write function profiler code.  */
 
 void
-output_function_profiler (file, labelno)
-  FILE *file;
-  int labelno;
+output_function_profiler (FILE *file, int labelno)
 {
   char buf[100];
   int save_lr = 8;
@@ -13229,7 +12887,7 @@ output_function_profiler (file, labelno)
 
 
 static int
-rs6000_use_dfa_pipeline_interface ()
+rs6000_use_dfa_pipeline_interface (void)
 {
   return 1;
 }
@@ -13241,11 +12899,9 @@ rs6000_use_dfa_pipeline_interface ()
    instructions to issue in this cycle.  */
 
 static int
-rs6000_variable_issue (stream, verbose, insn, more)
-  FILE *stream ATTRIBUTE_UNUSED;
-  int verbose ATTRIBUTE_UNUSED;
-  rtx insn;
-  int more;
+rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED, 
+		       int verbose ATTRIBUTE_UNUSED, 
+		       rtx insn, int more)
 {
   if (GET_CODE (PATTERN (insn)) == USE
       || GET_CODE (PATTERN (insn)) == CLOBBER)
@@ -13276,11 +12932,8 @@ rs6000_variable_issue (stream, verbose, insn, more)
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
 static int
-rs6000_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn ATTRIBUTE_UNUSED;
-     int cost;
+rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED, 
+		    int cost)
 {
   if (! recog_memoized (insn))
     return 0;
@@ -13340,9 +12993,7 @@ rs6000_adjust_cost (insn, link, dep_insn, cost)
    priorities of insns.  */
 
 static int
-rs6000_adjust_priority (insn, priority)
-     rtx insn ATTRIBUTE_UNUSED;
-     int priority;
+rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
 {
   /* On machines (like the 750) which have asymmetric integer units,
      where one integer unit can do multiply and divides and the other
@@ -13380,7 +13031,7 @@ rs6000_adjust_priority (insn, priority)
 /* Return how many instructions the machine can issue per cycle.  */
 
 static int
-rs6000_issue_rate ()
+rs6000_issue_rate (void)
 {
   /* Use issue rate of 1 for first scheduling pass to decrease degradation.  */
   if (!reload_completed)
@@ -13414,7 +13065,7 @@ rs6000_issue_rate ()
    scheduling.  */
 
 static int
-rs6000_use_sched_lookahead ()
+rs6000_use_sched_lookahead (void)
 {
   if (rs6000_cpu_attr == CPU_PPC8540)
     return 4;
@@ -13425,7 +13076,7 @@ rs6000_use_sched_lookahead ()
 /* Length in units of the trampoline for entering a nested function.  */
 
 int
-rs6000_trampoline_size ()
+rs6000_trampoline_size (void)
 {
   int ret = 0;
 
@@ -13452,10 +13103,7 @@ rs6000_trampoline_size ()
    CXT is an RTX for the static chain value for the function.  */
 
 void
-rs6000_initialize_trampoline (addr, fnaddr, cxt)
-     rtx addr;
-     rtx fnaddr;
-     rtx cxt;
+rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
 {
   enum machine_mode pmode = Pmode;
   int regsize = (TARGET_32BIT) ? 4 : 8;
@@ -13514,12 +13162,10 @@ const struct attribute_spec rs6000_attribute_table[] =
    struct attribute_spec.handler.  */
 
 static tree
-rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs)
-     tree *node;
-     tree name;
-     tree args ATTRIBUTE_UNUSED;
-     int flags ATTRIBUTE_UNUSED;
-     bool *no_add_attrs;
+rs6000_handle_longcall_attribute (tree *node, tree name, 
+				  tree args ATTRIBUTE_UNUSED, 
+				  int flags ATTRIBUTE_UNUSED, 
+				  bool *no_add_attrs)
 {
   if (TREE_CODE (*node) != FUNCTION_TYPE
       && TREE_CODE (*node) != FIELD_DECL
@@ -13536,8 +13182,7 @@ rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs)
 /* Set longcall attributes on all functions declared when
    rs6000_default_long_calls is true.  */
 static void
-rs6000_set_default_type_attributes (type)
-     tree type;
+rs6000_set_default_type_attributes (tree type)
 {
   if (rs6000_default_long_calls
       && (TREE_CODE (type) == FUNCTION_TYPE
@@ -13551,8 +13196,7 @@ rs6000_set_default_type_attributes (type)
    longcall attribute.  */
 
 struct rtx_def *
-rs6000_longcall_ref (call_ref)
-     rtx call_ref;
+rs6000_longcall_ref (rtx call_ref)
 {
   const char *call_name;
   tree node;
@@ -13586,10 +13230,8 @@ rs6000_longcall_ref (call_ref)
    data section.  */
 
 static void
-rs6000_elf_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align;
+rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x, 
+			       unsigned HOST_WIDE_INT align)
 {
   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
     toc_section ();
@@ -13603,10 +13245,8 @@ rs6000_elf_select_rtx_section (mode, x, align)
    the initial value of DECL requires link-time relocations.  */
 
 static void
-rs6000_elf_select_section (decl, reloc, align)
-     tree decl;
-     int reloc;
-     unsigned HOST_WIDE_INT align;
+rs6000_elf_select_section (tree decl, int reloc, 
+			   unsigned HOST_WIDE_INT align)
 {
   /* Pretend that we're always building for a shared library when
      ABI_AIX, because otherwise we end up with dynamic relocations
@@ -13625,9 +13265,7 @@ rs6000_elf_select_section (decl, reloc, align)
    initialized data and functions.  */
 
 static void
-rs6000_elf_unique_section (decl, reloc)
-     tree decl;
-     int reloc;
+rs6000_elf_unique_section (tree decl, int reloc)
 {
   /* As above, pretend that we're always building for a shared library
      when ABI_AIX, to avoid dynamic relocations in read-only sections.  */
@@ -13644,10 +13282,7 @@ rs6000_elf_unique_section (decl, reloc)
    read the prefixes.  */
 
 static void
-rs6000_elf_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
 {
   default_encode_section_info (decl, rtl, first);
 
@@ -13666,8 +13301,7 @@ rs6000_elf_encode_section_info (decl, rtl, first)
 }
 
 static bool
-rs6000_elf_in_small_data_p (decl)
-     tree decl;
+rs6000_elf_in_small_data_p (tree decl)
 {
   if (rs6000_sdata == SDATA_NONE)
     return false;
@@ -13709,8 +13343,7 @@ rs6000_elf_in_small_data_p (decl)
    increment the returned register via an "la" instruction.  */
 
 struct rtx_def *
-find_addr_reg (addr)
-     rtx addr;
+find_addr_reg (rtx addr)
 {
   while (GET_CODE (addr) == PLUS)
     {
@@ -13733,8 +13366,7 @@ find_addr_reg (addr)
 }
 
 void
-rs6000_fatal_bad_address (op)
-  rtx op;
+rs6000_fatal_bad_address (rtx op)
 {
   fatal_insn ("bad address", op);
 }
@@ -13746,8 +13378,7 @@ rs6000_fatal_bad_address (op)
    reference and a constant.  */
 
 int
-symbolic_operand (op)
-     rtx op;
+symbolic_operand (rtx op)
 {
   switch (GET_CODE (op))
     {
@@ -13774,10 +13405,7 @@ static tree stub_list = 0;
    procedure calls to the linked list.  */
 
 void 
-add_compiler_stub (label_name, function_name, line_number)
-     tree label_name;
-     tree function_name;
-     int line_number;
+add_compiler_stub (tree label_name, tree function_name, int line_number)
 {
   tree stub = build_tree_list (function_name, label_name);
   TREE_TYPE (stub) = build_int_2 (line_number, 0);
@@ -13794,7 +13422,7 @@ add_compiler_stub (label_name, function_name, line_number)
    linked list.  */
 
 void
-output_compiler_stub ()
+output_compiler_stub (void)
 {
   char tmp_buf[256];
   char label_buf[256];
@@ -13841,8 +13469,7 @@ output_compiler_stub ()
    already there or not.  */
 
 int
-no_previous_def (function_name)
-     tree function_name;
+no_previous_def (tree function_name)
 {
   tree stub;
   for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
@@ -13855,8 +13482,7 @@ no_previous_def (function_name)
    the function.  */
 
 tree
-get_prev_label (function_name)
-     tree function_name;
+get_prev_label (tree function_name)
 {
   tree stub;
   for (stub = stub_list; stub; stub = TREE_CHAIN (stub))
@@ -13871,10 +13497,7 @@ get_prev_label (function_name)
    CALL_DEST is the routine we are calling.  */
 
 char *
-output_call (insn, call_dest, operand_number)
-     rtx insn;
-     rtx call_dest;
-     int operand_number;
+output_call (rtx insn, rtx call_dest, int operand_number)
 {
   static char buf[256];
   if (GET_CODE (call_dest) == SYMBOL_REF && TARGET_LONG_BRANCH && !flag_pic)
@@ -13912,31 +13535,10 @@ output_call (insn, call_dest, operand_number)
 
 #endif /* RS6000_LONG_BRANCH */
 
-#define GEN_LOCAL_LABEL_FOR_SYMBOL(BUF,SYMBOL,LENGTH,N)		\
-  do {								\
-    const char *const symbol_ = (SYMBOL);			\
-    char *buffer_ = (BUF);					\
-    if (symbol_[0] == '"')					\
-      {								\
-        sprintf(buffer_, "\"L%d$%s", (N), symbol_+1);		\
-      }								\
-    else if (name_needs_quotes(symbol_))			\
-      {								\
-        sprintf(buffer_, "\"L%d$%s\"", (N), symbol_);		\
-      }								\
-    else							\
-      {								\
-        sprintf(buffer_, "L%d$%s", (N), symbol_);		\
-      }								\
-  } while (0)
-
-
 /* Generate PIC and indirect symbol stubs.  */
 
 void
-machopic_output_stub (file, symb, stub)
-     FILE *file;
-     const char *symb, *stub;
+machopic_output_stub (FILE *file, const char *symb, const char *stub)
 {
   unsigned int length;
   char *symbol_name, *lazy_ptr_name;
@@ -13946,7 +13548,6 @@ machopic_output_stub (file, symb, stub)
   /* Lose our funky encoding stuff so it doesn't contaminate the stub.  */
   symb = (*targetm.strip_name_encoding) (symb);
 
-  label += 1;
 
   length = strlen (symb);
   symbol_name = alloca (length + 32);
@@ -13955,9 +13556,6 @@ machopic_output_stub (file, symb, stub)
   lazy_ptr_name = alloca (length + 32);
   GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
 
-  local_label_0 = alloca (length + 32);
-  GEN_LOCAL_LABEL_FOR_SYMBOL (local_label_0, symb, length, 0);
-
   if (flag_pic == 2)
     machopic_picsymbol_stub1_section ();
   else
@@ -13969,6 +13567,10 @@ machopic_output_stub (file, symb, stub)
 
   if (flag_pic == 2)
     {
+      label++;
+      local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
+      sprintf (local_label_0, "\"L%011d$spb\"", label);
+    
       fprintf (file, "\tmflr r0\n");
       fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
       fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
@@ -14002,10 +13604,8 @@ machopic_output_stub (file, symb, stub)
 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
 
 rtx
-rs6000_machopic_legitimize_pic_address (orig, mode, reg)
-     rtx orig;
-     enum machine_mode mode;
-     rtx reg;
+rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode, 
+					rtx reg)
 {
   rtx base, offset;
 
@@ -14055,7 +13655,7 @@ rs6000_machopic_legitimize_pic_address (orig, mode, reg)
    real definition.  */
 
 void
-toc_section ()
+toc_section (void)
 {
 }
 
@@ -14063,10 +13663,7 @@ toc_section ()
 
 #if TARGET_ELF
 static unsigned int
-rs6000_elf_section_type_flags (decl, name, reloc)
-     tree decl;
-     const char *name;
-     int reloc;
+rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
 {
   unsigned int flags
     = default_section_type_flags_1 (decl, name, reloc,
@@ -14086,9 +13683,7 @@ rs6000_elf_section_type_flags (decl, name, reloc)
    that we have special handling for -mrelocatable.  */
 
 static void
-rs6000_elf_asm_out_constructor (symbol, priority)
-     rtx symbol;
-     int priority;
+rs6000_elf_asm_out_constructor (rtx symbol, int priority)
 {
   const char *section = ".ctors";
   char buf[16];
@@ -14117,9 +13712,7 @@ rs6000_elf_asm_out_constructor (symbol, priority)
 }
 
 static void
-rs6000_elf_asm_out_destructor (symbol, priority)
-     rtx symbol;
-     int priority;
+rs6000_elf_asm_out_destructor (rtx symbol, int priority)
 {
   const char *section = ".dtors";
   char buf[16];
@@ -14148,10 +13741,7 @@ rs6000_elf_asm_out_destructor (symbol, priority)
 }
 
 void
-rs6000_elf_declare_function_name (file, name, decl)
-     FILE *file;
-     const char *name;
-     tree decl;
+rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
 {
   if (TARGET_64BIT)
     {
@@ -14223,9 +13813,7 @@ rs6000_elf_declare_function_name (file, name, decl)
 
 #if TARGET_XCOFF
 static void
-rs6000_xcoff_asm_globalize_label (stream, name)
-     FILE *stream;
-     const char *name;
+rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
 {
   fputs (GLOBAL_ASM_OP, stream);
   RS6000_OUTPUT_BASENAME (stream, name);
@@ -14233,9 +13821,7 @@ rs6000_xcoff_asm_globalize_label (stream, name)
 }
 
 static void
-rs6000_xcoff_asm_named_section (name, flags)
-     const char *name;
-     unsigned int flags;
+rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
 {
   int smclass;
   static const char * const suffix[3] = { "PR", "RO", "RW" };
@@ -14253,10 +13839,8 @@ rs6000_xcoff_asm_named_section (name, flags)
 }
 
 static void
-rs6000_xcoff_select_section (decl, reloc, align)
-     tree decl;
-     int reloc;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+rs6000_xcoff_select_section (tree decl, int reloc, 
+			    unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
   if (decl_readonly_section_1 (decl, reloc, 1))
     {
@@ -14275,9 +13859,7 @@ rs6000_xcoff_select_section (decl, reloc, align)
 }
 
 static void
-rs6000_xcoff_unique_section (decl, reloc)
-     tree decl;
-     int reloc ATTRIBUTE_UNUSED;
+rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
 {
   const char *name;
 
@@ -14302,10 +13884,8 @@ rs6000_xcoff_unique_section (decl, reloc)
    toc entry.  */
 
 static void
-rs6000_xcoff_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x, 
+				unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
   if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
     toc_section ();
@@ -14316,8 +13896,7 @@ rs6000_xcoff_select_rtx_section (mode, x, align)
 /* Remove any trailing [DS] or the like from the symbol name.  */
 
 static const char *
-rs6000_xcoff_strip_name_encoding (name)
-     const char *name;
+rs6000_xcoff_strip_name_encoding (const char *name)
 {
   size_t len;
   if (*name == '*')
@@ -14332,10 +13911,7 @@ rs6000_xcoff_strip_name_encoding (name)
 /* Section attributes.  AIX is always PIC.  */
 
 static unsigned int
-rs6000_xcoff_section_type_flags (decl, name, reloc)
-     tree decl;
-     const char *name;
-     int reloc;
+rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
 {
   unsigned int align;
   unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
@@ -14365,7 +13941,7 @@ rs6000_xcoff_section_type_flags (decl, name, reloc)
    Finally, declare mcount when profiling to make the assembler happy.  */
 
 static void
-rs6000_xcoff_file_start ()
+rs6000_xcoff_file_start (void)
 {
   rs6000_gen_section_name (&xcoff_bss_section_name,
 			   main_input_filename, ".bss_");
@@ -14390,7 +13966,7 @@ rs6000_xcoff_file_start ()
    On the RS/6000, referencing data should automatically pull in text.  */
 
 static void
-rs6000_xcoff_file_end ()
+rs6000_xcoff_file_end (void)
 {
   text_section ();
   fputs ("_section_.text:\n", asm_out_file);
@@ -14406,8 +13982,7 @@ rs6000_xcoff_file_end ()
    functions at dynamic-link time.  */
 
 static bool
-rs6000_binds_local_p (decl)
-     tree decl;
+rs6000_binds_local_p (tree decl)
 {
   return default_binds_local_p_1 (decl, 0);
 }
@@ -14418,10 +13993,8 @@ rs6000_binds_local_p (decl)
    scanned.  In either case, *TOTAL contains the cost result.  */
 
 static bool
-rs6000_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code ATTRIBUTE_UNUSED;
-     int *total;
+rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, 
+		  int *total)
 {
   switch (code)
     {
@@ -14642,9 +14215,8 @@ rs6000_rtx_costs (x, code, outer_code, total)
    CLASS1 to one of CLASS2.  */
 
 int
-rs6000_register_move_cost (mode, from, to)
-     enum machine_mode mode;
-     enum reg_class from, to;
+rs6000_register_move_cost (enum machine_mode mode, 
+			   enum reg_class from, enum reg_class to)
 {
   /*  Moves from/to GENERAL_REGS.  */
   if (reg_classes_intersect_p (to, GENERAL_REGS)
@@ -14680,10 +14252,8 @@ rs6000_register_move_cost (mode, from, to)
    or from memory.  */
 
 int
-rs6000_memory_move_cost (mode, class, in)
-  enum machine_mode mode;
-  enum reg_class class;
-  int in ATTRIBUTE_UNUSED;
+rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class, 
+			 int in ATTRIBUTE_UNUSED)
 {
   if (reg_classes_intersect_p (class, GENERAL_REGS))
     return 4 * HARD_REGNO_NREGS (0, mode);
@@ -14783,24 +14353,16 @@ rs6000_libcall_value (enum machine_mode mode)
 /* Return true if TYPE is of type __ev64_opaque__.  */
 
 static bool
-is_ev64_opaque_type (type)
-     tree type;
+is_ev64_opaque_type (tree type)
 {
   return (TARGET_SPE
 	  && (type == opaque_V2SI_type_node
 	      || type == opaque_V2SF_type_node
-	      || type == opaque_p_V2SI_type_node
-	      || (TREE_CODE (type) == VECTOR_TYPE
-		  && TYPE_NAME (type)
-		  && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
-		  && DECL_NAME (TYPE_NAME (type))
-		  && strcmp (IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type))),
-			     "__ev64_opaque__") == 0)));
+	      || type == opaque_p_V2SI_type_node));
 }
 
 static rtx
-rs6000_dwarf_register_span (reg)
-     rtx reg;
+rs6000_dwarf_register_span (rtx reg)
 {
   unsigned regno;
 
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e91571967d5..dd10fa9953b 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1708,6 +1708,8 @@ typedef struct machine_function GTY(())
   const char *some_ld_name;
   /* Whether the instruction chain has been scanned already.  */
   int insn_chain_scanned_p;
+  /* Flags if __builtin_return_address (0) was used.  */
+  int ra_need_lr;
 } machine_function;
 
 /* Define a data type for recording info about an argument list
@@ -1734,7 +1736,6 @@ typedef struct rs6000_args
   int fregno;			/* next available FP register */
   int vregno;			/* next available AltiVec register */
   int nargs_prototype;		/* # args left in the current prototype */
-  int orig_nargs;		/* Original value of nargs_prototype */
   int prototype;		/* Whether a prototype was defined */
   int stdarg;			/* Whether function is a stdarg function.  */
   int call_cookie;		/* Do special things for this call */
@@ -1878,13 +1879,8 @@ typedef struct rs6000_args
 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
   rs6000_va_arg (valist, type)
 
-/* For AIX, the rule is that structures are passed left-aligned in
-   their stack slot.  However, GCC does not presently do this:
-   structures which are the same size as integer types are passed
-   right-aligned, as if they were in fact integers.  This only
-   matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
-   ABI_V4 does not use std_expand_builtin_va_arg.  */
-#define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
+#define PAD_VARARGS_DOWN \
+   (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
 
 /* Define this macro to be a nonzero value if the location where a function
    argument is passed depends on whether or not it is a named argument.  */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bf778e2e22c..5f91155179f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14039,7 +14039,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrsi_internal2"
   [(set (pc)
@@ -14063,7 +14063,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal1"
   [(set (pc)
@@ -14087,7 +14087,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal2"
   [(set (pc)
@@ -14111,7 +14111,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 ;; Similar, but we can use GE since we have a REG_NONNEG.
 
@@ -14137,7 +14137,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrsi_internal4"
   [(set (pc)
@@ -14161,7 +14161,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal3"
   [(set (pc)
@@ -14185,7 +14185,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal4"
   [(set (pc)
@@ -14209,7 +14209,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 ;; Similar but use EQ
 
@@ -14235,7 +14235,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrsi_internal6"
   [(set (pc)
@@ -14259,7 +14259,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal5"
   [(set (pc)
@@ -14283,7 +14283,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 (define_insn "*ctrdi_internal6"
   [(set (pc)
@@ -14307,7 +14307,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "4,12,16,16")])
+   (set_attr "length" "*,12,16,16")])
 
 ;; Now the splitters if we could not allocate the CTR register
 
@@ -14637,8 +14637,6 @@
   ""
   "
 {
-  if (TARGET_AIX)
-    rs6000_emit_eh_toc_restore (EH_RETURN_STACKADJ_RTX);
   if (TARGET_32BIT)
     emit_insn (gen_eh_set_lr_si (operands[0]));
   else
diff --git a/gcc/config/rs6000/spe.h b/gcc/config/rs6000/spe.h
index ca90b8068d8..16765161fde 100644
--- a/gcc/config/rs6000/spe.h
+++ b/gcc/config/rs6000/spe.h
@@ -45,7 +45,6 @@ typedef unsigned 		__vector __ev64_u32__;
 typedef long long 		__vector __ev64_s64__;
 typedef unsigned long long 	__vector __ev64_u64__;
 typedef float 			__vector __ev64_fs__;
-typedef int 			__vector __ev64_opaque__;
 
 #define __v2si __ev64_opaque__
 #define __v2sf __ev64_fs__
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index 82ab17be127..becdaa42bb2 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -37,6 +37,13 @@
   "efsabs %0,%1"
   [(set_attr "type" "fpsimple")])
 
+(define_insn "*nabssf2_gpr"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
+	(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
+  "TARGET_HARD_FLOAT && !TARGET_FPRS"
+  "efsnabs %0,%1"
+  [(set_attr "type" "fpsimple")])
+
 (define_insn "*addsf3_gpr"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
 	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 822a4380f2e..3e8b3540128 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -494,7 +494,7 @@ toc_section ()								\
     }									\
 }									\
 									\
-extern int in_toc_section PARAMS ((void));				\
+extern int in_toc_section (void);					\
 int in_toc_section ()							\
 {									\
   return in_section == in_toc;						\
@@ -1065,8 +1065,8 @@ extern int fixuplabelno;
 
 /* GNU/Linux support.  */
 #define LIB_LINUX_SPEC "%{mnewlib: --start-group -llinux -lc --end-group } \
-%{!mnewlib: %{shared:-lc} %{!shared: %{pthread:-lpthread } \
-%{profile:-lc_p} %{!profile:-lc}}}"
+%{!mnewlib: %{pthread:-lpthread} %{shared:-lc} \
+%{!shared: %{profile:-lc_p} %{!profile:-lc}}}"
 
 #ifdef HAVE_LD_PIE
 #define	STARTFILE_LINUX_SPEC "\
diff --git a/gcc/config/s390/s390-protos.h b/gcc/config/s390/s390-protos.h
index 7641fcb2076..40026d3b85f 100644
--- a/gcc/config/s390/s390-protos.h
+++ b/gcc/config/s390/s390-protos.h
@@ -21,76 +21,83 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 
 /* Declare functions in s390.c.  */
 
-extern void optimization_options PARAMS ((int, int));
-extern void override_options PARAMS ((void));
-extern int s390_arg_frame_offset PARAMS ((void));
-extern void s390_emit_prologue PARAMS ((void));
-extern void s390_emit_epilogue PARAMS ((void));
-extern void s390_function_profiler PARAMS ((FILE *, int));
+extern void optimization_options (int, int);
+extern void override_options (void);
+extern int s390_arg_frame_offset (void);
+extern void s390_load_got (int);
+extern void s390_emit_prologue (void);
+extern void s390_emit_epilogue (void);
+extern void s390_function_profiler (FILE *, int);
 
 #ifdef RTX_CODE
-extern int s390_extra_constraint PARAMS ((rtx, int));
-extern int const0_operand PARAMS ((rtx, enum machine_mode));
-extern int consttable_operand PARAMS ((rtx, enum machine_mode));
-extern int larl_operand PARAMS ((rtx, enum machine_mode));
-extern int s_operand PARAMS ((rtx, enum machine_mode));
-extern int s_imm_operand PARAMS ((rtx, enum machine_mode));
-extern int bras_sym_operand PARAMS ((rtx, enum machine_mode));
-extern int load_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern int store_multiple_operation PARAMS ((rtx, enum machine_mode));
-extern int s390_single_hi PARAMS ((rtx, enum machine_mode, int));
-extern int s390_extract_hi PARAMS ((rtx, enum machine_mode, int));
-extern int s390_single_qi PARAMS ((rtx, enum machine_mode, int));
-extern int s390_extract_qi PARAMS ((rtx, enum machine_mode, int));
-extern bool s390_split_ok_p PARAMS ((rtx, rtx, enum machine_mode, int));
-extern int tls_symbolic_operand PARAMS ((rtx));
+extern int s390_extra_constraint (rtx, int);
+extern int const0_operand (rtx, enum machine_mode);
+extern int consttable_operand (rtx, enum machine_mode);
+extern int larl_operand (rtx, enum machine_mode);
+extern int s_operand (rtx, enum machine_mode);
+extern int s_imm_operand (rtx, enum machine_mode);
+extern int bras_sym_operand (rtx, enum machine_mode);
+extern int load_multiple_operation (rtx, enum machine_mode);
+extern int store_multiple_operation (rtx, enum machine_mode);
+extern int s390_single_hi (rtx, enum machine_mode, int);
+extern int s390_extract_hi (rtx, enum machine_mode, int);
+extern int s390_single_qi (rtx, enum machine_mode, int);
+extern int s390_extract_qi (rtx, enum machine_mode, int);
+extern bool s390_split_ok_p (rtx, rtx, enum machine_mode, int);
+extern int tls_symbolic_operand (rtx);
 
-extern int s390_match_ccmode PARAMS ((rtx, enum machine_mode));
-extern enum machine_mode s390_tm_ccmode PARAMS ((rtx, rtx, int));
-extern enum machine_mode s390_select_ccmode PARAMS ((enum rtx_code, rtx, rtx));
-extern int symbolic_reference_mentioned_p PARAMS ((rtx));
-extern int tls_symbolic_reference_mentioned_p PARAMS ((rtx));
-extern rtx s390_tls_get_offset PARAMS ((void));
-extern int legitimate_la_operand_p PARAMS ((rtx));
-extern int preferred_la_operand_p PARAMS ((rtx));
-extern int legitimate_pic_operand_p PARAMS ((rtx));
-extern int legitimate_constant_p PARAMS ((rtx));
-extern int legitimate_reload_constant_p PARAMS ((rtx));
-extern int legitimate_address_p PARAMS ((enum machine_mode, rtx, int));
-extern rtx legitimize_pic_address PARAMS ((rtx, rtx));
-extern rtx legitimize_address PARAMS ((rtx, rtx, enum machine_mode));
-extern enum reg_class s390_preferred_reload_class PARAMS ((rtx, enum reg_class));
-extern enum reg_class s390_secondary_input_reload_class PARAMS ((enum reg_class, enum machine_mode, rtx));
-extern enum reg_class s390_secondary_output_reload_class PARAMS ((enum reg_class, enum machine_mode, rtx));
-extern int s390_plus_operand PARAMS ((rtx, enum machine_mode));
-extern void s390_expand_plus_operand PARAMS ((rtx, rtx, rtx));
-extern void emit_symbolic_move PARAMS ((rtx *));
-extern void s390_load_address PARAMS ((rtx, rtx));
-extern void s390_expand_movstr PARAMS ((rtx, rtx, rtx));
-extern void s390_expand_clrstr PARAMS ((rtx, rtx));
-extern void s390_expand_cmpstr PARAMS ((rtx, rtx, rtx, rtx));
-extern rtx s390_return_addr_rtx PARAMS ((int, rtx));
+extern int s390_match_ccmode (rtx, enum machine_mode);
+extern enum machine_mode s390_tm_ccmode (rtx, rtx, int);
+extern enum machine_mode s390_select_ccmode (enum rtx_code, rtx, rtx);
+extern int symbolic_reference_mentioned_p (rtx);
+extern int tls_symbolic_reference_mentioned_p (rtx);
+extern rtx s390_tls_get_offset (void);
+extern int legitimate_la_operand_p (rtx);
+extern int preferred_la_operand_p (rtx);
+extern int legitimate_pic_operand_p (rtx);
+extern int legitimate_constant_p (rtx);
+extern int legitimate_reload_constant_p (rtx);
+extern int legitimate_address_p (enum machine_mode, rtx, int);
+extern rtx legitimize_pic_address (rtx, rtx);
+extern rtx legitimize_address (rtx, rtx, enum machine_mode);
+extern enum reg_class s390_preferred_reload_class (rtx, enum reg_class);
+extern enum reg_class s390_secondary_input_reload_class (enum reg_class,
+							 enum machine_mode,
+							 rtx);
+extern enum reg_class s390_secondary_output_reload_class (enum reg_class,
+							  enum machine_mode,
+							  rtx);
+extern int s390_plus_operand (rtx, enum machine_mode);
+extern void s390_expand_plus_operand (rtx, rtx, rtx);
+extern void emit_symbolic_move (rtx *);
+extern void s390_load_address (rtx, rtx);
+extern void s390_expand_movstr (rtx, rtx, rtx);
+extern void s390_expand_clrstr (rtx, rtx);
+extern void s390_expand_cmpmem (rtx, rtx, rtx, rtx);
+extern rtx s390_return_addr_rtx (int, rtx);
 
-extern void s390_output_symbolic_const PARAMS ((FILE *, rtx));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern void s390_output_constant_pool PARAMS ((rtx, rtx));
-extern void s390_trampoline_template PARAMS ((FILE *));
-extern void s390_initialize_trampoline PARAMS ((rtx, rtx, rtx));
-extern rtx s390_gen_rtx_const_DI PARAMS ((int, int));
-extern void s390_output_dwarf_dtprel PARAMS ((FILE*, int, rtx));
-extern int s390_agen_dep_p PARAMS ((rtx, rtx));
+extern void s390_output_symbolic_const (FILE *, rtx);
+extern void print_operand_address (FILE *, rtx);
+extern void print_operand (FILE *, rtx, int);
+extern void s390_output_constant_pool (rtx, rtx);
+extern void s390_output_pool_entry (FILE *, rtx, enum machine_mode, 
+				    unsigned int);
+extern void s390_trampoline_template (FILE *);
+extern void s390_initialize_trampoline (rtx, rtx, rtx);
+extern rtx s390_gen_rtx_const_DI (int, int);
+extern void s390_output_dwarf_dtprel (FILE*, int, rtx);
+extern int s390_agen_dep_p (rtx, rtx);
 
 #endif /* RTX_CODE */
 
 #ifdef TREE_CODE
-extern int s390_function_arg_pass_by_reference PARAMS ((enum machine_mode, tree));
-extern void s390_function_arg_advance PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
-extern tree s390_build_va_list PARAMS ((void));
+extern int s390_function_arg_pass_by_reference (enum machine_mode, tree);
+extern void s390_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
+				       tree, int);
+extern tree s390_build_va_list (void);
 #ifdef RTX_CODE
-extern rtx s390_function_arg PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int));
-extern void s390_va_start PARAMS ((tree, rtx));
-extern rtx s390_va_arg PARAMS ((tree, tree));
+extern rtx s390_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern void s390_va_start (tree, rtx);
+extern rtx s390_va_arg (tree, tree);
 #endif /* RTX_CODE */
 #endif /* TREE_CODE */
-
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 7db180d8141..7086d5b6932 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -54,29 +54,28 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #define SYMBOL_FLAG_ALIGN1	(SYMBOL_FLAG_MACH_DEP << 0)
 
 
-static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
-static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx, 
-					     unsigned HOST_WIDE_INT));
-static void s390_encode_section_info PARAMS ((tree, rtx, int));
-static bool s390_cannot_force_const_mem PARAMS ((rtx));
-static rtx s390_delegitimize_address PARAMS ((rtx));
-static void s390_init_builtins PARAMS ((void));
-static rtx s390_expand_builtin PARAMS ((tree, rtx, rtx, 
-					enum machine_mode, int));
-static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					  HOST_WIDE_INT, tree));
-static enum attr_type s390_safe_attr_type PARAMS ((rtx));
-
-static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int s390_adjust_priority PARAMS ((rtx, int));
-static int s390_issue_rate PARAMS ((void));
-static int s390_use_dfa_pipeline_interface PARAMS ((void));
-static int s390_first_cycle_multipass_dfa_lookahead PARAMS ((void));
-static int s390_sched_reorder2 PARAMS ((FILE *, int, rtx *, int *, int));
-static bool s390_rtx_costs PARAMS ((rtx, int, int, int *));
-static int s390_address_cost PARAMS ((rtx));
-static void s390_reorg PARAMS ((void));
-
+static bool s390_assemble_integer (rtx, unsigned int, int);
+static void s390_select_rtx_section (enum machine_mode, rtx,
+				     unsigned HOST_WIDE_INT);
+static void s390_encode_section_info (tree, rtx, int);
+static bool s390_cannot_force_const_mem (rtx);
+static rtx s390_delegitimize_address (rtx);
+static void s390_init_builtins (void);
+static rtx s390_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
+static void s390_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+				  HOST_WIDE_INT, tree);
+static enum attr_type s390_safe_attr_type (rtx);
+
+static int s390_adjust_cost (rtx, rtx, rtx, int);
+static int s390_adjust_priority (rtx, int);
+static int s390_issue_rate (void);
+static int s390_use_dfa_pipeline_interface (void);
+static int s390_first_cycle_multipass_dfa_lookahead (void);
+static int s390_sched_reorder2 (FILE *, int, rtx *, int *, int);
+static bool s390_rtx_costs (rtx, int, int, int *);
+static int s390_address_cost (rtx);
+static void s390_reorg (void);
+static bool s390_valid_pointer_mode (enum machine_mode);
 
 #undef  TARGET_ASM_ALIGNED_HI_OP
 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
@@ -138,6 +137,9 @@ static void s390_reorg PARAMS ((void));
 #undef TARGET_MACHINE_DEPENDENT_REORG
 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
 
+#undef TARGET_VALID_POINTER_MODE
+#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 extern int reload_completed;
@@ -181,12 +183,13 @@ const char *s390_arch_string;		/* for -march=<xxx> */
 
 struct machine_function GTY(())
 {
-  /* Label of start of initial literal pool.  */
-  rtx literal_pool_label;
-
   /* Set, if some of the fprs 8-15 need to be saved (64 bit abi).  */
   int save_fprs_p;
 
+  /* Set if return address needs to be saved because the current
+     function uses __builtin_return_addr (0).  */
+  bool save_return_addr_p;
+
   /* Number of first and last gpr to be saved, restored.  */
   int first_save_gpr;
   int first_restore_gpr;
@@ -199,50 +202,46 @@ struct machine_function GTY(())
   const char *some_ld_name;
 };
 
-static int s390_match_ccmode_set PARAMS ((rtx, enum machine_mode));
-static int s390_branch_condition_mask PARAMS ((rtx));
-static const char *s390_branch_condition_mnemonic PARAMS ((rtx, int));
-static int check_mode PARAMS ((rtx, enum machine_mode *));
-static int general_s_operand PARAMS ((rtx, enum machine_mode, int));
-static int s390_short_displacement PARAMS ((rtx));
-static int s390_decompose_address PARAMS ((rtx, struct s390_address *));
-static rtx get_thread_pointer PARAMS ((void));
-static rtx legitimize_tls_address PARAMS ((rtx, rtx));
-static const char *get_some_local_dynamic_name PARAMS ((void));
-static int get_some_local_dynamic_name_1 PARAMS ((rtx *, void *));
-static int reg_used_in_mem_p PARAMS ((int, rtx));
-static int addr_generation_dependency_p PARAMS ((rtx, rtx));
-static int s390_split_branches PARAMS ((rtx, bool *));
-static void find_constant_pool_ref PARAMS ((rtx, rtx *));
-static void replace_constant_pool_ref PARAMS ((rtx *, rtx, rtx));
-static int find_base_register_in_addr PARAMS ((struct s390_address *));
-static bool find_base_register_ref PARAMS ((rtx));
-static void replace_base_register_ref PARAMS ((rtx *, rtx));
-static void s390_optimize_prolog PARAMS ((int));
-static bool s390_fixup_clobbered_return_reg PARAMS ((rtx));
-static int find_unused_clobbered_reg PARAMS ((void));
-static void s390_frame_info PARAMS ((void));
-static rtx save_fpr PARAMS ((rtx, int, int));
-static rtx restore_fpr PARAMS ((rtx, int, int));
-static rtx save_gprs PARAMS ((rtx, int, int, int));
-static rtx restore_gprs PARAMS ((rtx, int, int, int));
-static int s390_function_arg_size PARAMS ((enum machine_mode, tree));
-static bool s390_function_arg_float PARAMS ((enum machine_mode, tree));
-static struct machine_function * s390_init_machine_status PARAMS ((void));
+static int s390_match_ccmode_set (rtx, enum machine_mode);
+static int s390_branch_condition_mask (rtx);
+static const char *s390_branch_condition_mnemonic (rtx, int);
+static int check_mode (rtx, enum machine_mode *);
+static int general_s_operand (rtx, enum machine_mode, int);
+static int s390_short_displacement (rtx);
+static int s390_decompose_address (rtx, struct s390_address *);
+static rtx get_thread_pointer (void);
+static rtx legitimize_tls_address (rtx, rtx);
+static const char *get_some_local_dynamic_name (void);
+static int get_some_local_dynamic_name_1 (rtx *, void *);
+static int reg_used_in_mem_p (int, rtx);
+static int addr_generation_dependency_p (rtx, rtx);
+static int s390_split_branches (rtx, bool *);
+static void find_constant_pool_ref (rtx, rtx *);
+static void replace_constant_pool_ref (rtx *, rtx, rtx);
+static rtx find_ltrel_base (rtx);
+static void replace_ltrel_base (rtx *, rtx);
+static void s390_optimize_prolog (bool, bool);
+static int find_unused_clobbered_reg (void);
+static void s390_frame_info (void);
+static rtx save_fpr (rtx, int, int);
+static rtx restore_fpr (rtx, int, int);
+static rtx save_gprs (rtx, int, int, int);
+static rtx restore_gprs (rtx, int, int, int);
+static int s390_function_arg_size (enum machine_mode, tree);
+static bool s390_function_arg_float (enum machine_mode, tree);
+static struct machine_function * s390_init_machine_status (void);
 
 /* Check whether integer displacement is in range.  */
 #define DISP_IN_RANGE(d) \
   (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \
                            : ((d) >= 0 && (d) <= 4095))
- 
+
 /* Return true if SET either doesn't set the CC register, or else
-   the source and destination have matching CC modes and that 
+   the source and destination have matching CC modes and that
    CC mode is at least as constrained as REQ_MODE.  */
- 
+
 static int
-s390_match_ccmode_set (set, req_mode)
-     rtx set;
-     enum machine_mode req_mode;
+s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
 {
   enum machine_mode set_mode;
 
@@ -280,23 +279,21 @@ s390_match_ccmode_set (set, req_mode)
       if (req_mode != CCAmode)
         return 0;
       break;
- 
+
     default:
       abort ();
     }
- 
+
   return (GET_MODE (SET_SRC (set)) == set_mode);
 }
 
-/* Return true if every SET in INSN that sets the CC register 
-   has source and destination with matching CC modes and that 
-   CC mode is at least as constrained as REQ_MODE.  
+/* Return true if every SET in INSN that sets the CC register
+   has source and destination with matching CC modes and that
+   CC mode is at least as constrained as REQ_MODE.
    If REQ_MODE is VOIDmode, always return false.  */
- 
+
 int
-s390_match_ccmode (insn, req_mode)
-     rtx insn;
-     enum machine_mode req_mode;
+s390_match_ccmode (rtx insn, enum machine_mode req_mode)
 {
   int i;
 
@@ -319,18 +316,15 @@ s390_match_ccmode (insn, req_mode)
   return 1;
 }
 
-/* If a test-under-mask instruction can be used to implement 
+/* If a test-under-mask instruction can be used to implement
    (compare (and ... OP1) OP2), return the CC mode required
-   to do that.  Otherwise, return VOIDmode.  
+   to do that.  Otherwise, return VOIDmode.
    MIXED is true if the instruction can distinguish between
    CC1 and CC2 for mixed selected bits (TMxx), it is false
    if the instruction cannot (TM).  */
 
 enum machine_mode
-s390_tm_ccmode (op1, op2, mixed)
-     rtx op1;
-     rtx op2;
-     int mixed;
+s390_tm_ccmode (rtx op1, rtx op2, int mixed)
 {
   int bit0, bit1;
 
@@ -358,25 +352,23 @@ s390_tm_ccmode (op1, op2, mixed)
   return VOIDmode;
 }
 
-/* Given a comparison code OP (EQ, NE, etc.) and the operands 
-   OP0 and OP1 of a COMPARE, return the mode to be used for the 
+/* Given a comparison code OP (EQ, NE, etc.) and the operands
+   OP0 and OP1 of a COMPARE, return the mode to be used for the
    comparison.  */
 
 enum machine_mode
-s390_select_ccmode (code, op0, op1) 
-     enum rtx_code code;
-     rtx op0;
-     rtx op1;
+s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
 {
   switch (code)
     {
       case EQ:
       case NE:
 	if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
-	    && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K')) 
+	    && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
 	  return CCAPmode;
-	if (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
-	    || GET_CODE (op1) == NEG)
+	if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
+	     || GET_CODE (op1) == NEG)
+	    && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
 	  return CCLmode;
 
 	if (GET_CODE (op0) == AND)
@@ -392,11 +384,11 @@ s390_select_ccmode (code, op0, op1)
 	      }
 	  }
 
-	if (register_operand (op0, HImode) 
+	if (register_operand (op0, HImode)
 	    && GET_CODE (op1) == CONST_INT
 	    && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
 	  return CCT3mode;
-	if (register_operand (op0, QImode) 
+	if (register_operand (op0, QImode)
 	    && GET_CODE (op1) == CONST_INT
 	    && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
 	  return CCT3mode;
@@ -408,7 +400,7 @@ s390_select_ccmode (code, op0, op1)
       case GE:
       case GT:
 	  if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
-	      && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K')) 
+	      && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (op0, 1)), 'K'))
             {
 	      if (INTVAL (XEXP((op0), 1)) < 0)
 	        return CCANmode;
@@ -430,7 +422,8 @@ s390_select_ccmode (code, op0, op1)
 
       case LTU:
       case GEU:
-	if (GET_CODE (op0) == PLUS)
+	if (GET_CODE (op0) == PLUS
+	    && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
 	  return CCL1mode;
 
 	if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
@@ -440,7 +433,8 @@ s390_select_ccmode (code, op0, op1)
 
       case LEU:
       case GTU:
-	if (GET_CODE (op0) == MINUS)
+	if (GET_CODE (op0) == MINUS
+	    && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
 	  return CCL2mode;
 
 	if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
@@ -453,13 +447,12 @@ s390_select_ccmode (code, op0, op1)
     }
 }
 
-/* Return branch condition mask to implement a branch 
+/* Return branch condition mask to implement a branch
    specified by CODE.  */
 
 static int
-s390_branch_condition_mask (code)
-    rtx code;
-{ 
+s390_branch_condition_mask (rtx code)
+{
   const int CC0 = 1 << 3;
   const int CC1 = 1 << 2;
   const int CC2 = 1 << 1;
@@ -647,14 +640,12 @@ s390_branch_condition_mask (code)
     }
 }
 
-/* If INV is false, return assembler mnemonic string to implement 
-   a branch specified by CODE.  If INV is true, return mnemonic 
+/* If INV is false, return assembler mnemonic string to implement
+   a branch specified by CODE.  If INV is true, return mnemonic
    for the corresponding inverted branch.  */
 
 static const char *
-s390_branch_condition_mnemonic (code, inv)
-     rtx code;
-     int inv;
+s390_branch_condition_mnemonic (rtx code, int inv)
 {
   static const char *const mnemonic[16] =
     {
@@ -676,15 +667,12 @@ s390_branch_condition_mnemonic (code, inv)
 }
 
 /* If OP is an integer constant of mode MODE with exactly one
-   HImode subpart unequal to DEF, return the number of that 
+   HImode subpart unequal to DEF, return the number of that
    subpart.  As a special case, all HImode subparts of OP are
    equal to DEF, return zero.  Otherwise, return -1.  */
 
 int
-s390_single_hi (op, mode, def)
-     rtx op;
-     enum machine_mode mode;
-     int def;
+s390_single_hi (rtx op, enum machine_mode mode, int def)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -739,17 +727,14 @@ s390_single_hi (op, mode, def)
       return part == -1 ? 0 : (n_parts - 1 - part);
     }
 
-  return -1;      
+  return -1;
 }
 
-/* Extract the HImode part number PART from integer 
+/* Extract the HImode part number PART from integer
    constant OP of mode MODE.  */
 
 int
-s390_extract_hi (op, mode, part)
-    rtx op;
-    enum machine_mode mode;
-    int part;
+s390_extract_hi (rtx op, enum machine_mode mode, int part)
 {
   int n_parts = GET_MODE_SIZE (mode) / 2;
   if (part < 0 || part >= n_parts)
@@ -772,22 +757,19 @@ s390_extract_hi (op, mode, part)
         value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
         part -= HOST_BITS_PER_WIDE_INT / 16;
 
-      return ((value >> (16 * part)) & 0xffff); 
+      return ((value >> (16 * part)) & 0xffff);
     }
 
   abort ();
 }
 
 /* If OP is an integer constant of mode MODE with exactly one
-   QImode subpart unequal to DEF, return the number of that 
+   QImode subpart unequal to DEF, return the number of that
    subpart.  As a special case, all QImode subparts of OP are
    equal to DEF, return zero.  Otherwise, return -1.  */
 
 int
-s390_single_qi (op, mode, def)
-     rtx op;
-     enum machine_mode mode;
-     int def;
+s390_single_qi (rtx op, enum machine_mode mode, int def)
 {
   if (GET_CODE (op) == CONST_INT)
     {
@@ -842,17 +824,14 @@ s390_single_qi (op, mode, def)
       return part == -1 ? 0 : (n_parts - 1 - part);
     }
 
-  return -1;      
+  return -1;
 }
 
-/* Extract the QImode part number PART from integer 
+/* Extract the QImode part number PART from integer
    constant OP of mode MODE.  */
 
 int
-s390_extract_qi (op, mode, part)
-    rtx op;
-    enum machine_mode mode;
-    int part;
+s390_extract_qi (rtx op, enum machine_mode mode, int part)
 {
   int n_parts = GET_MODE_SIZE (mode);
   if (part < 0 || part >= n_parts)
@@ -875,22 +854,18 @@ s390_extract_qi (op, mode, part)
         value = (unsigned HOST_WIDE_INT) CONST_DOUBLE_HIGH (op),
         part -= HOST_BITS_PER_WIDE_INT / 8;
 
-      return ((value >> (8 * part)) & 0xff); 
+      return ((value >> (8 * part)) & 0xff);
     }
 
   abort ();
 }
 
-/* Check whether we can (and want to) split a double-word 
-   move in mode MODE from SRC to DST into two single-word 
+/* Check whether we can (and want to) split a double-word
+   move in mode MODE from SRC to DST into two single-word
    moves, moving the subword FIRST_SUBWORD first.  */
 
 bool
-s390_split_ok_p (dst, src, mode, first_subword)
-     rtx dst;
-     rtx src;
-     enum machine_mode mode;
-     int first_subword;
+s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
 {
   /* Floating point registers cannot be split.  */
   if (FP_REG_P (src) || FP_REG_P (dst))
@@ -918,7 +893,7 @@ s390_split_ok_p (dst, src, mode, first_subword)
 }
 
 
-/* Change optimizations to be performed, depending on the 
+/* Change optimizations to be performed, depending on the
    optimization level.
 
    LEVEL is the optimization level specified; 2 if `-O2' is
@@ -927,9 +902,7 @@ s390_split_ok_p (dst, src, mode, first_subword)
    SIZE is nonzero if `-Os' is specified and zero otherwise.  */
 
 void
-optimization_options (level, size)
-     int level ATTRIBUTE_UNUSED;
-     int size ATTRIBUTE_UNUSED;
+optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
 {
   /* ??? There are apparently still problems with -fcaller-saves.  */
   flag_caller_saves = 0;
@@ -940,7 +913,7 @@ optimization_options (level, size)
 }
 
 void
-override_options ()
+override_options (void)
 {
   int i;
   static struct pta
@@ -954,7 +927,7 @@ override_options ()
       {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT},
       {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT},
       {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH},
-      {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH 
+      {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH
 				    | PF_LONG_DISPLACEMENT},
     };
 
@@ -1027,14 +1000,13 @@ const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
   FP_REGS,      FP_REGS,   FP_REGS,   FP_REGS,
-  ADDR_REGS,    NO_REGS,   ADDR_REGS 
+  ADDR_REGS,    NO_REGS,   ADDR_REGS
 };
 
 /* Return attribute type of insn.  */
 
 static enum attr_type
-s390_safe_attr_type (insn)
-     rtx insn;
+s390_safe_attr_type (rtx insn)
 {
   if (recog_memoized (insn) >= 0)
     return get_attr_type (insn);
@@ -1045,11 +1017,9 @@ s390_safe_attr_type (insn)
 /* Return true if OP a (const_int 0) operand.
    OP is the current operation.
    MODE is the current operation mode.  */
- 
+
 int
-const0_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+const0_operand (register rtx op, enum machine_mode mode)
 {
   return op == CONST0_RTX (mode);
 }
@@ -1059,20 +1029,16 @@ const0_operand (op, mode)
    MODE is the current operation mode.  */
 
 int
-consttable_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+consttable_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return CONSTANT_P (op);
 }
 
 /* Return true if the mode of operand OP matches MODE.
-   If MODE is set to VOIDmode, set it to the mode of OP.  */ 
+   If MODE is set to VOIDmode, set it to the mode of OP.  */
 
 static int
-check_mode (op, mode)
-     register rtx op;
-     enum machine_mode *mode;
+check_mode (register rtx op, enum machine_mode *mode)
 {
   if (*mode == VOIDmode)
       *mode = GET_MODE (op);
@@ -1089,9 +1055,7 @@ check_mode (op, mode)
    MODE is the current operation mode.  */
 
 int
-larl_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+larl_operand (register rtx op, enum machine_mode mode)
 {
   if (! check_mode (op, &mode))
     return 0;
@@ -1119,7 +1083,7 @@ larl_operand (op, mode)
       if (INTVAL (XEXP (op, 1)) >= (HOST_WIDE_INT)1 << 32
 	  || INTVAL (XEXP (op, 1)) < -((HOST_WIDE_INT)1 << 32))
         return 0;
-#endif	
+#endif
       op = XEXP (op, 0);
     }
 
@@ -1134,10 +1098,10 @@ larl_operand (op, mode)
   /* Now we must have a @GOTENT offset or @PLT stub
      or an @INDNTPOFF TLS offset.  */
   if (GET_CODE (op) == UNSPEC
-      && XINT (op, 1) == 111)
+      && XINT (op, 1) == UNSPEC_GOTENT)
     return 1;
   if (GET_CODE (op) == UNSPEC
-      && XINT (op, 1) == 113)
+      && XINT (op, 1) == UNSPEC_PLT)
     return 1;
   if (GET_CODE (op) == UNSPEC
       && XINT (op, 1) == UNSPEC_INDNTPOFF)
@@ -1153,10 +1117,8 @@ larl_operand (op, mode)
    be accepted or not.  */
 
 static int
-general_s_operand (op, mode, allow_immediate)
-     register rtx op;
-     enum machine_mode mode;
-     int allow_immediate;
+general_s_operand (register rtx op, enum machine_mode mode,
+		   int allow_immediate)
 {
   struct s390_address addr;
 
@@ -1167,37 +1129,37 @@ general_s_operand (op, mode, allow_immediate)
 
   /* Just like memory_operand, allow (subreg (mem ...))
      after reload.  */
-  if (reload_completed 
-      && GET_CODE (op) == SUBREG 
+  if (reload_completed
+      && GET_CODE (op) == SUBREG
       && GET_CODE (SUBREG_REG (op)) == MEM)
     op = SUBREG_REG (op);
 
   switch (GET_CODE (op))
     {
-      /* Constants that we are sure will be forced to the
-         literal pool in reload are OK as s-operand.  Note
-	 that we cannot call s390_preferred_reload_class here
-	 because it might not be known yet at this point 
-	 whether the current function is a leaf or not.  */
+      /* Constants are OK as s-operand if ALLOW_IMMEDIATE
+	 is true and we are still before reload.  */
       case CONST_INT:
       case CONST_DOUBLE:
 	if (!allow_immediate || reload_completed)
-	  break;
-	if (!legitimate_reload_constant_p (op))
-	  return 1;
-	if (!TARGET_64BIT)
-	  return 1;
-	break;
+	  return 0;
+	return 1;
 
       /* Memory operands are OK unless they already use an
 	 index register.  */
       case MEM:
 	if (GET_CODE (XEXP (op, 0)) == ADDRESSOF)
 	  return 1;
-	if (s390_decompose_address (XEXP (op, 0), &addr) 
-	    && !addr.indx)
-	  return 1;
-	break;
+	if (!s390_decompose_address (XEXP (op, 0), &addr))
+	  return 0;
+	if (addr.indx)
+	  return 0;
+	/* Do not allow literal pool references unless ALLOW_IMMEDIATE 
+	   is true.  This prevents compares between two literal pool 
+	   entries from being accepted.  */
+	if (!allow_immediate 
+	    && addr.base && REGNO (addr.base) == BASE_REGISTER)
+	  return 0;
+	return 1;
 
       default:
 	break;
@@ -1211,23 +1173,19 @@ general_s_operand (op, mode, allow_immediate)
    MODE is the current operation mode.  */
 
 int
-s_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+s_operand (register rtx op, enum machine_mode mode)
 {
   return general_s_operand (op, mode, 0);
 }
 
-/* Return true if OP is a valid S-type operand or an immediate 
-   operand that can be addressed as S-type operand by forcing 
+/* Return true if OP is a valid S-type operand or an immediate
+   operand that can be addressed as S-type operand by forcing
    it into the literal pool.
    OP is the current operation.
    MODE is the current operation mode.  */
 
 int
-s_imm_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+s_imm_operand (register rtx op, enum machine_mode mode)
 {
   return general_s_operand (op, mode, 1);
 }
@@ -1235,8 +1193,7 @@ s_imm_operand (op, mode)
 /* Return true if DISP is a valid short displacement.  */
 
 static int
-s390_short_displacement (disp)
-     rtx disp;
+s390_short_displacement (rtx disp)
 {
   /* No displacement is OK.  */
   if (!disp)
@@ -1249,7 +1206,7 @@ s390_short_displacement (disp)
   /* GOT offset is not OK, the GOT can be large.  */
   if (GET_CODE (disp) == CONST
       && GET_CODE (XEXP (disp, 0)) == UNSPEC
-      && XINT (XEXP (disp, 0), 1) == 110)
+      && XINT (XEXP (disp, 0), 1) == UNSPEC_GOT)
     return 0;
 
   /* All other symbolic constants are literal pool references,
@@ -1263,9 +1220,7 @@ s390_short_displacement (disp)
 /* Return true if OP is a valid operand for a C constraint.  */
 
 int
-s390_extra_constraint (op, c)
-     rtx op;
-     int c;
+s390_extra_constraint (rtx op, int c)
 {
   struct s390_address addr;
 
@@ -1356,10 +1311,7 @@ s390_extra_constraint (op, c)
    scanned.  In either case, *TOTAL contains the cost result.  */
 
 static bool
-s390_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code;
-     int *total;
+s390_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   switch (code)
     {
@@ -1427,8 +1379,7 @@ s390_rtx_costs (x, code, outer_code, total)
 /* Return the cost of an address rtx ADDR.  */
 
 static int
-s390_address_cost (addr)
-     rtx addr;
+s390_address_cost (rtx addr)
 {
   struct s390_address ad;
   if (!s390_decompose_address (addr, &ad))
@@ -1442,9 +1393,7 @@ s390_address_cost (addr)
    MODE is the current operation mode.  */
 
 int
-bras_sym_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+bras_sym_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   register enum rtx_code code = GET_CODE (op);
 
@@ -1455,7 +1404,7 @@ bras_sym_operand (op, mode)
   /* Allow @PLT stubs.  */
   if (code == CONST
       && GET_CODE (XEXP (op, 0)) == UNSPEC
-      && XINT (XEXP (op, 0), 1) == 113)
+      && XINT (XEXP (op, 0), 1) == UNSPEC_PLT)
     return 1;
   return 0;
 }
@@ -1464,8 +1413,7 @@ bras_sym_operand (op, mode)
    otherwise return 0.  */
 
 int
-tls_symbolic_operand (op)
-     register rtx op;
+tls_symbolic_operand (register rtx op)
 {
   if (GET_CODE (op) != SYMBOL_REF)
     return 0;
@@ -1473,14 +1421,12 @@ tls_symbolic_operand (op)
 }
 
 /* Return true if OP is a load multiple operation.  It is known to be a
-   PARALLEL and the first section will be tested. 
+   PARALLEL and the first section will be tested.
    OP is the current operation.
    MODE is the current operation mode.  */
 
 int
-load_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int dest_regno;
@@ -1503,7 +1449,7 @@ load_multiple_operation (op, mode)
   if (GET_CODE (src_addr) == REG)
     off = 0;
   else if (GET_CODE (src_addr) == PLUS
-	   && GET_CODE (XEXP (src_addr, 0)) == REG 
+	   && GET_CODE (XEXP (src_addr, 0)) == REG
 	   && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
     {
       off = INTVAL (XEXP (src_addr, 1));
@@ -1537,14 +1483,12 @@ load_multiple_operation (op, mode)
 }
 
 /* Return true if OP is a store multiple operation.  It is known to be a
-   PARALLEL and the first section will be tested. 
+   PARALLEL and the first section will be tested.
    OP is the current operation.
    MODE is the current operation mode.  */
 
 int
-store_multiple_operation (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   int count = XVECLEN (op, 0);
   unsigned int src_regno;
@@ -1566,7 +1510,7 @@ store_multiple_operation (op, mode)
   if (GET_CODE (dest_addr) == REG)
     off = 0;
   else if (GET_CODE (dest_addr) == PLUS
-	   && GET_CODE (XEXP (dest_addr, 0)) == REG 
+	   && GET_CODE (XEXP (dest_addr, 0)) == REG
 	   && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
     {
       off = INTVAL (XEXP (dest_addr, 1));
@@ -1602,8 +1546,7 @@ store_multiple_operation (op, mode)
 /* Return true if OP contains a symbol reference */
 
 int
-symbolic_reference_mentioned_p (op)
-     rtx op;
+symbolic_reference_mentioned_p (rtx op)
 {
   register const char *fmt;
   register int i;
@@ -1633,8 +1576,7 @@ symbolic_reference_mentioned_p (op)
 /* Return true if OP contains a reference to a thread-local symbol.  */
 
 int
-tls_symbolic_reference_mentioned_p (op)
-     rtx op;
+tls_symbolic_reference_mentioned_p (rtx op)
 {
   register const char *fmt;
   register int i;
@@ -1662,19 +1604,18 @@ tls_symbolic_reference_mentioned_p (op)
 }
 
 
-/* Return true if OP is a legitimate general operand when 
-   generating PIC code.  It is given that flag_pic is on 
+/* Return true if OP is a legitimate general operand when
+   generating PIC code.  It is given that flag_pic is on
    and that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 
 int
-legitimate_pic_operand_p (op)
-     register rtx op;
+legitimate_pic_operand_p (register rtx op)
 {
   /* Accept all non-symbolic constants.  */
   if (!SYMBOLIC_CONST (op))
     return 1;
 
-  /* Reject everything else; must be handled 
+  /* Reject everything else; must be handled
      via emit_symbolic_move.  */
   return 0;
 }
@@ -1683,15 +1624,14 @@ legitimate_pic_operand_p (op)
    It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE.  */
 
 int
-legitimate_constant_p (op)
-     register rtx op;
+legitimate_constant_p (register rtx op)
 {
   /* Accept all non-symbolic constants.  */
   if (!SYMBOLIC_CONST (op))
     return 1;
 
   /* Accept immediate LARL operands.  */
-  if (TARGET_64BIT && larl_operand (op, VOIDmode))
+  if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode))
     return 1;
 
   /* Thread-local symbols are never legal constants.  This is
@@ -1716,8 +1656,7 @@ legitimate_constant_p (op)
    not constant (TLS) or not known at final link time (PIC).  */
 
 static bool
-s390_cannot_force_const_mem (x)
-     rtx x;
+s390_cannot_force_const_mem (rtx x)
 {
   switch (GET_CODE (x))
     {
@@ -1749,10 +1688,10 @@ s390_cannot_force_const_mem (x)
       switch (XINT (x, 1))
 	{
 	/* Only lt-relative or GOT-relative UNSPECs are OK.  */
-	case 100:
-	case 104:
-	case 112:
-	case 114:
+	case UNSPEC_LTREL_OFFSET:
+	case UNSPEC_GOT:
+	case UNSPEC_GOTOFF:
+	case UNSPEC_PLTOFF:
 	case UNSPEC_TLSGD:
 	case UNSPEC_TLSLDM:
 	case UNSPEC_NTPOFF:
@@ -1772,17 +1711,16 @@ s390_cannot_force_const_mem (x)
 }
 
 /* Returns true if the constant value OP is a legitimate general
-   operand during and after reload.  The difference to 
+   operand during and after reload.  The difference to
    legitimate_constant_p is that this function will not accept
    a constant that would need to be forced to the literal pool
    before it can be used as operand.  */
 
 int
-legitimate_reload_constant_p (op)
-     register rtx op;
+legitimate_reload_constant_p (register rtx op)
 {
   /* Accept la(y) operands.  */
-  if (GET_CODE (op) == CONST_INT 
+  if (GET_CODE (op) == CONST_INT
       && DISP_IN_RANGE (INTVAL (op)))
     return 1;
 
@@ -1792,12 +1730,12 @@ legitimate_reload_constant_p (op)
     return 1;
 
   /* Accept lliXX operands.  */
-  if (TARGET_64BIT
+  if (TARGET_ZARCH
       && s390_single_hi (op, DImode, 0) >= 0)
   return 1;
 
   /* Accept larl operands.  */
-  if (TARGET_64BIT
+  if (TARGET_CPU_ZARCH
       && larl_operand (op, VOIDmode))
     return 1;
 
@@ -1809,9 +1747,7 @@ legitimate_reload_constant_p (op)
    return the class of reg to actually use.  */
 
 enum reg_class
-s390_preferred_reload_class (op, class)
-     rtx op;
-     enum reg_class class;
+s390_preferred_reload_class (rtx op, enum reg_class class)
 {
   /* This can happen if a floating point constant is being
      reloaded into an integer register.  Leave well alone.  */
@@ -1858,10 +1794,8 @@ s390_preferred_reload_class (op, class)
    is not a legitimate operand of the LOAD ADDRESS instruction.  */
 
 enum reg_class
-s390_secondary_input_reload_class (class, mode, in)
-     enum reg_class class ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-     rtx in;
+s390_secondary_input_reload_class (enum reg_class class ATTRIBUTE_UNUSED,
+				   enum machine_mode mode, rtx in)
 {
   if (s390_plus_operand (in, mode))
     return ADDR_REGS;
@@ -1872,14 +1806,12 @@ s390_secondary_input_reload_class (class, mode, in)
 /* Return the register class of a scratch register needed to
    store a register of class CLASS in MODE into OUT:
 
-   We need a temporary when storing a double-word to a 
+   We need a temporary when storing a double-word to a
    non-offsettable memory address.  */
 
 enum reg_class
-s390_secondary_output_reload_class (class, mode, out)
-     enum reg_class class;
-     enum machine_mode mode;
-     rtx out;
+s390_secondary_output_reload_class (enum reg_class class,
+				    enum machine_mode mode, rtx out)
 {
   if ((TARGET_64BIT ? mode == TImode
                     : (mode == DImode || mode == DFmode))
@@ -1893,14 +1825,12 @@ s390_secondary_output_reload_class (class, mode, out)
 }
 
 /* Return true if OP is a PLUS that is not a legitimate
-   operand for the LA instruction. 
+   operand for the LA instruction.
    OP is the current operation.
    MODE is the current operation mode.  */
 
 int
-s390_plus_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+s390_plus_operand (register rtx op, enum machine_mode mode)
 {
   if (!check_mode (op, &mode) || mode != Pmode)
     return FALSE;
@@ -1919,10 +1849,8 @@ s390_plus_operand (op, mode)
    SCRATCH may be used as scratch register.  */
 
 void
-s390_expand_plus_operand (target, src, scratch)
-     register rtx target;
-     register rtx src;
-     register rtx scratch;
+s390_expand_plus_operand (register rtx target, register rtx src,
+			  register rtx scratch)
 {
   rtx sum1, sum2;
   struct s390_address ad;
@@ -1988,14 +1916,14 @@ s390_expand_plus_operand (target, src, scratch)
    canonical form so that they will be recognized.  */
 
 static int
-s390_decompose_address (addr, out)
-     register rtx addr;
-     struct s390_address *out;
+s390_decompose_address (register rtx addr, struct s390_address *out)
 {
   rtx base = NULL_RTX;
   rtx indx = NULL_RTX;
   rtx disp = NULL_RTX;
   int pointer = FALSE;
+  int base_ptr = FALSE;
+  int indx_ptr = FALSE;
 
   /* Decompose address into base + index + displacement.  */
 
@@ -2041,35 +1969,18 @@ s390_decompose_address (addr, out)
     disp = addr;		/* displacement */
 
 
-  /* Prefer to use pointer as base, not index.  */
-  if (base && indx)
-    {
-      int base_ptr = GET_CODE (base) == UNSPEC
-		     || (REG_P (base) && REG_POINTER (base));
-      int indx_ptr = GET_CODE (indx) == UNSPEC
-		     || (REG_P (indx) && REG_POINTER (indx));
-
-      if (!base_ptr && indx_ptr)
-	{
-	  rtx tmp = base;
-	  base = indx;
-	  indx = tmp;
-	}
-    }
-
   /* Validate base register.  */
   if (base)
     {
       if (GET_CODE (base) == UNSPEC)
         {
-          if (XVECLEN (base, 0) != 1 || XINT (base, 1) != 101)
-	      return FALSE;
-	  base = XVECEXP (base, 0, 0);
-	  pointer = TRUE;
+          if (XVECLEN (base, 0) != 1 || XINT (base, 1) != UNSPEC_LTREL_BASE)
+	    return FALSE;
+	  base = gen_rtx_REG (Pmode, BASE_REGISTER);
 	}
 
       if (GET_CODE (base) != REG || GET_MODE (base) != Pmode)
-	  return FALSE;
+	return FALSE;
 
       if (REGNO (base) == BASE_REGISTER
 	  || REGNO (base) == STACK_POINTER_REGNUM
@@ -2082,7 +1993,7 @@ s390_decompose_address (addr, out)
 	      && REGNO (base) <= LAST_VIRTUAL_REGISTER)
           || (flag_pic
               && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
-        pointer = TRUE;
+        pointer = base_ptr = TRUE;
     }
 
   /* Validate index register.  */
@@ -2090,14 +2001,13 @@ s390_decompose_address (addr, out)
     {
       if (GET_CODE (indx) == UNSPEC)
         {
-          if (XVECLEN (indx, 0) != 1 || XINT (indx, 1) != 101)
-	      return FALSE;
-	  indx = XVECEXP (indx, 0, 0);
-	  pointer = TRUE;
+          if (XVECLEN (indx, 0) != 1 || XINT (indx, 1) != UNSPEC_LTREL_BASE)
+	    return FALSE;
+	  indx = gen_rtx_REG (Pmode, BASE_REGISTER);
 	}
 
       if (GET_CODE (indx) != REG || GET_MODE (indx) != Pmode)
-	  return FALSE;
+	return FALSE;
 
       if (REGNO (indx) == BASE_REGISTER
 	  || REGNO (indx) == STACK_POINTER_REGNUM
@@ -2110,7 +2020,16 @@ s390_decompose_address (addr, out)
 	      && REGNO (indx) <= LAST_VIRTUAL_REGISTER)
           || (flag_pic
               && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
-        pointer = TRUE;
+        pointer = indx_ptr = TRUE;
+    }
+
+  /* Prefer to use pointer as base, not index.  */
+  if (base && indx && !base_ptr
+      && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
+    {
+      rtx tmp = base;
+      base = indx;
+      indx = tmp;
     }
 
   /* Validate displacement.  */
@@ -2134,11 +2053,11 @@ s390_decompose_address (addr, out)
 	    }
         }
 
-      /* In the small-PIC case, the linker converts @GOT12 
+      /* In the small-PIC case, the linker converts @GOT
          and @GOTNTPOFF offsets to possible displacements.  */
       else if (GET_CODE (disp) == CONST
                && GET_CODE (XEXP (disp, 0)) == UNSPEC
-               && (XINT (XEXP (disp, 0), 1) == 110
+               && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
 		   || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
         {
           if (flag_pic != 1)
@@ -2155,7 +2074,7 @@ s390_decompose_address (addr, out)
         {
 	  pointer = TRUE;
         }
- 
+
       /* Likewise if a constant offset is present.  */
       else if (GET_CODE (disp) == CONST
                && GET_CODE (XEXP (disp, 0)) == PLUS
@@ -2167,7 +2086,7 @@ s390_decompose_address (addr, out)
 	  pointer = TRUE;
         }
 
-      /* We can convert literal pool addresses to 
+      /* We can convert literal pool addresses to
          displacements by basing them off the base register.  */
       else
         {
@@ -2194,7 +2113,7 @@ s390_decompose_address (addr, out)
           if (offset && offset >= GET_MODE_SIZE (get_pool_mode (disp)))
             return FALSE;
 
-          /* Either base or index must be free to 
+          /* Either base or index must be free to
              hold the base register.  */
           if (base && indx)
             return FALSE;
@@ -2205,7 +2124,8 @@ s390_decompose_address (addr, out)
           else
             base = gen_rtx_REG (Pmode, BASE_REGISTER);
 
-          disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), 100);
+          disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
+				 UNSPEC_LTREL_OFFSET);
           disp = gen_rtx_CONST (Pmode, disp);
 
           if (offset)
@@ -2217,7 +2137,7 @@ s390_decompose_address (addr, out)
 
   if (!base && !indx)
     pointer = TRUE;
-   
+
   if (out)
     {
       out->base = base;
@@ -2233,10 +2153,8 @@ s390_decompose_address (addr, out)
    STRICT specifies whether strict register checking applies.  */
 
 int
-legitimate_address_p (mode, addr, strict)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     register rtx addr;
-     int strict;
+legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED,
+		      register rtx addr, int strict)
 {
   struct s390_address ad;
   if (!s390_decompose_address (addr, &ad))
@@ -2265,8 +2183,7 @@ legitimate_address_p (mode, addr, strict)
    address, as LA performs only a 31-bit addition.  */
 
 int
-legitimate_la_operand_p (op)
-     register rtx op;
+legitimate_la_operand_p (register rtx op)
 {
   struct s390_address addr;
   if (!s390_decompose_address (op, &addr))
@@ -2280,10 +2197,9 @@ legitimate_la_operand_p (op)
 
 /* Return 1 if OP is a valid operand for the LA instruction,
    and we prefer to use LA over addition to compute it.  */
-   
+
 int
-preferred_la_operand_p (op)
-     register rtx op;
+preferred_la_operand_p (register rtx op)
 {
   struct s390_address addr;
   if (!s390_decompose_address (op, &addr))
@@ -2307,9 +2223,7 @@ preferred_la_operand_p (op)
    where legitimate_la_operand_p (SRC) returns false.  */
 
 void
-s390_load_address (dst, src)
-     rtx dst;
-     rtx src;
+s390_load_address (rtx dst, rtx src)
 {
   if (TARGET_64BIT)
     emit_move_insn (dst, src);
@@ -2336,9 +2250,7 @@ s390_load_address (dst, src)
    reg also appears in the address.  */
 
 rtx
-legitimize_pic_address (orig, reg)
-     rtx orig;
-     rtx reg;
+legitimize_pic_address (rtx orig, rtx reg)
 {
   rtx addr = orig;
   rtx new = orig;
@@ -2348,27 +2260,27 @@ legitimize_pic_address (orig, reg)
       || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr)))
     {
       /* This is a local symbol.  */
-      if (TARGET_64BIT && larl_operand (addr, VOIDmode))
+      if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode))
         {
-          /* Access local symbols PC-relative via LARL.  
-             This is the same as in the non-PIC case, so it is 
+          /* Access local symbols PC-relative via LARL.
+             This is the same as in the non-PIC case, so it is
              handled automatically ...  */
         }
       else
         {
-          /* Access local symbols relative to the literal pool.  */
+          /* Access local symbols relative to the GOT.  */
 
           rtx temp = reg? reg : gen_reg_rtx (Pmode);
 
-          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 100);
+	  if (reload_in_progress || reload_completed)
+	    regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
+
+          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
           addr = gen_rtx_CONST (Pmode, addr);
           addr = force_const_mem (Pmode, addr);
 	  emit_move_insn (temp, addr);
 
-          base = gen_rtx_REG (Pmode, BASE_REGISTER);
-          base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 101);
-          new = gen_rtx_PLUS (Pmode, base, temp);
-
+          new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
           if (reg != 0)
             {
               emit_move_insn (reg, new);
@@ -2384,12 +2296,12 @@ legitimize_pic_address (orig, reg)
       if (flag_pic == 1)
         {
           /* Assume GOT offset < 4k.  This is handled the same way
-             in both 31- and 64-bit code (@GOT12).  */
+             in both 31- and 64-bit code (@GOT).  */
 
 	  if (reload_in_progress || reload_completed)
 	    regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
 
-          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 110);
+          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
           new = gen_rtx_CONST (Pmode, new);
           new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new);
           new = gen_rtx_MEM (Pmode, new);
@@ -2397,14 +2309,14 @@ legitimize_pic_address (orig, reg)
           emit_move_insn (reg, new);
           new = reg;
         }
-      else if (TARGET_64BIT)
+      else if (TARGET_CPU_ZARCH)
         {
           /* If the GOT offset might be >= 4k, we determine the position
              of the GOT entry via a PC-relative LARL (@GOTENT).  */
 
           rtx temp = gen_reg_rtx (Pmode);
 
-          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 111);
+          new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
           new = gen_rtx_CONST (Pmode, new);
           emit_move_insn (temp, new);
 
@@ -2415,7 +2327,7 @@ legitimize_pic_address (orig, reg)
         }
       else
         {
-          /* If the GOT offset might be >= 4k, we have to load it 
+          /* If the GOT offset might be >= 4k, we have to load it
              from the literal pool (@GOT).  */
 
           rtx temp = gen_reg_rtx (Pmode);
@@ -2423,7 +2335,7 @@ legitimize_pic_address (orig, reg)
 	  if (reload_in_progress || reload_completed)
 	    regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
 
-          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 112);
+          addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
           addr = gen_rtx_CONST (Pmode, addr);
           addr = force_const_mem (Pmode, addr);
           emit_move_insn (temp, addr);
@@ -2434,7 +2346,7 @@ legitimize_pic_address (orig, reg)
           emit_move_insn (reg, new);
           new = reg;
         }
-    }      
+    }
   else
     {
       if (GET_CODE (addr) == CONST)
@@ -2446,35 +2358,41 @@ legitimize_pic_address (orig, reg)
                 abort ();
               switch (XINT (addr, 1))
                 {
-                  /* If someone moved an @GOT or lt-relative UNSPEC
+                  /* If someone moved a GOT-relative UNSPEC
                      out of the literal pool, force them back in.  */
-                  case 100:
-                  case 112:
-                  case 114:
+                  case UNSPEC_GOTOFF:
+                  case UNSPEC_PLTOFF:
                     new = force_const_mem (Pmode, orig);
                     break;
 
+                  /* @GOT is OK as is if small.  */
+		  case UNSPEC_GOT:
+		    if (flag_pic == 2)
+		      new = force_const_mem (Pmode, orig);
+		    break;
+
                   /* @GOTENT is OK as is.  */
-                  case 111:
+                  case UNSPEC_GOTENT:
                     break;
 
                   /* @PLT is OK as is on 64-bit, must be converted to
-                     lt-relative PLT on 31-bit.  */
-                  case 113:
-                    if (!TARGET_64BIT)
+                     GOT-relative @PLTOFF on 31-bit.  */
+                  case UNSPEC_PLT:
+                    if (!TARGET_CPU_ZARCH)
                       {
                         rtx temp = reg? reg : gen_reg_rtx (Pmode);
 
+			if (reload_in_progress || reload_completed)
+			  regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
+
                         addr = XVECEXP (addr, 0, 0);
-                        addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), 114);
+                        addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
+					       UNSPEC_PLTOFF);
                         addr = gen_rtx_CONST (Pmode, addr);
                         addr = force_const_mem (Pmode, addr);
 	                emit_move_insn (temp, addr);
 
-                        base = gen_rtx_REG (Pmode, BASE_REGISTER);
-                        base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 101);
-                        new = gen_rtx_PLUS (Pmode, base, temp);
-
+                        new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
                         if (reg != 0)
                           {
                             emit_move_insn (reg, new);
@@ -2494,17 +2412,17 @@ legitimize_pic_address (orig, reg)
       if (GET_CODE (addr) == PLUS)
 	{
 	  rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1);
-	  /* Check first to see if this is a constant offset 
+	  /* Check first to see if this is a constant offset
              from a local symbol reference.  */
 	  if ((GET_CODE (op0) == LABEL_REF
 		|| (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0)))
 	      && GET_CODE (op1) == CONST_INT)
 	    {
-              if (TARGET_64BIT && larl_operand (op0, VOIDmode))
+              if (TARGET_CPU_ZARCH && larl_operand (op0, VOIDmode))
                 {
                   if (INTVAL (op1) & 1)
                     {
-                      /* LARL can't handle odd offsets, so emit a 
+                      /* LARL can't handle odd offsets, so emit a
                          pair of LARL and LA.  */
                       rtx temp = reg? reg : gen_reg_rtx (Pmode);
 
@@ -2533,20 +2451,21 @@ legitimize_pic_address (orig, reg)
                 }
               else
                 {
-                  /* Access local symbols relative to the literal pool.  */
+                  /* Access local symbols relative to the GOT.  */
 
                   rtx temp = reg? reg : gen_reg_rtx (Pmode);
 
-                  addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), 100);
+		  if (reload_in_progress || reload_completed)
+		    regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1;
+
+                  addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0),
+					 UNSPEC_GOTOFF);
                   addr = gen_rtx_PLUS (Pmode, addr, op1);
                   addr = gen_rtx_CONST (Pmode, addr);
                   addr = force_const_mem (Pmode, addr);
-        	  emit_move_insn (temp, addr);
-
-                  base = gen_rtx_REG (Pmode, BASE_REGISTER);
-                  base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 101);
-                  new = gen_rtx_PLUS (Pmode, base, temp);
+	  emit_move_insn (temp, addr);
 
+                  new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
                   if (reg != 0)
                     {
                       emit_move_insn (reg, new);
@@ -2555,7 +2474,7 @@ legitimize_pic_address (orig, reg)
                 }
 	    }
 
-          /* Now, check whether it is an LT-relative symbol plus offset
+          /* Now, check whether it is a GOT relative symbol plus offset
              that was pulled out of the literal pool.  Force it back in.  */
 
 	  else if (GET_CODE (op0) == UNSPEC
@@ -2563,7 +2482,7 @@ legitimize_pic_address (orig, reg)
             {
 	      if (XVECLEN (op0, 0) != 1)
                 abort ();
-              if (XINT (op0, 1) != 100)
+              if (XINT (op0, 1) != UNSPEC_GOTOFF)
                 abort ();
 
               new = force_const_mem (Pmode, orig);
@@ -2599,7 +2518,7 @@ legitimize_pic_address (orig, reg)
 /* Load the thread pointer into a register.  */
 
 static rtx
-get_thread_pointer ()
+get_thread_pointer (void)
 {
   rtx tp;
 
@@ -2614,7 +2533,7 @@ get_thread_pointer ()
 
 static GTY(()) rtx s390_tls_symbol;
 rtx
-s390_tls_get_offset ()
+s390_tls_get_offset (void)
 {
   if (!s390_tls_symbol)
     s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
@@ -2626,9 +2545,7 @@ s390_tls_get_offset ()
    this (thread-local) address.  REG may be used as temporary.  */
 
 static rtx
-legitimize_tls_address (addr, reg)
-     rtx addr;
-     rtx reg;
+legitimize_tls_address (rtx addr, rtx reg)
 {
   rtx new, tls_call, temp, base, r2, insn;
 
@@ -2708,7 +2625,7 @@ legitimize_tls_address (addr, reg)
 	    temp = gen_reg_rtx (Pmode);
 	    emit_move_insn (temp, new);
 	  }
-	else if (TARGET_64BIT)
+	else if (TARGET_CPU_ZARCH)
 	  {
 	    /* If the GOT offset might be >= 4k, we determine the position
 	       of the GOT entry via a PC-relative LARL.  */
@@ -2725,7 +2642,7 @@ legitimize_tls_address (addr, reg)
 	  }
 	else if (flag_pic)
 	  {
-	    /* If the GOT offset might be >= 4k, we have to load it 
+	    /* If the GOT offset might be >= 4k, we have to load it
 	       from the literal pool.  */
 
 	    if (reload_in_progress || reload_completed)
@@ -2797,7 +2714,7 @@ legitimize_tls_address (addr, reg)
       switch (XINT (XEXP (addr, 0), 1))
 	{
 	case UNSPEC_INDNTPOFF:
-	  if (TARGET_64BIT)
+	  if (TARGET_CPU_ZARCH)
 	    new = addr;
 	  else
 	    abort ();
@@ -2817,8 +2734,7 @@ legitimize_tls_address (addr, reg)
 /* Emit insns to move operands[1] into operands[0].  */
 
 void
-emit_symbolic_move (operands)
-     rtx *operands;
+emit_symbolic_move (rtx *operands)
 {
   rtx temp = no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode);
 
@@ -2842,10 +2758,8 @@ emit_symbolic_move (operands)
    See comments by legitimize_pic_address for details.  */
 
 rtx
-legitimize_address (x, oldx, mode)
-     register rtx x;
-     register rtx oldx ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+legitimize_address (register rtx x, register rtx oldx ATTRIBUTE_UNUSED,
+		    enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   rtx constant_term = const0_rtx;
 
@@ -2859,8 +2773,8 @@ legitimize_address (x, oldx, mode)
   else if (flag_pic)
     {
       if (SYMBOLIC_CONST (x)
-          || (GET_CODE (x) == PLUS 
-              && (SYMBOLIC_CONST (XEXP (x, 0)) 
+          || (GET_CODE (x) == PLUS
+              && (SYMBOLIC_CONST (XEXP (x, 0))
                   || SYMBOLIC_CONST (XEXP (x, 1)))))
 	  x = legitimize_pic_address (x, 0);
 
@@ -2872,7 +2786,7 @@ legitimize_address (x, oldx, mode)
 
   /* Optimize loading of large displacements by splitting them
      into the multiple of 4K and the rest; this allows the
-     former to be CSE'd if possible. 
+     former to be CSE'd if possible.
 
      Don't do this if the displacement is added to a register
      pointing into the stack frame, as the offsets will
@@ -2927,21 +2841,18 @@ legitimize_address (x, oldx, mode)
 /* Emit code to move LEN bytes from DST to SRC.  */
 
 void
-s390_expand_movstr (dst, src, len)
-     rtx dst;
-     rtx src;
-     rtx len;
+s390_expand_movstr (rtx dst, rtx src, rtx len)
 {
-  rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) = 
+  rtx (*gen_short) (rtx, rtx, rtx) =
     TARGET_64BIT ? gen_movstr_short_64 : gen_movstr_short_31;
-  rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) = 
+  rtx (*gen_long) (rtx, rtx, rtx, rtx) =
     TARGET_64BIT ? gen_movstr_long_64 : gen_movstr_long_31;
 
 
   if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
     {
       if (INTVAL (len) > 0)
-        emit_insn ((*gen_short) (dst, src, GEN_INT (INTVAL (len) - 1)));
+        emit_insn (gen_short (dst, src, GEN_INT (INTVAL (len) - 1)));
     }
 
   else if (TARGET_MVCLE)
@@ -2951,15 +2862,15 @@ s390_expand_movstr (dst, src, len)
       rtx reg0 = gen_reg_rtx (double_mode);
       rtx reg1 = gen_reg_rtx (double_mode);
 
-      emit_move_insn (gen_highpart (single_mode, reg0), 
+      emit_move_insn (gen_highpart (single_mode, reg0),
 		      force_operand (XEXP (dst, 0), NULL_RTX));
-      emit_move_insn (gen_highpart (single_mode, reg1), 
+      emit_move_insn (gen_highpart (single_mode, reg1),
 		      force_operand (XEXP (src, 0), NULL_RTX));
 
       convert_move (gen_lowpart (single_mode, reg0), len, 1);
       convert_move (gen_lowpart (single_mode, reg1), len, 1);
 
-      emit_insn ((*gen_long) (reg0, reg1, reg0, reg1));
+      emit_insn (gen_long (reg0, reg1, reg0, reg1));
     }
 
   else
@@ -2973,7 +2884,7 @@ s390_expand_movstr (dst, src, len)
       if (mode == VOIDmode)
         mode = word_mode;
 
-      type = (*lang_hooks.types.type_for_mode) (mode, 1);
+      type = lang_hooks.types.type_for_mode (mode, 1);
       if (!type)
         abort ();
 
@@ -2983,14 +2894,14 @@ s390_expand_movstr (dst, src, len)
       blocks = gen_reg_rtx (mode);
 
       convert_move (count, len, 1);
-      emit_cmp_and_jump_insns (count, const0_rtx, 
+      emit_cmp_and_jump_insns (count, const0_rtx,
 			       EQ, NULL_RTX, mode, 1, end_label);
 
       emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
       emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
       dst = change_address (dst, VOIDmode, dst_addr);
       src = change_address (src, VOIDmode, src_addr);
-     
+
       temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
       if (temp != count)
         emit_move_insn (count, temp);
@@ -3004,19 +2915,19 @@ s390_expand_movstr (dst, src, len)
 					   make_tree (type, blocks),
 					   make_tree (type, const0_rtx)));
 
-      emit_insn ((*gen_short) (dst, src, GEN_INT (255)));
-      s390_load_address (dst_addr, 
+      emit_insn (gen_short (dst, src, GEN_INT (255)));
+      s390_load_address (dst_addr,
 			 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
-      s390_load_address (src_addr, 
+      s390_load_address (src_addr,
 			 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
-      
+
       temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
       if (temp != blocks)
         emit_move_insn (blocks, temp);
 
       expand_end_loop ();
 
-      emit_insn ((*gen_short) (dst, src, convert_to_mode (word_mode, count, 1)));
+      emit_insn (gen_short (dst, src, convert_to_mode (word_mode, count, 1)));
       emit_label (end_label);
     }
 }
@@ -3024,20 +2935,18 @@ s390_expand_movstr (dst, src, len)
 /* Emit code to clear LEN bytes at DST.  */
 
 void
-s390_expand_clrstr (dst, len)
-     rtx dst;
-     rtx len;
+s390_expand_clrstr (rtx dst, rtx len)
 {
-  rtx (*gen_short) PARAMS ((rtx, rtx)) = 
+  rtx (*gen_short) (rtx, rtx) =
     TARGET_64BIT ? gen_clrstr_short_64 : gen_clrstr_short_31;
-  rtx (*gen_long) PARAMS ((rtx, rtx, rtx)) = 
+  rtx (*gen_long) (rtx, rtx, rtx) =
     TARGET_64BIT ? gen_clrstr_long_64 : gen_clrstr_long_31;
 
 
   if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
     {
       if (INTVAL (len) > 0)
-        emit_insn ((*gen_short) (dst, GEN_INT (INTVAL (len) - 1)));
+        emit_insn (gen_short (dst, GEN_INT (INTVAL (len) - 1)));
     }
 
   else if (TARGET_MVCLE)
@@ -3047,14 +2956,14 @@ s390_expand_clrstr (dst, len)
       rtx reg0 = gen_reg_rtx (double_mode);
       rtx reg1 = gen_reg_rtx (double_mode);
 
-      emit_move_insn (gen_highpart (single_mode, reg0), 
+      emit_move_insn (gen_highpart (single_mode, reg0),
 		      force_operand (XEXP (dst, 0), NULL_RTX));
       convert_move (gen_lowpart (single_mode, reg0), len, 1);
 
       emit_move_insn (gen_highpart (single_mode, reg1), const0_rtx);
       emit_move_insn (gen_lowpart (single_mode, reg1), const0_rtx);
 
-      emit_insn ((*gen_long) (reg0, reg1, reg0));
+      emit_insn (gen_long (reg0, reg1, reg0));
     }
 
   else
@@ -3068,7 +2977,7 @@ s390_expand_clrstr (dst, len)
       if (mode == VOIDmode)
         mode = word_mode;
 
-      type = (*lang_hooks.types.type_for_mode) (mode, 1);
+      type = lang_hooks.types.type_for_mode (mode, 1);
       if (!type)
         abort ();
 
@@ -3078,12 +2987,12 @@ s390_expand_clrstr (dst, len)
       blocks = gen_reg_rtx (mode);
 
       convert_move (count, len, 1);
-      emit_cmp_and_jump_insns (count, const0_rtx, 
+      emit_cmp_and_jump_insns (count, const0_rtx,
 			       EQ, NULL_RTX, mode, 1, end_label);
 
       emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
       dst = change_address (dst, VOIDmode, dst_addr);
-     
+
       temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
       if (temp != count)
         emit_move_insn (count, temp);
@@ -3097,17 +3006,17 @@ s390_expand_clrstr (dst, len)
 					   make_tree (type, blocks),
 					   make_tree (type, const0_rtx)));
 
-      emit_insn ((*gen_short) (dst, GEN_INT (255)));
-      s390_load_address (dst_addr, 
+      emit_insn (gen_short (dst, GEN_INT (255)));
+      s390_load_address (dst_addr,
 			 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
-      
+
       temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
       if (temp != blocks)
         emit_move_insn (blocks, temp);
 
       expand_end_loop ();
 
-      emit_insn ((*gen_short) (dst, convert_to_mode (word_mode, count, 1)));
+      emit_insn (gen_short (dst, convert_to_mode (word_mode, count, 1)));
       emit_label (end_label);
     }
 }
@@ -3116,17 +3025,13 @@ s390_expand_clrstr (dst, len)
    and return the result in TARGET.  */
 
 void
-s390_expand_cmpstr (target, op0, op1, len)
-     rtx target;
-     rtx op0;
-     rtx op1;
-     rtx len;
-{
-  rtx (*gen_short) PARAMS ((rtx, rtx, rtx)) = 
-    TARGET_64BIT ? gen_cmpstr_short_64 : gen_cmpstr_short_31;
-  rtx (*gen_long) PARAMS ((rtx, rtx, rtx, rtx)) = 
-    TARGET_64BIT ? gen_cmpstr_long_64 : gen_cmpstr_long_31;
-  rtx (*gen_result) PARAMS ((rtx)) =
+s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
+{
+  rtx (*gen_short) (rtx, rtx, rtx) =
+    TARGET_64BIT ? gen_cmpmem_short_64 : gen_cmpmem_short_31;
+  rtx (*gen_long) (rtx, rtx, rtx, rtx) =
+    TARGET_64BIT ? gen_cmpmem_long_64 : gen_cmpmem_long_31;
+  rtx (*gen_result) (rtx) =
     GET_MODE (target) == DImode ? gen_cmpint_di : gen_cmpint_si;
 
   op0 = protect_from_queue (op0, 0);
@@ -3137,8 +3042,8 @@ s390_expand_cmpstr (target, op0, op1, len)
     {
       if (INTVAL (len) > 0)
         {
-          emit_insn ((*gen_short) (op0, op1, GEN_INT (INTVAL (len) - 1)));
-          emit_insn ((*gen_result) (target));
+          emit_insn (gen_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
+          emit_insn (gen_result (target));
         }
       else
         emit_move_insn (target, const0_rtx);
@@ -3151,16 +3056,16 @@ s390_expand_cmpstr (target, op0, op1, len)
       rtx reg0 = gen_reg_rtx (double_mode);
       rtx reg1 = gen_reg_rtx (double_mode);
 
-      emit_move_insn (gen_highpart (single_mode, reg0), 
+      emit_move_insn (gen_highpart (single_mode, reg0),
 		      force_operand (XEXP (op0, 0), NULL_RTX));
-      emit_move_insn (gen_highpart (single_mode, reg1), 
+      emit_move_insn (gen_highpart (single_mode, reg1),
 		      force_operand (XEXP (op1, 0), NULL_RTX));
 
       convert_move (gen_lowpart (single_mode, reg0), len, 1);
       convert_move (gen_lowpart (single_mode, reg1), len, 1);
 
-      emit_insn ((*gen_long) (reg0, reg1, reg0, reg1));
-      emit_insn ((*gen_result) (target));
+      emit_insn (gen_long (reg0, reg1, reg0, reg1));
+      emit_insn (gen_result (target));
     }
 
 #if 0
@@ -3177,7 +3082,7 @@ s390_expand_cmpstr (target, op0, op1, len)
       if (mode == VOIDmode)
         mode = word_mode;
 
-      type = (*lang_hooks.types.type_for_mode) (mode, 1);
+      type = lang_hooks.types.type_for_mode (mode, 1);
       if (!type)
         abort ();
 
@@ -3187,14 +3092,14 @@ s390_expand_cmpstr (target, op0, op1, len)
       blocks = gen_reg_rtx (mode);
 
       convert_move (count, len, 1);
-      emit_cmp_and_jump_insns (count, const0_rtx, 
+      emit_cmp_and_jump_insns (count, const0_rtx,
 			       EQ, NULL_RTX, mode, 1, end_label);
 
       emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
       emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
       op0 = change_address (op0, VOIDmode, addr0);
       op1 = change_address (op1, VOIDmode, addr1);
-     
+
       temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, 0);
       if (temp != count)
         emit_move_insn (count, temp);
@@ -3208,28 +3113,28 @@ s390_expand_cmpstr (target, op0, op1, len)
 					   make_tree (type, blocks),
 					   make_tree (type, const0_rtx)));
 
-      emit_insn ((*gen_short) (op0, op1, GEN_INT (255)));
+      emit_insn (gen_short (op0, op1, GEN_INT (255)));
       temp = gen_rtx_NE (VOIDmode, gen_rtx_REG (CCSmode, 33), const0_rtx);
-      temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, 
+      temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
 			gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
       temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
       emit_jump_insn (temp);
 
-      s390_load_address (addr0, 
+      s390_load_address (addr0,
 			 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
-      s390_load_address (addr1, 
+      s390_load_address (addr1,
 			 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
-      
+
       temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, 0);
       if (temp != blocks)
         emit_move_insn (blocks, temp);
 
       expand_end_loop ();
 
-      emit_insn ((*gen_short) (op0, op1, convert_to_mode (word_mode, count, 1)));
+      emit_insn (gen_short (op0, op1, convert_to_mode (word_mode, count, 1)));
       emit_label (end_label);
 
-      emit_insn ((*gen_result) (target));
+      emit_insn (gen_result (target));
     }
 #endif
 }
@@ -3238,10 +3143,7 @@ s390_expand_cmpstr (target, op0, op1, len)
    We need to emit DTP-relative relocations.  */
 
 void
-s390_output_dwarf_dtprel (file, size, x)
-     FILE *file;
-     int size;
-     rtx x;
+s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
 {
   switch (size)
     {
@@ -3263,8 +3165,7 @@ s390_output_dwarf_dtprel (file, size, x)
    and turn them back into a direct symbol reference.  */
 
 static rtx
-s390_delegitimize_address (orig_x)
-     rtx orig_x;
+s390_delegitimize_address (rtx orig_x)
 {
   rtx x = orig_x, y;
 
@@ -3279,7 +3180,7 @@ s390_delegitimize_address (orig_x)
     {
       y = XEXP (XEXP (x, 1), 0);
       if (GET_CODE (y) == UNSPEC
-	  && XINT (y, 1) == 110)
+	  && XINT (y, 1) == UNSPEC_GOT)
 	return XVECEXP (y, 0, 0);
       return orig_x;
     }
@@ -3288,19 +3189,19 @@ s390_delegitimize_address (orig_x)
     {
       y = XEXP (x, 0);
       if (GET_CODE (y) == UNSPEC
-	  && XINT (y, 1) == 111)
+	  && XINT (y, 1) == UNSPEC_GOTENT)
 	return XVECEXP (y, 0, 0);
       return orig_x;
     }
 
-  return orig_x;      
+  return orig_x;
 }
 
 /* Locate some local-dynamic symbol still in use by this function
    so that we can print its name in local-dynamic base patterns.  */
 
 static const char *
-get_some_local_dynamic_name ()
+get_some_local_dynamic_name (void)
 {
   rtx insn;
 
@@ -3316,9 +3217,7 @@ get_some_local_dynamic_name ()
 }
 
 static int
-get_some_local_dynamic_name_1 (px, data)
-     rtx *px;
-     void *data ATTRIBUTE_UNUSED;
+get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
 {
   rtx x = *px;
 
@@ -3338,13 +3237,11 @@ get_some_local_dynamic_name_1 (px, data)
   return 0;
 }
 
-/* Output symbolic constant X in assembler syntax to 
+/* Output symbolic constant X in assembler syntax to
    stdio stream FILE.  */
 
 void
-s390_output_symbolic_const (file, x)
-     FILE *file;
-     rtx x;
+s390_output_symbolic_const (FILE *file, rtx x)
 {
   switch (GET_CODE (x))
     {
@@ -3378,37 +3275,25 @@ s390_output_symbolic_const (file, x)
         output_operand_lossage ("invalid UNSPEC as operand (1)");
       switch (XINT (x, 1))
         {
-        case 100:
-        case 104:
-	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
-          fprintf (file, "-");	
-	  s390_output_symbolic_const (file, cfun->machine->literal_pool_label);
- 	  break;
-        case 105:
-	  s390_output_symbolic_const (file, cfun->machine->literal_pool_label);
-          fprintf (file, "-");
-	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
-	  break;
-	case 110:
-	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
-	  fprintf (file, "@GOT12");
-	  break;
-	case 111:
+	case UNSPEC_GOTENT:
 	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
 	  fprintf (file, "@GOTENT");
 	  break;
-	case 112:
+	case UNSPEC_GOT:
 	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
 	  fprintf (file, "@GOT");
 	  break;
-	case 113:
+	case UNSPEC_GOTOFF:
+	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
+	  fprintf (file, "@GOTOFF");
+	  break;
+	case UNSPEC_PLT:
 	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
 	  fprintf (file, "@PLT");
 	  break;
-	case 114:
+	case UNSPEC_PLTOFF:
 	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
-          fprintf (file, "@PLT-");
-	  s390_output_symbolic_const (file, cfun->machine->literal_pool_label);
+	  fprintf (file, "@PLTOFF");
 	  break;
 	case UNSPEC_TLSGD:
 	  s390_output_symbolic_const (file, XVECEXP (x, 0, 0));
@@ -3446,13 +3331,11 @@ s390_output_symbolic_const (file, x)
     }
 }
 
-/* Output address operand ADDR in assembler syntax to 
+/* Output address operand ADDR in assembler syntax to
    stdio stream FILE.  */
 
 void
-print_operand_address (file, addr)
-     FILE *file;
-     rtx addr;
+print_operand_address (FILE *file, rtx addr)
 {
   struct s390_address ad;
 
@@ -3460,7 +3343,7 @@ print_operand_address (file, addr)
       || (ad.base && !REG_OK_FOR_BASE_STRICT_P (ad.base))
       || (ad.indx && !REG_OK_FOR_INDEX_STRICT_P (ad.indx)))
     output_operand_lossage ("Cannot decompose address.");
- 
+
   if (ad.disp)
     s390_output_symbolic_const (file, ad.disp);
   else
@@ -3473,8 +3356,8 @@ print_operand_address (file, addr)
     fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
 }
 
-/* Output operand X in assembler syntax to stdio stream FILE.  
-   CODE specified the format flag.  The following format flags 
+/* Output operand X in assembler syntax to stdio stream FILE.
+   CODE specified the format flag.  The following format flags
    are recognized:
 
     'C': print opcode suffix for branch condition.
@@ -3490,10 +3373,7 @@ print_operand_address (file, addr)
     'h': print integer X as if it's a signed word.  */
 
 void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
+print_operand (FILE *file, rtx x, int code)
 {
   switch (code)
     {
@@ -3630,10 +3510,7 @@ print_operand (file, x, code)
    handle values smaller than INT_MIN when printed in decimal.  */
 
 static bool
-s390_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   if (size == 8 && aligned_p
       && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
@@ -3645,25 +3522,23 @@ s390_assemble_integer (x, size, aligned_p)
   return default_assemble_integer (x, size, aligned_p);
 }
 
-/* Returns true if register REGNO is used  for forming 
+/* Returns true if register REGNO is used  for forming
    a memory address in expression X.  */
 
 static int
-reg_used_in_mem_p (regno, x)
-     int regno;
-     rtx x;
+reg_used_in_mem_p (int regno, rtx x)
 {
   enum rtx_code code = GET_CODE (x);
   int i, j;
   const char *fmt;
-  
+
   if (code == MEM)
     {
       if (refers_to_regno_p (regno, regno+1,
 			     XEXP (x, 0), 0))
 	return 1;
     }
-  else if (code == SET 
+  else if (code == SET
 	   && GET_CODE (SET_DEST (x)) == PC)
     {
       if (refers_to_regno_p (regno, regno+1,
@@ -3677,7 +3552,7 @@ reg_used_in_mem_p (regno, x)
       if (fmt[i] == 'e'
 	  && reg_used_in_mem_p (regno, XEXP (x, i)))
 	return 1;
-      
+
       else if (fmt[i] == 'E')
 	for (j = 0; j < XVECLEN (x, i); j++)
 	  if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
@@ -3689,10 +3564,8 @@ reg_used_in_mem_p (regno, x)
 /* Returns true if expression DEP_RTX sets an address register
    used by instruction INSN to address memory.  */
 
-static int 
-addr_generation_dependency_p (dep_rtx, insn)
-     rtx dep_rtx; 
-     rtx insn;
+static int
+addr_generation_dependency_p (rtx dep_rtx, rtx insn)
 {
   rtx target, pat;
 
@@ -3734,15 +3607,13 @@ addr_generation_dependency_p (dep_rtx, insn)
 
 /* Return 1, if dep_insn sets register used in insn in the agen unit.  */
 
-int 
-s390_agen_dep_p(dep_insn, insn)
-     rtx dep_insn;
-     rtx insn;
-{ 
+int
+s390_agen_dep_p (rtx dep_insn, rtx insn)
+{
   rtx dep_rtx = PATTERN (dep_insn);
   int i;
-  
-  if (GET_CODE (dep_rtx) == SET  
+
+  if (GET_CODE (dep_rtx) == SET
       && addr_generation_dependency_p (dep_rtx, insn))
     return 1;
   else if (GET_CODE (dep_rtx) == PARALLEL)
@@ -3757,22 +3628,18 @@ s390_agen_dep_p(dep_insn, insn)
 }
 
 /* Return the modified cost of the dependency of instruction INSN
-   on instruction DEP_INSN through the link LINK.  COST is the 
+   on instruction DEP_INSN through the link LINK.  COST is the
    default cost of that dependency.
 
    Data dependencies are all handled without delay.  However, if a
-   register is modified and subsequently used as base or index 
+   register is modified and subsequently used as base or index
    register of a memory reference, at least 4 cycles need to pass
-   between setting and using the register to avoid pipeline stalls.  
+   between setting and using the register to avoid pipeline stalls.
    An exception is the LA instruction. An address generated by LA can
    be used by introducing only a one cycle stall on the pipeline.  */
 
 static int
-s390_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
+s390_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 {
   rtx dep_rtx;
   int i;
@@ -3791,7 +3658,7 @@ s390_adjust_cost (insn, link, dep_insn, cost)
   /* DFA based scheduling checks address dependency in md file.  */
   if (s390_use_dfa_pipeline_interface ())
   {
-    /* Operand forward in case of lr, load and la.  */ 
+    /* Operand forward in case of lr, load and la.  */
     if (s390_tune == PROCESSOR_2084_Z990
         && cost == 1
 	&& (s390_safe_attr_type (dep_insn) == TYPE_LA
@@ -3803,15 +3670,15 @@ s390_adjust_cost (insn, link, dep_insn, cost)
 
   dep_rtx = PATTERN (dep_insn);
 
-  if (GET_CODE (dep_rtx) == SET 
+  if (GET_CODE (dep_rtx) == SET
       && addr_generation_dependency_p (dep_rtx, insn))
-    cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;  
+    cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
   else if (GET_CODE (dep_rtx) == PARALLEL)
     {
       for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
 	{
 	  if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
-	    cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;  
+	    cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
 	}
     }
 
@@ -3820,15 +3687,13 @@ s390_adjust_cost (insn, link, dep_insn, cost)
 /* A C statement (sans semicolon) to update the integer scheduling priority
    INSN_PRIORITY (INSN).  Increase the priority to execute the INSN earlier,
    reduce the priority to execute INSN later.  Do not define this macro if
-   you do not need to adjust the scheduling priorities of insns. 
+   you do not need to adjust the scheduling priorities of insns.
 
-   A STD instruction should be scheduled earlier, 
+   A STD instruction should be scheduled earlier,
    in order to use the bypass.  */
 
 static int
-s390_adjust_priority (insn, priority)
-     rtx insn ATTRIBUTE_UNUSED;
-     int priority;
+s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
 {
   if (! INSN_P (insn))
     return priority;
@@ -3854,9 +3719,9 @@ s390_adjust_priority (insn, priority)
 /* The number of instructions that can be issued per cycle.  */
 
 static int
-s390_issue_rate ()
+s390_issue_rate (void)
 {
-  if (s390_tune == PROCESSOR_2084_Z990) 
+  if (s390_tune == PROCESSOR_2084_Z990)
     return 3;
   return 1;
 }
@@ -3865,7 +3730,7 @@ s390_issue_rate ()
    insn scheduler.  */
 
 static int
-s390_use_dfa_pipeline_interface ()
+s390_use_dfa_pipeline_interface (void)
 {
   if (s390_tune == PROCESSOR_2064_Z900
       || s390_tune == PROCESSOR_2084_Z990)
@@ -3875,7 +3740,7 @@ s390_use_dfa_pipeline_interface ()
 }
 
 static int
-s390_first_cycle_multipass_dfa_lookahead ()
+s390_first_cycle_multipass_dfa_lookahead (void)
 {
   return s390_use_dfa_pipeline_interface () ? 4 : 0;
 }
@@ -3884,28 +3749,25 @@ s390_first_cycle_multipass_dfa_lookahead ()
    Triggers default sort algorithm to better slot instructions.  */
 
 static int
-s390_sched_reorder2 (dump, sched_verbose, ready, pn_ready, clock_var)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     rtx *ready ATTRIBUTE_UNUSED;
-     int *pn_ready ATTRIBUTE_UNUSED;
-     int clock_var ATTRIBUTE_UNUSED;
+s390_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
+		     int sched_verbose ATTRIBUTE_UNUSED,
+		     rtx *ready ATTRIBUTE_UNUSED,
+		     int *pn_ready ATTRIBUTE_UNUSED,
+		     int clock_var ATTRIBUTE_UNUSED)
 {
     return s390_issue_rate();
 }
 
 
-/* Split all branches that exceed the maximum distance.  
-   Returns true if this created a new literal pool entry.  
+/* Split all branches that exceed the maximum distance.
+   Returns true if this created a new literal pool entry.
 
    Code generated by this routine is allowed to use
    TEMP_REG as temporary scratch register.  If this is
    done, TEMP_USED is set to true.  */
 
-static int 
-s390_split_branches (temp_reg, temp_used)
-     rtx temp_reg;
-     bool *temp_used;
+static int
+s390_split_branches (rtx temp_reg, bool *temp_used)
 {
   int new_literal = 0;
   rtx insn, pat, tmp, target;
@@ -3928,15 +3790,15 @@ s390_split_branches (temp_reg, temp_used)
       if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
 	continue;
 
-      if (GET_CODE (SET_SRC (pat)) == LABEL_REF) 
+      if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
 	{
 	  label = &SET_SRC (pat);
-	} 
-      else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) 
+	}
+      else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
 	{
-	  if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) 
+	  if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
 	    label = &XEXP (SET_SRC (pat), 1);
-          else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) 
+          else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
             label = &XEXP (SET_SRC (pat), 2);
 	  else
 	    continue;
@@ -3944,12 +3806,12 @@ s390_split_branches (temp_reg, temp_used)
       else
 	continue;
 
-      if (get_attr_length (insn) <= (TARGET_64BIT ? 6 : 4))
+      if (get_attr_length (insn) <= (TARGET_CPU_ZARCH ? 6 : 4))
 	continue;
 
       *temp_used = 1;
 
-      if (TARGET_64BIT)
+      if (TARGET_CPU_ZARCH)
 	{
 	  tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, *label), insn);
 	  INSN_ADDRESSES_NEW (tmp, -1);
@@ -3968,14 +3830,16 @@ s390_split_branches (temp_reg, temp_used)
       else
 	{
 	  new_literal = 1;
-	  tmp = gen_rtx_UNSPEC (SImode, gen_rtvec (1, *label), 104);
-	  tmp = gen_rtx_CONST (SImode, tmp);
-	  tmp = force_const_mem (SImode, tmp);
-	  tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
+	  target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
+				   UNSPEC_LTREL_OFFSET);
+	  target = gen_rtx_CONST (Pmode, target);
+	  target = force_const_mem (Pmode, target);
+	  tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
 	  INSN_ADDRESSES_NEW (tmp, -1);
 
-	  target = gen_rtx_REG (Pmode, BASE_REGISTER);
-	  target = gen_rtx_PLUS (Pmode, target, temp_reg);
+          target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (target, 0)),
+				   UNSPEC_LTREL_BASE);
+	  target = gen_rtx_PLUS (Pmode, temp_reg, target);
 	}
 
       if (!validate_change (insn, label, target, 0))
@@ -3986,22 +3850,29 @@ s390_split_branches (temp_reg, temp_used)
 }
 
 
-/* Find a literal pool symbol referenced in RTX X, and store 
-   it at REF.  Will abort if X contains references to more than 
+/* Find a literal pool symbol referenced in RTX X, and store
+   it at REF.  Will abort if X contains references to more than
    one such pool symbol; multiple references to the same symbol
-   are allowed, however. 
+   are allowed, however.
 
-   The rtx pointed to by REF must be initialized to NULL_RTX 
+   The rtx pointed to by REF must be initialized to NULL_RTX
    by the caller before calling this routine.  */
 
 static void
-find_constant_pool_ref (x, ref)
-     rtx x;
-     rtx *ref;
+find_constant_pool_ref (rtx x, rtx *ref)
 {
   int i, j;
   const char *fmt;
 
+  /* Ignore LTREL_BASE references.  */
+  if (GET_CODE (x) == UNSPEC
+      && XINT (x, 1) == UNSPEC_LTREL_BASE)
+    return;
+  /* Likewise POOL_ENTRY insns.  */
+  if (GET_CODE (x) == UNSPEC_VOLATILE
+      && XINT (x, 1) == UNSPECV_POOL_ENTRY)
+    return;
+
   if (GET_CODE (x) == SYMBOL_REF
       && CONSTANT_POOL_ADDRESS_P (x))
     {
@@ -4030,10 +3901,7 @@ find_constant_pool_ref (x, ref)
    in X by the address ADDR.  Fix up MEMs as required.  */
 
 static void
-replace_constant_pool_ref (x, ref, addr)
-     rtx *x;
-     rtx ref;
-     rtx addr;
+replace_constant_pool_ref (rtx *x, rtx ref, rtx addr)
 {
   int i, j;
   const char *fmt;
@@ -4100,135 +3968,55 @@ replace_constant_pool_ref (x, ref, addr)
     }
 }
 
-/* Check whether ADDR is an address that uses the base register, 
-   without actually constituting a literal pool access.  (This happens
-   in 31-bit PIC mode, where the base register is used as anchor for
-   relative addressing of local symbols.) 
-
-   Returns 1 if the base register occupies the base slot,
-   returns 2 if the base register occupies the index slot,
-   returns 0 if the address is not of this form.  */
-
-static int
-find_base_register_in_addr (addr)
-     struct s390_address *addr;
-{
-  /* If DISP is complex, we might have a literal pool reference.  */
-  if (addr->disp && GET_CODE (addr->disp) != CONST_INT)
-    return 0;
-
-  if (addr->base && REG_P (addr->base) && REGNO (addr->base) == BASE_REGISTER)
-    return 1;
-
-  if (addr->indx && REG_P (addr->indx) && REGNO (addr->indx) == BASE_REGISTER)
-    return 2;
-
-  return 0;
-}
-
-/* Return true if X contains an address that uses the base register, 
-   without actually constituting a literal pool access.  */
+/* Check whether X contains an UNSPEC_LTREL_BASE.
+   Return its constant pool symbol if found, NULL_RTX otherwise.  */
 
-static bool
-find_base_register_ref (x)
-     rtx x;
+static rtx
+find_ltrel_base (rtx x)
 {
-  bool retv = FALSE;
-  struct s390_address addr;
   int i, j;
   const char *fmt;
 
-  /* Addresses can only occur inside a MEM ...  */
-  if (GET_CODE (x) == MEM)
-    {
-      if (s390_decompose_address (XEXP (x, 0), &addr)
-	  && find_base_register_in_addr (&addr))
-	return TRUE;
-    }
-
-  /* ... or a load-address type pattern.  */
-  if (GET_CODE (x) == SET && GET_CODE (SET_DEST (x)) == REG)
-    {
-      if (s390_decompose_address (SET_SRC (x), &addr)
-	  && find_base_register_in_addr (&addr))
-	return TRUE;
-    }
+  if (GET_CODE (x) == UNSPEC
+      && XINT (x, 1) == UNSPEC_LTREL_BASE)
+    return XVECEXP (x, 0, 0);
 
   fmt = GET_RTX_FORMAT (GET_CODE (x));
   for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
     {
       if (fmt[i] == 'e')
         {
-          retv |= find_base_register_ref (XEXP (x, i));
+          rtx fnd = find_ltrel_base (XEXP (x, i));
+	  if (fnd)
+	    return fnd;
         }
       else if (fmt[i] == 'E')
         {
           for (j = 0; j < XVECLEN (x, i); j++)
-            retv |= find_base_register_ref (XVECEXP (x, i, j));
+	    {
+              rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
+	      if (fnd)
+		return fnd;
+	    }
         }
     }
 
-  return retv;
+  return NULL_RTX;
 }
 
-/* If X contains an address that uses the base register,
-   without actually constituting a literal pool access,
-   replace the base register with REPL in all such cases.
-
-   Handles both MEMs and load address patterns.  */
+/* Replace any occurrence of UNSPEC_LTREL_BASE in X with BASE.  */
 
 static void
-replace_base_register_ref (x, repl)
-     rtx *x;
-     rtx repl;
+replace_ltrel_base (rtx *x, rtx base)
 {
-  struct s390_address addr;
-  rtx new_addr;
-  int i, j, pos;
+  int i, j;
   const char *fmt;
 
-  /* Addresses can only occur inside a MEM ...  */
-  if (GET_CODE (*x) == MEM)
+  if (GET_CODE (*x) == UNSPEC
+      && XINT (*x, 1) == UNSPEC_LTREL_BASE)
     {
-      if (s390_decompose_address (XEXP (*x, 0), &addr)
-	  && (pos = find_base_register_in_addr (&addr)))
-	{
-	  if (pos == 1)
-	    addr.base = repl;
-	  else
-	    addr.indx = repl;
-
-	  new_addr = addr.base;
-	  if (addr.indx)
-	    new_addr = gen_rtx_PLUS (Pmode, new_addr, addr.indx);
-	  if (addr.disp)
-	    new_addr = gen_rtx_PLUS (Pmode, new_addr, addr.disp);
-
-	  *x = replace_equiv_address (*x, new_addr);
-	  return;
-	}
-    }
-
-  /* ... or a load-address type pattern.  */
-  if (GET_CODE (*x) == SET && GET_CODE (SET_DEST (*x)) == REG)
-    {
-      if (s390_decompose_address (SET_SRC (*x), &addr)
-	  && (pos = find_base_register_in_addr (&addr)))
-	{
-	  if (pos == 1)
-	    addr.base = repl;
-	  else
-	    addr.indx = repl;
-
-	  new_addr = addr.base;
-	  if (addr.indx)
-	    new_addr = gen_rtx_PLUS (Pmode, new_addr, addr.indx);
-	  if (addr.disp)
-	    new_addr = gen_rtx_PLUS (Pmode, new_addr, addr.disp);
-
-	  SET_SRC (*x) = new_addr;
-	  return;
-	}
+      *x = base;
+      return;
     }
 
   fmt = GET_RTX_FORMAT (GET_CODE (*x));
@@ -4236,37 +4024,30 @@ replace_base_register_ref (x, repl)
     {
       if (fmt[i] == 'e')
         {
-          replace_base_register_ref (&XEXP (*x, i), repl);
+          replace_ltrel_base (&XEXP (*x, i), base);
         }
       else if (fmt[i] == 'E')
         {
           for (j = 0; j < XVECLEN (*x, i); j++)
-            replace_base_register_ref (&XVECEXP (*x, i, j), repl);
+            replace_ltrel_base (&XVECEXP (*x, i, j), base);
         }
     }
 }
 
 
-/* We keep a list of constants we which we have to add to internal
+/* We keep a list of constants which we have to add to internal
    constant tables in the middle of large functions.  */
 
-#define NR_C_MODES 6
-enum machine_mode constant_modes[NR_C_MODES] = 
+#define NR_C_MODES 7
+enum machine_mode constant_modes[NR_C_MODES] =
 {
+  TImode,
   DFmode, DImode,
   SFmode, SImode,
   HImode,
   QImode
 };
 
-rtx (*gen_consttable[NR_C_MODES])(rtx) =
-{
-  gen_consttable_df, gen_consttable_di,
-  gen_consttable_sf, gen_consttable_si,
-  gen_consttable_hi,
-  gen_consttable_qi
-};
-
 struct constant
 {
   struct constant *next;
@@ -4284,45 +4065,36 @@ struct constant_pool
   struct constant *constants[NR_C_MODES];
   rtx label;
   int size;
-  bool anchor;
 };
 
-static struct constant_pool * s390_chunkify_start PARAMS ((rtx, bool *));
-static void s390_chunkify_finish PARAMS ((struct constant_pool *, rtx));
-static void s390_chunkify_cancel PARAMS ((struct constant_pool *));
+static struct constant_pool * s390_mainpool_start (void);
+static void s390_mainpool_finish (struct constant_pool *, rtx base_reg);
+static void s390_mainpool_cancel (struct constant_pool *);
+
+static struct constant_pool * s390_chunkify_start (rtx base_reg);
+static void s390_chunkify_finish (struct constant_pool *, rtx base_reg);
+static void s390_chunkify_cancel (struct constant_pool *);
 
-static struct constant_pool *s390_start_pool PARAMS ((struct constant_pool **, rtx));
-static void s390_end_pool PARAMS ((struct constant_pool *, rtx));
-static void s390_add_pool_insn PARAMS ((struct constant_pool *, rtx));
-static struct constant_pool *s390_find_pool PARAMS ((struct constant_pool *, rtx));
-static void s390_add_constant PARAMS ((struct constant_pool *, rtx, enum machine_mode));
-static rtx s390_find_constant PARAMS ((struct constant_pool *, rtx, enum machine_mode));
-static void s390_add_anchor PARAMS ((struct constant_pool *));
-static rtx s390_dump_pool PARAMS ((struct constant_pool *));
-static void s390_free_pool PARAMS ((struct constant_pool *));
+static struct constant_pool *s390_start_pool (struct constant_pool **, rtx);
+static void s390_end_pool (struct constant_pool *, rtx);
+static void s390_add_pool_insn (struct constant_pool *, rtx);
+static struct constant_pool *s390_find_pool (struct constant_pool *, rtx);
+static void s390_add_constant (struct constant_pool *, rtx, enum machine_mode);
+static rtx s390_find_constant (struct constant_pool *, rtx, enum machine_mode);
+static rtx s390_dump_pool (struct constant_pool *, bool);
+static struct constant_pool *s390_alloc_pool (void);
+static void s390_free_pool (struct constant_pool *);
 
 /* Create new constant pool covering instructions starting at INSN
    and chain it to the end of POOL_LIST.  */
 
 static struct constant_pool *
-s390_start_pool (pool_list, insn)
-     struct constant_pool **pool_list;
-     rtx insn;
+s390_start_pool (struct constant_pool **pool_list, rtx insn)
 {
   struct constant_pool *pool, **prev;
-  int i;
-
-  pool = (struct constant_pool *) xmalloc (sizeof *pool);
-  pool->next = NULL;
-  for (i = 0; i < NR_C_MODES; i++)
-    pool->constants[i] = NULL;
 
-  pool->label = gen_label_rtx ();
+  pool = s390_alloc_pool ();
   pool->first_insn = insn;
-  pool->pool_insn = NULL_RTX;
-  pool->insns = BITMAP_XMALLOC ();
-  pool->size = 0;
-  pool->anchor = FALSE;
 
   for (prev = pool_list; *prev; prev = &(*prev)->next)
     ;
@@ -4335,9 +4107,7 @@ s390_start_pool (pool_list, insn)
    placeholder insn representing the pool.  */
 
 static void
-s390_end_pool (pool, insn)
-     struct constant_pool *pool;
-     rtx insn;
+s390_end_pool (struct constant_pool *pool, rtx insn)
 {
   rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
 
@@ -4351,9 +4121,7 @@ s390_end_pool (pool, insn)
 /* Add INSN to the list of insns covered by POOL.  */
 
 static void
-s390_add_pool_insn (pool, insn)
-     struct constant_pool *pool;
-     rtx insn;
+s390_add_pool_insn (struct constant_pool *pool, rtx insn)
 {
   bitmap_set_bit (pool->insns, INSN_UID (insn));
 }
@@ -4361,9 +4129,7 @@ s390_add_pool_insn (pool, insn)
 /* Return pool out of POOL_LIST that covers INSN.  */
 
 static struct constant_pool *
-s390_find_pool (pool_list, insn)
-     struct constant_pool *pool_list;
-     rtx insn;
+s390_find_pool (struct constant_pool *pool_list, rtx insn)
 {
   struct constant_pool *pool;
 
@@ -4377,10 +4143,7 @@ s390_find_pool (pool_list, insn)
 /* Add constant VAL of mode MODE to the constant pool POOL.  */
 
 static void
-s390_add_constant (pool, val, mode)
-     struct constant_pool *pool;
-     rtx val;
-     enum machine_mode mode;
+s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
 {
   struct constant *c;
   int i;
@@ -4409,77 +4172,55 @@ s390_add_constant (pool, val, mode)
 /* Find constant VAL of mode MODE in the constant pool POOL.
    Return an RTX describing the distance from the start of
    the pool to the location of the new constant.  */
- 
+
 static rtx
-s390_find_constant (pool, val, mode)
-     struct constant_pool *pool;
-     rtx val;
-     enum machine_mode mode;
+s390_find_constant (struct constant_pool *pool, rtx val,
+		    enum machine_mode mode)
 {
   struct constant *c;
   rtx offset;
   int i;
- 
+
   for (i = 0; i < NR_C_MODES; i++)
     if (constant_modes[i] == mode)
       break;
   if (i == NR_C_MODES)
     abort ();
- 
+
   for (c = pool->constants[i]; c != NULL; c = c->next)
     if (rtx_equal_p (val, c->value))
       break;
- 
+
   if (c == NULL)
     abort ();
- 
+
   offset = gen_rtx_MINUS (Pmode, gen_rtx_LABEL_REF (Pmode, c->label),
                                  gen_rtx_LABEL_REF (Pmode, pool->label));
   offset = gen_rtx_CONST (Pmode, offset);
   return offset;
 }
 
-/* Set 'anchor' flag in POOL.  */
-
-static void
-s390_add_anchor (pool)
-     struct constant_pool *pool;
-{
-  if (!pool->anchor)
-    {
-      pool->anchor = TRUE;
-      pool->size += 4;
-    }
-}
-
-/* Dump out the constants in POOL.  */
+/* Dump out the constants in POOL.  If REMOTE_LABEL is true,
+   do not emit the pool base label.  */
 
 static rtx
-s390_dump_pool (pool)
-     struct constant_pool *pool;
+s390_dump_pool (struct constant_pool *pool, bool remote_label)
 {
   struct constant *c;
   rtx insn;
   int i;
 
-  /* Pool start insn switches to proper section 
+  /* Pool start insn switches to proper section
      and guarantees necessary alignment.  */
-  if (TARGET_64BIT)
+  if (TARGET_CPU_ZARCH)
     insn = emit_insn_after (gen_pool_start_64 (), pool->pool_insn);
   else
     insn = emit_insn_after (gen_pool_start_31 (), pool->pool_insn);
   INSN_ADDRESSES_NEW (insn, -1);
 
-  insn = emit_label_after (pool->label, insn);
-  INSN_ADDRESSES_NEW (insn, -1);
-
-  /* Emit anchor if we need one.  */
-  if (pool->anchor)
+  if (!remote_label)
     {
-      rtx anchor = gen_rtx_LABEL_REF (VOIDmode, pool->label);
-      anchor = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, anchor), 105);
-      anchor = gen_rtx_CONST (VOIDmode, anchor);
-      insn = emit_insn_after (gen_consttable_si (anchor), insn);
+      insn = emit_label_after (pool->label, insn);
       INSN_ADDRESSES_NEW (insn, -1);
     }
 
@@ -4488,27 +4229,31 @@ s390_dump_pool (pool)
   for (i = 0; i < NR_C_MODES; i++)
     for (c = pool->constants[i]; c; c = c->next)
       {
-	/* Convert 104 unspecs to pool-relative references.  */
+	/* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references.  */
 	rtx value = c->value;
 	if (GET_CODE (value) == CONST
 	    && GET_CODE (XEXP (value, 0)) == UNSPEC
-	    && XINT (XEXP (value, 0), 1) == 104
+	    && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
 	    && XVECLEN (XEXP (value, 0), 0) == 1)
 	  {
 	    value = gen_rtx_MINUS (Pmode, XVECEXP (XEXP (value, 0), 0, 0),
-	    			   gen_rtx_LABEL_REF (VOIDmode, pool->label));
+				   gen_rtx_LABEL_REF (VOIDmode, pool->label));
 	    value = gen_rtx_CONST (VOIDmode, value);
 	  }
 
 	insn = emit_label_after (c->label, insn);
 	INSN_ADDRESSES_NEW (insn, -1);
-	insn = emit_insn_after (gen_consttable[i] (value), insn);
+
+	value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i], 
+					 gen_rtvec (1, value),
+					 UNSPECV_POOL_ENTRY);
+	insn = emit_insn_after (value, insn);
 	INSN_ADDRESSES_NEW (insn, -1);
       }
 
-  /* Pool end insn switches back to previous section 
+  /* Pool end insn switches back to previous section
      and guarantees necessary alignment.  */
-  if (TARGET_64BIT)
+  if (TARGET_CPU_ZARCH)
     insn = emit_insn_after (gen_pool_end_64 (), insn);
   else
     insn = emit_insn_after (gen_pool_end_31 (), insn);
@@ -4523,11 +4268,32 @@ s390_dump_pool (pool)
   return insn;
 }
 
+/* Allocate new constant_pool structure.  */
+
+static struct constant_pool *
+s390_alloc_pool (void)
+{
+  struct constant_pool *pool;
+  int i;
+
+  pool = (struct constant_pool *) xmalloc (sizeof *pool);
+  pool->next = NULL;
+  for (i = 0; i < NR_C_MODES; i++)
+    pool->constants[i] = NULL;
+
+  pool->label = gen_label_rtx ();
+  pool->first_insn = NULL_RTX;
+  pool->pool_insn = NULL_RTX;
+  pool->insns = BITMAP_XMALLOC ();
+  pool->size = 0;
+
+  return pool;
+}
+
 /* Free all memory used by POOL.  */
 
 static void
-s390_free_pool (pool)
-     struct constant_pool *pool;
+s390_free_pool (struct constant_pool *pool)
 {
   int i;
 
@@ -4544,90 +4310,259 @@ s390_free_pool (pool)
 
   BITMAP_XFREE (pool->insns);
   free (pool);
-} 
+}
 
 
-/* Chunkify the literal pool if required.
+/* Collect main literal pool.  Return NULL on overflow.  */
 
-   Code generated by this routine is allowed to use
-   TEMP_REG as temporary scratch register.  If this is
-   done, TEMP_USED is set to true.  */
+static struct constant_pool *
+s390_mainpool_start (void)
+{
+  struct constant_pool *pool;
+  rtx insn;
+
+  pool = s390_alloc_pool ();
+
+  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+    {
+      if (GET_CODE (insn) == INSN
+	  && GET_CODE (PATTERN (insn)) == UNSPEC_VOLATILE
+	  && XINT (PATTERN (insn), 1) == UNSPECV_MAIN_POOL)
+	{
+	  if (pool->pool_insn)
+	    abort ();
+	  pool->pool_insn = insn;
+	}
+
+      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
+	{
+	  rtx pool_ref = NULL_RTX;
+	  find_constant_pool_ref (PATTERN (insn), &pool_ref);
+	  if (pool_ref)
+	    {
+	      rtx constant = get_pool_constant (pool_ref);
+	      enum machine_mode mode = get_pool_mode (pool_ref);
+	      s390_add_constant (pool, constant, mode);
+	    }
+	}
+    }
+
+  if (!pool->pool_insn)
+    abort ();
+
+  if (pool->size >= 4096)
+    {
+      s390_free_pool (pool);
+      pool = NULL;
+    }
+
+  return pool;
+}
+
+/* POOL holds the main literal pool as collected by s390_mainpool_start.
+   Modify the current function to output the pool constants as well as
+   the pool register setup instruction.  BASE_REG is the register to
+   be used as pool base register.  */
+
+static void
+s390_mainpool_finish (struct constant_pool *pool, rtx base_reg)
+{
+  rtx insn;
+
+  /* If the pool is empty, we're done.  */
+  if (pool->size == 0)
+    {
+      remove_insn (pool->pool_insn);
+      s390_free_pool (pool);
+      return;
+    }
+
+  /* We need correct insn addresses.  */
+  shorten_branches (get_insns ());
+
+  /* On zSeries, we use a LARL to load the pool register.  The pool is
+     located in the .rodata section, so we emit it after the function.  */
+  if (TARGET_CPU_ZARCH)
+    {
+      insn = gen_main_base_64 (base_reg, pool->label);
+      insn = emit_insn_after (insn, pool->pool_insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+      remove_insn (pool->pool_insn);
+     
+      insn = get_last_insn (); 
+      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
+      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
+
+      s390_dump_pool (pool, 0);
+    }
+
+  /* On S/390, if the total size of the function's code plus literal pool
+     does not exceed 4096 bytes, we use BASR to set up a function base
+     pointer, and emit the literal pool at the end of the function.  */
+  else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
+	   + pool->size + 8 /* alignment slop */ < 4096)
+    {
+      insn = gen_main_base_31_small (base_reg, pool->label);
+      insn = emit_insn_after (insn, pool->pool_insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+      remove_insn (pool->pool_insn);
+
+      insn = emit_label_after (pool->label, insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+
+      insn = get_last_insn ();
+      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
+      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
+
+      s390_dump_pool (pool, 1);
+    }
+
+  /* Otherwise, we emit an inline literal pool and use BASR to branch
+     over it, setting up the pool register at the same time.  */
+  else
+    {
+      rtx pool_end = gen_label_rtx ();
+
+      insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
+      insn = emit_insn_after (insn, pool->pool_insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+      remove_insn (pool->pool_insn);
+
+      insn = emit_label_after (pool->label, insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+
+      pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
+      INSN_ADDRESSES_NEW (pool->pool_insn, -1);
+
+      insn = emit_label_after (pool_end, pool->pool_insn);
+      INSN_ADDRESSES_NEW (insn, -1);
+
+      s390_dump_pool (pool, 1);
+    }
+
+
+  /* Replace all literal pool references.  */
+
+  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
+    {
+      if (INSN_P (insn))
+	replace_ltrel_base (&PATTERN (insn), base_reg);
+
+      if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
+        {
+          rtx addr, pool_ref = NULL_RTX;
+          find_constant_pool_ref (PATTERN (insn), &pool_ref);
+          if (pool_ref)
+            {
+              addr = s390_find_constant (pool, get_pool_constant (pool_ref),
+                                               get_pool_mode (pool_ref));
+              addr = gen_rtx_PLUS (Pmode, base_reg, addr);
+              replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
+              INSN_CODE (insn) = -1;
+            }
+        }
+    }
+
+
+  /* Free the pool.  */
+  s390_free_pool (pool);
+}
+
+/* POOL holds the main literal pool as collected by s390_mainpool_start.
+   We have decided we cannot use this pool, so revert all changes
+   to the current function that were done by s390_mainpool_start.  */
+static void
+s390_mainpool_cancel (struct constant_pool *pool)
+{
+  /* We didn't actually change the instruction stream, so simply
+     free the pool memory.  */
+  s390_free_pool (pool);
+}
+
+
+/* Chunkify the literal pool.  BASE_REG is to be used as pool
+   register.  */
 
 #define S390_POOL_CHUNK_MIN	0xc00
 #define S390_POOL_CHUNK_MAX	0xe00
 
-static struct constant_pool * 
-s390_chunkify_start (temp_reg, temp_used)
-     rtx temp_reg;
-     bool *temp_used;
+static struct constant_pool *
+s390_chunkify_start (rtx base_reg)
 {
-  rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
-
   struct constant_pool *curr_pool = NULL, *pool_list = NULL;
   int extra_size = 0;
   bitmap far_labels;
+  rtx pending_ltrel = NULL_RTX;
   rtx insn;
 
-  rtx (*gen_reload_base) PARAMS ((rtx, rtx)) =
-    TARGET_64BIT? gen_reload_base_64 : gen_reload_base_31;
-
+  rtx (*gen_reload_base) (rtx, rtx) =
+    TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
 
-  /* Do we need to chunkify the literal pool?  */
-
-  if (get_pool_size () < S390_POOL_CHUNK_MAX)
-    return NULL;
 
   /* We need correct insn addresses.  */
 
   shorten_branches (get_insns ());
 
-  /* Scan all insns and move literals to pool chunks.
-     Also, emit anchor reload insns before every insn that uses 
-     the literal pool base register as anchor pointer.  */
+  /* Scan all insns and move literals to pool chunks.  */
 
   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
     {
+      /* Check for pending LTREL_BASE.  */
+      if (INSN_P (insn))
+	{
+	  rtx ltrel_base = find_ltrel_base (PATTERN (insn));
+	  if (ltrel_base)
+	    {
+	      if (ltrel_base == pending_ltrel)
+		pending_ltrel = NULL_RTX;
+	      else
+		abort ();
+	    }
+	}
+
       if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN)
 	{
 	  rtx pool_ref = NULL_RTX;
 	  find_constant_pool_ref (PATTERN (insn), &pool_ref);
 	  if (pool_ref)
 	    {
+	      rtx constant = get_pool_constant (pool_ref);
+	      enum machine_mode mode = get_pool_mode (pool_ref);
+
 	      if (!curr_pool)
 		curr_pool = s390_start_pool (&pool_list, insn);
 
-	      s390_add_constant (curr_pool, get_pool_constant (pool_ref), 
-					    get_pool_mode (pool_ref));
+	      s390_add_constant (curr_pool, constant, mode);
 	      s390_add_pool_insn (curr_pool, insn);
-	    }
-
-	  else if (!TARGET_64BIT && flag_pic
-                   && find_base_register_ref (PATTERN (insn)))
-	    {
-	      rtx new = gen_reload_anchor (temp_reg, base_reg);
-	      new = emit_insn_before (new, insn);
-	      INSN_ADDRESSES_NEW (new, INSN_ADDRESSES (INSN_UID (insn)));
-	      extra_size += 8;
-	      *temp_used = 1;
-	      
-	      if (!curr_pool)
-		curr_pool = s390_start_pool (&pool_list, new);
 
-	      s390_add_anchor (curr_pool);
-	      s390_add_pool_insn (curr_pool, insn);
+	      /* Don't split the pool chunk between a LTREL_OFFSET load
+		 and the corresponding LTREL_BASE.  */
+	      if (GET_CODE (constant) == CONST
+		  && GET_CODE (XEXP (constant, 0)) == UNSPEC
+		  && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
+		{
+		  if (pending_ltrel)
+		    abort ();
+		  pending_ltrel = pool_ref;
+		}
 	    }
 	}
 
       if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL)
-	if (curr_pool)
-	  s390_add_pool_insn (curr_pool, insn);
+	{
+	  if (curr_pool)
+	    s390_add_pool_insn (curr_pool, insn);
+	  /* An LTREL_BASE must follow within the same basic block.  */
+	  if (pending_ltrel)
+	    abort ();
+	}
 
-      if (!curr_pool 
+      if (!curr_pool
 	  || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
           || INSN_ADDRESSES (INSN_UID (insn)) == -1)
 	continue;
 
-      if (TARGET_64BIT)
+      if (TARGET_CPU_ZARCH)
 	{
 	  if (curr_pool->size < S390_POOL_CHUNK_MAX)
 	    continue;
@@ -4638,7 +4573,7 @@ s390_chunkify_start (temp_reg, temp_used)
       else
 	{
           int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
-		 	   - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
+			   - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
 			 + extra_size;
 
 	  /* We will later have to insert base register reload insns.
@@ -4672,13 +4607,12 @@ s390_chunkify_start (temp_reg, temp_used)
 	      if (get_attr_length (insn) == 0)
 		continue;
 
-	      /* Don't separate insns created by s390_split_branches.  */
-	      if (GET_CODE (insn) == INSN 
-		  && GET_CODE (PATTERN (insn)) == SET
-		  && rtx_equal_p (SET_DEST (PATTERN (insn)), temp_reg))
+	      /* Don't separate LTREL_BASE from the corresponding
+		 LTREL_OFFSET load.  */
+	      if (pending_ltrel)
 		continue;
 
- 	      label = gen_label_rtx ();
+	      label = gen_label_rtx ();
 	      jump = emit_jump_insn_after (gen_jump (label), insn);
 	      barrier = emit_barrier_after (jump);
 	      insn = emit_label_after (label, barrier);
@@ -4698,9 +4632,11 @@ s390_chunkify_start (temp_reg, temp_used)
 
   if (curr_pool)
     s390_end_pool (curr_pool, NULL_RTX);
+  if (pending_ltrel)
+    abort ();
 
 
-  /* Find all labels that are branched into 
+  /* Find all labels that are branched into
      from an insn belonging to a different chunk.  */
 
   far_labels = BITMAP_XMALLOC ();
@@ -4714,11 +4650,11 @@ s390_chunkify_start (temp_reg, temp_used)
 	 Don't do that, however, if it is the label before
 	 a jump table.  */
 
-      if (GET_CODE (insn) == CODE_LABEL 
+      if (GET_CODE (insn) == CODE_LABEL
 	  && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
 	{
 	  rtx vec_insn = next_real_insn (insn);
-	  rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? 
+	  rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
 			PATTERN (vec_insn) : NULL_RTX;
 	  if (!vec_pat
 	      || !(GET_CODE (vec_pat) == ADDR_VEC
@@ -4728,22 +4664,22 @@ s390_chunkify_start (temp_reg, temp_used)
 
       /* If we have a direct jump (conditional or unconditional)
 	 or a casesi jump, check all potential targets.  */
-      else if (GET_CODE (insn) == JUMP_INSN) 
+      else if (GET_CODE (insn) == JUMP_INSN)
 	{
           rtx pat = PATTERN (insn);
 	  if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2)
 	    pat = XVECEXP (pat, 0, 0);
 
-          if (GET_CODE (pat) == SET) 
+          if (GET_CODE (pat) == SET)
             {
 	      rtx label = JUMP_LABEL (insn);
 	      if (label)
 		{
-	          if (s390_find_pool (pool_list, label) 
+	          if (s390_find_pool (pool_list, label)
 		      != s390_find_pool (pool_list, insn))
 		    bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
 		}
-            } 
+            }
 	  else if (GET_CODE (pat) == PARALLEL
 		   && XVECLEN (pat, 0) == 2
 		   && GET_CODE (XVECEXP (pat, 0, 0)) == SET
@@ -4753,7 +4689,7 @@ s390_chunkify_start (temp_reg, temp_used)
 	      /* Find the jump table used by this casesi jump.  */
 	      rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0);
 	      rtx vec_insn = next_real_insn (vec_label);
-	      rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? 
+	      rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ?
 			    PATTERN (vec_insn) : NULL_RTX;
 	      if (vec_pat
 		  && (GET_CODE (vec_pat) == ADDR_VEC
@@ -4765,7 +4701,7 @@ s390_chunkify_start (temp_reg, temp_used)
 		    {
 		      rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
 
-		      if (s390_find_pool (pool_list, label) 
+		      if (s390_find_pool (pool_list, label)
 			  != s390_find_pool (pool_list, insn))
 			bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
 		    }
@@ -4786,7 +4722,7 @@ s390_chunkify_start (temp_reg, temp_used)
   /* Insert base register reload insns at every far label.  */
 
   for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-    if (GET_CODE (insn) == CODE_LABEL 
+    if (GET_CODE (insn) == CODE_LABEL
         && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
       {
 	struct constant_pool *pool = s390_find_pool (pool_list, insn);
@@ -4810,26 +4746,24 @@ s390_chunkify_start (temp_reg, temp_used)
 }
 
 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
-   After we have decided to use this list, finish implementing 
-   all changes to the current function as required.
+   After we have decided to use this list, finish implementing
+   all changes to the current function as required.  BASE_REG is
+   to be used as pool base register.  */
 
-   Code generated by this routine is allowed to use
-   TEMP_REG as temporary scratch register.  */
- 
 static void
-s390_chunkify_finish (pool_list, temp_reg)
-     struct constant_pool *pool_list;
-     rtx temp_reg;
+s390_chunkify_finish (struct constant_pool *pool_list, rtx base_reg)
 {
-  rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
   struct constant_pool *curr_pool = NULL;
   rtx insn;
- 
- 
+
+
   /* Replace all literal pool references.  */
 
-  for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 
+  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
     {
+      if (INSN_P (insn))
+	replace_ltrel_base (&PATTERN (insn), base_reg);
+
       curr_pool = s390_find_pool (pool_list, insn);
       if (!curr_pool)
 	continue;
@@ -4846,20 +4780,14 @@ s390_chunkify_finish (pool_list, temp_reg)
               replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
               INSN_CODE (insn) = -1;
             }
-
-	  else if (!TARGET_64BIT && flag_pic
-                   && find_base_register_ref (PATTERN (insn)))
-	    {
-	      replace_base_register_ref (&PATTERN (insn), temp_reg);
-	    }
         }
     }
 
   /* Dump out all literal pools.  */
- 
+
   for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
-    s390_dump_pool (curr_pool);
- 
+    s390_dump_pool (curr_pool, 0);
+
   /* Free pool list.  */
 
   while (pool_list)
@@ -4873,10 +4801,9 @@ s390_chunkify_finish (pool_list, temp_reg)
 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
    We have decided we cannot use this list, so revert all changes
    to the current function that were done by s390_chunkify_start.  */
- 
+
 static void
-s390_chunkify_cancel (pool_list)
-     struct constant_pool *pool_list;
+s390_chunkify_cancel (struct constant_pool *pool_list)
 {
   struct constant_pool *curr_pool = NULL;
   rtx insn;
@@ -4906,7 +4833,7 @@ s390_chunkify_cancel (pool_list)
       remove_insn (curr_pool->pool_insn);
     }
 
-  /* Remove all base/anchor register reload insns.  */
+  /* Remove all base register reload insns.  */
 
   for (insn = get_insns (); insn; )
     {
@@ -4915,8 +4842,7 @@ s390_chunkify_cancel (pool_list)
       if (GET_CODE (insn) == INSN
 	  && GET_CODE (PATTERN (insn)) == SET
 	  && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
-	  && (XINT (SET_SRC (PATTERN (insn)), 1) == 210
-	      || XINT (SET_SRC (PATTERN (insn)), 1) == 211))
+	  && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
 	remove_insn (insn);
 
       insn = next_insn;
@@ -4933,99 +4859,90 @@ s390_chunkify_cancel (pool_list)
 }
 
 
-/* Index of constant pool chunk that is currently being processed.
-   Set to -1 before function output has started.  */
-int s390_pool_count = -1;
-
-/* Number of elements of current constant pool.  */
-int s390_nr_constants;
-
-/* Output main constant pool to stdio stream FILE.  */ 
+/* Output to FILE the constant pool entry EXP in mode MODE
+   with alignment ALIGN.  */
 
 void
-s390_output_constant_pool (start_label, end_label)
-     rtx start_label;
-     rtx end_label;
+s390_output_pool_entry (FILE *file, rtx exp, enum machine_mode mode, 
+			unsigned int align)
 {
-  if (TARGET_64BIT) 
-    {
-      readonly_data_section ();
-      ASM_OUTPUT_ALIGN (asm_out_file, 3);
-      (*targetm.asm_out.internal_label) (asm_out_file, "L", 
-					 CODE_LABEL_NUMBER (start_label));
-    } 
-  else 
-    {
-      (*targetm.asm_out.internal_label) (asm_out_file, "L",
-					 CODE_LABEL_NUMBER (start_label));
-      ASM_OUTPUT_ALIGN (asm_out_file, 2);      
-    }
+  REAL_VALUE_TYPE r;
 
-  s390_pool_count = 0;
-  output_constant_pool (current_function_name, current_function_decl);
-  s390_pool_count = -1;
-  if (TARGET_64BIT)
-    function_section (current_function_decl);
-  else
+  switch (GET_MODE_CLASS (mode))
     {
-      ASM_OUTPUT_ALIGN (asm_out_file, 1);
-      (*targetm.asm_out.internal_label) (asm_out_file, "L", 
-					 CODE_LABEL_NUMBER (end_label));
+    case MODE_FLOAT:
+      if (GET_CODE (exp) != CONST_DOUBLE)
+	abort ();
+
+      REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
+      assemble_real (r, mode, align);
+      break;
+
+    case MODE_INT:
+      if (GET_CODE (exp) == CONST
+	  || GET_CODE (exp) == SYMBOL_REF
+	  || GET_CODE (exp) == LABEL_REF)
+	{
+	  fputs (integer_asm_op (GET_MODE_SIZE (mode), TRUE), file);
+	  s390_output_symbolic_const (file, exp);
+	  fputc ('\n', file);
+	}
+      else
+	{
+	  assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
+	}
+      break;
+
+    default:
+      abort ();
     }
 }
 
+
 /* Rework the prolog/epilog to avoid saving/restoring
-   registers unnecessarily.  If TEMP_REGNO is nonnegative,
-   it specifies the number of a caller-saved register used 
-   as temporary scratch register by code emitted during 
-   machine dependent reorg.  */
+   registers unnecessarily.  BASE_USED specifies whether
+   the literal pool base register needs to be saved, 
+   TEMP_USED specifies whether the return register needs
+   to be saved.  */
 
 static void
-s390_optimize_prolog (temp_regno)
-     int temp_regno;
+s390_optimize_prolog (bool base_used, bool temp_used)
 {
   int save_first, save_last, restore_first, restore_last;
   int i, j;
   rtx insn, new_insn, next_insn;
 
   /* Recompute regs_ever_live data for special registers.  */
-  regs_ever_live[BASE_REGISTER] = 0;
-  regs_ever_live[RETURN_REGNUM] = 0;
+  regs_ever_live[BASE_REGISTER] = base_used;
+  regs_ever_live[RETURN_REGNUM] = temp_used;
   regs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
 
-  /* If there is (possibly) any pool entry, we need to
-     load the base register.  
-     ??? FIXME: this should be more precise.  */
-  if (get_pool_size ())
-    regs_ever_live[BASE_REGISTER] = 1;
-
-  /* In non-leaf functions, the prolog/epilog code relies 
-     on RETURN_REGNUM being saved in any case.  */
-  if (!current_function_is_leaf)
+  /* In non-leaf functions, the prolog/epilog code relies
+     on RETURN_REGNUM being saved in any case.  We also need
+     to save the return register if __builtin_return_address (0)
+     was used in the current function.  */
+  if (!current_function_is_leaf 
+      || cfun->machine->save_return_addr_p)
     regs_ever_live[RETURN_REGNUM] = 1;
 
-  /* We need to save/restore the temporary register.  */
-  if (temp_regno >= 0)
-    regs_ever_live[temp_regno] = 1;
-
 
   /* Find first and last gpr to be saved.  */
-  
+
   for (i = 6; i < 16; i++)
     if (regs_ever_live[i])
       if (!global_regs[i]
-	  || i == STACK_POINTER_REGNUM 
+	  || i == STACK_POINTER_REGNUM
           || i == RETURN_REGNUM
-          || i == BASE_REGISTER 
+          || i == BASE_REGISTER
           || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
 	break;
 
   for (j = 15; j > i; j--)
     if (regs_ever_live[j])
       if (!global_regs[j]
-	  || j == STACK_POINTER_REGNUM 
+	  || j == STACK_POINTER_REGNUM
           || j == RETURN_REGNUM
-          || j == BASE_REGISTER 
+          || j == BASE_REGISTER
           || (flag_pic && j == (int)PIC_OFFSET_TABLE_REGNUM))
 	break;
 
@@ -5126,98 +5043,53 @@ s390_optimize_prolog (temp_regno)
     }
 }
 
-/* Check whether any insn in the function makes use of the original
-   value of RETURN_REG (e.g. for __builtin_return_address).
-   If so, insert an insn reloading that value.
-
-   Return true if any such insn was found.  */
-
-static bool
-s390_fixup_clobbered_return_reg (return_reg)
-    rtx return_reg;
-{
-  bool replacement_done = 0;
-  rtx insn;
-
-  /* If we never called __builtin_return_address, register 14
-     might have been used as temp during the prolog; we do
-     not want to touch those uses.  */
-  if (!has_hard_reg_initial_val (Pmode, REGNO (return_reg)))
-    return false;
-
-  for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-    {
-      rtx reg, off, new_insn;
-
-      if (GET_CODE (insn) != INSN)
-	continue;
-      if (!reg_referenced_p (return_reg, PATTERN (insn)))
-	continue;
-      if (GET_CODE (PATTERN (insn)) == PARALLEL
-	  && store_multiple_operation (PATTERN (insn), VOIDmode))
-	continue;
-
-      if (frame_pointer_needed)
-	reg = hard_frame_pointer_rtx;
-      else
-	reg = stack_pointer_rtx;
-
-      off = GEN_INT (cfun->machine->frame_size + REGNO (return_reg) * UNITS_PER_WORD);
-      if (!DISP_IN_RANGE (INTVAL (off)))
-	{
-	  off = force_const_mem (Pmode, off);
-	  new_insn = gen_rtx_SET (Pmode, return_reg, off);
-	  new_insn = emit_insn_before (new_insn, insn);
-	  INSN_ADDRESSES_NEW (new_insn, -1);
-	  off = return_reg;
-	}
-
-      new_insn = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, reg, off));
-      new_insn = gen_rtx_SET (Pmode, return_reg, new_insn);
-      new_insn = emit_insn_before (new_insn, insn);
-      INSN_ADDRESSES_NEW (new_insn, -1);
-
-      replacement_done = 1;
-    }
-
-  return replacement_done;
-}
-
 /* Perform machine-dependent processing.  */
 
 static void
-s390_reorg ()
+s390_reorg (void)
 {
-  bool fixed_up_clobbered_return_reg = 0;
   rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
-  bool temp_used = 0;
+  rtx base_reg = gen_rtx_REG (Pmode, BASE_REGISTER);
+  bool temp_used = false;
+  bool base_used = false;
+  bool pool_overflow = false;
 
   /* Make sure all splits have been performed; splits after
      machine_dependent_reorg might confuse insn length counts.  */
   split_all_insns_noflow ();
 
 
-  /* There are two problematic situations we need to correct:
- 
+  /* In small leaf functions, try to use an unused call-clobbered
+     register as base register to avoid save/restore overhead.  */
+  if (current_function_is_leaf && !regs_ever_live[5])
+    base_reg = gen_rtx_REG (Pmode, 5);
+
+
+  /* Install the main literal pool and the associated base
+     register load insns.
+
+     In addition, there are two problematic situations we need 
+     to correct:
+
      - the literal pool might be > 4096 bytes in size, so that
        some of its elements cannot be directly accessed
- 
+
      - a branch target might be > 64K away from the branch, so that
        it is not possible to use a PC-relative instruction.
- 
+
      To fix those, we split the single literal pool into multiple
      pool chunks, reloading the pool base register at various
      points throughout the function to ensure it always points to
      the pool chunk the following code expects, and / or replace
      PC-relative branches by absolute branches.
- 
+
      However, the two problems are interdependent: splitting the
      literal pool can move a branch further away from its target,
      causing the 64K limit to overflow, and on the other hand,
      replacing a PC-relative branch by an absolute branch means
      we need to put the branch target address into the literal
      pool, possibly causing it to overflow.
- 
+
      So, we loop trying to fix up both problems until we manage
      to satisfy both conditions at the same time.  Note that the
      loop is guaranteed to terminate as every pass of the loop
@@ -5225,49 +5097,51 @@ s390_reorg ()
      in the function.  (This is not completely true as there
      might be branch-over-pool insns introduced by chunkify_start.
      Those never need to be split however.)  */
- 
+
   for (;;)
     {
-      struct constant_pool *pool_list;
- 
-      /* Try to chunkify the literal pool.  */
-      pool_list = s390_chunkify_start (temp_reg, &temp_used);
+      struct constant_pool *pool = NULL;
+
+      /* Collect the literal pool.  */
+      if (!pool_overflow)
+	{
+	  pool = s390_mainpool_start ();
+	  if (!pool)
+	    pool_overflow = true;
+	}
+
+      /* If literal pool overflowed, start to chunkify it.  */
+      if (pool_overflow)
+        pool = s390_chunkify_start (base_reg);
 
       /* Split out-of-range branches.  If this has created new
 	 literal pool entries, cancel current chunk list and
 	 recompute it.  */
       if (s390_split_branches (temp_reg, &temp_used))
         {
-          if (pool_list)
-            s390_chunkify_cancel (pool_list);
- 
+          if (pool_overflow)
+            s390_chunkify_cancel (pool);
+	  else
+            s390_mainpool_cancel (pool);
+
           continue;
         }
 
-      /* Check whether we have clobbered a use of the return
-	 register (e.g. for __builtin_return_address).  If so,
-	 add insns reloading the register where necessary.  */
-      if (temp_used && !fixed_up_clobbered_return_reg
-	  && s390_fixup_clobbered_return_reg (temp_reg))
-	{
-	  fixed_up_clobbered_return_reg = 1;
+      /* If we made it up to here, both conditions are satisfied.
+	 Finish up literal pool related changes.  */
+      if ((pool_overflow || pool->size > 0)
+	   && REGNO (base_reg) == BASE_REGISTER)
+	base_used = true;
 
-	  /* The fixup insns might have caused a jump to overflow.  */
-	  if (pool_list)
-	    s390_chunkify_cancel (pool_list);
+      if (pool_overflow)
+	s390_chunkify_finish (pool, base_reg);
+      else
+	s390_mainpool_finish (pool, base_reg);
 
-	  continue;
-	}
- 
-      /* If we made it up to here, both conditions are satisfied.
-	 Finish up pool chunkification if required.  */
-      if (pool_list)
-	s390_chunkify_finish (pool_list, temp_reg);
- 
       break;
     }
- 
-  s390_optimize_prolog (temp_used? RETURN_REGNUM : -1);
+
+  s390_optimize_prolog (base_used, temp_used);
 }
 
 
@@ -5276,32 +5150,30 @@ s390_reorg ()
    frame pointer of that frame.  */
 
 rtx
-s390_return_addr_rtx (count, frame)
-     int count;
-     rtx frame;
+s390_return_addr_rtx (int count, rtx frame)
 {
   rtx addr;
 
-  /* For the current frame, we use the initial value of RETURN_REGNUM.
-     This works both in leaf and non-leaf functions.  */
+  /* For the current frame, we need to make sure the initial
+     value of RETURN_REGNUM is actually saved.  */
 
   if (count == 0)
-    return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
+    cfun->machine->save_return_addr_p = true;
 
-  /* For frames farther back, we read the stack slot where the
+  /* To retrieve the return address we read the stack slot where the
      corresponding RETURN_REGNUM value was saved.  */
 
   addr = plus_constant (frame, RETURN_REGNUM * UNITS_PER_WORD);
   addr = memory_address (Pmode, addr);
   return gen_rtx_MEM (Pmode, addr);
-} 
+}
 
 /* Find first call clobbered register unsused in a function.
    This could be used as base register in a leaf function
    or for holding the return address before epilogue.  */
 
 static int
-find_unused_clobbered_reg ()
+find_unused_clobbered_reg (void)
 {
   int i;
   for (i = 0; i < 6; i++)
@@ -5313,7 +5185,7 @@ find_unused_clobbered_reg ()
 /* Fill FRAME with info about frame of current function.  */
 
 static void
-s390_frame_info ()
+s390_frame_info (void)
 {
   char gprs_ever_live[16];
   int i, j;
@@ -5325,7 +5197,7 @@ s390_frame_info ()
   /* fprs 8 - 15 are caller saved for 64 Bit ABI.  */
   cfun->machine->save_fprs_p = 0;
   if (TARGET_64BIT)
-    for (i = 24; i < 32; i++) 
+    for (i = 24; i < 32; i++)
       if (regs_ever_live[i] && !global_regs[i])
 	{
           cfun->machine->save_fprs_p = 1;
@@ -5335,10 +5207,10 @@ s390_frame_info ()
   cfun->machine->frame_size = fsize + cfun->machine->save_fprs_p * 64;
 
   /* Does function need to setup frame and save area.  */
-  
+
   if (! current_function_is_leaf
       || cfun->machine->frame_size > 0
-      || current_function_calls_alloca 
+      || current_function_calls_alloca
       || current_function_stdarg)
     cfun->machine->frame_size += STARTING_FRAME_OFFSET;
 
@@ -5358,7 +5230,7 @@ s390_frame_info ()
   gprs_ever_live[BASE_REGISTER] = 1;
   gprs_ever_live[RETURN_REGNUM] = 1;
   gprs_ever_live[STACK_POINTER_REGNUM] = cfun->machine->frame_size > 0;
-  
+
   for (i = 6; i < 16; i++)
     if (gprs_ever_live[i])
       break;
@@ -5378,11 +5250,11 @@ s390_frame_info ()
     cfun->machine->first_save_gpr = 2;
 }
 
-/* Return offset between argument pointer and frame pointer 
+/* Return offset between argument pointer and frame pointer
    initially after prologue.  */
 
-int 
-s390_arg_frame_offset ()
+int
+s390_arg_frame_offset (void)
 {
   HOST_WIDE_INT fsize = get_frame_size ();
   int save_fprs_p, i;
@@ -5390,7 +5262,7 @@ s390_arg_frame_offset ()
   /* fprs 8 - 15 are caller saved for 64 Bit ABI.  */
   save_fprs_p = 0;
   if (TARGET_64BIT)
-    for (i = 24; i < 32; i++) 
+    for (i = 24; i < 32; i++)
       if (regs_ever_live[i] && !global_regs[i])
 	{
           save_fprs_p = 1;
@@ -5400,23 +5272,20 @@ s390_arg_frame_offset ()
   fsize = fsize + save_fprs_p * 64;
 
   /* Does function need to setup frame and save area.  */
-  
+
   if (! current_function_is_leaf
       || fsize > 0
-      || current_function_calls_alloca 
+      || current_function_calls_alloca
       || current_function_stdarg)
     fsize += STARTING_FRAME_OFFSET;
   return fsize + STACK_POINTER_OFFSET;
 }
 
 /* Emit insn to save fpr REGNUM at offset OFFSET relative
-   to register BASE.  Return generated insn.  */ 
+   to register BASE.  Return generated insn.  */
 
 static rtx
-save_fpr (base, offset, regnum)
-     rtx base;
-     int offset;
-     int regnum;     
+save_fpr (rtx base, int offset, int regnum)
 {
   rtx addr;
   addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
@@ -5426,13 +5295,10 @@ save_fpr (base, offset, regnum)
 }
 
 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
-   to register BASE.  Return generated insn.  */ 
+   to register BASE.  Return generated insn.  */
 
 static rtx
-restore_fpr (base, offset, regnum)
-     rtx base;
-     int offset;
-     int regnum;
+restore_fpr (rtx base, int offset, int regnum)
 {
   rtx addr;
   addr = gen_rtx_MEM (DFmode, plus_constant (base, offset));
@@ -5442,15 +5308,11 @@ restore_fpr (base, offset, regnum)
 }
 
 /* Generate insn to save registers FIRST to LAST into
-   the register save area located at offset OFFSET 
+   the register save area located at offset OFFSET
    relative to register BASE.  */
 
 static rtx
-save_gprs (base, offset, first, last)
-     rtx base;
-     int offset;
-     int first;
-     int last;
+save_gprs (rtx base, int offset, int first, int last)
 {
   rtx addr, insn, note;
   int i;
@@ -5481,7 +5343,7 @@ save_gprs (base, offset, first, last)
      inside the store-multiple pattern.
 
      However, we must not emit DWARF records for registers 2..5
-     if they are stored for use by variable arguments ...  
+     if they are stored for use by variable arguments ...
 
      ??? Unfortunately, it is not enough to simply not the the
      FRAME_RELATED flags for those SETs, because the first SET
@@ -5502,13 +5364,13 @@ save_gprs (base, offset, first, last)
   else if (last >= 6)
     {
       addr = plus_constant (base, offset + 6 * UNITS_PER_WORD);
-      note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), 
+      note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
 				 gen_rtx_REG (Pmode, 6),
 				 GEN_INT (last - 6 + 1));
       note = PATTERN (note);
 
       REG_NOTES (insn) =
-	gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 
+	gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
 			   note, REG_NOTES (insn));
 
       for (i = 0; i < XVECLEN (note, 0); i++)
@@ -5522,15 +5384,11 @@ save_gprs (base, offset, first, last)
 }
 
 /* Generate insn to restore registers FIRST to LAST from
-   the register save area located at offset OFFSET 
+   the register save area located at offset OFFSET
    relative to register BASE.  */
 
 static rtx
-restore_gprs (base, offset, first, last)
-     rtx base;
-     int offset;
-     int first;
-     int last;
+restore_gprs (rtx base, int offset, int first, int last)
 {
   rtx addr, insn;
 
@@ -5555,63 +5413,98 @@ restore_gprs (base, offset, first, last)
   return insn;
 }
 
+/* Emit code to load the GOT register.  If MAYBE_DEAD is true,
+   annotate generated insns with REG_MAYBE_DEAD notes.  */
+
+static GTY(()) rtx got_symbol;
+void
+s390_load_got (int maybe_dead)
+{
+  if (!got_symbol)
+    {
+      got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
+      SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
+    }
+
+  if (TARGET_CPU_ZARCH)
+    {
+      rtx insn = emit_move_insn (pic_offset_table_rtx, got_symbol);
+      if (maybe_dead)
+        REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
+                                             REG_NOTES (insn));
+    }
+  else
+    {
+      rtx offset, insn;
+
+      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
+			       UNSPEC_LTREL_OFFSET);
+      offset = gen_rtx_CONST (Pmode, offset);
+      offset = force_const_mem (Pmode, offset);
+
+      insn = emit_move_insn (pic_offset_table_rtx, offset);
+      if (maybe_dead)
+	REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
+					     REG_NOTES (insn));
+
+      offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
+			       UNSPEC_LTREL_BASE);
+      offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset);
+
+      insn = emit_move_insn (pic_offset_table_rtx, offset);
+      if (maybe_dead)
+	REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
+					     REG_NOTES (insn));
+    }
+}
+
 /* Expand the prologue into a bunch of separate insns.  */
 
 void
-s390_emit_prologue ()
+s390_emit_prologue (void)
 {
   rtx insn, addr;
   rtx temp_reg;
-  rtx pool_start_label, pool_end_label;
   int i;
 
   /* Compute frame_info.  */
 
   s390_frame_info ();
 
-  /* Choose best register to use for temp use within prologue.  */
-  
+  /* Choose best register to use for temp use within prologue.
+     See below for why TPF must use the register 1.  */
+
   if (!current_function_is_leaf
-      && !has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
-      && get_pool_size () < S390_POOL_CHUNK_MAX / 2)
+      && !TARGET_TPF)
     temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
   else
     temp_reg = gen_rtx_REG (Pmode, 1);
 
   /* Save call saved gprs.  */
 
-  insn = save_gprs (stack_pointer_rtx, 0, 
+  insn = save_gprs (stack_pointer_rtx, 0,
 		    cfun->machine->first_save_gpr, cfun->machine->last_save_gpr);
   emit_insn (insn);
 
-  /* Dump constant pool and set constant pool register.  */
+  /* Dummy insn to mark literal pool slot.  */
+
+  emit_insn (gen_main_pool ());
 
-  pool_start_label = gen_label_rtx();
-  pool_end_label = gen_label_rtx();
-  cfun->machine->literal_pool_label = pool_start_label;
-  
-  if (TARGET_64BIT)
-    insn = emit_insn (gen_literal_pool_64 (gen_rtx_REG (Pmode, BASE_REGISTER),
-                 			   pool_start_label, pool_end_label));
-  else
-    insn = emit_insn (gen_literal_pool_31 (gen_rtx_REG (Pmode, BASE_REGISTER),
-					     pool_start_label, pool_end_label));  
-  
   /* Save fprs for variable args.  */
 
   if (current_function_stdarg)
     {
-      /* Save fpr 0 and 2.  */ 
+      /* Save fpr 0 and 2.  */
+
+      save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16);
+      save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17);
 
-      save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 32, 16); 
-      save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 24, 17); 
-      
       if (TARGET_64BIT)
 	{
 	  /* Save fpr 4 and 6.  */
- 
-	  save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18); 
-	  save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19); 
+
+	  save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 16, 18);
+	  save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
 	}
     }
 
@@ -5627,7 +5520,7 @@ s390_emit_prologue ()
 	}
       if (regs_ever_live[19] && !global_regs[19])
 	{
-	  insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19); 
+	  insn = save_fpr (stack_pointer_rtx, STACK_POINTER_OFFSET - 8, 19);
 	  RTX_FRAME_RELATED_P (insn) = 1;
 	}
     }
@@ -5639,19 +5532,19 @@ s390_emit_prologue ()
       rtx frame_off = GEN_INT (-cfun->machine->frame_size);
 
       /* Save incoming stack pointer into temp reg.  */
-      
+
       if (TARGET_BACKCHAIN || cfun->machine->save_fprs_p)
 	{
 	  insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
 	}
-      
+
       /* Subtract frame size from stack pointer.  */
 
       if (DISP_IN_RANGE (INTVAL (frame_off)))
 	{
-	  insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 
-			      gen_rtx_PLUS (Pmode, stack_pointer_rtx, 
-				      	    frame_off));
+	  insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
+			      gen_rtx_PLUS (Pmode, stack_pointer_rtx,
+					    frame_off));
 	  insn = emit_insn (insn);
 	}
       else
@@ -5663,7 +5556,7 @@ s390_emit_prologue ()
 	}
 
       RTX_FRAME_RELATED_P (insn) = 1;
-      REG_NOTES (insn) = 
+      REG_NOTES (insn) =
 	gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
 			   gen_rtx_SET (VOIDmode, stack_pointer_rtx,
 				   gen_rtx_PLUS (Pmode, stack_pointer_rtx,
@@ -5671,7 +5564,7 @@ s390_emit_prologue ()
 			   REG_NOTES (insn));
 
       /* Set backchain.  */
-      
+
       if (TARGET_BACKCHAIN)
 	{
 	  addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
@@ -5691,7 +5584,7 @@ s390_emit_prologue ()
     }
 
   /* Save fprs 8 - 15 (64 bit ABI).  */
-  
+
   if (cfun->machine->save_fprs_p)
     {
       insn = emit_insn (gen_add2_insn (temp_reg, GEN_INT(-64)));
@@ -5699,22 +5592,22 @@ s390_emit_prologue ()
       for (i = 24; i < 32; i++)
 	if (regs_ever_live[i] && !global_regs[i])
 	  {
-	    rtx addr = plus_constant (stack_pointer_rtx, 
+	    rtx addr = plus_constant (stack_pointer_rtx,
 				      cfun->machine->frame_size - 64 + (i-24)*8);
 
 	    insn = save_fpr (temp_reg, (i-24)*8, i);
 	    RTX_FRAME_RELATED_P (insn) = 1;
-	    REG_NOTES (insn) = 
+	    REG_NOTES (insn) =
 	      gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
-		gen_rtx_SET (VOIDmode, 
+		gen_rtx_SET (VOIDmode,
 			     gen_rtx_MEM (DFmode, addr),
 			     gen_rtx_REG (DFmode, i)),
 		REG_NOTES (insn));
 	  }
     }
-	    
+
   /* Set frame pointer, if needed.  */
-  
+
   if (frame_pointer_needed)
     {
       insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
@@ -5722,54 +5615,69 @@ s390_emit_prologue ()
     }
 
   /* Set up got pointer, if needed.  */
-  
+
   if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
+    s390_load_got(true);
+
+  if (TARGET_TPF)
     {
-      rtx got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
-      SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
+      /* Generate a BAS instruction to serve as a function
+	 entry intercept to facilitate the use of tracing
+	 algorithms located at the branch target.
 
-      if (TARGET_64BIT)
-	{
-	  insn = emit_insn (gen_movdi (pic_offset_table_rtx,
-				       got_symbol));		 
+	 This must use register 1.  */
+      rtx addr;
+      rtx unkn;
+      rtx link;
 
-          /* It can happen that the GOT pointer isn't really needed ...  */
-          REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
-                                               REG_NOTES (insn));
-	}
-      else
-	{
-          got_symbol = gen_rtx_UNSPEC (VOIDmode, 
-				       gen_rtvec (1, got_symbol), 100);
-          got_symbol = gen_rtx_CONST (VOIDmode, got_symbol);
-	  got_symbol = force_const_mem (Pmode, got_symbol);
-	  insn = emit_move_insn (pic_offset_table_rtx,
-				 got_symbol);		 
-          REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
-                                               REG_NOTES (insn));
-
-          got_symbol = gen_rtx_REG (Pmode, BASE_REGISTER);
-          got_symbol = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol), 101);
-          got_symbol = gen_rtx_PLUS (Pmode, got_symbol, pic_offset_table_rtx);
-	  insn = emit_move_insn (pic_offset_table_rtx, got_symbol);
-          REG_NOTES(insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD, NULL_RTX,
-                                               REG_NOTES (insn));
-	}
-    }      
+      addr = GEN_INT (0xfe0);
+      unkn = CONST0_RTX (SImode);
+      link = gen_rtx_REG (Pmode, 1);
+
+      emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
+
+      /* Emit a blockage here so that all code
+	 lies between the profiling mechanisms.  */
+      emit_insn (gen_blockage ());
+    }
 }
 
 /* Expand the epilogue into a bunch of separate insns.  */
 
 void
-s390_emit_epilogue ()
+s390_emit_epilogue (void)
 {
   rtx frame_pointer, return_reg;
   int area_bottom, area_top, offset = 0;
   rtvec p;
 
+  if (TARGET_TPF)
+    {
+
+      /* Generate a BAS instruction to serve as a function
+	 entry intercept to facilitate the use of tracing
+	 algorithms located at the branch target.
+
+	 This must use register 1.  */
+
+      rtx addr;
+      rtx unkn;
+      rtx link;
+
+      addr = GEN_INT (0xfe6);
+      unkn = CONST0_RTX (SImode);
+      link = gen_rtx_REG (Pmode, 1);
+
+      /* Emit a blockage here so that all code
+         lies between the profiling mechanisms.  */
+      emit_insn (gen_blockage ());
+
+      emit_call_insn (gen_call_exp (gen_rtx_MEM (QImode, addr), unkn, link));
+    }
+
   /* Check whether to use frame or stack pointer for restore.  */
 
-  frame_pointer = frame_pointer_needed ? 
+  frame_pointer = frame_pointer_needed ?
     hard_frame_pointer_rtx : stack_pointer_rtx;
 
   /* Compute which parts of the save area we need to access.  */
@@ -5813,7 +5721,7 @@ s390_emit_epilogue ()
 	}
     }
 
-  /* Check whether we can access the register save area.  
+  /* Check whether we can access the register save area.
      If not, increment the frame pointer as required.  */
 
   if (area_top <= area_bottom)
@@ -5830,12 +5738,12 @@ s390_emit_epilogue ()
     {
       rtx insn, frame_off;
 
-      offset = area_bottom < 0 ? -area_bottom : 0; 
+      offset = area_bottom < 0 ? -area_bottom : 0;
       frame_off = GEN_INT (cfun->machine->frame_size - offset);
 
       if (DISP_IN_RANGE (INTVAL (frame_off)))
 	{
-	  insn = gen_rtx_SET (VOIDmode, frame_pointer, 
+	  insn = gen_rtx_SET (VOIDmode, frame_pointer,
 			      gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
 	  insn = emit_insn (insn);
 	}
@@ -5857,7 +5765,7 @@ s390_emit_epilogue ()
       if (cfun->machine->save_fprs_p)
 	for (i = 24; i < 32; i++)
 	  if (regs_ever_live[i] && !global_regs[i])
-	    restore_fpr (frame_pointer, 
+	    restore_fpr (frame_pointer,
 			 offset - 64 + (i-24) * 8, i);
     }
   else
@@ -5870,7 +5778,7 @@ s390_emit_epilogue ()
 
   /* Return register.  */
 
-  return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); 
+  return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
 
   /* Restore call saved gprs.  */
 
@@ -5879,29 +5787,29 @@ s390_emit_epilogue ()
       rtx insn, addr;
       int i;
 
-      /* Check for global register and save them 
+      /* Check for global register and save them
 	 to stack location from where they get restored.  */
 
-      for (i = cfun->machine->first_restore_gpr; 
+      for (i = cfun->machine->first_restore_gpr;
 	   i <= cfun->machine->last_save_gpr;
 	   i++)
 	{
-	  /* These registers are special and need to be 
+	  /* These registers are special and need to be
 	     restored in any case.  */
-	  if (i == STACK_POINTER_REGNUM 
+	  if (i == STACK_POINTER_REGNUM
               || i == RETURN_REGNUM
-              || i == BASE_REGISTER 
+              || i == BASE_REGISTER
               || (flag_pic && i == (int)PIC_OFFSET_TABLE_REGNUM))
 	    continue;
 
 	  if (global_regs[i])
 	    {
-	      addr = plus_constant (frame_pointer, 
+	      addr = plus_constant (frame_pointer,
 		     offset + i * UNITS_PER_WORD);
 	      addr = gen_rtx_MEM (Pmode, addr);
 	      set_mem_alias_set (addr, s390_sr_alias_set);
 	      emit_move_insn (addr, gen_rtx_REG (Pmode, i));
-	    }  
+	    }
 	}
 
       /* Fetch return address from stack before load multiple,
@@ -5913,9 +5821,9 @@ s390_emit_epilogue ()
 	  if (!return_regnum)
 	    return_regnum = 4;
 	  return_reg = gen_rtx_REG (Pmode, return_regnum);
-	
-	  addr = plus_constant (frame_pointer, 
-				offset + RETURN_REGNUM * UNITS_PER_WORD); 
+
+	  addr = plus_constant (frame_pointer,
+				offset + RETURN_REGNUM * UNITS_PER_WORD);
 	  addr = gen_rtx_MEM (Pmode, addr);
 	  set_mem_alias_set (addr, s390_sr_alias_set);
 	  emit_move_insn (return_reg, addr);
@@ -5925,10 +5833,10 @@ s390_emit_epilogue ()
 	 explicit in insn RTX code, we have to add a barrier here
 	 to prevent incorrect scheduling.  */
 
-      emit_insn (gen_blockage());      
+      emit_insn (gen_blockage());
 
-      insn = restore_gprs (frame_pointer, offset, 
-			   cfun->machine->first_restore_gpr, 
+      insn = restore_gprs (frame_pointer, offset,
+			   cfun->machine->first_restore_gpr,
 			   cfun->machine->last_save_gpr);
       emit_insn (insn);
     }
@@ -5936,21 +5844,19 @@ s390_emit_epilogue ()
   /* Return to caller.  */
 
   p = rtvec_alloc (2);
-  
+
   RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
   RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
   emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
 }
 
 
-/* Return the size in bytes of a function argument of 
+/* Return the size in bytes of a function argument of
    type TYPE and/or mode MODE.  At least one of TYPE or
    MODE must be specified.  */
 
 static int
-s390_function_arg_size (mode, type)
-     enum machine_mode mode;
-     tree type;
+s390_function_arg_size (enum machine_mode mode, tree type)
 {
   if (type)
     return int_size_in_bytes (type);
@@ -5967,9 +5873,7 @@ s390_function_arg_size (mode, type)
    is to be passed in a floating-point register, if available.  */
 
 static bool
-s390_function_arg_float (mode, type)
-     enum machine_mode mode;
-     tree type;
+s390_function_arg_float (enum machine_mode mode, tree type)
 {
   /* Soft-float changes the ABI: no floating-point registers are used.  */
   if (TARGET_SOFT_FLOAT)
@@ -6012,9 +5916,7 @@ s390_function_arg_float (mode, type)
    reference.  */
 
 int
-s390_function_arg_pass_by_reference (mode, type)
-     enum machine_mode mode;
-     tree type;
+s390_function_arg_pass_by_reference (enum machine_mode mode, tree type)
 {
   int size = s390_function_arg_size (mode, type);
 
@@ -6028,7 +5930,7 @@ s390_function_arg_pass_by_reference (mode, type)
       if (TREE_CODE (type) == COMPLEX_TYPE)
         return 1;
     }
-    
+
   return 0;
 }
 
@@ -6039,11 +5941,8 @@ s390_function_arg_pass_by_reference (mode, type)
    matching an ellipsis).  */
 
 void
-s390_function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
+			   tree type, int named ATTRIBUTE_UNUSED)
 {
   if (s390_function_arg_pass_by_reference (mode, type))
     {
@@ -6071,7 +5970,7 @@ s390_function_arg_advance (cum, mode, type, named)
    CUM is a variable of type CUMULATIVE_ARGS which gives info about
     the preceding args and about the function being called.
    NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).  
+    (otherwise it is an extra parameter matching an ellipsis).
 
    On S/390, we use general purpose registers 2 through 6 to
    pass integer, pointer, and certain structure arguments, and
@@ -6080,11 +5979,8 @@ s390_function_arg_advance (cum, mode, type, named)
    are pushed to the stack.  */
 
 rtx
-s390_function_arg (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
+		   int named ATTRIBUTE_UNUSED)
 {
   if (s390_function_arg_pass_by_reference (mode, type))
       return 0;
@@ -6119,12 +6015,12 @@ s390_function_arg (cum, mode, type, named)
             long __fpr;
             void *__overflow_arg_area;
             void *__reg_save_area;
-            
+
         } va_list[1];
 
    where __gpr and __fpr hold the number of general purpose
    or floating point arguments used up to now, respectively,
-   __overflow_arg_area points to the stack location of the 
+   __overflow_arg_area points to the stack location of the
    next argument passed on the stack, and __reg_save_area
    always points to the start of the register area in the
    call frame of the current function.  The function prologue
@@ -6132,18 +6028,18 @@ s390_function_arg (cum, mode, type, named)
    area if the function uses variable arguments.  */
 
 tree
-s390_build_va_list ()
+s390_build_va_list (void)
 {
   tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
 
-  record = (*lang_hooks.types.make_type) (RECORD_TYPE);
+  record = lang_hooks.types.make_type (RECORD_TYPE);
 
   type_decl =
     build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
 
-  f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"), 
+  f_gpr = build_decl (FIELD_DECL, get_identifier ("__gpr"),
 		      long_integer_type_node);
-  f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"), 
+  f_fpr = build_decl (FIELD_DECL, get_identifier ("__fpr"),
 		      long_integer_type_node);
   f_ovf = build_decl (FIELD_DECL, get_identifier ("__overflow_arg_area"),
 		      ptr_type_node);
@@ -6182,9 +6078,7 @@ s390_build_va_list ()
        (relative to the virtual arg pointer).  */
 
 void
-s390_va_start (valist, nextarg)
-     tree valist;
-     rtx nextarg ATTRIBUTE_UNUSED;
+s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
 {
   HOST_WIDE_INT n_gpr, n_fpr;
   int off;
@@ -6239,15 +6133,15 @@ s390_va_start (valist, nextarg)
   expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
 }
 
-/* Implement va_arg by updating the va_list structure 
+/* Implement va_arg by updating the va_list structure
    VALIST as required to retrieve an argument of type
-   TYPE, and returning that argument. 
-   
+   TYPE, and returning that argument.
+
    Generates code equivalent to:
-   
+
    if (integral value) {
      if (size  <= 4 && args.gpr < 5 ||
-         size  > 4 && args.gpr < 4 ) 
+         size  > 4 && args.gpr < 4 )
        ret = args.reg_save_area[args.gpr+8]
      else
        ret = *args.overflow_arg_area++;
@@ -6264,9 +6158,7 @@ s390_va_start (valist, nextarg)
    } */
 
 rtx
-s390_va_arg (valist, type)
-     tree valist;
-     tree type;
+s390_va_arg (tree valist, tree type)
 {
   tree f_gpr, f_fpr, f_ovf, f_sav;
   tree gpr, fpr, ovf, sav, reg, t, u;
@@ -6333,6 +6225,7 @@ s390_va_arg (valist, type)
       reg = gpr;
       n_reg = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
       sav_ofs = 2 * UNITS_PER_WORD;
+
       if (size < UNITS_PER_WORD)
 	sav_ofs += UNITS_PER_WORD - size;
 
@@ -6401,10 +6294,10 @@ s390_va_arg (valist, type)
 
   emit_label (lab_over);
 
-  /* If less than max_regs a registers are retrieved out 
+  /* If less than max_regs a registers are retrieved out
      of register save area, increment.  */
 
-  u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, 
+  u = build (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
 	     build_int_2 (n_reg, 0));
   TREE_SIDE_EFFECTS (u) = 1;
   expand_expr (u, const0_rtx, VOIDmode, EXPAND_NORMAL);
@@ -6442,7 +6335,7 @@ static unsigned int const code_for_builtin_31[S390_BUILTIN_max] = {
 };
 
 static void
-s390_init_builtins ()
+s390_init_builtins (void)
 {
   tree ftype;
 
@@ -6464,16 +6357,13 @@ s390_init_builtins ()
    IGNORE is nonzero if the value is to be ignored.  */
 
 static rtx
-s390_expand_builtin (exp, target, subtarget, mode, ignore)
-     tree exp;
-     rtx target;
-     rtx subtarget ATTRIBUTE_UNUSED;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     int ignore ATTRIBUTE_UNUSED;
+s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
+		     enum machine_mode mode ATTRIBUTE_UNUSED,
+		     int ignore ATTRIBUTE_UNUSED)
 {
 #define MAX_ARGS 2
 
-  unsigned int const *code_for_builtin = 
+  unsigned int const *code_for_builtin =
     TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31;
 
   tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
@@ -6556,8 +6446,7 @@ s390_expand_builtin (exp, target, subtarget, mode, ignore)
    gpr 0 is used to hold the static chain.  */
 
 void
-s390_trampoline_template (file)
-     FILE *file;
+s390_trampoline_template (FILE *file)
 {
   if (TARGET_64BIT)
     {
@@ -6584,18 +6473,15 @@ s390_trampoline_template (file)
    CXT is an RTX for the static chain value for the function.  */
 
 void
-s390_initialize_trampoline (addr, fnaddr, cxt)
-     rtx addr;
-     rtx fnaddr;
-     rtx cxt;
+s390_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
 {
-  emit_move_insn (gen_rtx 
+  emit_move_insn (gen_rtx
 		  (MEM, Pmode,
-		   memory_address (Pmode, 
+		   memory_address (Pmode,
 		   plus_constant (addr, (TARGET_64BIT ? 20 : 12) ))), cxt);
   emit_move_insn (gen_rtx
 		  (MEM, Pmode,
-		   memory_address (Pmode, 
+		   memory_address (Pmode,
 		   plus_constant (addr, (TARGET_64BIT ? 28 : 16) ))), fnaddr);
 }
 
@@ -6603,16 +6489,14 @@ s390_initialize_trampoline (addr, fnaddr, cxt)
    LOW and HIGH, independent of the host word size.  */
 
 rtx
-s390_gen_rtx_const_DI (high, low)
-     int high;
-     int low;
+s390_gen_rtx_const_DI (int high, int low)
 {
 #if HOST_BITS_PER_WIDE_INT >= 64
   HOST_WIDE_INT val;
   val = (HOST_WIDE_INT)high;
   val <<= 32;
   val |= (HOST_WIDE_INT)low;
-  
+
   return GEN_INT (val);
 #else
 #if HOST_BITS_PER_WIDE_INT >= 32
@@ -6621,15 +6505,13 @@ s390_gen_rtx_const_DI (high, low)
   abort ();
 #endif
 #endif
-} 
+}
 
 /* Output assembler code to FILE to increment profiler label # LABELNO
    for profiling a function entry.  */
 
 void
-s390_function_profiler (file, labelno)
-     FILE *file;
-     int labelno;
+s390_function_profiler (FILE *file, int labelno)
 {
   rtx op[7];
 
@@ -6649,7 +6531,7 @@ s390_function_profiler (file, labelno)
   op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
   if (flag_pic)
     {
-      op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), 113);
+      op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
       op[4] = gen_rtx_CONST (Pmode, op[4]);
     }
 
@@ -6668,7 +6550,7 @@ s390_function_profiler (file, labelno)
       output_asm_insn ("bras\t%2,%l6", op);
       output_asm_insn (".long\t%4", op);
       output_asm_insn (".long\t%3", op);
-      (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (op[6]));
+      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
       output_asm_insn ("l\t%0,0(%2)", op);
       output_asm_insn ("l\t%2,4(%2)", op);
       output_asm_insn ("basr\t%0,%0", op);
@@ -6681,10 +6563,10 @@ s390_function_profiler (file, labelno)
 
       output_asm_insn ("st\t%0,%1", op);
       output_asm_insn ("bras\t%2,%l6", op);
-      (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (op[5]));
+      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
       output_asm_insn (".long\t%4-%l5", op);
       output_asm_insn (".long\t%3-%l5", op);
-      (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (op[6]));
+      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
       output_asm_insn ("lr\t%0,%2", op);
       output_asm_insn ("a\t%0,0(%2)", op);
       output_asm_insn ("a\t%2,4(%2)", op);
@@ -6697,12 +6579,11 @@ s390_function_profiler (file, labelno)
    constants go in the function section; in 64-bit mode in .rodata.  */
 
 static void
-s390_select_rtx_section (mode, x, align)
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx x ATTRIBUTE_UNUSED;
-     unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
+s390_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED,
+			 rtx x ATTRIBUTE_UNUSED,
+			 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
 {
-  if (TARGET_64BIT)
+  if (TARGET_CPU_ZARCH)
     readonly_data_section ();
   else
     function_section (current_function_decl);
@@ -6712,33 +6593,27 @@ s390_select_rtx_section (mode, x, align)
    into its SYMBOL_REF_FLAGS.  */
 
 static void
-s390_encode_section_info (decl, rtl, first)
-     tree decl;
-     rtx rtl;
-     int first;
+s390_encode_section_info (tree decl, rtx rtl, int first)
 {
   default_encode_section_info (decl, rtl, first);
 
   /* If a variable has a forced alignment to < 2 bytes, mark it with
      SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand.  */
-  if (TREE_CODE (decl) == VAR_DECL 
+  if (TREE_CODE (decl) == VAR_DECL
       && DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
     SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
 }
 
 /* Output thunk to FILE that implements a C++ virtual function call (with
-   multiple inheritance) to FUNCTION.  The thunk adjusts the this pointer 
+   multiple inheritance) to FUNCTION.  The thunk adjusts the this pointer
    by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
    stored at VCALL_OFFSET in the vtable whose address is located at offset 0
    relative to the resulting this pointer.  */
 
 static void
-s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset;
-     tree function;
+s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
+		      HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
+		      tree function)
 {
   rtx op[10];
   int nonlocal = 0;
@@ -6749,12 +6624,12 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
     {
       nonlocal = 1;
       op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
-			      TARGET_64BIT ? 113 : flag_pic == 2 ? 112 : 110);
+			      TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
       op[0] = gen_rtx_CONST (Pmode, op[0]);
     }
 
   /* Operand 1 is the 'this' pointer.  */
-  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     op[1] = gen_rtx_REG (Pmode, 3);
   else
     op[1] = gen_rtx_REG (Pmode, 2);
@@ -6781,9 +6656,9 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
   if (TARGET_64BIT)
     {
       /* Setup literal pool pointer if required.  */
-      if ((!DISP_IN_RANGE (delta) 
+      if ((!DISP_IN_RANGE (delta)
 	   && !CONST_OK_FOR_LETTER_P (delta, 'K'))
-	  || (!DISP_IN_RANGE (vcall_offset) 
+	  || (!DISP_IN_RANGE (vcall_offset)
 	      && !CONST_OK_FOR_LETTER_P (vcall_offset, 'K')))
 	{
 	  op[5] = gen_label_rtx ();
@@ -6828,7 +6703,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
 	      output_asm_insn ("ag\t%1,0(%4)", op);
 	    }
 	}
-        
+
       /* Jump to target.  */
       output_asm_insn ("jg\t%0", op);
 
@@ -6836,19 +6711,19 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
       if (op[5])
 	{
 	  output_asm_insn (".align\t4", op);
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[5]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[5]));
 	}
       if (op[6])
 	{
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[6]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[6]));
 	  output_asm_insn (".long\t%2", op);
 	}
       if (op[7])
 	{
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[7]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[7]));
 	  output_asm_insn (".long\t%3", op);
 	}
     }
@@ -6863,8 +6738,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
 	{
 	  op[5] = gen_label_rtx ();
 	  output_asm_insn ("basr\t%4,0", op);
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[5]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[5]));
 	}
 
       /* Add DELTA to this pointer.  */
@@ -6914,8 +6789,8 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
 	     Re-setup the base pointer (with a different base).  */
 	  op[5] = gen_label_rtx ();
 	  output_asm_insn ("basr\t%4,0", op);
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[5]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[5]));
 	}
 
       /* Jump to target.  */
@@ -6953,7 +6828,7 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
 	  SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
 	}
 
-      (*targetm.asm_out.internal_label) (file, "L", CODE_LABEL_NUMBER (op[8]));
+      targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
       if (!flag_pic)
 	output_asm_insn (".long\t%0", op);
       else
@@ -6961,23 +6836,29 @@ s390_output_mi_thunk (file, thunk, delta, vcall_offset, function)
 
       if (op[6])
 	{
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[6]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[6]));
 	  output_asm_insn (".long\t%2", op);
 	}
       if (op[7])
 	{
-	  (*targetm.asm_out.internal_label) (file, "L",
-					     CODE_LABEL_NUMBER (op[7]));
+	  targetm.asm_out.internal_label (file, "L",
+					  CODE_LABEL_NUMBER (op[7]));
 	  output_asm_insn (".long\t%3", op);
 	}
     }
 }
 
+bool
+s390_valid_pointer_mode (enum machine_mode mode)
+{
+  return (mode == SImode || (TARGET_64BIT && mode == DImode));
+}
+
 /* How to allocate a 'struct machine_function'.  */
 
 static struct machine_function *
-s390_init_machine_status ()
+s390_init_machine_status (void)
 {
   return ggc_alloc_cleared (sizeof (struct machine_function));
 }
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 15bcc87b8ee..5cd1d46d666 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -26,18 +26,18 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 /* Override the __fixdfdi etc. routines when building libgcc2.
    ??? This should be done in a cleaner way ...  */
 #if defined (IN_LIBGCC2) && !defined (__s390x__)
-#include <s390/fixdfdi.h>
+#include <config/s390/fixdfdi.h>
 #endif
 
-/* Which processor to generate code or schedule for. The cpu attribute 
+/* Which processor to generate code or schedule for. The cpu attribute
    defines a list that mirrors this list, so changes to s390.md must be
    made at the same time.  */
 
 enum processor_type
 {
-  PROCESSOR_9672_G5,		
-  PROCESSOR_9672_G6,		
-  PROCESSOR_2064_Z900,		
+  PROCESSOR_9672_G5,
+  PROCESSOR_9672_G6,
+  PROCESSOR_2064_Z900,
   PROCESSOR_2084_Z990,
   PROCESSOR_max
 };
@@ -94,6 +94,7 @@ extern int target_flags;
 #define MASK_64BIT                 0x10
 #define MASK_ZARCH                 0x20
 #define MASK_MVCLE                 0x40
+#define MASK_TPF                   0x80
 
 #define TARGET_HARD_FLOAT          (target_flags & MASK_HARD_FLOAT)
 #define TARGET_SOFT_FLOAT          (!(target_flags & MASK_HARD_FLOAT))
@@ -103,6 +104,7 @@ extern int target_flags;
 #define TARGET_64BIT               (target_flags & MASK_64BIT)
 #define TARGET_ZARCH               (target_flags & MASK_ZARCH)
 #define TARGET_MVCLE               (target_flags & MASK_MVCLE)
+#define TARGET_TPF                 (target_flags & MASK_TPF)
 
 /* ??? Once this actually works, it could be made a runtime option.  */
 #define TARGET_IBM_FLOAT           0
@@ -129,6 +131,8 @@ extern int target_flags;
   { "esa",         -32, N_("ESA/390 architecture")},                   \
   { "mvcle",        64, N_("mvcle use")},                              \
   { "no-mvcle",    -64, N_("mvc&ex")},                                 \
+  { "tpf",         128, N_("enable tpf OS code")},                     \
+  { "no-tpf",     -128, N_("disable tpf OS code")},                    \
   { "", TARGET_DEFAULT, 0 } }
 
 #define TARGET_OPTIONS                                          \
@@ -264,7 +268,7 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
 /* We have 16 general purpose registers (registers 0-15),
    and 16 floating point registers (registers 16-31).
    (On non-IEEE machines, we have only 4 fp registers.)
- 
+
    Amongst the general purpose registers, some are used
    for specific purposes:
    GPR 11: Hard frame pointer (if needed)
@@ -272,7 +276,7 @@ if (INTEGRAL_MODE_P (MODE) &&	        	    	\
    GPR 13: Literal pool base register
    GPR 14: Return address register
    GPR 15: Stack pointer
- 
+
    Registers 32-34 are 'fake' hard registers that do not
    correspond to actual hardware:
    Reg 32: Argument pointer
@@ -376,19 +380,19 @@ do								\
 
 
 /* Fitting values into registers.  */
- 
+
 /* Integer modes <= word size fit into any GPR.
    Integer modes > word size fit into successive GPRs, starting with
    an even-numbered register.
    SImode and DImode fit into FPRs as well.
- 
+
    Floating point modes <= word size fit into any FPR or GPR.
    Floating point modes > word size (i.e. DFmode on 32-bit) fit
    into any FPR, or an even-odd GPR pair.
- 
+
    Complex floating point modes fit either into two FPRs, or into
    successive GPRs (again starting with an even number).
- 
+
    Condition code modes fit only into the CC register.  */
 
 #define HARD_REGNO_NREGS(REGNO, MODE)                           \
@@ -430,19 +434,19 @@ do								\
    ? reg_classes_intersect_p (FP_REGS, CLASS) : 0)
 
 /* Register classes.  */
- 
+
 /* We use the following register classes:
    GENERAL_REGS     All general purpose registers
    ADDR_REGS        All general purpose registers except %r0
                     (These registers can be used in address generation)
    FP_REGS          All floating point registers
- 
+
    GENERAL_FP_REGS  Union of GENERAL_REGS and FP_REGS
    ADDR_FP_REGS     Union of ADDR_REGS and FP_REGS
- 
+
    NO_REGS          No registers
    ALL_REGS         All registers
- 
+
    Note that the 'fake' frame pointer and argument pointer registers
    are included amongst the address registers here.  The condition
    code register is only included in ALL_REGS.  */
@@ -539,7 +543,7 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER];
 
 
 /* Stack layout and calling conventions.  */
- 
+
 /* Our stack grows from higher to lower addresses.  However, local variables
    are accessed by positive offsets, and function arguments are stored at
    increasing addresses.  */
@@ -569,7 +573,7 @@ extern int current_function_outgoing_args_size;
    the argument area.  */
 #define FIRST_PARM_OFFSET(FNDECL) 0
 
-/* The return address of the current frame is retrieved 
+/* The return address of the current frame is retrieved
    from the initial value of register RETURN_REGNUM.
    For frames farther back, we use the stack slot where
    the corresponding RETURN_REGNUM register was saved.  */
@@ -577,7 +581,7 @@ extern int current_function_outgoing_args_size;
 #define DYNAMIC_CHAIN_ADDRESS(FRAME)						\
   ((FRAME) != hard_frame_pointer_rtx ? (FRAME) :				\
    plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET))
-     
+
 #define RETURN_ADDR_RTX(COUNT, FRAME)						\
   s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME)))
 
@@ -586,7 +590,7 @@ extern int current_function_outgoing_args_size;
 
 
 /* Exception handling.  */
- 
+
 /* Describe calling conventions for DWARF-2 exception handling.  */
 #define INCOMING_RETURN_ADDR_RTX  gen_rtx_REG (Pmode, RETURN_REGNUM)
 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET
@@ -596,7 +600,7 @@ extern int current_function_outgoing_args_size;
 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM)
 #define EH_RETURN_HANDLER_RTX \
   gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \
-                                     TARGET_64BIT? -48 : -40))
+               -STACK_POINTER_OFFSET + UNITS_PER_WORD*RETURN_REGNUM))
 
 /* Select a format to encode pointers in exception handling data.  */
 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL)			    \
@@ -612,8 +616,8 @@ extern int current_function_outgoing_args_size;
 #define HARD_FRAME_POINTER_REGNUM 11
 #define ARG_POINTER_REGNUM 32
 
-/* The static chain must be call-clobbered, but not used for 
-   function argument passing.  As register 1 is clobbered by 
+/* The static chain must be call-clobbered, but not used for
+   function argument passing.  As register 1 is clobbered by
    the trampoline code, we only have one option.  */
 #define STATIC_CHAIN_REGNUM 0
 
@@ -633,7 +637,7 @@ extern int current_function_outgoing_args_size;
 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},	        \
  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},    \
  { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM},	        \
- { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}  
+ { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
 
 #define CAN_ELIMINATE(FROM, TO) (1)
 
@@ -654,7 +658,7 @@ extern int current_function_outgoing_args_size;
 
 
 /* Stack arguments.  */
- 
+
 /* We need current_function_outgoing_args to be valid.  */
 #define ACCUMULATE_OUTGOING_ARGS 1
 
@@ -663,7 +667,7 @@ extern int current_function_outgoing_args_size;
 
 
 /* Register arguments.  */
- 
+
 typedef struct s390_arg_structure
 {
   int gprs;			/* gpr so far */
@@ -692,7 +696,7 @@ CUMULATIVE_ARGS;
 
 
 /* Scalar return values.  */
- 
+
 /* We return scalars in general purpose register 2 for integral values,
    and floating point register 0 for fp values.  */
 #define FUNCTION_VALUE(VALTYPE, FUNC)				\
@@ -726,7 +730,7 @@ CUMULATIVE_ARGS;
 
 
 /* Function entry and exit.  */
- 
+
 /* When returning from a function, the stack pointer does not matter.  */
 #define EXIT_IGNORE_STACK       1
 
@@ -763,7 +767,7 @@ CUMULATIVE_ARGS;
 
 
 /* Library calls.  */
- 
+
 /* We should use memcpy, not bcopy.  */
 #define TARGET_MEM_FUNCTIONS
 
@@ -790,7 +794,7 @@ CUMULATIVE_ARGS;
 #define REG_OK_FOR_INDEX_NONSTRICT_P(X)   	\
 ((GET_MODE (X) == Pmode) &&			\
  ((REGNO (X) >= FIRST_PSEUDO_REGISTER) 		\
-  || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))  
+  || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS))
 
 #define REG_OK_FOR_BASE_NONSTRICT_P(X)    REG_OK_FOR_INDEX_NONSTRICT_P (X)
 
@@ -860,7 +864,7 @@ CUMULATIVE_ARGS;
 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
    return the mode to be used for the comparison.  */
 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y))
- 
+
 /* Define the information needed to generate branch and scc insns.  This is
    stored from the compare operation.  Note that we can't use "rtx" here
    since it hasn't been defined!  */
@@ -933,7 +937,7 @@ extern struct rtx_def *s390_compare_op0, *s390_compare_op1;
 
 /* Position independent code.  */
 
-extern int flag_pic; 
+extern int flag_pic;
 
 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM)
 
@@ -1008,65 +1012,6 @@ do {									\
 } while (0)
 
 
-/* Constant Pool for all symbols operands which are changed with
-   force_const_mem during insn generation (expand_insn).  */
-
-extern int s390_pool_count;
-extern int s390_nr_constants;
-
-#define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size)  	        \
-{								       	\
-  struct pool_constant *pool;					       	\
-								        \
-    if (s390_pool_count == -1)                                        	\
-     {							                \
-       s390_nr_constants = 0;				                \
-       for (pool = first_pool; pool; pool = pool->next)	                \
-	 if (pool->mark) s390_nr_constants++;		                \
-       return;                                      	                \
-     }                                                                  \
-}
-
-#define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \
-{									    \
-  fprintf (FILE, ".LC%d:\n", LABELNO);					    \
-									    \
-  /* Output the value of the constant itself.  */			    \
-  switch (GET_MODE_CLASS (MODE))					    \
-    {									    \
-    case MODE_FLOAT:							    \
-      if (GET_CODE (EXP) != CONST_DOUBLE)				    \
-	abort ();							    \
-									    \
-      REAL_VALUE_FROM_CONST_DOUBLE (r, EXP);				    \
-      assemble_real (r, MODE, ALIGN);					    \
-      break;								    \
-									    \
-    case MODE_INT:							    \
-    case MODE_PARTIAL_INT:						    \
-      if (GET_CODE (EXP) == CONST					    \
-	  || GET_CODE (EXP) == SYMBOL_REF				    \
-	  || GET_CODE (EXP) == LABEL_REF)				    \
-        {								    \
-	  fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE);		    \
-          s390_output_symbolic_const (FILE, EXP);			    \
-          fputc ('\n', (FILE));						    \
-	}								    \
-      else								    \
-	{								    \
-	  assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1);	    \
-	  if (GET_MODE_SIZE (MODE) == 1)				    \
-	    ASM_OUTPUT_SKIP ((FILE), (unsigned HOST_WIDE_INT)1);	    \
-	}								    \
-      break;								    \
-									    \
-    default:								    \
-      abort ();								    \
-    }									    \
-  goto WIN;								    \
-}
-
-
 /* Miscellaneous parameters.  */
 
 /* Define the codes that are matched by predicates in aux-output.c.  */
@@ -1086,14 +1031,6 @@ extern int s390_nr_constants;
    tablejump instruction.  */
 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
 
-/* Load from integral MODE < SI from memory into register makes sign_extend
-   or zero_extend  
-   In our case sign_extension happens for Halfwords, other no extension.  */
-#define LOAD_EXTEND_OP(MODE) 					\
-(TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND :               \
-                 (MODE) == HImode ? SIGN_EXTEND : NIL)          \
-              : ((MODE) == HImode ? SIGN_EXTEND : NIL))
-
 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
    is done just by pretending it is already truncated.  */
 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
@@ -1103,6 +1040,9 @@ extern int s390_nr_constants;
    between pointers and any other objects of this machine mode.  */
 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode))
 
+/* This is -1 for "pointer mode" extend.  See ptr_extend in s390.md.  */
+#define POINTERS_EXTEND_UNSIGNED -1
+
 /* A function address in a call instruction is a byte address (for
    indexing purposes) so give the MEM rtx a byte's mode.  */
 #define FUNCTION_MODE QImode
@@ -1110,4 +1050,4 @@ extern int s390_nr_constants;
 /* This macro definition sets up a default value for `main' to return.  */
 #define DEFAULT_MAIN_RETURN  c_expand_return (integer_zero_node)
 
-#endif 
+#endif
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 703f0d7a484..b2eff87c640 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -50,7 +50,24 @@
 ;;
 
 (define_constants
-  [; TLS relocation specifiers
+  [; Miscellaneous
+   (UNSPEC_ROUND		1)
+   (UNSPEC_SETHIGH		10)
+
+   ; GOT/PLT and lt-relative accesses
+   (UNSPEC_LTREL_OFFSET		100)
+   (UNSPEC_LTREL_BASE		101)
+   (UNSPEC_GOTENT		110)
+   (UNSPEC_GOT			111)
+   (UNSPEC_GOTOFF		112)
+   (UNSPEC_PLT			113)
+   (UNSPEC_PLTOFF		114)
+
+   ; Literal pool
+   (UNSPEC_RELOAD_BASE		210)
+   (UNSPEC_MAIN_BASE		211)
+
+   ; TLS relocation specifiers
    (UNSPEC_TLSGD		500)
    (UNSPEC_TLSLDM		501)
    (UNSPEC_NTPOFF               502)
@@ -69,7 +86,17 @@
 ;;
 
 (define_constants
-  [; TLS support
+  [; Blockage
+   (UNSPECV_BLOCKAGE		0)
+
+   ; Literal pool
+   (UNSPECV_POOL		200)
+   (UNSPECV_POOL_START		201)
+   (UNSPECV_POOL_END		202)
+   (UNSPECV_POOL_ENTRY		203)
+   (UNSPECV_MAIN_POOL		300)
+
+   ; TLS support
    (UNSPECV_SET_TP		500)
   ])
 
@@ -90,7 +117,7 @@
 		     fmuld,fmuls,fdivd,fdivs,
 		     ftoi,itof,fsqrtd,fsqrts,
                      other,o2,o3"
-  (const_string "integer")) 
+  (const_string "integer"))
 
 ;; Operand type. Used to default length attribute values
 
@@ -122,7 +149,7 @@
          (eq_attr "op_type" "SIY") (const_string "agen")]
   (const_string "reg")))
 
-;; Generic pipeline function unit.  
+;; Generic pipeline function unit.
 
 (define_function_unit "integer" 1 0
   (eq_attr "type" "none") 0 0)
@@ -261,11 +288,11 @@
 ;   CCU:  Equal    ULess     UGreater  --           (CL, CLR, CLI, CLM)
 ;   CCS:  Equal    SLess     SGreater  --           (C, CR, CH, CHI, ICM)
 ;   CCT:  Zero     Mixed     Mixed     Ones         (TM, TMH, TML)
- 
+
 ;   CCZ  -> CCL / CCZ1
 ;   CCZ1 -> CCA/CCU/CCS/CCT
 ;   CCS  -> CCA
- 
+
 ;   String:    CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
 ;   Clobber:   CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
 
@@ -279,48 +306,44 @@
         (compare:CC (match_operand:DI 0 "register_operand" "")
                     (match_operand:DI 1 "general_operand" "")))]
   "TARGET_64BIT"
-  "
 {
   s390_compare_op0 = operands[0];
   s390_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpsi"
   [(set (reg:CC 33)
         (compare:CC (match_operand:SI 0 "register_operand" "")
                     (match_operand:SI 1 "general_operand" "")))]
   ""
-  "
 {
   s390_compare_op0 = operands[0];
   s390_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpdf"
   [(set (reg:CC 33)
         (compare:CC (match_operand:DF 0 "register_operand" "")
                     (match_operand:DF 1 "general_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   s390_compare_op0 = operands[0];
   s390_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 (define_expand "cmpsf"
   [(set (reg:CC 33)
         (compare:CC (match_operand:SF 0 "register_operand" "")
                     (match_operand:SF 1 "general_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   s390_compare_op0 = operands[0];
   s390_compare_op1 = operands[1];
   DONE;
-}")
+})
 
 
 ; Test-under-Mask (zero_extract) instructions
@@ -332,11 +355,10 @@
                                   (match_operand:DI 2 "const_int_operand" "n"))
                  (const_int 0)))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
-   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
+   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64
    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
       == INTVAL (operands[2]) >> 4"
-  "*
 {
   int part = INTVAL (operands[2]) >> 4;
   int block = (1 << INTVAL (operands[1])) - 1;
@@ -346,13 +368,13 @@
 
   switch (part)
     {
-      case 0: return \"tmhh\\t%0,%x2\";
-      case 1: return \"tmhl\\t%0,%x2\";
-      case 2: return \"tmlh\\t%0,%x2\";
-      case 3: return \"tmll\\t%0,%x2\";
+      case 0: return "tmhh\t%0,%x2";
+      case 1: return "tmhl\t%0,%x2";
+      case 2: return "tmlh\t%0,%x2";
+      case 3: return "tmll\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*tmsi_ext"
@@ -362,11 +384,10 @@
                                   (match_operand:SI 2 "const_int_operand" "n"))
                  (const_int 0)))]
   "s390_match_ccmode(insn, CCTmode)
-   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
+   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32
    && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4
       == INTVAL (operands[2]) >> 4"
-  "*
 {
   int part = INTVAL (operands[2]) >> 4;
   int block = (1 << INTVAL (operands[1])) - 1;
@@ -376,11 +397,11 @@
 
   switch (part)
     {
-      case 0: return \"tmh\\t%0,%x2\";
-      case 1: return \"tml\\t%0,%x2\";
+      case 0: return "tmh\t%0,%x2";
+      case 1: return "tml\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*tmqi_ext"
@@ -390,16 +411,15 @@
                                   (match_operand:SI 2 "const_int_operand" "n,n"))
                  (const_int 0)))]
   "s390_match_ccmode(insn, CCTmode)
-   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
+   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
    && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
-  "*
 {
   int block = (1 << INTVAL (operands[1])) - 1;
   int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
 
   operands[2] = GEN_INT (block << shift);
-  return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\";
-}"
+  return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2";
+}
   [(set_attr "op_type" "SI,SIY")])
 
 ; Test-under-Mask instructions
@@ -409,18 +429,16 @@
         (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S")
                          (match_operand:DI 1 "immediate_operand" "n,n"))
                  (match_operand:DI 2 "immediate_operand" "n,n")))]
-  "TARGET_64BIT
-   && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
+  "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
    && s390_single_qi (operands[1], DImode, 0) >= 0"
-  "*
 {
   int part = s390_single_qi (operands[1], DImode, 0);
   operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part));
 
-  operands[0] = gen_rtx_MEM (QImode, 
+  operands[0] = gen_rtx_MEM (QImode,
 			     plus_constant (XEXP (operands[0], 0), part));
-  return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
-}"
+  return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
+}
   [(set_attr "op_type" "SI,SIY")])
 
 (define_insn "*tmsi_mem"
@@ -430,15 +448,14 @@
                  (match_operand:SI 2 "immediate_operand" "n,n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
    && s390_single_qi (operands[1], SImode, 0) >= 0"
-  "*
 {
   int part = s390_single_qi (operands[1], SImode, 0);
   operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));
 
-  operands[0] = gen_rtx_MEM (QImode, 
+  operands[0] = gen_rtx_MEM (QImode,
 			     plus_constant (XEXP (operands[0], 0), part));
-  return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
-}"
+  return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
+}
   [(set_attr "op_type" "SI")])
 
 (define_insn "*tmhi_mem"
@@ -448,15 +465,14 @@
                  (match_operand:SI 2 "immediate_operand" "n,n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))
    && s390_single_qi (operands[1], HImode, 0) >= 0"
-  "*
 {
   int part = s390_single_qi (operands[1], HImode, 0);
   operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));
 
-  operands[0] = gen_rtx_MEM (QImode, 
+  operands[0] = gen_rtx_MEM (QImode,
 			     plus_constant (XEXP (operands[0], 0), part));
-  return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\";
-}"
+  return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1";
+}
   [(set_attr "op_type" "SI")])
 
 (define_insn "*tmqi_mem"
@@ -466,8 +482,8 @@
                  (match_operand:SI 2 "immediate_operand" "n,n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
   "@
-   tm\\t%0,%b1
-   tmy\\t%0,%b1"
+   tm\t%0,%b1
+   tmy\t%0,%b1"
   [(set_attr "op_type" "SI,SIY")])
 
 (define_insn "*tmdi_reg"
@@ -478,20 +494,19 @@
   "TARGET_64BIT
    && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
    && s390_single_hi (operands[1], DImode, 0) >= 0"
-  "*
 {
   int part = s390_single_hi (operands[1], DImode, 0);
   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 
   switch (part)
     {
-      case 0: return \"tmhh\\t%0,%x1\";
-      case 1: return \"tmhl\\t%0,%x1\";
-      case 2: return \"tmlh\\t%0,%x1\";
-      case 3: return \"tmll\\t%0,%x1\";
+      case 0: return "tmhh\t%0,%x1";
+      case 1: return "tmhl\t%0,%x1";
+      case 2: return "tmlh\t%0,%x1";
+      case 3: return "tmll\t%0,%x1";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*tmsi_reg"
@@ -501,18 +516,17 @@
                  (match_operand:SI 2 "immediate_operand" "n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
    && s390_single_hi (operands[1], SImode, 0) >= 0"
-  "*
 {
   int part = s390_single_hi (operands[1], SImode, 0);
   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
 
   switch (part)
     {
-      case 0: return \"tmh\\t%0,%x1\";
-      case 1: return \"tml\\t%0,%x1\";
+      case 0: return "tmh\t%0,%x1";
+      case 1: return "tml\t%0,%x1";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*tmhi_full"
@@ -520,7 +534,7 @@
         (compare (match_operand:HI 0 "register_operand" "d")
                  (match_operand:HI 1 "immediate_operand" "n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
-  "tml\\t%0,65535"
+  "tml\t%0,65535"
   [(set_attr "op_type" "RX")])
 
 (define_insn "*tmqi_full"
@@ -528,7 +542,7 @@
         (compare (match_operand:QI 0 "register_operand" "d")
                  (match_operand:QI 1 "immediate_operand" "n")))]
   "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))"
-  "tml\\t%0,255"
+  "tml\t%0,255"
   [(set_attr "op_type" "RI")])
 
 
@@ -542,7 +556,7 @@
    (set (match_operand:DI 2 "register_operand" "=d")
         (sign_extend:DI (match_dup 0)))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
-  "ltgfr\\t%2,%0"
+  "ltgfr\t%2,%0"
   [(set_attr "op_type" "RRE")])
 
 (define_insn "*tstdi"
@@ -552,7 +566,7 @@
    (set (match_operand:DI 2 "register_operand" "=d")
         (match_dup 0))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
-  "ltgr\\t%2,%0"
+  "ltgr\t%2,%0"
   [(set_attr "op_type" "RRE")])
 
 (define_insn "*tstdi_cconly"
@@ -560,7 +574,7 @@
         (compare (match_operand:DI 0 "register_operand" "d")
                  (match_operand:DI 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
-  "ltgr\\t%0,%0"
+  "ltgr\t%0,%0"
   [(set_attr "op_type" "RRE")])
 
 (define_insn "*tstdi_cconly_31"
@@ -568,7 +582,7 @@
         (compare (match_operand:DI 0 "register_operand" "d")
                  (match_operand:DI 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
-  "srda\\t%0,0"
+  "srda\t%0,0"
   [(set_attr "op_type" "RS")
    (set_attr "atype"   "reg")])
 
@@ -581,9 +595,9 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   ltr\\t%2,%0
-   icm\\t%2,15,%0
-   icmy\\t%2,15,%0"
+   ltr\t%2,%0
+   icm\t%2,15,%0
+   icmy\t%2,15,%0"
   [(set_attr "op_type" "RR,RS,RSY")])
 
 (define_insn "*tstsi_cconly"
@@ -593,9 +607,9 @@
    (clobber (match_scratch:SI 2 "=X,d,d"))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   ltr\\t%0,%0
-   icm\\t%2,15,%0
-   icmy\\t%2,15,%0"
+   ltr\t%0,%0
+   icm\t%2,15,%0
+   icmy\t%2,15,%0"
   [(set_attr "op_type" "RR,RS,RSY")])
 
 (define_insn "*tstsi_cconly2"
@@ -603,7 +617,7 @@
         (compare (match_operand:SI 0 "register_operand" "d")
                  (match_operand:SI 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode)"
-  "ltr\\t%0,%0"
+  "ltr\t%0,%0"
   [(set_attr "op_type" "RR")])
 
 (define_insn "*tsthiCCT"
@@ -614,9 +628,9 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   icm\\t%2,3,%0
-   icmy\\t%2,3,%0
-   tml\\t%0,65535"
+   icm\t%2,3,%0
+   icmy\t%2,3,%0
+   tml\t%0,65535"
   [(set_attr "op_type" "RS,RSY,RI")])
 
 (define_insn "*tsthiCCT_cconly"
@@ -626,9 +640,9 @@
    (clobber (match_scratch:HI 2 "=d,d,X"))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   icm\\t%2,3,%0
-   icmy\\t%2,3,%0
-   tml\\t%0,65535"
+   icm\t%2,3,%0
+   icmy\t%2,3,%0
+   tml\t%0,65535"
   [(set_attr "op_type" "RS,RSY,RI")])
 
 (define_insn "*tsthi"
@@ -639,8 +653,8 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   icm\\t%2,3,%0
-   icmy\\t%2,3,%0"
+   icm\t%2,3,%0
+   icmy\t%2,3,%0"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*tsthi_cconly"
@@ -650,8 +664,8 @@
    (clobber (match_scratch:HI 2 "=d,d"))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   icm\\t%2,3,%0
-   icmy\\t%2,3,%0"
+   icm\t%2,3,%0
+   icmy\t%2,3,%0"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*tstqiCCT"
@@ -662,9 +676,9 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   icm\\t%2,1,%0
-   icmy\\t%2,1,%0
-   tml\\t%0,255"
+   icm\t%2,1,%0
+   icmy\t%2,1,%0
+   tml\t%0,255"
   [(set_attr "op_type" "RS,RSY,RI")])
 
 (define_insn "*tstqiCCT_cconly"
@@ -673,9 +687,9 @@
                  (match_operand:QI 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   cli\\t%0,0
-   cliy\\t%0,0
-   tml\\t%0,255"
+   cli\t%0,0
+   cliy\t%0,0
+   tml\t%0,255"
   [(set_attr "op_type" "SI,SIY,RI")])
 
 (define_insn "*tstqi"
@@ -686,8 +700,8 @@
         (match_dup 0))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   icm\\t%2,1,%0
-   icmy\\t%2,1,%0"
+   icm\t%2,1,%0
+   icmy\t%2,1,%0"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*tstqi_cconly"
@@ -697,8 +711,8 @@
    (clobber (match_scratch:QI 2 "=d,d"))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   icm\\t%2,1,%0
-   icmy\\t%2,1,%0"
+   icm\t%2,1,%0
+   icmy\t%2,1,%0"
   [(set_attr "op_type" "RS,RSY")])
 
 
@@ -710,8 +724,8 @@
                  (match_operand:DI 0 "register_operand" "d,d")))]
   "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
   "@
-   cgfr\\t%0,%1
-   cgf\\t%0,%1"
+   cgfr\t%0,%1
+   cgf\t%0,%1"
   [(set_attr "op_type" "RRE,RXY")])
 
 (define_insn "*cmpdi_ccs"
@@ -720,19 +734,19 @@
                  (match_operand:DI 1 "general_operand" "d,K,m")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
   "@
-   cgr\\t%0,%1
-   cghi\\t%0,%c1
-   cg\\t%0,%1"
+   cgr\t%0,%1
+   cghi\t%0,%c1
+   cg\t%0,%1"
   [(set_attr "op_type" "RRE,RI,RXY")])
-   
+
 (define_insn "*cmpsi_ccs_sign"
   [(set (reg 33)
         (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
                  (match_operand:SI 0 "register_operand" "d,d")))]
   "s390_match_ccmode(insn, CCSRmode)"
   "@
-   ch\\t%0,%1
-   chy\\t%0,%1"
+   ch\t%0,%1
+   chy\t%0,%1"
   [(set_attr "op_type" "RX,RXY")])
 
 (define_insn "*cmpsi_ccs"
@@ -741,12 +755,12 @@
                  (match_operand:SI 1 "general_operand" "d,K,R,T")))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   cr\\t%0,%1
-   chi\\t%0,%c1
-   c\\t%0,%1
-   cy\\t%0,%1"
+   cr\t%0,%1
+   chi\t%0,%c1
+   c\t%0,%1
+   cy\t%0,%1"
   [(set_attr "op_type" "RR,RI,RX,RXY")])
-   
+
 
 ; Compare (unsigned) instructions
 
@@ -756,8 +770,8 @@
                  (match_operand:DI 0 "register_operand" "d,d")))]
   "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT"
   "@
-   clgfr\\t%0,%1
-   clgf\\t%0,%1"
+   clgfr\t%0,%1
+   clgf\t%0,%1"
   [(set_attr "op_type" "RRE,RXY")])
 
 (define_insn "*cmpdi_ccu"
@@ -766,8 +780,8 @@
                  (match_operand:DI 1 "general_operand" "d,m")))]
   "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
   "@
-   clgr\\t%0,%1
-   clg\\t%0,%1"
+   clgr\t%0,%1
+   clg\t%0,%1"
   [(set_attr "op_type" "RRE,RXY")])
 
 (define_insn "*cmpsi_ccu"
@@ -776,9 +790,9 @@
                  (match_operand:SI 1 "general_operand" "d,R,T")))]
   "s390_match_ccmode(insn, CCUmode)"
   "@
-   clr\\t%0,%1
-   cl\\t%0,%1
-   cly\\t%0,%1"
+   clr\t%0,%1
+   cl\t%0,%1
+   cly\t%0,%1"
   [(set_attr "op_type" "RR,RX,RXY")])
 
 (define_insn "*cmphi_ccu"
@@ -787,8 +801,8 @@
                  (match_operand:HI 1 "s_imm_operand" "Q,S")))]
   "s390_match_ccmode(insn, CCUmode)"
   "@
-   clm\\t%0,3,%1
-   clmy\\t%0,3,%1"
+   clm\t%0,3,%1
+   clmy\t%0,3,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*cmpqi_ccu"
@@ -797,8 +811,8 @@
                  (match_operand:QI 1 "s_imm_operand" "Q,S")))]
   "s390_match_ccmode(insn, CCUmode)"
   "@
-   clm\\t%0,1,%1
-   clmy\\t%0,1,%1"
+   clm\t%0,1,%1
+   clmy\t%0,1,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*cli"
@@ -807,8 +821,8 @@
                  (match_operand:QI 1 "immediate_operand" "n,n")))]
   "s390_match_ccmode (insn, CCUmode)"
   "@
-   cli\\t%0,%b1
-   cliy\\t%0,%b1"
+   cli\t%0,%b1
+   cliy\t%0,%b1"
   [(set_attr "op_type" "SI,SIY")])
 
 (define_insn "*cmpdi_ccu_mem"
@@ -816,7 +830,7 @@
         (compare (match_operand:DI 0 "s_operand" "Q")
                  (match_operand:DI 1 "s_imm_operand" "Q")))]
   "s390_match_ccmode(insn, CCUmode)"
-  "clc\\t%O0(8,%R0),%1"
+  "clc\t%O0(8,%R0),%1"
   [(set_attr "op_type" "SS")])
 
 (define_insn "*cmpsi_ccu_mem"
@@ -824,7 +838,7 @@
         (compare (match_operand:SI 0 "s_operand" "Q")
                  (match_operand:SI 1 "s_imm_operand" "Q")))]
   "s390_match_ccmode(insn, CCUmode)"
-  "clc\\t%O0(4,%R0),%1"
+  "clc\t%O0(4,%R0),%1"
    [(set_attr "op_type" "SS")])
 
 (define_insn "*cmphi_ccu_mem"
@@ -832,7 +846,7 @@
         (compare (match_operand:HI 0 "s_operand" "Q")
                  (match_operand:HI 1 "s_imm_operand" "Q")))]
   "s390_match_ccmode(insn, CCUmode)"
-  "clc\\t%O0(2,%R0),%1"
+  "clc\t%O0(2,%R0),%1"
   [(set_attr "op_type" "SS")])
 
 (define_insn "*cmpqi_ccu_mem"
@@ -840,7 +854,7 @@
         (compare (match_operand:QI 0 "s_operand" "Q")
                  (match_operand:QI 1 "s_imm_operand" "Q")))]
   "s390_match_ccmode(insn, CCUmode)"
-  "clc\\t%O0(1,%R0),%1"
+  "clc\t%O0(1,%R0),%1"
   [(set_attr "op_type" "SS")])
 
 
@@ -851,7 +865,7 @@
         (compare (match_operand:DF 0 "register_operand" "f")
                  (match_operand:DF 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ltdbr\\t%0,%0"
+  "ltdbr\t%0,%0"
    [(set_attr "op_type" "RRE")
     (set_attr "type"  "fsimpd")])
 
@@ -860,7 +874,7 @@
         (compare (match_operand:DF 0 "register_operand" "f")
                  (match_operand:DF 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "ltdr\\t%0,%0"
+  "ltdr\t%0,%0"
    [(set_attr "op_type" "RR")
     (set_attr "type"  "fsimpd")])
 
@@ -870,8 +884,8 @@
                  (match_operand:DF 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   cdbr\\t%0,%1
-   cdb\\t%0,%1"
+   cdbr\t%0,%1
+   cdb\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
     (set_attr "type"  "fsimpd")])
 
@@ -881,8 +895,8 @@
                  (match_operand:DF 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   cdr\\t%0,%1
-   cd\\t%0,%1"
+   cdr\t%0,%1
+   cd\t%0,%1"
    [(set_attr "op_type" "RR,RX")
     (set_attr "type"  "fsimpd")])
 
@@ -894,7 +908,7 @@
         (compare (match_operand:SF 0 "register_operand" "f")
                  (match_operand:SF 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ltebr\\t%0,%0"
+  "ltebr\t%0,%0"
    [(set_attr "op_type" "RRE")
     (set_attr "type"  "fsimps")])
 
@@ -903,7 +917,7 @@
         (compare (match_operand:SF 0 "register_operand" "f")
                  (match_operand:SF 1 "const0_operand" "")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lter\\t%0,%0"
+  "lter\t%0,%0"
    [(set_attr "op_type" "RR")
     (set_attr "type"  "fsimps")])
 
@@ -913,8 +927,8 @@
                  (match_operand:SF 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   cebr\\t%0,%1
-   ceb\\t%0,%1"
+   cebr\t%0,%1
+   ceb\t%0,%1"
    [(set_attr "op_type" "RRE,RXE")
     (set_attr "type"  "fsimps")])
 
@@ -924,8 +938,8 @@
                  (match_operand:SF 1 "general_operand" "f,R")))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   cer\\t%0,%1
-   ce\\t%0,%1"
+   cer\t%0,%1
+   ce\t%0,%1"
    [(set_attr "op_type" "RR,RX")
     (set_attr "type"  "fsimps")])
 
@@ -943,11 +957,11 @@
         (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
   "TARGET_64BIT"
   "@
-   lmg\\t%0,%N0,%1
-   stmg\\t%1,%N1,%0
+   lmg\t%0,%N0,%1
+   stmg\t%1,%N1,%0
    #
    #
-   mvc\\t%O0(16,%R0),%1"
+   mvc\t%O0(16,%R0),%1"
   [(set_attr "op_type" "RSY,RSY,NN,NN,SS")
    (set_attr "type" "lm,stm,*,*,cs")])
 
@@ -1011,7 +1025,6 @@
   [(set (match_operand:DI 0 "general_operand" "")
         (match_operand:DI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Handle symbolic constants.  */
   if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
@@ -1020,11 +1033,11 @@
   /* During and after reload, we need to force constants
      to the literal pool ourselves, if necessary.  */
   if ((reload_in_progress || reload_completed)
-      && CONSTANT_P (operands[1]) 
+      && CONSTANT_P (operands[1])
       && (!legitimate_reload_constant_p (operands[1])
           || FP_REG_P (operands[0])))
     operands[1] = force_const_mem (DImode, operands[1]);
-}")
+})
 
 (define_insn "*movdi_lhi"
   [(set (match_operand:DI 0 "register_operand" "=d")
@@ -1033,7 +1046,7 @@
    && GET_CODE (operands[1]) == CONST_INT
    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
    && !FP_REG_P (operands[0])"
-  "lghi\\t%0,%h1"
+  "lghi\t%0,%h1"
   [(set_attr "op_type" "RI")])
 
 (define_insn "*movdi_lli"
@@ -1041,30 +1054,29 @@
         (match_operand:DI 1 "immediate_operand" "n"))]
   "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0
    && !FP_REG_P (operands[0])"
-  "*
 {
   int part = s390_single_hi (operands[1], DImode, 0);
   operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part));
 
   switch (part)
     {
-      case 0: return \"llihh\\t%0,%x1\";
-      case 1: return \"llihl\\t%0,%x1\";
-      case 2: return \"llilh\\t%0,%x1\";
-      case 3: return \"llill\\t%0,%x1\";
+      case 0: return "llihh\t%0,%x1";
+      case 1: return "llihl\t%0,%x1";
+      case 2: return "llilh\t%0,%x1";
+      case 3: return "llill\t%0,%x1";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*movdi_lay"
   [(set (match_operand:DI 0 "register_operand" "=d")
         (match_operand:DI 1 "address_operand" "p"))]
-  "TARGET_64BIT 
+  "TARGET_64BIT
    && TARGET_LONG_DISPLACEMENT
    && GET_CODE (operands[1]) == CONST_INT
    && !FP_REG_P (operands[0])"
-  "lay\\t%0,%a1"
+  "lay\t%0,%a1"
   [(set_attr "op_type" "RXY")
    (set_attr "type" "la")])
 
@@ -1073,7 +1085,7 @@
         (match_operand:DI 1 "larl_operand" "X"))]
   "TARGET_64BIT
    && !FP_REG_P (operands[0])"
-  "larl\\t%0,%1"
+  "larl\t%0,%1"
    [(set_attr "op_type" "RIL")
     (set_attr "type"    "larl")])
 
@@ -1082,15 +1094,15 @@
         (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))]
   "TARGET_64BIT"
   "@
-   lgr\\t%0,%1
-   lg\\t%0,%1
-   stg\\t%1,%0
-   ldr\\t%0,%1
-   ld\\t%0,%1
-   ldy\\t%0,%1
-   std\\t%1,%0
-   stdy\\t%1,%0
-   mvc\\t%O0(8,%R0),%1"
+   lgr\t%0,%1
+   lg\t%0,%1
+   stg\t%1,%0
+   ldr\t%0,%1
+   ld\t%0,%1
+   ldy\t%0,%1
+   std\t%1,%0
+   stdy\t%1,%0
+   mvc\t%O0(8,%R0),%1"
   [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS")
    (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")])
 
@@ -1099,16 +1111,16 @@
         (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
   "!TARGET_64BIT"
   "@
-   lm\\t%0,%N0,%1
-   stm\\t%1,%N1,%0
+   lm\t%0,%N0,%1
+   stm\t%1,%N1,%0
    #
    #
-   ldr\\t%0,%1
-   ld\\t%0,%1
-   ldy\\t%0,%1
-   std\\t%1,%0
-   stdy\\t%1,%0
-   mvc\\t%O0(8,%R0),%1"
+   ldr\t%0,%1
+   ld\t%0,%1
+   ldy\t%0,%1
+   std\t%1,%0
+   stdy\t%1,%0
+   mvc\t%O0(8,%R0),%1"
   [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS")
    (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")])
 
@@ -1185,14 +1197,13 @@
   [(set (match_operand:SI 0 "general_operand" "")
         (match_operand:SI 1 "general_operand" ""))]
   ""
-  "
 {
   /* Handle symbolic constants.  */
   if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
     emit_symbolic_move (operands);
 
-  /* expr.c tries to load an effective address using 
-     force_reg.  This fails because we don't have a 
+  /* expr.c tries to load an effective address using
+     force_reg.  This fails because we don't have a
      generic load_address pattern.  Convert the move
      to a proper arithmetic operation instead, unless
      it is guaranteed to be OK.  */
@@ -1207,11 +1218,11 @@
   /* During and after reload, we need to force constants
      to the literal pool ourselves, if necessary.  */
   if ((reload_in_progress || reload_completed)
-      && CONSTANT_P (operands[1]) 
+      && CONSTANT_P (operands[1])
       && (!legitimate_reload_constant_p (operands[1])
           || FP_REG_P (operands[0])))
     operands[1] = force_const_mem (SImode, operands[1]);
-}")
+})
 
 (define_insn "*movsi_lhi"
   [(set (match_operand:SI 0 "register_operand" "=d")
@@ -1219,26 +1230,25 @@
   "GET_CODE (operands[1]) == CONST_INT
    && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
    && !FP_REG_P (operands[0])"
-  "lhi\\t%0,%h1"
+  "lhi\t%0,%h1"
   [(set_attr "op_type" "RI")])
 
 (define_insn "*movsi_lli"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (match_operand:SI 1 "immediate_operand" "n"))]
-  "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0
+  "TARGET_ZARCH && s390_single_hi (operands[1], SImode, 0) >= 0
    && !FP_REG_P (operands[0])"
-  "*
 {
   int part = s390_single_hi (operands[1], SImode, 0);
   operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part));
 
   switch (part)
     {
-      case 0: return \"llilh\\t%0,%x1\";
-      case 1: return \"llill\\t%0,%x1\";
+      case 0: return "llilh\t%0,%x1";
+      case 1: return "llill\t%0,%x1";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type" "RI")])
 
 (define_insn "*movsi_lay"
@@ -1247,26 +1257,35 @@
   "TARGET_LONG_DISPLACEMENT
    && GET_CODE (operands[1]) == CONST_INT
    && !FP_REG_P (operands[0])"
-  "lay\\t%0,%a1"
+  "lay\t%0,%a1"
   [(set_attr "op_type" "RXY")
    (set_attr "type" "la")])
 
+(define_insn "*movsi_larl"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (match_operand:SI 1 "larl_operand" "X"))]
+  "!TARGET_64BIT && TARGET_CPU_ZARCH
+   && !FP_REG_P (operands[0])"
+  "larl\t%0,%1"
+   [(set_attr "op_type" "RIL")
+    (set_attr "type"    "larl")])
+
 (define_insn "*movsi"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q")
         (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))]
   ""
   "@
-   lr\\t%0,%1
-   l\\t%0,%1
-   ly\\t%0,%1
-   st\\t%1,%0
-   sty\\t%1,%0
-   ler\\t%0,%1
-   le\\t%0,%1
-   ley\\t%0,%1
-   ste\\t%1,%0
-   stey\\t%1,%0
-   mvc\\t%O0(4,%R0),%1"
+   lr\t%0,%1
+   l\t%0,%1
+   ly\t%0,%1
+   st\t%1,%0
+   sty\t%1,%0
+   ler\t%0,%1
+   le\t%0,%1
+   ley\t%0,%1
+   ste\t%1,%0
+   stey\t%1,%0
+   mvc\t%O0(4,%R0),%1"
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
    (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")])
 
@@ -1285,18 +1304,36 @@
 ; movhi instruction pattern(s).
 ;
 
-(define_insn "movhi"
+(define_expand "movhi"
+  [(set (match_operand:HI 0 "nonimmediate_operand" "")
+        (match_operand:HI 1 "general_operand" ""))]
+  ""
+{
+  /* Make it explicit that loading a register from memory 
+     always sign-extends (at least) to SImode.  */
+  if (optimize && !no_new_pseudos
+      && register_operand (operands[0], VOIDmode)
+      && memory_operand (operands[1], VOIDmode))
+    {
+      rtx tmp = gen_reg_rtx (SImode);
+      rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
+      emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
+      operands[1] = gen_lowpart (HImode, tmp);
+    }
+})
+
+(define_insn "*movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
         (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
   ""
   "@
-   lr\\t%0,%1
-   lhi\\t%0,%h1
-   lh\\t%0,%1
-   lhy\\t%0,%1
-   sth\\t%1,%0
-   sthy\\t%1,%0
-   mvc\\t%O0(2,%R0),%1"
+   lr\t%0,%1
+   lhi\t%0,%h1
+   lh\t%0,%1
+   lhy\t%0,%1
+   sth\t%1,%0
+   sthy\t%1,%0
+   mvc\t%O0(2,%R0),%1"
   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
    (set_attr "type" "lr,*,*,*,store,store,cs")])
 
@@ -1314,36 +1351,38 @@
 ; movqi instruction pattern(s).
 ;
 
-(define_insn "movqi_64"
-  [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
-        (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
-  "TARGET_64BIT"
-  "@
-   lr\\t%0,%1
-   lhi\\t%0,%b1
-   llgc\\t%0,%1
-   stc\\t%1,%0
-   stcy\\t%1,%0
-   mvi\\t%0,%b1
-   mviy\\t%0,%b1
-   mvc\\t%O0(1,%R0),%1"
-  [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
-   (set_attr "type" "lr,*,*,store,store,store,store,cs")])
-
-(define_insn "movqi"
+(define_expand "movqi"
+  [(set (match_operand:QI 0 "nonimmediate_operand" "")
+        (match_operand:QI 1 "general_operand" ""))]
+  ""
+{
+  /* On 64-bit, zero-extending from memory to register
+     is just as fast as a QImode load.  */
+  if (TARGET_64BIT && optimize && !no_new_pseudos
+      && register_operand (operands[0], VOIDmode)
+      && memory_operand (operands[1], VOIDmode))
+    {
+      rtx tmp = gen_reg_rtx (DImode);
+      rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
+      emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
+      operands[1] = gen_lowpart (QImode, tmp);
+    }
+})
+
+(define_insn "*movqi"
   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
         (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
   ""
   "@
-   lr\\t%0,%1
-   lhi\\t%0,%b1
-   ic\\t%0,%1
-   icy\\t%0,%1
-   stc\\t%1,%0
-   stcy\\t%1,%0
-   mvi\\t%0,%b1
-   mviy\\t%0,%b1
-   mvc\\t%O0(1,%R0),%1"
+   lr\t%0,%1
+   lhi\t%0,%b1
+   ic\t%0,%1
+   icy\t%0,%1
+   stc\t%1,%0
+   stcy\t%1,%0
+   mvi\t%0,%b1
+   mviy\t%0,%b1
+   mvc\t%O0(1,%R0),%1"
   [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
    (set_attr "type" "lr,*,*,*,store,store,store,store,cs")])
 
@@ -1366,8 +1405,8 @@
                          (match_operand:QI 1 "memory_operand" "R,T"))]
   ""
   "@
-   ic\\t%0,%1
-   icy\\t%0,%1"
+   ic\t%0,%1
+   icy\t%0,%1"
   [(set_attr "op_type"  "RX,RXY")])
 
 ;
@@ -1380,8 +1419,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   icm\\t%0,3,%1
-   icmy\\t%0,3,%1"
+   icm\t%0,3,%1
+   icmy\t%0,3,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 ;
@@ -1393,9 +1432,9 @@
                          (match_operand:SI 1 "general_operand" "d,R,T"))]
   "TARGET_64BIT"
   "@
-   lr\\t%0,%1
-   l\\t%0,%1
-   ly\\t%0,%1"
+   lr\t%0,%1
+   l\t%0,%1
+   ly\t%0,%1"
   [(set_attr "op_type" "RR,RX,RXY")
    (set_attr "type" "lr,load,load")])
 
@@ -1407,29 +1446,28 @@
   [(set (match_operand:DF 0 "nonimmediate_operand" "")
         (match_operand:DF 1 "general_operand"  ""))]
   ""
-  "
 {
   /* During and after reload, we need to force constants
      to the literal pool ourselves, if necessary.  */
   if ((reload_in_progress || reload_completed)
       && CONSTANT_P (operands[1]))
     operands[1] = force_const_mem (DFmode, operands[1]);
-}")
+})
 
 (define_insn "*movdf_64"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
         (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
   "TARGET_64BIT"
   "@
-   ldr\\t%0,%1
-   ld\\t%0,%1
-   ldy\\t%0,%1
-   std\\t%1,%0
-   stdy\\t%1,%0
-   lgr\\t%0,%1
-   lg\\t%0,%1
-   stg\\t%1,%0
-   mvc\\t%O0(8,%R0),%1"
+   ldr\t%0,%1
+   ld\t%0,%1
+   ldy\t%0,%1
+   std\t%1,%0
+   stdy\t%1,%0
+   lgr\t%0,%1
+   lg\t%0,%1
+   stg\t%1,%0
+   mvc\t%O0(8,%R0),%1"
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
    (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")])
 
@@ -1438,16 +1476,16 @@
         (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
   "!TARGET_64BIT"
   "@
-   ldr\\t%0,%1
-   ld\\t%0,%1
-   ldy\\t%0,%1
-   std\\t%1,%0
-   stdy\\t%1,%0
-   lm\\t%0,%N0,%1
-   stm\\t%1,%N1,%0
+   ldr\t%0,%1
+   ld\t%0,%1
+   ldy\t%0,%1
+   std\t%1,%0
+   stdy\t%1,%0
+   lm\t%0,%N0,%1
+   stm\t%1,%N1,%0
    #
    #
-   mvc\\t%O0(8,%R0),%1"
+   mvc\t%O0(8,%R0),%1"
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS")
    (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")])
 
@@ -1512,31 +1550,30 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
         (match_operand:SF 1 "general_operand"  ""))]
   ""
-  "
 {
   /* During and after reload, we need to force constants
      to the literal pool ourselves, if necessary.  */
   if ((reload_in_progress || reload_completed)
       && CONSTANT_P (operands[1]))
     operands[1] = force_const_mem (SFmode, operands[1]);
-}")
+})
 
 (define_insn "*movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
         (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
   ""
   "@
-   ler\\t%0,%1
-   le\\t%0,%1
-   ley\\t%0,%1
-   ste\\t%1,%0
-   stey\\t%1,%0
-   lr\\t%0,%1
-   l\\t%0,%1
-   ly\\t%0,%1
-   st\\t%1,%0
-   sty\\t%1,%0
-   mvc\\t%O0(4,%R0),%1"
+   ler\t%0,%1
+   le\t%0,%1
+   ley\t%0,%1
+   ste\t%1,%0
+   stey\t%1,%0
+   lr\t%0,%1
+   l\t%0,%1
+   ly\t%0,%1
+   st\t%1,%0
+   sty\t%1,%0
+   mvc\t%O0(4,%R0),%1"
   [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
    (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")])
 
@@ -1549,7 +1586,6 @@
 			  (match_operand 1 "" ""))
 		     (use (match_operand 2 "" ""))])]
   ""
-  "
 {
   int regno;
   int count;
@@ -1602,19 +1638,18 @@
 		     change_address (operands[1], Pmode,
 				     plus_constant (from,
 						    off + i * UNITS_PER_WORD)));
-}")
+})
 
 (define_insn "*load_multiple_di"
   [(match_parallel 0 "load_multiple_operation"
 		   [(set (match_operand:DI 1 "register_operand" "=r")
 			 (match_operand:DI 2 "s_operand" "QS"))])]
   ""
-  "*
 {
   int words = XVECLEN (operands[0], 0);
   operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
-  return \"lmg\\t%1,%0,%2\";
-}"
+  return "lmg\t%1,%0,%2";
+}
    [(set_attr "op_type" "RSY")
     (set_attr "type"    "lm")])
 
@@ -1623,17 +1658,16 @@
 		   [(set (match_operand:SI 1 "register_operand" "=r,r")
 			 (match_operand:SI 2 "s_operand" "Q,S"))])]
   ""
-  "*
 {
   int words = XVECLEN (operands[0], 0);
   operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
-  return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\";
-}"
+  return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2";
+}
    [(set_attr "op_type" "RS,RSY")
     (set_attr "type"    "lm")])
 
 ;
-; store multiple pattern(s). 
+; store multiple pattern(s).
 ;
 
 (define_expand "store_multiple"
@@ -1641,7 +1675,6 @@
 			  (match_operand 1 "" ""))
 		     (use (match_operand 2 "" ""))])]
   ""
-  "
 {
   int regno;
   int count;
@@ -1683,7 +1716,7 @@
       if (to == frame_pointer_rtx || to == arg_pointer_rtx)
 	FAIL;
     }
-  else	
+  else
     {
       to = force_reg (Pmode, XEXP (operands[0], 0));
       off = 0;
@@ -1696,19 +1729,18 @@
 				     plus_constant (to,
 						    off + i * UNITS_PER_WORD)),
 		     gen_rtx_REG (Pmode, regno + i));
-}")
+})
 
 (define_insn "*store_multiple_di"
   [(match_parallel 0 "store_multiple_operation"
 		   [(set (match_operand:DI 1 "s_operand" "=QS")
 			 (match_operand:DI 2 "register_operand" "r"))])]
   ""
-  "*
 {
   int words = XVECLEN (operands[0], 0);
   operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
-  return \"stmg\\t%2,%0,%1\";
-}"
+  return "stmg\t%2,%0,%1";
+}
    [(set_attr "op_type" "RSY")
     (set_attr "type"    "stm")])
 
@@ -1718,12 +1750,11 @@
 		   [(set (match_operand:SI 1 "s_operand" "=Q,S")
 			 (match_operand:SI 2 "register_operand" "r,r"))])]
   ""
-  "*
 {
   int words = XVECLEN (operands[0], 0);
   operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
-  return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\";
-}"
+  return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1";
+}
    [(set_attr "op_type" "RS,RSY")
     (set_attr "type"    "stm")])
 
@@ -1760,22 +1791,21 @@
    (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
    (clobber (match_scratch:DI 3 "=X,&a"))]
   "TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"mvc\\t%O0(%b2+1,%R0),%1\";
+	return "mvc\t%O0(%b2+1,%R0),%1";
 
       case 1:
-	output_asm_insn (\"bras\\t%3,.+10\", operands);
-	output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
-	return \"ex\\t%2,0(%3)\";
+	output_asm_insn ("bras\t%3,.+10", operands);
+	output_asm_insn ("mvc\t%O0(1,%R0),%1", operands);
+	return "ex\t%2,0(%3)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
@@ -1787,22 +1817,21 @@
    (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
    (clobber (match_scratch:SI 3 "=X,&a"))]
   "!TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"mvc\\t%O0(%b2+1,%R0),%1\";
+	return "mvc\t%O0(%b2+1,%R0),%1";
 
       case 1:
-	output_asm_insn (\"bras\\t%3,.+10\", operands);
-	output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands);
-	return \"ex\\t%2,0(%3)\";
+	output_asm_insn ("bras\t%3,.+10", operands);
+	output_asm_insn ("mvc\t%O0(1,%R0),%1", operands);
+	return "ex\t%2,0(%3)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
@@ -1823,7 +1852,7 @@
         (mem:BLK (subreg:DI (match_dup 3) 0)))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "mvcle\\t%0,%1,0\;jo\\t.-4"
+  "mvcle\t%0,%1,0\;jo\t.-4"
   [(set_attr "op_type" "NN")
    (set_attr "type"    "vs")
    (set_attr "length"  "8")])
@@ -1841,7 +1870,7 @@
         (mem:BLK (subreg:SI (match_dup 3) 0)))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
-  "mvcle\\t%0,%1,0\;jo\\t.-4"
+  "mvcle\t%0,%1,0\;jo\t.-4"
   [(set_attr "op_type" "NN")
    (set_attr "type"    "vs")
    (set_attr "length"  "8")])
@@ -1876,22 +1905,21 @@
    (clobber (match_scratch:DI 2 "=X,&a"))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"xc\\t%O0(%b1+1,%R0),%0\";
+	return "xc\t%O0(%b1+1,%R0),%0";
 
       case 1:
-	output_asm_insn (\"bras\\t%2,.+10\", operands);
-	output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
-	return \"ex\\t%1,0(%2)\";
+	output_asm_insn ("bras\t%2,.+10", operands);
+	output_asm_insn ("xc\t%O0(1,%R0),%0", operands);
+	return "ex\t%1,0(%2)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
@@ -1904,22 +1932,21 @@
    (clobber (match_scratch:SI 2 "=X,&a"))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"xc\\t%O0(%b1+1,%R0),%0\";
+	return "xc\t%O0(%b1+1,%R0),%0";
 
       case 1:
-	output_asm_insn (\"bras\\t%2,.+10\", operands);
-	output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands);
-	return \"ex\\t%1,0(%2)\";
+	output_asm_insn ("bras\t%2,.+10", operands);
+	output_asm_insn ("xc\t%O0(1,%R0),%0", operands);
+	return "ex\t%1,0(%2)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
@@ -1937,7 +1964,7 @@
    (use (match_operand:TI 1 "register_operand" "d"))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "mvcle\\t%0,%1,0\;jo\\t.-4"
+  "mvcle\t%0,%1,0\;jo\t.-4"
   [(set_attr "op_type" "NN")
    (set_attr "type"    "vs")
    (set_attr "length"  "8")])
@@ -1952,89 +1979,87 @@
    (use (match_operand:DI 1 "register_operand" "d"))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
-  "mvcle\\t%0,%1,0\;jo\\t.-4"
+  "mvcle\t%0,%1,0\;jo\t.-4"
   [(set_attr "op_type" "NN")
    (set_attr "type"    "vs")
    (set_attr "length"  "8")])
 
 ;
-; cmpstrM instruction pattern(s).
+; cmpmemM instruction pattern(s).
 ;
 
-(define_expand "cmpstrdi"
+(define_expand "cmpmemdi"
   [(set (match_operand:DI 0 "register_operand" "")
         (compare:DI (match_operand:BLK 1 "memory_operand" "")
                     (match_operand:BLK 2 "memory_operand" "") ) )
    (use (match_operand:DI 3 "general_operand" ""))
    (use (match_operand:DI 4 "" ""))]
   "TARGET_64BIT"
-  "s390_expand_cmpstr (operands[0], operands[1], 
+  "s390_expand_cmpmem (operands[0], operands[1],
                        operands[2], operands[3]); DONE;")
 
-(define_expand "cmpstrsi"
+(define_expand "cmpmemsi"
   [(set (match_operand:SI 0 "register_operand" "")
         (compare:SI (match_operand:BLK 1 "memory_operand" "")
                     (match_operand:BLK 2 "memory_operand" "") ) )
    (use (match_operand:SI 3 "general_operand" ""))
    (use (match_operand:SI 4 "" ""))]
   ""
-  "s390_expand_cmpstr (operands[0], operands[1], 
+  "s390_expand_cmpmem (operands[0], operands[1],
                        operands[2], operands[3]); DONE;")
 
 ; Compare a block that is up to 256 bytes in length.
 ; The block length is taken as (operands[2] % 256) + 1.
 
-(define_insn "cmpstr_short_64"
+(define_insn "cmpmem_short_64"
   [(set (reg:CCS 33)
         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
                      (match_operand:BLK 1 "memory_operand" "Q,Q")))
    (use (match_operand:DI 2 "nonmemory_operand" "n,a"))
    (clobber (match_scratch:DI 3 "=X,&a"))]
   "TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"clc\\t%O0(%b2+1,%R0),%1\";
+	return "clc\t%O0(%b2+1,%R0),%1";
 
       case 1:
-	output_asm_insn (\"bras\\t%3,.+10\", operands);
-	output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
-	return \"ex\\t%2,0(%3)\";
+	output_asm_insn ("bras\t%3,.+10", operands);
+	output_asm_insn ("clc\t%O0(1,%R0),%1", operands);
+	return "ex\t%2,0(%3)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
    (set_attr "length"  "*,14")])
 
-(define_insn "cmpstr_short_31"
+(define_insn "cmpmem_short_31"
   [(set (reg:CCS 33)
         (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q")
                      (match_operand:BLK 1 "memory_operand" "Q,Q")))
    (use (match_operand:SI 2 "nonmemory_operand" "n,a"))
    (clobber (match_scratch:SI 3 "=X,&a"))]
   "!TARGET_64BIT"
-  "*
 {
   switch (which_alternative)
     {
       case 0:
-	return \"clc\\t%O0(%b2+1,%R0),%1\";
+	return "clc\t%O0(%b2+1,%R0),%1";
 
       case 1:
-	output_asm_insn (\"bras\\t%3,.+10\", operands);
-	output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands);
-	return \"ex\\t%2,0(%3)\";
+	output_asm_insn ("bras\t%3,.+10", operands);
+	output_asm_insn ("clc\t%O0(1,%R0),%1", operands);
+	return "ex\t%2,0(%3)";
 
       default:
         abort ();
     }
-}"
+}
   [(set_attr "op_type" "SS,NN")
    (set_attr "type"    "cs,cs")
    (set_attr "atype"   "*,agen")
@@ -2042,7 +2067,7 @@
 
 ; Compare a block of arbitrary length.
 
-(define_insn "cmpstr_long_64"
+(define_insn "cmpmem_long_64"
   [(clobber (match_operand:TI 0 "register_operand" "=d"))
    (clobber (match_operand:TI 1 "register_operand" "=d"))
    (set (reg:CCS 33)
@@ -2051,11 +2076,11 @@
    (use (match_dup 2))
    (use (match_dup 3))]
   "TARGET_64BIT"
-  "clcl\\t%0,%1"
+  "clcl\t%0,%1"
   [(set_attr "op_type" "RR")
    (set_attr "type"    "vs")])
 
-(define_insn "cmpstr_long_31"
+(define_insn "cmpmem_long_31"
   [(clobber (match_operand:DI 0 "register_operand" "=d"))
    (clobber (match_operand:DI 1 "register_operand" "=d"))
    (set (reg:CCS 33)
@@ -2064,7 +2089,7 @@
    (use (match_dup 2))
    (use (match_dup 3))]
   "!TARGET_64BIT"
-  "clcl\\t%0,%1"
+  "clcl\t%0,%1"
   [(set_attr "op_type" "RR")
    (set_attr "type"    "vs")])
 
@@ -2074,14 +2099,13 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
         (compare:SI (reg:CCS 33) (const_int 0)))]
   ""
-  "*
 {
-   output_asm_insn (\"lhi\\t%0,1\", operands);
-   output_asm_insn (\"jh\\t.+12\", operands);
-   output_asm_insn (\"jl\\t.+6\", operands);
-   output_asm_insn (\"sr\\t%0,%0\", operands);
-   return \"lcr\\t%0,%0\";
-}"
+   output_asm_insn ("lhi\t%0,1", operands);
+   output_asm_insn ("jh\t.+12", operands);
+   output_asm_insn ("jl\t.+6", operands);
+   output_asm_insn ("sr\t%0,%0", operands);
+   return "lcr\t%0,%0";
+}
   [(set_attr "op_type" "NN")
    (set_attr "length"  "16")
    (set_attr "type"    "other")])
@@ -2090,14 +2114,13 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
         (compare:DI (reg:CCS 33) (const_int 0)))]
   "TARGET_64BIT"
-  "*
 {
-   output_asm_insn (\"lghi\\t%0,1\", operands);
-   output_asm_insn (\"jh\\t.+12\", operands);
-   output_asm_insn (\"jl\\t.+6\", operands);
-   output_asm_insn (\"sgr\\t%0,%0\", operands);
-   return \"lcgr\\t%0,%0\";
-}"
+   output_asm_insn ("lghi\t%0,1", operands);
+   output_asm_insn ("jh\t.+12", operands);
+   output_asm_insn ("jl\t.+6", operands);
+   output_asm_insn ("sgr\t%0,%0", operands);
+   return "lcgr\t%0,%0";
+}
   [(set_attr "op_type" "NN")
    (set_attr "length"  "22")
    (set_attr "type"    "other")])
@@ -2109,40 +2132,40 @@
 
 (define_insn "*sethighqisi"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
+        (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
    (clobber (reg:CC 33))]
   ""
   "@
-   icm\\t%0,8,%1
-   icmy\\t%0,8,%1"
+   icm\t%0,8,%1
+   icmy\t%0,8,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*sethighhisi"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10))
+        (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
    (clobber (reg:CC 33))]
   ""
   "@
-   icm\\t%0,12,%1
-   icmy\\t%0,12,%1"
+   icm\t%0,12,%1
+   icmy\t%0,12,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn "*sethighqidi_64"
   [(set (match_operand:DI 0 "register_operand" "=d")
-        (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10))
+        (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "icmh\\t%0,8,%1"
+  "icmh\t%0,8,%1"
   [(set_attr "op_type" "RSY")])
 
 (define_insn "*sethighqidi_31"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10))
+        (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
   "@
-   icm\\t%0,8,%1
-   icmy\\t%0,8,%1"
+   icm\t%0,8,%1
+   icmy\t%0,8,%1"
   [(set_attr "op_type" "RS,RSY")])
 
 (define_insn_and_split "*extractqi"
@@ -2156,14 +2179,13 @@
   "#"
   "&& reload_completed"
   [(parallel
-    [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
+    [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
      (clobber (reg:CC 33))])
     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-  "
 {
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
   operands[1] = change_address (operands[1], QImode, 0);
-}"
+}
   [(set_attr "atype"   "agen")])
 
 (define_insn_and_split "*extracthi"
@@ -2177,14 +2199,13 @@
   "#"
   "&& reload_completed"
   [(parallel
-    [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
+    [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
      (clobber (reg:CC 33))])
     (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
-  "
 {
   operands[2] = GEN_INT (32 - INTVAL (operands[2]));
   operands[1] = change_address (operands[1], HImode, 0);
-}"
+}
   [(set_attr "atype"   "agen")])
 
 ;
@@ -2213,8 +2234,8 @@
         (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
   "TARGET_64BIT"
   "@
-   lgfr\\t%0,%1
-   lgf\\t%0,%1"
+   lgfr\t%0,%1
+   lgf\t%0,%1"
   [(set_attr "op_type" "RRE,RXY")])
 
 ;
@@ -2238,7 +2259,7 @@
     {
       operands[1] = gen_lowpart (DImode, operands[1]);
       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
-      emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); 
+      emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
       DONE;
     }
 }
@@ -2248,7 +2269,7 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
         (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_64BIT"
-  "lgh\\t%0,%1"
+  "lgh\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 ;
@@ -2272,7 +2293,7 @@
     {
       operands[1] = gen_lowpart (DImode, operands[1]);
       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
-      emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); 
+      emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
       DONE;
     }
 }
@@ -2282,7 +2303,7 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
         (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
   "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
-  "lgb\\t%0,%1"
+  "lgb\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 (define_split
@@ -2290,7 +2311,7 @@
         (sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
   "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
   [(parallel
-    [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10))
+    [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
      (clobber (reg:CC 33))])
    (parallel
     [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
@@ -2309,7 +2330,7 @@
 {
   operands[1] = gen_lowpart (SImode, operands[1]);
   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
-  emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); 
+  emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
   DONE;
 }
 ")
@@ -2319,8 +2340,8 @@
         (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
   ""
   "@
-   lh\\t%0,%1
-   lhy\\t%0,%1"
+   lh\t%0,%1
+   lhy\t%0,%1"
   [(set_attr "op_type" "RX,RXY")])
 
 ;
@@ -2335,7 +2356,7 @@
 {
   operands[1] = gen_lowpart (SImode, operands[1]);
   emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
-  emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); 
+  emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
   DONE;
 }
 ")
@@ -2343,16 +2364,16 @@
 (define_insn "*extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
-  "lb\\t%0,%1"
+  "TARGET_LONG_DISPLACEMENT"
+  "lb\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
         (sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
-  "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed"
+  "!TARGET_LONG_DISPLACEMENT && !reload_completed"
   [(parallel
-    [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10))
+    [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
      (clobber (reg:CC 33))])
    (parallel
     [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
@@ -2389,8 +2410,8 @@
         (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
   "TARGET_64BIT"
   "@
-   llgfr\\t%0,%1
-   llgf\\t%0,%1"
+   llgfr\t%0,%1
+   llgf\t%0,%1"
   [(set_attr "op_type" "RRE,RXY")])
 
 ;
@@ -2414,7 +2435,7 @@
     {
       operands[1] = gen_lowpart (DImode, operands[1]);
       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
-      emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); 
+      emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
       DONE;
     }
 }
@@ -2424,10 +2445,81 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
         (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_64BIT"
-  "llgh\\t%0,%1"
+  "llgh\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 ;
+; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
+;
+
+(define_insn "*llgt_sisi"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+		(const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_sisi_split"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+		(const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:SI (match_dup 1)
+		(const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_didi"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%N1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_didi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (match_dup 1)
+                (const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_sidi"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+		(const_int 2147483647)))]
+  "TARGET_64BIT"
+  "llgt\t%0,%1"
+  [(set_attr "op_type"  "RXE")])
+
+(define_insn_and_split "*llgt_sidi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) 
+		(const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (subreg:DI (match_dup 1) 0) 
+		(const_int 2147483647)))]
+  "")
+
+;
 ; zero_extendqidi2 instruction pattern(s)
 ;
 
@@ -2448,7 +2540,7 @@
     {
       operands[1] = gen_lowpart (DImode, operands[1]);
       emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
-      emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); 
+      emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
       DONE;
     }
 }
@@ -2458,7 +2550,7 @@
   [(set (match_operand:DI 0 "register_operand" "=d")
         (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
   "TARGET_64BIT"
-  "llgc\\t%0,%1"
+  "llgc\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 ;
@@ -2481,12 +2573,12 @@
   [(set (match_operand:SI 0 "register_operand" "=d")
         (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_64BIT"
-  "llgh\\t%0,%1"
+  "llgh\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 (define_insn_and_split "*zero_extendhisi2_31"
   [(set (match_operand:SI 0 "register_operand" "=&d")
-        (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
+        (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
   "#"
@@ -2497,7 +2589,7 @@
      (clobber (reg:CC 33))])]
   "operands[2] = gen_lowpart (HImode, operands[0]);"
   [(set_attr "atype" "agen")])
- 
+
 ;
 ; zero_extendqisi2 instruction pattern(s).
 ;
@@ -2517,21 +2609,21 @@
 (define_insn "*zero_extendqisi2_64"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_64BIT"
-  "llgc\\t%0,%1"
+  "TARGET_ZARCH"
+  "llgc\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 (define_insn_and_split "*zero_extendqisi2_31"
   [(set (match_operand:SI 0 "register_operand" "=&d")
         (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
-  "!TARGET_64BIT"
+  "!TARGET_ZARCH"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (const_int 0))
    (set (strict_low_part (match_dup 2)) (match_dup 1))]
   "operands[2] = gen_lowpart (QImode, operands[0]);"
   [(set_attr "atype" "agen")])
- 
+
 ;
 ; zero_extendqihi2 instruction pattern(s).
 ;
@@ -2539,7 +2631,7 @@
 (define_expand "zero_extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "")
         (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
-  "TARGET_64BIT"
+  "TARGET_ZARCH"
   "
 {
   operands[1] = gen_lowpart (HImode, operands[1]);
@@ -2551,14 +2643,14 @@
 (define_insn "*zero_extendqihi2_64"
   [(set (match_operand:HI 0 "register_operand" "=d")
         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  "TARGET_64BIT"
-  "llgc\\t%0,%1"
+  "TARGET_ZARCH"
+  "llgc\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
 (define_insn_and_split "*zero_extendqihi2_31"
   [(set (match_operand:HI 0 "register_operand" "=&d")
         (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
-  "!TARGET_64BIT"
+  "!TARGET_ZARCH"
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (const_int 0))
@@ -2575,20 +2667,19 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
   rtx temp = gen_reg_rtx (DFmode);
   operands[1] = force_reg (DFmode, operands[1]);
 
-  emit_insn (gen_cmpdf (operands[1], 
+  emit_insn (gen_cmpdf (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode)));
+          REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
   emit_jump_insn (gen_blt (label1));
   emit_insn (gen_subdf3 (temp, operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode)));
+          REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
   emit_jump (label2);
 
@@ -2596,26 +2687,25 @@
   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
   emit_label (label2);
   DONE;
-}")
+})
 
 (define_expand "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "")
         (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   operands[1] = force_reg (DFmode, operands[1]);
   emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
   DONE;
-}")
+})
 
 (define_insn "fix_truncdfdi2_ieee"
   [(set (match_operand:DI 0 "register_operand" "=d")
         (fix:DI (match_operand:DF 1 "register_operand" "f")))
-   (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
+   (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC 33))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cgdbr\\t%0,%h2,%1"
+  "cgdbr\t%0,%h2,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "ftoi")])
 
@@ -2627,20 +2717,19 @@
   [(set (match_operand:SI 0 "register_operand" "")
         (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
   rtx temp = gen_reg_rtx (DFmode);
 
   operands[1] = force_reg (DFmode,operands[1]);
-  emit_insn (gen_cmpdf (operands[1], 
+  emit_insn (gen_cmpdf (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode)));
+          REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
   emit_jump_insn (gen_blt (label1));
   emit_insn (gen_subdf3 (temp, operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode)));
+          REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
   emit_jump (label2);
 
@@ -2648,15 +2737,14 @@
   emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
   emit_label (label2);
   DONE;
-}")
+})
 
 (define_expand "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "")
         (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
-  if (TARGET_IBM_FLOAT) 
+  if (TARGET_IBM_FLOAT)
     {
       /* This is the algorithm from POP chapter A.5.7.2.  */
 
@@ -2665,25 +2753,25 @@
       rtx two32  = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
 
       operands[1] = force_reg (DFmode, operands[1]);
-      emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], 
+      emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
 					 two31r, two32, temp));
-    } 
-  else 
+    }
+  else
     {
       operands[1] = force_reg (DFmode, operands[1]);
       emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
     }
 
   DONE;
-}")
+})
 
 (define_insn "fix_truncdfsi2_ieee"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (fix:SI (match_operand:DF 1 "register_operand" "f")))
-    (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
+    (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
     (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cfdbr\\t%0,%h2,%1"
+  "cfdbr\t%0,%h2,%1"
    [(set_attr "op_type" "RRE")
     (set_attr "type"    "other" )])
 
@@ -2695,14 +2783,13 @@
    (use (match_operand:BLK 4 "memory_operand" "m"))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "*
 {
-   output_asm_insn (\"sd\\t%1,%2\", operands);
-   output_asm_insn (\"aw\\t%1,%3\", operands);
-   output_asm_insn (\"std\\t%1,%4\", operands);
-   output_asm_insn (\"xi\\t%N4,128\", operands);
-   return \"l\\t%0,%N4\";
-}"
+   output_asm_insn ("sd\t%1,%2", operands);
+   output_asm_insn ("aw\t%1,%3", operands);
+   output_asm_insn ("std\t%1,%4", operands);
+   output_asm_insn ("xi\t%N4,128", operands);
+   return "l\t%0,%N4";
+}
   [(set_attr "op_type" "NN")
    (set_attr "type"    "ftoi")
    (set_attr "atype"   "agen")
@@ -2716,21 +2803,20 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
   rtx temp = gen_reg_rtx (SFmode);
 
   operands[1] = force_reg (SFmode, operands[1]);
-  emit_insn (gen_cmpsf (operands[1], 
+  emit_insn (gen_cmpsf (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode)));
+          REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
   emit_jump_insn (gen_blt (label1));
 
   emit_insn (gen_subsf3 (temp, operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode)));
+          REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
   emit_jump (label2);
 
@@ -2738,26 +2824,25 @@
   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
   emit_label (label2);
   DONE;
-}")
+})
 
 (define_expand "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "")
         (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   operands[1] = force_reg (SFmode, operands[1]);
   emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
   DONE;
-}")
+})
 
 (define_insn "fix_truncsfdi2_ieee"
   [(set (match_operand:DI 0 "register_operand" "=d")
         (fix:DI (match_operand:SF 1 "register_operand"  "f")))
-   (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
+   (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
    (clobber (reg:CC 33))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cgebr\\t%0,%h2,%1"
+  "cgebr\t%0,%h2,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "ftoi")])
 
@@ -2769,7 +2854,6 @@
   [(set (match_operand:SI 0 "register_operand" "")
         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "
 {
   rtx label1 = gen_label_rtx ();
   rtx label2 = gen_label_rtx ();
@@ -2778,11 +2862,11 @@
   operands[1] = force_reg (SFmode, operands[1]);
   emit_insn (gen_cmpsf (operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode)));
+          REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
   emit_jump_insn (gen_blt (label1));
   emit_insn (gen_subsf3 (temp, operands[1],
 	CONST_DOUBLE_FROM_REAL_VALUE (
-          REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode)));
+          REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
   emit_jump (label2);
 
@@ -2790,13 +2874,12 @@
   emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
   emit_label (label2);
   DONE;
-}")
+})
 
 (define_expand "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "")
         (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   if (TARGET_IBM_FLOAT)
     {
@@ -2812,15 +2895,15 @@
     }
 
   DONE;
-}")
+})
 
 (define_insn "fix_truncsfsi2_ieee"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (fix:SI (match_operand:SF 1 "register_operand" "f")))
-    (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
+    (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
     (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cfebr\\t%0,%h2,%1"
+  "cfebr\t%0,%h2,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "ftoi")])
 
@@ -2833,7 +2916,7 @@
         (float:DF (match_operand:DI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cdgbr\\t%0,%1"
+  "cdgbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "itof" )])
 
@@ -2846,7 +2929,7 @@
         (float:SF (match_operand:DI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cegbr\\t%0,%1"
+  "cegbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "itof" )])
 
@@ -2860,26 +2943,25 @@
           (float:DF (match_operand:SI 1 "register_operand" "")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
-  "
 {
-  if (TARGET_IBM_FLOAT) 
+  if (TARGET_IBM_FLOAT)
     {
       /* This is the algorithm from POP chapter A.5.7.1.  */
 
       rtx temp  = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
-      rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);	   
+      rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
 
       emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
       DONE;
     }
-}")
+})
 
 (define_insn "floatsidf2_ieee"
   [(set (match_operand:DF 0 "register_operand" "=f")
         (float:DF (match_operand:SI 1 "register_operand"  "d")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cdfbr\\t%0,%1"
+  "cdfbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"   "itof" )])
 
@@ -2890,14 +2972,13 @@
    (use (match_operand:BLK 3 "memory_operand" "m"))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "*
 {
-   output_asm_insn (\"st\\t%1,%N3\", operands);
-   output_asm_insn (\"xi\\t%N3,128\", operands);
-   output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
-   output_asm_insn (\"ld\\t%0,%3\", operands);
-   return \"sd\\t%0,%2\";
-}"
+   output_asm_insn ("st\t%1,%N3", operands);
+   output_asm_insn ("xi\t%N3,128", operands);
+   output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
+   output_asm_insn ("ld\t%0,%3", operands);
+   return "sd\t%0,%2";
+}
   [(set_attr "op_type" "NN")
    (set_attr "type"    "other" )
    (set_attr "atype"   "agen")
@@ -2913,7 +2994,6 @@
           (float:SF (match_operand:SI 1 "register_operand" "")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
-  "
 {
   if (TARGET_IBM_FLOAT)
     {
@@ -2923,14 +3003,14 @@
       emit_insn (gen_truncdfsf2 (operands[0], temp));
       DONE;
     }
-}")
+})
 
 (define_insn "floatsisf2_ieee"
   [(set (match_operand:SF 0 "register_operand" "=f")
         (float:SF (match_operand:SI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "cefbr\\t%0,%1"
+  "cefbr\t%0,%1"
   [(set_attr "op_type" "RRE")
    (set_attr "type"    "itof" )])
 
@@ -2948,7 +3028,7 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
         (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "ledbr\\t%0,%1"
+  "ledbr\t%0,%1"
   [(set_attr "op_type"  "RRE")])
 
 (define_insn "truncdfsf2_ibm"
@@ -2956,8 +3036,8 @@
         (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   lrer\\t%0,%1
-   le\\t%0,%1"
+   lrer\t%0,%1
+   le\t%0,%1"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"   "floads,floads")])
 
@@ -2969,22 +3049,21 @@
   [(set (match_operand:DF 0 "register_operand" "")
         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   if (TARGET_IBM_FLOAT)
     {
       emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
       DONE;
     }
-}")
+})
 
 (define_insn "extendsfdf2_ieee"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
         (float_extend:DF (match_operand:SF 1 "nonimmediate_operand"  "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   ldebr\\t%0,%1
-   ldeb\\t%0,%1"
+   ldebr\t%0,%1
+   ldeb\t%0,%1"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"   "floads,floads")])
 
@@ -2994,12 +3073,12 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   sdr\\t%0,%0\;ler\\t%0,%1
-   sdr\\t%0,%0\;le\\t%0,%1"
+   sdr\t%0,%0\;ler\t%0,%1
+   sdr\t%0,%0\;le\t%0,%1"
   [(set_attr "op_type"  "NN,NN")
    (set_attr "atype"    "reg,agen")
    (set_attr "length"   "4,6")
-   (set_attr "type"     "o2,o2")]) 
+   (set_attr "type"     "o2,o2")])
 
 
 ;;
@@ -3024,12 +3103,12 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   agfr\\t%0,%2
-   agf\\t%0,%2"
+   agfr\t%0,%2
+   agf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_zero_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
                           (match_operand:DI 1 "register_operand" "0,0"))
                  (const_int 0)))
@@ -3037,20 +3116,20 @@
         (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   algfr\\t%0,%2
-   algf\\t%0,%2"
+   algfr\t%0,%2
+   algf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_zero_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
                           (match_operand:DI 1 "register_operand" "0,0"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   algfr\\t%0,%2
-   algf\\t%0,%2"
+   algfr\t%0,%2
+   algf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_zero"
@@ -3060,25 +3139,25 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   algfr\\t%0,%2
-   algf\\t%0,%2"
+   algfr\t%0,%2
+   algf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_imm_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
                           (match_operand:DI 2 "const_int_operand" "K"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d")
         (plus:DI (match_dup 1) (match_dup 2)))]
-  "TARGET_64BIT	 
-   && s390_match_ccmode (insn, CCAmode) 
+  "TARGET_64BIT
+   && s390_match_ccmode (insn, CCAmode)
    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
-  "aghi\\t%0,%h2"
+  "aghi\t%0,%h2"
   [(set_attr "op_type"  "RI")])
 
 (define_insn "*adddi3_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
@@ -3086,31 +3165,31 @@
         (plus:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   algr\\t%0,%2
-   alg\\t%0,%2"
+   algr\t%0,%2
+   alg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   algr\\t%0,%2
-   alg\\t%0,%2"
+   algr\t%0,%2
+   alg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_cconly2"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                  (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
   "@
-   algr\\t%0,%2
-   alg\\t%0,%2"
+   algr\t%0,%2
+   alg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*adddi3_64"
@@ -3120,9 +3199,9 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   agr\\t%0,%2
-   aghi\\t%0,%h2
-   ag\\t%0,%2"
+   agr\t%0,%2
+   aghi\t%0,%h2
+   ag\t%0,%2"
   [(set_attr "op_type"  "RRE,RI,RXY")])
 
 (define_insn_and_split "*adddi3_31"
@@ -3172,8 +3251,8 @@
         (match_operand:QI 1 "address_operand" "U,W"))]
   "TARGET_64BIT"
   "@
-   la\\t%0,%a1
-   lay\\t%0,%a1"
+   la\t%0,%a1
+   lay\t%0,%a1"
   [(set_attr "op_type" "RX,RXY")
    (set_attr "type"    "la")])
 
@@ -3208,19 +3287,18 @@
               (match_operand:DI 1 "s390_plus_operand" "")
               (match_operand:DI 2 "register_operand" "=&a")])]
   "TARGET_64BIT"
-  "
 {
   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
+
 
- 
 ;
 ; addsi3 instruction pattern(s).
 ;
 
 (define_insn "*addsi3_imm_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
                           (match_operand:SI 2 "const_int_operand" "K"))
                  (const_int 0)))
@@ -3228,100 +3306,100 @@
         (plus:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCAmode)
    && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
-  "ahi\\t%0,%h2"
+  "ahi\t%0,%h2"
   [(set_attr "op_type"  "RI")])
 
 (define_insn "*addsi3_carry1_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (match_dup 1)))
    (set (match_operand:SI 0 "register_operand" "=d,d,d")
         (plus:SI (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCL1mode)" 
+  "s390_match_ccmode (insn, CCL1mode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_carry1_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (match_dup 1)))
    (clobber (match_scratch:SI 0 "=d,d,d"))]
-  "s390_match_ccmode (insn, CCL1mode)" 
+  "s390_match_ccmode (insn, CCL1mode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_carry2_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (match_dup 2)))
    (set (match_operand:SI 0 "register_operand" "=d,d,d")
         (plus:SI (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCL1mode)" 
+  "s390_match_ccmode (insn, CCL1mode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_carry2_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (match_dup 2)))
    (clobber (match_scratch:SI 0 "=d,d,d"))]
-  "s390_match_ccmode (insn, CCL1mode)" 
+  "s390_match_ccmode (insn, CCL1mode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=d,d,d")
         (plus:SI (match_dup 1) (match_dup 2)))]
-  "s390_match_ccmode (insn, CCLmode)" 
+  "s390_match_ccmode (insn, CCLmode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                           (match_operand:SI 2 "general_operand" "d,R,T"))
                  (const_int 0)))
    (clobber (match_scratch:SI 0 "=d,d,d"))]
-  "s390_match_ccmode (insn, CCLmode)" 
+  "s390_match_ccmode (insn, CCLmode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_cconly2"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                  (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCLmode)"
   "@
-   alr\\t%0,%2
-   al\\t%0,%2
-   aly\\t%0,%2"
+   alr\t%0,%2
+   al\t%0,%2
+   aly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*addsi3_sign"
@@ -3331,8 +3409,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   ah\\t%0,%2
-   ahy\\t%0,%2"
+   ah\t%0,%2
+   ahy\t%0,%2"
   [(set_attr "op_type"  "RX,RXY")])
 
 (define_insn "*addsi3_sub"
@@ -3342,8 +3420,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   ah\\t%0,%2
-   ahy\\t%0,%2"
+   ah\t%0,%2
+   ahy\t%0,%2"
   [(set_attr "op_type"  "RX,RXY")])
 
 (define_insn "addsi3"
@@ -3353,10 +3431,10 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   ar\\t%0,%2
-   ahi\\t%0,%h2
-   a\\t%0,%2
-   ay\\t%0,%2"
+   ar\t%0,%2
+   ahi\t%0,%h2
+   a\t%0,%2
+   ay\t%0,%2"
   [(set_attr "op_type"  "RR,RI,RX,RXY")])
 
 (define_insn "*la_31"
@@ -3364,8 +3442,8 @@
         (match_operand:QI 1 "address_operand" "U,W"))]
   "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
   "@
-   la\\t%0,%a1
-   lay\\t%0,%a1"
+   la\t%0,%a1
+   lay\t%0,%a1"
   [(set_attr "op_type"  "RX,RXY")
    (set_attr "type"     "la")])
 
@@ -3401,8 +3479,8 @@
                 (const_int 2147483647)))]
   "!TARGET_64BIT"
   "@
-   la\\t%0,%a1
-   lay\\t%0,%a1"
+   la\t%0,%a1
+   lay\t%0,%a1"
   [(set_attr "op_type"  "RX,RXY")
    (set_attr "type"     "la")])
 
@@ -3414,7 +3492,7 @@
   "!TARGET_64BIT"
   "#"
   "&& reload_completed"
-  [(set (match_dup 0) 
+  [(set (match_dup 0)
         (and:SI (match_dup 1) (const_int 2147483647)))]
   ""
   [(set_attr "op_type"  "RX")
@@ -3426,8 +3504,8 @@
    (use (const_int 0))]
   "!TARGET_64BIT"
   "@
-   la\\t%0,%a1
-   lay\\t%0,%a1"
+   la\t%0,%a1
+   lay\t%0,%a1"
   [(set_attr "op_type"  "RX")
    (set_attr "type"     "la")])
 
@@ -3436,11 +3514,10 @@
               (match_operand:SI 1 "s390_plus_operand" "")
               (match_operand:SI 2 "register_operand" "=&a")])]
   "!TARGET_64BIT"
-  "
 {
   s390_expand_plus_operand (operands[0], operands[1], operands[2]);
   DONE;
-}")
+})
 
 
 ;
@@ -3463,8 +3540,35 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   adbr\\t%0,%2
-   adb\\t%0,%2"
+   adbr\t%0,%2
+   adb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimpd,fsimpd")])
+
+(define_insn "*adddf3_cc"
+  [(set (reg 33)
+	(compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+			  (match_operand:DF 2 "general_operand" "f,R"))
+		 (match_operand:DF 3 "const0_operand" "")))
+   (set (match_operand:DF 0 "register_operand" "=f,f")
+	(plus:DF (match_dup 1) (match_dup 2)))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   adbr\t%0,%2
+   adb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimpd,fsimpd")])
+
+(define_insn "*adddf3_cconly"
+  [(set (reg 33)
+	(compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+			  (match_operand:DF 2 "general_operand" "f,R"))
+		 (match_operand:DF 3 "const0_operand" "")))
+   (clobber (match_scratch:DF 0 "=f,f"))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+  adbr\t%0,%2
+  adb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fsimpd,fsimpd")])
 
@@ -3475,8 +3579,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   adr\\t%0,%2
-   ad\\t%0,%2"
+   adr\t%0,%2
+   ad\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fsimpd,fsimpd")])
 
@@ -3500,8 +3604,35 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   aebr\\t%0,%2
-   aeb\\t%0,%2"
+   aebr\t%0,%2
+   aeb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimps,fsimps")])
+
+(define_insn "*addsf3_cc"
+  [(set (reg 33)
+	(compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+			  (match_operand:SF 2 "general_operand" "f,R"))
+		 (match_operand:SF 3 "const0_operand" "")))
+   (set (match_operand:SF 0 "register_operand" "=f,f")
+	(plus:SF (match_dup 1) (match_dup 2)))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   aebr\t%0,%2
+   aeb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimps,fsimps")])
+
+(define_insn "*addsf3_cconly"
+  [(set (reg 33)
+	(compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+			  (match_operand:SF 2 "general_operand" "f,R"))
+		 (match_operand:SF 3 "const0_operand" "")))
+   (clobber (match_scratch:SF 0 "=f,f"))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   aebr\t%0,%2
+   aeb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fsimps,fsimps")])
 
@@ -3512,8 +3643,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   aer\\t%0,%2
-   ae\\t%0,%2"
+   aer\t%0,%2
+   ae\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fsimps,fsimps")])
 
@@ -3533,12 +3664,12 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   sgfr\\t%0,%2
-   sgf\\t%0,%2"
+   sgfr\t%0,%2
+   sgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_zero_cc"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
                  (const_int 0)))
@@ -3546,20 +3677,20 @@
         (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   slgfr\\t%0,%2
-   slgf\\t%0,%2"
+   slgfr\t%0,%2
+   slgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_zero_cconly"
-  [(set (reg 33) 
+  [(set (reg 33)
         (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
                            (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
   "@
-   slgfr\\t%0,%2
-   slgf\\t%0,%2"
+   slgfr\t%0,%2
+   slgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_zero"
@@ -3569,8 +3700,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   slgfr\\t%0,%2
-   slgf\\t%0,%2"
+   slgfr\t%0,%2
+   slgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_cc"
@@ -3582,8 +3713,8 @@
         (minus:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode (insn, CCLmode)"
   "@
-   slgr\\t%0,%2
-   slg\\t%0,%2"
+   slgr\t%0,%2
+   slg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_cconly"
@@ -3594,8 +3725,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode (insn, CCLmode)"
   "@
-   slgr\\t%0,%2
-   slg\\t%0,%2"
+   slgr\t%0,%2
+   slg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*subdi3_64"
@@ -3605,8 +3736,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   sgr\\t%0,%2
-   sg\\t%0,%2"
+   sgr\t%0,%2
+   sg\t%0,%2"
   [(set_attr "op_type"  "RRE,RRE")])
 
 (define_insn_and_split "*subdi3_31"
@@ -3664,9 +3795,9 @@
         (minus:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCL2mode)"
   "@
-   slr\\t%0,%2
-   sl\\t%0,%2
-   sly\\t%0,%2"
+   slr\t%0,%2
+   sl\t%0,%2
+   sly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*subsi3_borrow_cconly"
@@ -3677,9 +3808,9 @@
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCL2mode)"
   "@
-   slr\\t%0,%2
-   sl\\t%0,%2
-   sly\\t%0,%2"
+   slr\t%0,%2
+   sl\t%0,%2
+   sly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXE")])
 
 (define_insn "*subsi3_cc"
@@ -3691,9 +3822,9 @@
         (minus:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCLmode)"
   "@
-   slr\\t%0,%2
-   sl\\t%0,%2
-   sly\\t%0,%2"
+   slr\t%0,%2
+   sl\t%0,%2
+   sly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*subsi3_cconly"
@@ -3704,9 +3835,9 @@
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCLmode)"
   "@
-   slr\\t%0,%2
-   sl\\t%0,%2
-   sly\\t%0,%2"
+   slr\t%0,%2
+   sl\t%0,%2
+   sly\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*subsi3_sign"
@@ -3716,8 +3847,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   sh\\t%0,%2
-   shy\\t%0,%2"
+   sh\t%0,%2
+   shy\t%0,%2"
   [(set_attr "op_type"  "RX,RXY")])
 
 (define_insn "*subsi3_sub"
@@ -3727,8 +3858,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   sh\\t%0,%2
-   shy\\t%0,%2"
+   sh\t%0,%2
+   shy\t%0,%2"
   [(set_attr "op_type"  "RX,RXY")])
 
 (define_insn "subsi3"
@@ -3738,9 +3869,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   sr\\t%0,%2
-   s\\t%0,%2
-   sy\\t%0,%2"
+   sr\t%0,%2
+   s\t%0,%2
+   sy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 
@@ -3764,8 +3895,35 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sdbr\\t%0,%2
-   sdb\\t%0,%2"
+   sdbr\t%0,%2
+   sdb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimpd,fsimpd")])
+
+(define_insn "*subdf3_cc"
+  [(set (reg 33)
+	(compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+			   (match_operand:DF 2 "general_operand" "f,R"))
+		 (match_operand:DF 3 "const0_operand" "")))
+   (set (match_operand:DF 0 "register_operand" "=f,f")
+	(plus:DF (match_dup 1) (match_dup 2)))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   sdbr\t%0,%2
+   sdb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimpd,fsimpd")])
+
+(define_insn "*subdf3_cconly"
+  [(set (reg 33)
+	(compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
+			   (match_operand:DF 2 "general_operand" "f,R"))
+		 (match_operand:DF 3 "const0_operand" "")))
+   (clobber (match_scratch:DF 0 "=f,f"))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   sdbr\t%0,%2
+   sdb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fsimpd,fsimpd")])
 
@@ -3776,8 +3934,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   sdr\\t%0,%2
-   sd\\t%0,%2"
+   sdr\t%0,%2
+   sd\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fsimpd,fsimpd")])
 
@@ -3801,8 +3959,35 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sebr\\t%0,%2
-   seb\\t%0,%2"
+   sebr\t%0,%2
+   seb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimps,fsimps")])
+
+(define_insn "*subsf3_cc"
+  [(set (reg 33)
+	(compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+			   (match_operand:SF 2 "general_operand" "f,R"))
+		 (match_operand:SF 3 "const0_operand" "")))
+   (set (match_operand:SF 0 "register_operand" "=f,f")
+	(minus:SF (match_dup 1) (match_dup 2)))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   sebr\t%0,%2
+   seb\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type"     "fsimps,fsimps")])
+
+(define_insn "*subsf3_cconly"
+  [(set (reg 33)
+	(compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
+			   (match_operand:SF 2 "general_operand" "f,R"))
+		 (match_operand:SF 3 "const0_operand" "")))
+   (clobber (match_scratch:SF 0 "=f,f"))]
+  "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "@
+   sebr\t%0,%2
+   seb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fsimps,fsimps")])
 
@@ -3813,8 +3998,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   ser\\t%0,%2
-   se\\t%0,%2"
+   ser\t%0,%2
+   se\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fsimps,fsimps")])
 
@@ -3833,21 +4018,20 @@
                  (match_operand:DI 1 "register_operand" "0,0")))]
   "TARGET_64BIT"
   "@
-   msgfr\\t%0,%2
-   msgf\\t%0,%2"
+   msgfr\t%0,%2
+   msgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")
    (set_attr "type"     "imul")])
 
-
 (define_insn "muldi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
         (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
                  (match_operand:DI 2 "general_operand" "d,K,m")))]
   "TARGET_64BIT"
   "@
-   msgr\\t%0,%2
-   mghi\\t%0,%h2
-   msg\\t%0,%2"
+   msgr\t%0,%2
+   mghi\t%0,%h2
+   msg\t%0,%2"
   [(set_attr "op_type"  "RRE,RI,RXY")
    (set_attr "type"     "imul")])
 
@@ -3855,16 +4039,25 @@
 ; mulsi3 instruction pattern(s).
 ;
 
+(define_insn "*mulsi3_sign"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
+                 (match_operand:SI 1 "register_operand" "0")))]
+  ""
+  "mh\t%0,%2"
+  [(set_attr "op_type"  "RX")
+   (set_attr "type"     "imul")])
+
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
         (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
                   (match_operand:SI 2 "general_operand" "d,K,R,T")))]
   ""
   "@
-   msr\\t%0,%2
-   mhi\\t%0,%h2
-   ms\\t%0,%2
-   msy\\t%0,%2"
+   msr\t%0,%2
+   mhi\t%0,%h2
+   ms\t%0,%2
+   msy\t%0,%2"
   [(set_attr "op_type"  "RRE,RI,RX,RXY")
    (set_attr "type"     "imul")])
 
@@ -3872,40 +4065,36 @@
 ; mulsidi3 instruction pattern(s).
 ;
 
-(define_expand "mulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
-		 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
+(define_insn "mulsidi3"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (mult:DI (sign_extend:DI
+	           (match_operand:SI 1 "register_operand" "%0,0"))
+                 (sign_extend:DI
+	           (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
   "!TARGET_64BIT"
-  "
-{
-  rtx insn;
+  "@
+   mr\t%0,%2
+   m\t%0,%2"
+  [(set_attr "op_type"  "RR,RX")
+   (set_attr "type"     "imul")])
 
-  emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
-  insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2]));
+;
+; umulsidi3 instruction pattern(s).
+;
 
-  REG_NOTES (insn) =
-	gen_rtx_EXPR_LIST (REG_EQUAL, 
-                           gen_rtx_MULT (DImode, 
-				gen_rtx_SIGN_EXTEND (DImode, operands[1]),
-				gen_rtx_SIGN_EXTEND (DImode, operands[2])),
-			   REG_NOTES (insn));
-  DONE;
-}")
- 
-(define_insn "mulsi_6432"
-   [(set (match_operand:DI 0 "register_operand" "=d,d")
-         (mult:DI (sign_extend:DI 
-	            (truncate:SI (match_operand:DI 1 "register_operand" "0,0")))
-                  (sign_extend:DI
-	            (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
-   "!TARGET_64BIT"
-   "@
-    mr\\t%0,%2
-    m\\t%0,%2"
-  [(set_attr "op_type"  "RR,RX")
+(define_insn "umulsidi3"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (mult:DI (zero_extend:DI
+	           (match_operand:SI 1 "register_operand" "%0,0"))
+                 (zero_extend:DI
+	           (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
+  "!TARGET_64BIT && TARGET_CPU_ZARCH"
+  "@
+   mlr\t%0,%2
+   ml\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXY")
    (set_attr "type"     "imul")])
- 
+
 ;
 ; muldf3 instruction pattern(s).
 ;
@@ -3926,8 +4115,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   mdbr\\t%0,%2
-   mdb\\t%0,%2"
+   mdbr\t%0,%2
+   mdb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fmuld")])
 
@@ -3938,11 +4127,35 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   mdr\\t%0,%2
-   md\\t%0,%2"
+   mdr\t%0,%2
+   md\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"    "fmuld")])
 
+(define_insn "*fmadddf"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
+			  (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
+		 (match_operand:DF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   madbr\t%0,%1,%2
+   madb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuld")])
+
+(define_insn "*fmsubdf"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
+			   (match_operand:DF 2 "nonimmediate_operand"  "f,R"))
+		 (match_operand:DF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   msdbr\t%0,%1,%2
+   msdb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuld")])
+
 ;
 ; mulsf3 instruction pattern(s).
 ;
@@ -3963,8 +4176,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   meebr\\t%0,%2
-   meeb\\t%0,%2"
+   meebr\t%0,%2
+   meeb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fmuls")])
 
@@ -3975,11 +4188,34 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   mer\\t%0,%2
-   me\\t%0,%2"
+   mer\t%0,%2
+   me\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fmuls")])
 
+(define_insn "*fmaddsf"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
+			  (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
+		 (match_operand:SF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   maebr\t%0,%1,%2
+   maeb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuls")])
+
+(define_insn "*fmsubsf"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
+			   (match_operand:SF 2 "nonimmediate_operand"  "f,R"))
+		  (match_operand:SF 3 "register_operand" "0,0")))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations"
+  "@
+   msebr\t%0,%1,%2
+   mseb\t%0,%1,%2"
+  [(set_attr "op_type"  "RRE,RXE")
+   (set_attr "type" "fmuls")])
 
 ;;
 ;;- Divide and modulo instructions.
@@ -3991,31 +4227,20 @@
 
 (define_expand "divmoddi4"
   [(parallel [(set (match_operand:DI 0 "general_operand" "")
-		   (div:DI (match_operand:DI 1 "general_operand" "")
+		   (div:DI (match_operand:DI 1 "register_operand" "")
 			   (match_operand:DI 2 "general_operand" "")))
 	      (set (match_operand:DI 3 "general_operand" "")
 		   (mod:DI (match_dup 1) (match_dup 2)))])
    (clobber (match_dup 4))]
   "TARGET_64BIT"
-  "
 {
-  rtx insn, div_equal, mod_equal, equal;
+  rtx insn, div_equal, mod_equal;
 
   div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
   mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
-  equal = gen_rtx_IOR (TImode,
-		       gen_rtx_ZERO_EXTEND (TImode, div_equal),
-		       gen_rtx_ASHIFT (TImode,
-				       gen_rtx_ZERO_EXTEND (TImode, mod_equal),
-				       GEN_INT (64)));
 
   operands[4] = gen_reg_rtx(TImode);
-  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
-  emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
-  emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
-  insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2]));
-  REG_NOTES (insn) =
-	gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+  emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
 
   insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
   REG_NOTES (insn) =
@@ -4026,23 +4251,23 @@
         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
 
   DONE;
-}")
+})
 
 (define_insn "divmodtidi3"
   [(set (match_operand:TI 0 "register_operand" "=d,d")
         (ior:TI
           (zero_extend:TI
-            (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
+            (div:DI (match_operand:DI 1 "register_operand" "0,0")
                     (match_operand:DI 2 "general_operand" "d,m")))
           (ashift:TI
             (zero_extend:TI
-              (mod:DI (truncate:DI (match_dup 1)) 
+              (mod:DI (match_dup 1)
                       (match_dup 2)))
             (const_int 64))))]
   "TARGET_64BIT"
   "@
-   dsgr\\t%0,%2
-   dsg\\t%0,%2"
+   dsgr\t%0,%2
+   dsg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")
    (set_attr "type"     "idiv")])
 
@@ -4050,17 +4275,17 @@
   [(set (match_operand:TI 0 "register_operand" "=d,d")
         (ior:TI
           (zero_extend:TI
-            (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0"))
+            (div:DI (match_operand:DI 1 "register_operand" "0,0")
                     (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
           (ashift:TI
             (zero_extend:TI
-              (mod:DI (truncate:DI (match_dup 1)) 
+              (mod:DI (match_dup 1)
                       (sign_extend:DI (match_dup 2))))
             (const_int 64))))]
   "TARGET_64BIT"
   "@
-   dsgfr\\t%0,%2
-   dsgf\\t%0,%2"
+   dsgfr\t%0,%2
+   dsgf\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")
    (set_attr "type"     "idiv")])
 
@@ -4076,7 +4301,6 @@
 		   (umod:DI (match_dup 1) (match_dup 2)))])
    (clobber (match_dup 4))]
   "TARGET_64BIT"
-  "
 {
   rtx insn, div_equal, mod_equal, equal;
 
@@ -4105,11 +4329,11 @@
         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
 
   DONE;
-}")
+})
 
 (define_insn "udivmodtidi3"
   [(set (match_operand:TI 0 "register_operand" "=d,d")
-        (ior:TI (zero_extend:TI 
+        (ior:TI (zero_extend:TI
                   (truncate:DI
                     (udiv:TI (match_operand:TI 1 "register_operand" "0,0")
                              (zero_extend:TI
@@ -4121,8 +4345,8 @@
                   (const_int 64))))]
   "TARGET_64BIT"
   "@
-   dlgr\\t%0,%2
-   dlg\\t%0,%2"
+   dlgr\t%0,%2
+   dlg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")
    (set_attr "type"     "idiv")])
 
@@ -4138,7 +4362,6 @@
 		   (mod:SI (match_dup 1) (match_dup 2)))])
    (clobber (match_dup 4))]
   "!TARGET_64BIT"
-  "
 {
   rtx insn, div_equal, mod_equal, equal;
 
@@ -4165,14 +4388,14 @@
         gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
 
   DONE;
-}")
+})
 
 (define_insn "divmoddisi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
         (ior:DI (zero_extend:DI
                   (truncate:SI
                     (div:DI (match_operand:DI 1 "register_operand" "0,0")
-                            (sign_extend:DI 
+                            (sign_extend:DI
                               (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
                 (ashift:DI
                   (zero_extend:DI
@@ -4181,8 +4404,8 @@
                   (const_int 32))))]
   "!TARGET_64BIT"
   "@
-   dr\\t%0,%2
-   d\\t%0,%2"
+   dr\t%0,%2
+   d\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "idiv")])
 
@@ -4190,14 +4413,69 @@
 ; udivsi3 and umodsi3 instruction pattern(s).
 ;
 
+(define_expand "udivmodsi4"
+  [(parallel [(set (match_operand:SI 0 "general_operand" "")
+		   (udiv:SI (match_operand:SI 1 "general_operand" "")
+			    (match_operand:SI 2 "nonimmediate_operand" "")))
+	      (set (match_operand:SI 3 "general_operand" "")
+		   (umod:SI (match_dup 1) (match_dup 2)))])
+   (clobber (match_dup 4))]
+  "!TARGET_64BIT && TARGET_CPU_ZARCH"
+{
+  rtx insn, div_equal, mod_equal, equal;
+
+  div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
+  mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
+  equal = gen_rtx_IOR (DImode,
+		       gen_rtx_ZERO_EXTEND (DImode, div_equal),
+		       gen_rtx_ASHIFT (DImode,
+				       gen_rtx_ZERO_EXTEND (DImode, mod_equal),
+				       GEN_INT (32)));
+
+  operands[4] = gen_reg_rtx(DImode);
+  emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
+  emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
+  emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
+  insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
+  REG_NOTES (insn) =
+	gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
+
+  insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
+  REG_NOTES (insn) =
+        gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
+
+  insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
+  REG_NOTES (insn) =
+        gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
+
+  DONE;
+})
+
+(define_insn "udivmoddisi3"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (ior:DI (zero_extend:DI
+                  (truncate:SI
+                    (udiv:DI (match_operand:DI 1 "register_operand" "0,0")
+                             (zero_extend:DI
+                               (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
+                (ashift:DI
+                  (zero_extend:DI
+                    (truncate:SI
+                      (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))
+                  (const_int 32))))]
+  "!TARGET_64BIT && TARGET_CPU_ZARCH"
+  "@
+   dlr\t%0,%2
+   dl\t%0,%2"
+  [(set_attr "op_type"  "RRE,RXY")
+   (set_attr "type"     "idiv")])
 
 (define_expand "udivsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (udiv:SI (match_operand:SI 1 "general_operand" "")
                  (match_operand:SI 2 "general_operand" "")))
    (clobber (match_dup 3))]
-  "!TARGET_64BIT"
-  "
+  "!TARGET_64BIT && !TARGET_CPU_ZARCH"
 {
   rtx insn, udiv_equal, umod_equal, equal;
 
@@ -4226,32 +4504,32 @@
         }
       else
         {
-          operands[2] = force_reg (SImode, operands[2]);	
-          operands[2] = make_safe_from (operands[2], operands[0]);	
+          operands[2] = force_reg (SImode, operands[2]);
+          operands[2] = make_safe_from (operands[2], operands[0]);
 
 	  emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
 	  insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
 					     operands[2]));
 	  REG_NOTES (insn) =
 	    gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-	  
-	  insn = emit_move_insn (operands[0], 
+
+	  insn = emit_move_insn (operands[0],
 				 gen_lowpart (SImode, operands[3]));
 	  REG_NOTES (insn) =
-	    gen_rtx_EXPR_LIST (REG_EQUAL, 
+	    gen_rtx_EXPR_LIST (REG_EQUAL,
 			       udiv_equal, REG_NOTES (insn));
         }
     }
   else
-    {  
+    {
       rtx label1 = gen_label_rtx ();
       rtx label2 = gen_label_rtx ();
       rtx label3 = gen_label_rtx ();
 
-      operands[1] = force_reg (SImode, operands[1]);	
-      operands[1] = make_safe_from (operands[1], operands[0]);	
-      operands[2] = force_reg (SImode, operands[2]);	
-      operands[2] = make_safe_from (operands[2], operands[0]);	
+      operands[1] = force_reg (SImode, operands[1]);
+      operands[1] = make_safe_from (operands[1], operands[0]);
+      operands[2] = force_reg (SImode, operands[2]);
+      operands[2] = make_safe_from (operands[2], operands[0]);
 
       emit_move_insn (operands[0], const0_rtx);
       emit_insn (gen_cmpsi (operands[2], operands[1]));
@@ -4265,11 +4543,11 @@
 					 operands[2]));
       REG_NOTES (insn) =
       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-      
-      insn = emit_move_insn (operands[0], 
+
+      insn = emit_move_insn (operands[0],
 			     gen_lowpart (SImode, operands[3]));
       REG_NOTES (insn) =
-      gen_rtx_EXPR_LIST (REG_EQUAL, 
+      gen_rtx_EXPR_LIST (REG_EQUAL,
 			       udiv_equal, REG_NOTES (insn));
       emit_jump (label3);
       emit_label (label1);
@@ -4279,17 +4557,16 @@
       emit_move_insn (operands[0], const1_rtx);
       emit_label (label3);
     }
-  emit_move_insn (operands[0], operands[0]);	
+  emit_move_insn (operands[0], operands[0]);
   DONE;
-}")
+})
 
 (define_expand "umodsi3"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
                  (match_operand:SI 2 "nonimmediate_operand" "")))
    (clobber (match_dup 3))]
-  "!TARGET_64BIT"
-  "
+  "!TARGET_64BIT && !TARGET_CPU_ZARCH"
 {
   rtx insn, udiv_equal, umod_equal, equal;
 
@@ -4319,19 +4596,19 @@
         }
       else
         {
-          operands[2] = force_reg (SImode, operands[2]);	
-          operands[2] = make_safe_from (operands[2], operands[0]);	
+          operands[2] = force_reg (SImode, operands[2]);
+          operands[2] = make_safe_from (operands[2], operands[0]);
 
 	  emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
 	  insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
 					     operands[2]));
 	  REG_NOTES (insn) =
 	    gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-	  
-	  insn = emit_move_insn (operands[0], 
+
+	  insn = emit_move_insn (operands[0],
 				 gen_highpart (SImode, operands[3]));
 	  REG_NOTES (insn) =
-	    gen_rtx_EXPR_LIST (REG_EQUAL, 
+	    gen_rtx_EXPR_LIST (REG_EQUAL,
 			       umod_equal, REG_NOTES (insn));
         }
     }
@@ -4341,12 +4618,12 @@
       rtx label2 = gen_label_rtx ();
       rtx label3 = gen_label_rtx ();
 
-      operands[1] = force_reg (SImode, operands[1]);	
-      operands[1] = make_safe_from (operands[1], operands[0]);	
-      operands[2] = force_reg (SImode, operands[2]);	
-      operands[2] = make_safe_from (operands[2], operands[0]);	
+      operands[1] = force_reg (SImode, operands[1]);
+      operands[1] = make_safe_from (operands[1], operands[0]);
+      operands[2] = force_reg (SImode, operands[2]);
+      operands[2] = make_safe_from (operands[2], operands[0]);
 
-      emit_move_insn(operands[0], operands[1]);	
+      emit_move_insn(operands[0], operands[1]);
       emit_insn (gen_cmpsi (operands[2], operands[1]));
       emit_jump_insn (gen_bgtu (label3));
       emit_insn (gen_cmpsi (operands[2], const1_rtx));
@@ -4358,11 +4635,11 @@
 					 operands[2]));
       REG_NOTES (insn) =
       gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
-      
-      insn = emit_move_insn (operands[0], 
+
+      insn = emit_move_insn (operands[0],
 			     gen_highpart (SImode, operands[3]));
       REG_NOTES (insn) =
-      gen_rtx_EXPR_LIST (REG_EQUAL, 
+      gen_rtx_EXPR_LIST (REG_EQUAL,
 			 umod_equal, REG_NOTES (insn));
       emit_jump (label3);
       emit_label (label1);
@@ -4373,7 +4650,7 @@
       emit_label (label3);
     }
   DONE;
-}")
+})
 
 ;
 ; divdf3 instruction pattern(s).
@@ -4395,8 +4672,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   ddbr\\t%0,%2
-   ddb\\t%0,%2"
+   ddbr\t%0,%2
+   ddb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fdivd")])
 
@@ -4407,8 +4684,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   ddr\\t%0,%2
-   dd\\t%0,%2"
+   ddr\t%0,%2
+   dd\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fdivd")])
 
@@ -4432,8 +4709,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   debr\\t%0,%2
-   deb\\t%0,%2"
+   debr\t%0,%2
+   deb\t%0,%2"
   [(set_attr "op_type"  "RRE,RXE")
    (set_attr "type"     "fdivs")])
 
@@ -4444,8 +4721,8 @@
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
   "@
-   der\\t%0,%2
-   de\\t%0,%2"
+   der\t%0,%2
+   de\t%0,%2"
   [(set_attr "op_type"  "RR,RX")
    (set_attr "type"     "fdivs")])
 
@@ -4467,8 +4744,8 @@
         (and:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   ngr\\t%0,%2
-   ng\\t%0,%2"
+   ngr\t%0,%2
+   ng\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*anddi3_cconly"
@@ -4479,8 +4756,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   ngr\\t%0,%2
-   ng\\t%0,%2"
+   ngr\t%0,%2
+   ng\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*anddi3_ni"
@@ -4489,20 +4766,19 @@
                 (match_operand:DI 2 "immediate_operand" "n")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0"
-  "*
 {
   int part = s390_single_hi (operands[2], DImode, -1);
   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
 
   switch (part)
     {
-      case 0: return \"nihh\\t%0,%x2\";
-      case 1: return \"nihl\\t%0,%x2\";
-      case 2: return \"nilh\\t%0,%x2\";
-      case 3: return \"nill\\t%0,%x2\";
+      case 0: return "nihh\t%0,%x2";
+      case 1: return "nihl\t%0,%x2";
+      case 2: return "nilh\t%0,%x2";
+      case 3: return "nill\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type"  "RI")])
 
 (define_insn "anddi3"
@@ -4512,8 +4788,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   ngr\\t%0,%2
-   ng\\t%0,%2"
+   ngr\t%0,%2
+   ng\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*anddi3_ss"
@@ -4522,7 +4798,7 @@
                 (match_operand:DI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(8,%R0),%1"
+  "nc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*anddi3_ss_inv"
@@ -4531,7 +4807,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(8,%R0),%1"
+  "nc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4547,9 +4823,9 @@
         (and:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   nr\\t%0,%2
-   n\\t%0,%2
-   ny\\t%0,%2"
+   nr\t%0,%2
+   n\t%0,%2
+   ny\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*andsi3_cconly"
@@ -4560,9 +4836,9 @@
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   nr\\t%0,%2
-   n\\t%0,%2
-   ny\\t%0,%2"
+   nr\t%0,%2
+   n\t%0,%2
+   ny\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*andsi3_ni"
@@ -4570,19 +4846,18 @@
         (and:SI (match_operand:SI 1 "nonimmediate_operand" "0")
                 (match_operand:SI 2 "immediate_operand" "n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0"
-  "*
+  "TARGET_ZARCH && s390_single_hi (operands[2], SImode, -1) >= 0"
 {
   int part = s390_single_hi (operands[2], SImode, -1);
   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
 
   switch (part)
     {
-      case 0: return \"nilh\\t%0,%x2\";
-      case 1: return \"nill\\t%0,%x2\";
+      case 0: return "nilh\t%0,%x2";
+      case 1: return "nill\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type"  "RI")])
 
 (define_insn "andsi3"
@@ -4592,9 +4867,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   nr\\t%0,%2
-   n\\t%0,%2
-   ny\\t%0,%2"
+   nr\t%0,%2
+   n\t%0,%2
+   ny\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*andsi3_ss"
@@ -4603,7 +4878,7 @@
                 (match_operand:SI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(4,%R0),%1"
+  "nc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*andsi3_ss_inv"
@@ -4612,7 +4887,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(4,%R0),%1"
+  "nc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4624,10 +4899,10 @@
         (and:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT"
+  "TARGET_ZARCH"
   "@
-   nr\\t%0,%2
-   nill\\t%0,%x2"
+   nr\t%0,%2
+   nill\t%0,%x2"
   [(set_attr "op_type"  "RR,RI")])
 
 (define_insn "andhi3"
@@ -4636,7 +4911,7 @@
                 (match_operand:HI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "nr\\t%0,%2"
+  "nr\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*andhi3_ss"
@@ -4645,7 +4920,7 @@
                 (match_operand:HI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(2,%R0),%1"
+  "nc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*andhi3_ss_inv"
@@ -4654,7 +4929,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "nc\\t%O0(2,%R0),%1"
+  "nc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4666,10 +4941,10 @@
         (and:QI (match_operand:QI 1 "register_operand" "%0,0")
                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT"
+  "TARGET_ZARCH"
   "@
-   nr\\t%0,%2
-   nill\\t%0,%b2"
+   nr\t%0,%2
+   nill\t%0,%b2"
   [(set_attr "op_type"  "RR,RI")])
 
 (define_insn "andqi3"
@@ -4678,7 +4953,7 @@
                 (match_operand:QI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "nr\\t%0,%2"
+  "nr\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*andqi3_ss"
@@ -4688,9 +4963,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   ni\\t%0,%b1
-   niy\\t%0,%b1
-   nc\\t%O0(1,%R0),%1"
+   ni\t%0,%b1
+   niy\t%0,%b1
+   nc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 (define_insn "*andqi3_ss_inv"
@@ -4700,9 +4975,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   ni\\t%0,%b1
-   niy\\t%0,%b1
-   nc\\t%O0(1,%R0),%1"
+   ni\t%0,%b1
+   niy\t%0,%b1
+   nc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 
@@ -4723,8 +4998,8 @@
         (ior:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   ogr\\t%0,%2
-   og\\t%0,%2"
+   ogr\t%0,%2
+   og\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*iordi3_cconly"
@@ -4735,8 +5010,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   ogr\\t%0,%2
-   og\\t%0,%2"
+   ogr\t%0,%2
+   og\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*iordi3_oi"
@@ -4745,20 +5020,19 @@
                 (match_operand:DI 2 "immediate_operand" "n")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0"
-  "*
 {
   int part = s390_single_hi (operands[2], DImode, 0);
   operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part));
 
   switch (part)
     {
-      case 0: return \"oihh\\t%0,%x2\";
-      case 1: return \"oihl\\t%0,%x2\";
-      case 2: return \"oilh\\t%0,%x2\";
-      case 3: return \"oill\\t%0,%x2\";
+      case 0: return "oihh\t%0,%x2";
+      case 1: return "oihl\t%0,%x2";
+      case 2: return "oilh\t%0,%x2";
+      case 3: return "oill\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type"  "RI")])
 
 (define_insn "iordi3"
@@ -4768,8 +5042,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   ogr\\t%0,%2
-   og\\t%0,%2"
+   ogr\t%0,%2
+   og\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*iordi3_ss"
@@ -4778,7 +5052,7 @@
                 (match_operand:DI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(8,%R0),%1"
+  "oc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*iordi3_ss_inv"
@@ -4787,7 +5061,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(8,%R0),%1"
+  "oc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4803,9 +5077,9 @@
         (ior:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   or\\t%0,%2
-   o\\t%0,%2
-   oy\\t%0,%2"
+   or\t%0,%2
+   o\t%0,%2
+   oy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*iorsi3_cconly"
@@ -4816,9 +5090,9 @@
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   or\\t%0,%2
-   o\\t%0,%2
-   oy\\t%0,%2"
+   or\t%0,%2
+   o\t%0,%2
+   oy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*iorsi3_oi"
@@ -4826,19 +5100,18 @@
         (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0")
                 (match_operand:SI 2 "immediate_operand" "n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0"
-  "*
+  "TARGET_ZARCH && s390_single_hi (operands[2], SImode, 0) >= 0"
 {
   int part = s390_single_hi (operands[2], SImode, 0);
   operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part));
 
   switch (part)
     {
-      case 0: return \"oilh\\t%0,%x2\";
-      case 1: return \"oill\\t%0,%x2\";
+      case 0: return "oilh\t%0,%x2";
+      case 1: return "oill\t%0,%x2";
       default: abort ();
     }
-}"
+}
   [(set_attr "op_type"  "RI")])
 
 (define_insn "iorsi3"
@@ -4848,9 +5121,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   or\\t%0,%2
-   o\\t%0,%2
-   oy\\t%0,%2"
+   or\t%0,%2
+   o\t%0,%2
+   oy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*iorsi3_ss"
@@ -4859,7 +5132,7 @@
                 (match_operand:SI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(4,%R0),%1"
+  "oc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*iorsi3_ss_inv"
@@ -4868,7 +5141,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(4,%R0),%1"
+  "oc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4880,10 +5153,10 @@
         (ior:HI (match_operand:HI 1 "register_operand" "%0,0")
                 (match_operand:HI 2 "nonmemory_operand" "d,n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT"
+  "TARGET_ZARCH"
   "@
-   or\\t%0,%2
-   oill\\t%0,%x2"
+   or\t%0,%2
+   oill\t%0,%x2"
   [(set_attr "op_type"  "RR,RI")])
 
 (define_insn "iorhi3"
@@ -4892,7 +5165,7 @@
                 (match_operand:HI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "or\\t%0,%2"
+  "or\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*iorhi3_ss"
@@ -4901,7 +5174,7 @@
                 (match_operand:HI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(2,%R0),%1"
+  "oc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*iorhi3_ss_inv"
@@ -4910,7 +5183,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "oc\\t%O0(2,%R0),%1"
+  "oc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -4922,10 +5195,10 @@
         (ior:QI (match_operand:QI 1 "register_operand" "%0,0")
                 (match_operand:QI 2 "nonmemory_operand" "d,n")))
    (clobber (reg:CC 33))]
-  "TARGET_64BIT"
+  "TARGET_ZARCH"
   "@
-   or\\t%0,%2
-   oill\\t%0,%b2"
+   or\t%0,%2
+   oill\t%0,%b2"
   [(set_attr "op_type"  "RR,RI")])
 
 (define_insn "iorqi3"
@@ -4934,7 +5207,7 @@
                 (match_operand:QI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "or\\t%0,%2"
+  "or\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*iorqi3_ss"
@@ -4944,9 +5217,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   oi\\t%0,%b1
-   oiy\\t%0,%b1
-   oc\\t%O0(1,%R0),%1"
+   oi\t%0,%b1
+   oiy\t%0,%b1
+   oc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 (define_insn "*iorqi3_ss_inv"
@@ -4956,9 +5229,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   oi\\t%0,%b1
-   oiy\\t%0,%b1
-   oc\\t%O0(1,%R0),%1"
+   oi\t%0,%b1
+   oiy\t%0,%b1
+   oc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 
@@ -4979,8 +5252,8 @@
         (xor:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   xgr\\t%0,%2
-   xg\\t%0,%2"
+   xgr\t%0,%2
+   xg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*xordi3_cconly"
@@ -4991,8 +5264,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
   "@
-   xgr\\t%0,%2
-   xr\\t%0,%2"
+   xgr\t%0,%2
+   xr\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "xordi3"
@@ -5002,8 +5275,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   xgr\\t%0,%2
-   xg\\t%0,%2"
+   xgr\t%0,%2
+   xg\t%0,%2"
   [(set_attr "op_type"  "RRE,RXY")])
 
 (define_insn "*xordi3_ss"
@@ -5012,7 +5285,7 @@
                 (match_operand:DI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(8,%R0),%1"
+  "xc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*xordi3_ss_inv"
@@ -5021,7 +5294,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(8,%R0),%1"
+  "xc\t%O0(8,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -5037,9 +5310,9 @@
         (xor:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   xr\\t%0,%2
-   x\\t%0,%2
-   xy\\t%0,%2"
+   xr\t%0,%2
+   x\t%0,%2
+   xy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*xorsi3_cconly"
@@ -5050,9 +5323,9 @@
    (clobber (match_scratch:SI 0 "=d,d,d"))]
   "s390_match_ccmode(insn, CCTmode)"
   "@
-   xr\\t%0,%2
-   x\\t%0,%2
-   xy\\t%0,%2"
+   xr\t%0,%2
+   x\t%0,%2
+   xy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "xorsi3"
@@ -5062,9 +5335,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   xr\\t%0,%2
-   x\\t%0,%2
-   xy\\t%0,%2"
+   xr\t%0,%2
+   x\t%0,%2
+   xy\t%0,%2"
   [(set_attr "op_type"  "RR,RX,RXY")])
 
 (define_insn "*xorsi3_ss"
@@ -5073,7 +5346,7 @@
                 (match_operand:SI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(4,%R0),%1"
+  "xc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*xorsi3_ss_inv"
@@ -5082,7 +5355,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(4,%R0),%1"
+  "xc\t%O0(4,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -5095,7 +5368,7 @@
                 (match_operand:HI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "xr\\t%0,%2"
+  "xr\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*xorhi3_ss"
@@ -5104,7 +5377,7 @@
                 (match_operand:HI 1 "s_imm_operand" "Q")))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(2,%R0),%1"
+  "xc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 (define_insn "*xorhi3_ss_inv"
@@ -5113,7 +5386,7 @@
                 (match_dup 0)))
    (clobber (reg:CC 33))]
   ""
-  "xc\\t%O0(2,%R0),%1"
+  "xc\t%O0(2,%R0),%1"
   [(set_attr "op_type"  "SS")])
 
 ;
@@ -5126,7 +5399,7 @@
                 (match_operand:QI 2 "nonmemory_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "xr\\t%0,%2"
+  "xr\t%0,%2"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*xorqi3_ss"
@@ -5136,9 +5409,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   xi\\t%0,%b1
-   xiy\\t%0,%b1
-   xc\\t%O0(1,%R0),%1"
+   xi\t%0,%b1
+   xiy\t%0,%b1
+   xc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 (define_insn "*xorqi3_ss_inv"
@@ -5148,9 +5421,9 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   xi\\t%0,%b1
-   xiy\\t%0,%b1
-   xc\\t%O0(1,%R0),%1"
+   xi\t%0,%b1
+   xiy\t%0,%b1
+   xc\t%O0(1,%R0),%1"
   [(set_attr "op_type"  "SI,SIY,SS")])
 
 
@@ -5175,7 +5448,7 @@
         (neg:DI (match_operand:DI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "lcgr\\t%0,%1"
+  "lcgr\t%0,%1"
   [(set_attr "op_type"  "RR")])
 
 (define_insn "*negdi2_31"
@@ -5183,18 +5456,17 @@
         (neg:DI (match_operand:DI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
-  "*
 {
   rtx xop[1];
   xop[0] = gen_label_rtx ();
-  output_asm_insn (\"lcr\\t%0,%1\", operands);
-  output_asm_insn (\"lcr\\t%N0,%N1\", operands);
-  output_asm_insn (\"je\\t%l0\", xop);
-  output_asm_insn (\"bctr\\t%0,0\", operands);
-  (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
+  output_asm_insn ("lcr\t%0,%1", operands);
+  output_asm_insn ("lcr\t%N0,%N1", operands);
+  output_asm_insn ("je\t%l0", xop);
+  output_asm_insn ("bctr\t%0,0", operands);
+  targetm.asm_out.internal_label (asm_out_file, "L",
 			     CODE_LABEL_NUMBER (xop[0]));
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "op_type"  "NN")
    (set_attr "type"     "other")
    (set_attr "length"   "10")])
@@ -5208,7 +5480,7 @@
         (neg:SI (match_operand:SI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "lcr\\t%0,%1"
+  "lcr\t%0,%1"
   [(set_attr "op_type"  "RR")])
 
 ;
@@ -5228,7 +5500,7 @@
         (neg:DF (match_operand:DF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcdbr\\t%0,%1"
+  "lcdbr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimpd")])
 
@@ -5237,7 +5509,7 @@
         (neg:DF (match_operand:DF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lcdr\\t%0,%1"
+  "lcdr\t%0,%1"
   [(set_attr "op_type"  "RR")
    (set_attr "type"     "fsimpd")])
 
@@ -5258,7 +5530,7 @@
         (neg:SF (match_operand:SF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lcebr\\t%0,%1"
+  "lcebr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimps")])
 
@@ -5267,7 +5539,7 @@
         (neg:SF (match_operand:SF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lcer\\t%0,%1"
+  "lcer\t%0,%1"
   [(set_attr "op_type"  "RR")
    (set_attr "type"     "fsimps")])
 
@@ -5285,7 +5557,7 @@
         (abs:DI (match_operand:DI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "lpgr\\t%0,%1"
+  "lpgr\t%0,%1"
   [(set_attr "op_type"  "RRE")])
 
 ;
@@ -5297,7 +5569,7 @@
         (abs:SI (match_operand:SI 1 "register_operand" "d")))
    (clobber (reg:CC 33))]
   ""
-  "lpr\\t%0,%1"
+  "lpr\t%0,%1"
   [(set_attr "op_type"  "RR")])
 
 ;
@@ -5317,7 +5589,7 @@
         (abs:DF (match_operand:DF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpdbr\\t%0,%1"
+  "lpdbr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimpd")])
 
@@ -5326,7 +5598,7 @@
         (abs:DF (match_operand:DF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lpdr\\t%0,%1"
+  "lpdr\t%0,%1"
   [(set_attr "op_type"  "RR")
    (set_attr "type"     "fsimpd")])
 
@@ -5347,7 +5619,7 @@
         (abs:SF (match_operand:SF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
-  "lpebr\\t%0,%1"
+  "lpebr\t%0,%1"
   [(set_attr "op_type"  "RRE")
    (set_attr "type"     "fsimps")])
 
@@ -5356,11 +5628,57 @@
         (abs:SF (match_operand:SF 1 "register_operand" "f")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
-  "lper\\t%0,%1"
+  "lper\t%0,%1"
   [(set_attr "op_type"  "RR")
    (set_attr "type"     "fsimps")])
 
 ;;
+;;- Negated absolute value instructions
+;;
+
+;
+; Integer
+;
+
+(define_insn "*negabssi2"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
+   (clobber (reg:CC 33))]
+  ""
+  "lnr\t%0,%1"
+  [(set_attr "op_type" "RR")])
+
+(define_insn "*negabsdi2"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+	(neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "lngr\t%0,%1"
+  [(set_attr "op_type" "RRE")])
+
+;
+; Floating point
+;
+
+(define_insn "*negabssf2"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+        (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
+   (clobber (reg:CC 33))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "lnebr\t%0,%1"
+  [(set_attr "op_type"  "RRE")
+   (set_attr "type"     "fsimps")])
+
+(define_insn "*negabsdf2"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+        (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
+   (clobber (reg:CC 33))]
+  "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
+  "lndbr\t%0,%1"
+  [(set_attr "op_type"  "RRE")
+   (set_attr "type"     "fsimpd")])
+
+;;
 ;;- Square root instructions.
 ;;
 
@@ -5373,8 +5691,8 @@
 	(sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sqdbr\\t%0,%1
-   sqdb\\t%0,%1"
+   sqdbr\t%0,%1
+   sqdb\t%0,%1"
   [(set_attr "op_type"  "RRE,RXE")])
 
 ;
@@ -5386,8 +5704,8 @@
 	(sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
   "@
-   sqebr\\t%0,%1
-   sqeb\\t%0,%1"
+   sqebr\t%0,%1
+   sqeb\t%0,%1"
   [(set_attr "op_type"  "RRE,RXE")])
 
 ;;
@@ -5397,7 +5715,7 @@
 ;
 ; one_cmpldi2 instruction pattern(s).
 ;
- 
+
 (define_expand "one_cmpldi2"
   [(parallel
     [(set (match_operand:DI 0 "register_operand" "")
@@ -5406,11 +5724,11 @@
      (clobber (reg:CC 33))])]
   "TARGET_64BIT"
   "")
- 
+
 ;
 ; one_cmplsi2 instruction pattern(s).
 ;
- 
+
 (define_expand "one_cmplsi2"
   [(parallel
     [(set (match_operand:SI 0 "register_operand" "")
@@ -5419,11 +5737,11 @@
      (clobber (reg:CC 33))])]
   ""
   "")
- 
+
 ;
 ; one_cmplhi2 instruction pattern(s).
 ;
- 
+
 (define_expand "one_cmplhi2"
   [(parallel
     [(set (match_operand:HI 0 "register_operand" "")
@@ -5432,11 +5750,11 @@
      (clobber (reg:CC 33))])]
   ""
   "")
- 
+
 ;
 ; one_cmplqi2 instruction pattern(s).
 ;
- 
+
 (define_expand "one_cmplqi2"
   [(parallel
     [(set (match_operand:QI 0 "register_operand" "")
@@ -5461,8 +5779,8 @@
 		   (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   "TARGET_64BIT"
   "@
-   rllg\\t%0,%1,%c2
-   rllg\\t%0,%1,0(%2)"
+   rllg\t%0,%1,%c2
+   rllg\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5474,10 +5792,10 @@
   [(set (match_operand:SI 0 "register_operand" "=d,d")
 	(rotate:SI (match_operand:SI 1 "register_operand" "d,d")
 		   (match_operand:SI 2 "nonmemory_operand" "J,a")))]
-  "TARGET_64BIT"
+  "TARGET_CPU_ZARCH"
   "@
-   rll\\t%0,%1,%c2
-   rll\\t%0,%1,0(%2)"
+   rll\t%0,%1,%c2
+   rll\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5503,8 +5821,8 @@
                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   "!TARGET_64BIT"
   "@
-   sldl\\t%0,%c2
-   sldl\\t%0,0(%2)"     
+   sldl\t%0,%c2
+   sldl\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5514,8 +5832,8 @@
                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   "TARGET_64BIT"
   "@
-   sllg\\t%0,%1,%2
-   sllg\\t%0,%1,0(%2)"
+   sllg\t%0,%1,%2
+   sllg\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5541,8 +5859,8 @@
         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
   "@
-   srda\\t%0,%c2
-   srda\\t%0,0(%2)"     
+   srda\t%0,%c2
+   srda\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5554,8 +5872,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
   "@
-   srda\\t%0,%c2
-   srda\\t%0,0(%2)"     
+   srda\t%0,%c2
+   srda\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5566,11 +5884,11 @@
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
   "@
-   srda\\t%0,%c2
-   srda\\t%0,0(%2)"     
+   srda\t%0,%c2
+   srda\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
- 
+
 (define_insn "*ashrdi3_cc_64"
   [(set (reg 33)
         (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
@@ -5580,8 +5898,8 @@
         (ashiftrt:DI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
   "@
-   srag\\t%0,%1,%c2
-   srag\\t%0,%1,0(%2)"
+   srag\t%0,%1,%c2
+   srag\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5593,8 +5911,8 @@
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
   "@
-   srag\\t%0,%1,%c2
-   srag\\t%0,%1,0(%2)"
+   srag\t%0,%1,%c2
+   srag\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5605,8 +5923,8 @@
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
   "@
-   srag\\t%0,%1,%c2
-   srag\\t%0,%1,0(%2)"
+   srag\t%0,%1,%c2
+   srag\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE")
    (set_attr "atype"    "reg")])
 
@@ -5621,8 +5939,8 @@
                    (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   ""
   "@
-   sll\\t%0,%c2
-   sll\\t%0,0(%2)"
+   sll\t%0,%c2
+   sll\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5639,8 +5957,8 @@
         (ashiftrt:SI (match_dup 1) (match_dup 2)))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   sra\\t%0,%c2
-   sra\\t%0,0(%2)"
+   sra\t%0,%c2
+   sra\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5653,8 +5971,8 @@
    (clobber (match_scratch:SI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCSmode)"
   "@
-   sra\\t%0,%c2
-   sra\\t%0,0(%2)"
+   sra\t%0,%c2
+   sra\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5665,8 +5983,8 @@
    (clobber (reg:CC 33))]
   ""
   "@
-   sra\\t%0,%c2
-   sra\\t%0,0(%2)"
+   sra\t%0,%c2
+   sra\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5692,8 +6010,8 @@
                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   "!TARGET_64BIT"
   "@
-   srdl\\t%0,%c2
-   srdl\\t%0,0(%2)"     
+   srdl\t%0,%c2
+   srdl\t%0,0(%2)"
    [(set_attr "op_type"  "RS,RS")
     (set_attr "atype"    "reg")])
 
@@ -5703,8 +6021,8 @@
                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   "TARGET_64BIT"
   "@
-   srlg\\t%0,%1,%c2
-   srlg\\t%0,%1,0(%2)"
+   srlg\t%0,%1,%c2
+   srlg\t%0,%1,0(%2)"
   [(set_attr "op_type"  "RSE,RSE")
    (set_attr "atype"    "reg")])
 
@@ -5718,8 +6036,8 @@
                      (match_operand:SI 2 "nonmemory_operand" "J,a")))]
   ""
   "@
-   srl\\t%0,%c2
-   srl\\t%0,0(%2)"
+   srl\t%0,%c2
+   srl\t%0,0(%2)"
   [(set_attr "op_type"  "RS")
    (set_attr "atype"    "reg")])
 
@@ -5735,7 +6053,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bne"
   [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
@@ -5744,7 +6062,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bgt"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5753,7 +6071,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bgtu"
   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
@@ -5762,7 +6080,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "blt"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5771,7 +6089,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bltu"
   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
@@ -5780,7 +6098,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bge"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5789,7 +6107,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bgeu"
   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
@@ -5798,7 +6116,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "ble"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5807,7 +6125,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bleu"
   [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
@@ -5816,7 +6134,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bunordered"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5825,7 +6143,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bordered"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5834,7 +6152,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "buneq"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5843,7 +6161,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bungt"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5852,7 +6170,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bunlt"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5861,7 +6179,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bunge"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5870,7 +6188,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bunle"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5879,7 +6197,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 (define_expand "bltgt"
   [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
@@ -5888,7 +6206,7 @@
                       (label_ref (match_operand 0 "" ""))
                       (pc)))]
   ""
-  "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
+  "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;")
 
 
 ;;
@@ -5897,26 +6215,25 @@
 
 (define_insn "cjump"
  [(set (pc)
-       (if_then_else 
+       (if_then_else
          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
 	 (label_ref (match_operand 0 "" ""))
 	 (pc)))]
   ""
-  "*
 {
   if (get_attr_length (insn) == 4)
-    return \"j%C1\\t%l0\";
-  else if (TARGET_64BIT)
-    return \"jg%C1\\t%l0\";
+    return "j%C1\t%l0";
+  else if (TARGET_CPU_ZARCH)
+    return "jg%C1\t%l0";
   else
     abort ();
-}"
+}
   [(set_attr "op_type" "RI")
    (set_attr "type"    "branch")
    (set (attr "length")
         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
                 (const_int 4)
-               (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+               (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
                  (const_int 6)
                (eq (symbol_ref "flag_pic") (const_int 0))
                  (const_int 6)] (const_int 8)))])
@@ -5928,14 +6245,13 @@
 	 (match_operand 0 "address_operand" "U")
 	 (pc)))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
-    return \"b%C1r\\t%0\";
+    return "b%C1r\t%0";
   else
-    return \"b%C1\\t%a0\";
-}"
-  [(set (attr "op_type") 
+    return "b%C1\t%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"    "branch")
@@ -5950,24 +6266,23 @@
  [(set (pc)
        (if_then_else
          (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
-         (pc) 
+         (pc)
 	 (label_ref (match_operand 0 "" ""))))]
   ""
-  "*
-{  
+{
   if (get_attr_length (insn) == 4)
-    return \"j%D1\\t%l0\";
-  else if (TARGET_64BIT)
-    return \"jg%D1\\t%l0\";
+    return "j%D1\t%l0";
+  else if (TARGET_CPU_ZARCH)
+    return "jg%D1\t%l0";
   else
     abort ();
-}"
+}
   [(set_attr "op_type" "RI")
    (set_attr "type"    "branch")
    (set (attr "length")
         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
                 (const_int 4)
-               (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+               (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
                  (const_int 6)
                (eq (symbol_ref "flag_pic") (const_int 0))
                  (const_int 6)] (const_int 8)))])
@@ -5979,14 +6294,13 @@
          (pc)
 	 (match_operand 0 "address_operand" "U")))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
-    return \"b%D1r\\t%0\";
+    return "b%D1r\t%0";
   else
-    return \"b%D1\\t%a0\";
-}"
-  [(set (attr "op_type") 
+    return "b%D1\t%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"  "branch")
@@ -5999,7 +6313,7 @@
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 0))]
   ""
-  "j\\t.+2"
+  "j\t.+2"
   [(set_attr "op_type" "RX")
    (set_attr "type"  "branch")])
 
@@ -6009,23 +6323,22 @@
 			    [(match_dup 2) (const_int 0)])
 	    (match_operand:SI 1 "general_operand" ""))]
   ""
-  "
 {
    enum machine_mode ccmode;
 
-   if (operands[1] != const0_rtx) FAIL;	
+   if (operands[1] != const0_rtx) FAIL;
 
-   ccmode = s390_select_ccmode (GET_CODE (operands[0]), 
-			        s390_compare_op0, s390_compare_op1);    
+   ccmode = s390_select_ccmode (GET_CODE (operands[0]),
+			        s390_compare_op0, s390_compare_op1);
    operands[2] = gen_rtx_REG (ccmode, 33);
    operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1);
-}")
+})
 
 (define_insn "*trap"
   [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)])
 	    (const_int 0))]
   ""
-  "j%C0\\t.+2";
+  "j%C0\t.+2";
   [(set_attr "op_type" "RI")
    (set_attr "type"  "branch")])
 
@@ -6034,7 +6347,7 @@
 ;;
 ;;  This is all complicated by the fact that since this is a jump insn
 ;;  we must handle our own output reloads.
- 
+
 (define_expand "doloop_end"
   [(use (match_operand 0 "" ""))        ; loop pseudo
    (use (match_operand 1 "" ""))        ; iterations; zero if unknown
@@ -6042,7 +6355,6 @@
    (use (match_operand 3 "" ""))        ; loop level
    (use (match_operand 4 "" ""))]       ; label
   ""
-  "
 {
   if (GET_MODE (operands[0]) == SImode)
     emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0]));
@@ -6052,7 +6364,7 @@
     FAIL;
 
   DONE;
-}")
+})
 
 (define_insn "doloop_si"
   [(set (pc)
@@ -6066,21 +6378,20 @@
    (clobber (match_scratch:SI 3 "=X,&d"))
    (clobber (reg:CC 33))]
   ""
-  "*
 {
   if (which_alternative != 0)
-    return \"#\";
+    return "#";
   else if (get_attr_length (insn) == 4)
-    return \"brct\\t%1,%l0\";
+    return "brct\t%1,%l0";
   else
     abort ();
-}"
+}
   [(set_attr "op_type"  "RI")
    (set_attr "type"  "branch")
    (set (attr "length")
         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
                 (const_int 4)
-               (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+               (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
                  (const_int 10)
                (eq (symbol_ref "flag_pic") (const_int 0))
                  (const_int 6)] (const_int 8)))])
@@ -6097,14 +6408,13 @@
    (clobber (match_scratch:SI 3 "=X,&d"))
    (clobber (reg:CC 33))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
-    return \"bctr\\t%1,%0\";
+    return "bctr\t%1,%0";
   else
-    return \"bct\\t%1,%a0\";
-}"
-  [(set (attr "op_type") 
+    return "bct\t%1,%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"  "branch")
@@ -6146,15 +6456,14 @@
    (clobber (match_scratch:DI 3 "=X,&d"))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
-  "*
 {
   if (which_alternative != 0)
-    return \"#\";
+    return "#";
   else if (get_attr_length (insn) == 4)
-    return \"brctg\\t%1,%l0\";
+    return "brctg\t%1,%l0";
   else
     abort ();
-}"
+}
   [(set_attr "op_type"  "RI")
    (set_attr "type"  "branch")
    (set (attr "length")
@@ -6173,14 +6482,13 @@
    (clobber (match_scratch:DI 3 "=X,&d"))
    (clobber (reg:CC 33))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RRE)
-    return \"bctgr\\t%1,%0\";
+    return "bctgr\t%1,%0";
   else
-    return \"bctg\\t%1,%a0\";
-}"
-  [(set (attr "op_type") 
+    return "bctg\t%1,%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RRE") (const_string "RXE")))
    (set_attr "type"  "branch")
@@ -6221,21 +6529,20 @@
 (define_insn "jump"
   [(set (pc) (label_ref (match_operand 0 "" "")))]
   ""
-  "*
 {
   if (get_attr_length (insn) == 4)
-    return \"j\\t%l0\";
-  else if (TARGET_64BIT)
-    return \"jg\\t%l0\";
+    return "j\t%l0";
+  else if (TARGET_CPU_ZARCH)
+    return "jg\t%l0";
   else
     abort ();
-}"
+}
   [(set_attr "op_type" "RI")
    (set_attr "type"  "branch")
    (set (attr "length")
         (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
                 (const_int 4)
-               (ne (symbol_ref "TARGET_64BIT") (const_int 0))
+               (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
                  (const_int 6)
                (eq (symbol_ref "flag_pic") (const_int 0))
                  (const_int 6)] (const_int 8)))])
@@ -6247,14 +6554,13 @@
 (define_insn "indirect_jump"
  [(set (pc) (match_operand 0 "address_operand" "U"))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
-    return \"br\\t%0\";
+    return "br\t%0";
   else
-    return \"b\\t%a0\";
-}"
-  [(set (attr "op_type") 
+    return "b\t%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"  "branch")
@@ -6268,14 +6574,13 @@
  [(set (pc) (match_operand 0 "address_operand" "U"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "*
 {
   if (get_attr_op_type (insn) == OP_TYPE_RR)
-    return \"br\\t%0\";
+    return "br\t%0";
   else
-    return \"b\\t%a0\";
-}"
-  [(set (attr "op_type") 
+    return "b\t%a0";
+}
+  [(set (attr "op_type")
         (if_then_else (match_operand 0 "register_operand" "")
                       (const_string "RR") (const_string "RX")))
    (set_attr "type"  "branch")
@@ -6288,7 +6593,6 @@
    (label_ref (match_operand 3 "" ""))
    (label_ref (match_operand 4 "" ""))]
   ""
-  "
 {
    rtx index  = gen_reg_rtx (SImode);
    rtx base   = gen_reg_rtx (Pmode);
@@ -6319,7 +6623,7 @@
    emit_jump_insn (gen_casesi_jump (target, operands[3]));
 
    DONE;
-}")
+})
 
 
 ;;
@@ -6338,7 +6642,6 @@
               (match_operand 1 "" "")
               (match_operand 2 "" "")])]
   ""
-  "
 {
   int i;
 
@@ -6357,13 +6660,13 @@
   emit_insn (gen_blockage ());
 
   DONE;
-}")
+})
 
 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
 ;; all of memory.  This blocks insns from being moved across this point.
 
 (define_insn "blockage"
-  [(unspec_volatile [(const_int 0)] 0)]
+  [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
   ""
   ""
   [(set_attr "type"    "none")
@@ -6380,9 +6683,8 @@
          (match_operand 1 "" ""))
    (use (match_operand 2 "" ""))]
   ""
-  "
 {
-  int plt_call = 0;
+  bool plt_call = false;
   rtx insn;
 
   /* Direct function calls need special treatment.  */
@@ -6394,20 +6696,20 @@
          replace the symbol itself with the PLT stub.  */
       if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
         {
-          sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
+          sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
           sym = gen_rtx_CONST (Pmode, sym);
-
-	  plt_call = 1;
+	  plt_call = true;
         }
 
-      /* Unless we can use the bras(l) insn, force the 
+      /* Unless we can use the bras(l) insn, force the
          routine address into a register.  */
-      if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
-        {
-          rtx target = gen_reg_rtx (Pmode);
-          emit_move_insn (target, sym);
-          sym = target;
-        }
+      if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
+	{
+	  if (flag_pic)
+	    sym = legitimize_pic_address (sym, 0);
+	  else
+	    sym = force_reg (Pmode, sym);
+	}
 
       operands[0] = gen_rtx_MEM (QImode, sym);
     }
@@ -6416,14 +6718,12 @@
   insn = emit_call_insn (gen_call_exp (operands[0], operands[1],
   				       gen_rtx_REG (Pmode, RETURN_REGNUM)));
 
-  /* In 31-bit, we must load the GOT register even if the 
-     compiler doesn't know about it, because the PLT glue 
-     code uses it.  In 64-bit, this is not necessary.  */
-  if (plt_call && !TARGET_64BIT)
+  /* 31-bit PLT stubs use the GOT register implicitly.  */
+  if (!TARGET_64BIT && plt_call)
     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
-
+  
   DONE;
-}")
+})
 
 (define_expand "call_exp"
   [(parallel [(call (match_operand 0 "" "")
@@ -6432,62 +6732,40 @@
   ""
   "")
 
-(define_insn "brasl"
-  [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:DI 2 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "brasl\\t%2,%0"
-  [(set_attr "op_type" "RIL")
-   (set_attr "type"    "jsr")])
-
-(define_insn "bras"
-  [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:SI 2 "register_operand" "=r"))]
-  "TARGET_SMALL_EXEC"
-  "bras\\t%2,%0"
+(define_insn "*bras"
+  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+         (match_operand 1 "const_int_operand" "n"))
+   (clobber (match_operand 2 "register_operand" "=r"))]
+  "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode"
+  "bras\t%2,%0"
   [(set_attr "op_type" "RI")
    (set_attr "type"    "jsr")])
 
-(define_insn "basr_64"
-  [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:DI 2 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "basr\\t%2,%0"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"   "agen")])
-
-(define_insn "basr_31"
-  [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:SI 2 "register_operand" "=r"))]
-  "!TARGET_64BIT"
-  "basr\\t%2,%0"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"    "agen")])
-
-(define_insn "bas_64"
-  [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:DI 2 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "bas\\t%2,%a0"
-  [(set_attr "op_type" "RX")
-   (set_attr "type"    "jsr")])
-
-(define_insn "bas_31"
-  [(call (mem:QI (match_operand:QI 0 "address_operand" "U"))
-         (match_operand:SI 1 "const_int_operand" "n"))
-   (clobber (match_operand:SI 2 "register_operand" "=r"))]
-  "!TARGET_64BIT"
-  "bas\\t%2,%a0"
-  [(set_attr "op_type" "RX")
+(define_insn "*brasl"
+  [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
+         (match_operand 1 "const_int_operand" "n"))
+   (clobber (match_operand 2 "register_operand" "=r"))]
+  "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode"
+  "brasl\t%2,%0"
+  [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")])
 
+(define_insn "*basr"
+  [(call (mem:QI (match_operand 0 "address_operand" "U"))
+         (match_operand 1 "const_int_operand" "n"))
+   (clobber (match_operand 2 "register_operand" "=r"))]
+  "GET_MODE (operands[2]) == Pmode"
+{
+  if (get_attr_op_type (insn) == OP_TYPE_RR)
+    return "basr\t%2,%0";
+  else
+    return "bas\t%2,%a0";
+}
+  [(set (attr "op_type")
+        (if_then_else (match_operand 0 "register_operand" "")
+                      (const_string "RR") (const_string "RX")))
+   (set_attr "type"  "jsr")
+   (set_attr "atype" "agen")])
 
 ;
 ; call_value instruction pattern(s).
@@ -6499,9 +6777,8 @@
               (match_operand 2 "" "")))
    (use (match_operand 3 "" ""))]
   ""
-  "
 {
-  int plt_call = 0;
+  bool plt_call = false;
   rtx insn;
 
   /* Direct function calls need special treatment.  */
@@ -6513,19 +6790,19 @@
          replace the symbol itself with the PLT stub.  */
       if (flag_pic && !SYMBOL_REF_LOCAL_P (sym))
         {
-          sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
+          sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
           sym = gen_rtx_CONST (Pmode, sym);
-
-	  plt_call = 1;
+	  plt_call = true;
         }
 
-      /* Unless we can use the bras(l) insn, force the 
+      /* Unless we can use the bras(l) insn, force the
          routine address into a register.  */
-      if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
+      if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
         {
-          rtx target = gen_reg_rtx (Pmode);
-          emit_move_insn (target, sym);
-          sym = target;
+	  if (flag_pic)
+	    sym = legitimize_pic_address (sym, 0);
+	  else
+	    sym = force_reg (Pmode, sym);
         }
 
       operands[1] = gen_rtx_MEM (QImode, sym);
@@ -6536,14 +6813,12 @@
 	    gen_call_value_exp (operands[0], operands[1], operands[2],
   				gen_rtx_REG (Pmode, RETURN_REGNUM)));
 
-  /* In 31-bit, we must load the GOT register even if the 
-     compiler doesn't know about it, because the PLT glue 
-     code uses it.  In 64-bit, this is not necessary.  */
-  if (plt_call && !TARGET_64BIT)
+  /* 31-bit PLT stubs use the GOT register implicitly.  */
+  if (!TARGET_64BIT && plt_call)
     use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx);
-
+  
   DONE;
-}")
+})
 
 (define_expand "call_value_exp"
   [(parallel [(set (match_operand 0 "" "")
@@ -6553,68 +6828,43 @@
   ""
   "")
 
-(define_insn "brasl_r"
+(define_insn "*bras_r"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
+        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
               (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "brasl\\t%3,%1"
-  [(set_attr "op_type" "RIL")
-   (set_attr "type"    "jsr")])
-
-(define_insn "bras_r"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  "TARGET_SMALL_EXEC"
-  "bras\\t%3,%1"
+   (clobber (match_operand 3 "register_operand" "=r"))]
+  "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
+  "bras\t%3,%1"
   [(set_attr "op_type" "RI")
    (set_attr "type"    "jsr")])
 
-(define_insn "basr_r_64"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "basr\\t%3,%1"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"   "agen")])
-
-(define_insn "basr_r_31"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  "!TARGET_64BIT"
-  "basr\\t%3,%1"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"   "agen")])
-
-(define_insn "bas_r_64"
+(define_insn "*brasl_r"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))]
-  "TARGET_64BIT"
-  "bas\\t%3,%a1"
-  [(set_attr "op_type" "RX")
+        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+              (match_operand 2 "const_int_operand" "n")))
+   (clobber (match_operand 3 "register_operand" "=r"))]
+  "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+  "brasl\t%3,%1"
+  [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")])
 
-(define_insn "bas_r_31"
+(define_insn "*basr_r"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  "!TARGET_64BIT"
-  "bas\\t%3,%a1"
-   [(set_attr "op_type" "RX")
-    (set_attr "type"    "jsr")])
-
+        (call (mem:QI (match_operand 1 "address_operand" "U"))
+              (match_operand 2 "const_int_operand" "n")))
+   (clobber (match_operand 3 "register_operand" "=r"))]
+  "GET_MODE (operands[3]) == Pmode"
+{
+  if (get_attr_op_type (insn) == OP_TYPE_RR)
+    return "basr\t%3,%1";
+  else
+    return "bas\t%3,%a1";
+}
+  [(set (attr "op_type")
+        (if_then_else (match_operand 1 "register_operand" "")
+                      (const_string "RR") (const_string "RX")))
+   (set_attr "type"  "jsr")
+   (set_attr "atype" "agen")])
 
 ;;
 ;;- Thread-local storage support.
@@ -6625,8 +6875,8 @@
         (unspec:DI [(const_int 0)] UNSPEC_TP))]
   "TARGET_64BIT"
   "@
-   ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1
-   stam\\t%%a0,%%a1,%0"
+   ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1
+   stam\t%%a0,%%a1,%0"
   [(set_attr "op_type" "NN,RS")
    (set_attr "atype"   "reg,*")
    (set_attr "type"    "o3,*")
@@ -6637,8 +6887,8 @@
         (unspec:SI [(const_int 0)] UNSPEC_TP))]
   "!TARGET_64BIT"
   "@
-   ear\\t%0,%%a0
-   stam\\t%%a0,%%a0,%0"
+   ear\t%0,%%a0
+   stam\t%%a0,%%a0,%0"
   [(set_attr "op_type" "RRE,RS")])
 
 (define_insn "set_tp_64"
@@ -6646,8 +6896,8 @@
    (clobber (match_scratch:SI 1 "=d,X"))]
   "TARGET_64BIT"
   "@
-   sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1
-   lam\\t%%a0,%%a1,%0"
+   sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1
+   lam\t%%a0,%%a1,%0"
   [(set_attr "op_type" "NN,RS")
    (set_attr "atype"   "reg,*")
    (set_attr "type"    "o3,*")
@@ -6657,17 +6907,17 @@
   [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)]
   "!TARGET_64BIT"
   "@
-   sar\\t%%a0,%0
-   lam\\t%%a0,%%a0,%0"
+   sar\t%%a0,%0
+   lam\t%%a0,%%a0,%0"
   [(set_attr "op_type" "RRE,RS")])
-  
+
 (define_insn "*tls_load_64"
   [(set (match_operand:DI 0 "register_operand" "=d")
         (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
                     (match_operand:DI 2 "" "")]
 		   UNSPEC_TLS_LOAD))]
   "TARGET_64BIT"
-  "lg\\t%0,%1%J2"
+  "lg\t%0,%1%J2"
   [(set_attr "op_type" "RXE")])
 
 (define_insn "*tls_load_31"
@@ -6677,8 +6927,8 @@
 		   UNSPEC_TLS_LOAD))]
   "!TARGET_64BIT"
   "@
-   l\\t%0,%1%J2
-   ly\\t%0,%1%J2"
+   l\t%0,%1%J2
+   ly\t%0,%1%J2"
   [(set_attr "op_type" "RX,RXY")])
 
 (define_expand "call_value_tls"
@@ -6686,7 +6936,6 @@
         (call (const_int 0) (const_int 0)))
    (use (match_operand 1 "" ""))]
   ""
-  "
 {
   rtx insn, sym;
 
@@ -6694,16 +6943,17 @@
     abort ();
 
   sym = s390_tls_get_offset ();
-  sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
+  sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT);
   sym = gen_rtx_CONST (Pmode, sym);
 
-  /* Unless we can use the bras(l) insn, force the 
+  /* Unless we can use the bras(l) insn, force the
      routine address into a register.  */
-  if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
+  if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
     {
-      rtx target = gen_reg_rtx (Pmode);
-      emit_move_insn (target, sym);
-      sym = target;
+      if (flag_pic)
+	sym = legitimize_pic_address (sym, 0);
+      else
+	sym = force_reg (Pmode, sym);
     }
 
   sym = gen_rtx_MEM (QImode, sym);
@@ -6721,7 +6971,7 @@
   CONST_OR_PURE_CALL_P (insn) = 1;
 
   DONE;
-}")
+})
 
 (define_expand "call_value_tls_exp"
   [(parallel [(set (match_operand 0 "" "")
@@ -6732,74 +6982,46 @@
   ""
   "")
 
-(define_insn "brasl_tls"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))
-   (use (match_operand:DI 4 "" ""))]
-  "TARGET_64BIT"
-  "brasl\\t%3,%1%J4"
-  [(set_attr "op_type" "RIL")
-   (set_attr "type"    "jsr")])
-
-(define_insn "bras_tls"
+(define_insn "*bras_tls"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))
-   (use (match_operand:SI 4 "" ""))]
-  "TARGET_SMALL_EXEC"
-  "bras\\t%3,%1%J4"
+        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+              (match_operand 2 "const_int_operand" "n")))
+   (clobber (match_operand 3 "register_operand" "=r"))
+   (use (match_operand 4 "" ""))]
+  "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode"
+  "bras\t%3,%1%J4"
   [(set_attr "op_type" "RI")
    (set_attr "type"    "jsr")])
 
-(define_insn "basr_tls_64"
+(define_insn "*brasl_tls"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))
-   (use (match_operand:DI 4 "" ""))]
-  "TARGET_64BIT"
-  "basr\\t%3,%1%J4"
-  [(set_attr "op_type" "RR")
+        (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
+              (match_operand 2 "const_int_operand" "n")))
+   (clobber (match_operand 3 "register_operand" "=r"))
+   (use (match_operand 4 "" ""))]
+  "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode"
+  "brasl\t%3,%1%J4"
+  [(set_attr "op_type" "RIL")
    (set_attr "type"    "jsr")])
 
-(define_insn "basr_tls_31"
+(define_insn "*basr_tls"
   [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))
-   (use (match_operand:SI 4 "" ""))]
-  "!TARGET_64BIT"
-  "basr\\t%3,%1%J4"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"   "agen")])
-
-(define_insn "bas_tls_64"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:DI 3 "register_operand" "=r"))
-   (use (match_operand:DI 4 "" ""))]
-  "TARGET_64BIT"
-  "bas\\t%3,%a1%J4"
-  [(set_attr "op_type" "RX")
-   (set_attr "type"    "jsr")
-   (set_attr "atype"   "agen")])
-
-(define_insn "bas_tls_31"
-  [(set (match_operand 0 "register_operand" "=df")
-        (call (mem:QI (match_operand:QI 1 "address_operand" "U"))
-              (match_operand:SI 2 "const_int_operand" "n")))
-   (clobber (match_operand:SI 3 "register_operand" "=r"))
-   (use (match_operand:SI 4 "" ""))]
-  "!TARGET_64BIT"
-  "bas\\t%3,%a1%J4"
-   [(set_attr "op_type" "RX")
-    (set_attr "type"    "jsr")
-    (set_attr "atype"   "agen")])
+        (call (mem:QI (match_operand 1 "address_operand" "U"))
+              (match_operand 2 "const_int_operand" "n")))
+   (clobber (match_operand 3 "register_operand" "=r"))
+   (use (match_operand 4 "" ""))]
+  "GET_MODE (operands[3]) == Pmode"
+{
+  if (get_attr_op_type (insn) == OP_TYPE_RR)
+    return "basr\t%3,%1%J4";
+  else
+    return "bas\t%3,%a1%J4";
+}
+  [(set (attr "op_type")
+        (if_then_else (match_operand 1 "register_operand" "")
+                      (const_string "RR") (const_string "RX")))
+   (set_attr "type"  "jsr")
+   (set_attr "atype" "agen")])
 
 ;;
 ;;- Miscellaneous instructions.
@@ -6815,12 +7037,11 @@
    (set (match_operand 0 "general_operand" "")
         (reg 15))]
  ""
- "
 {
     rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
     rtx chain = gen_rtx (MEM, Pmode, stack);
     rtx temp = gen_reg_rtx (Pmode);
-	
+
     emit_move_insn (temp, chain);
 
     if (TARGET_64BIT)
@@ -6830,9 +7051,9 @@
 
     emit_move_insn (chain, temp);
 
-    emit_move_insn (operands[0], virtual_stack_dynamic_rtx);	
+    emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
     DONE;
-}")
+})
 
 
 ;
@@ -6840,35 +7061,28 @@
 ;
 
 (define_expand "builtin_setjmp_setup"
-  [(unspec [(match_operand 0 "register_operand" "a")] 1)]
+  [(match_operand 0 "register_operand" "")]
   ""
-  "
 {
   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
 
   emit_move_insn (base, basereg);
   DONE;
-}")
+})
 
 (define_expand "builtin_setjmp_receiver"
-  [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
+  [(match_operand 0 "" "")]
   "flag_pic"
-  "
 {
-  rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
-  rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
-  SYMBOL_REF_FLAGS (got) = SYMBOL_FLAG_LOCAL;
-
-  emit_move_insn (gotreg, got);
-  emit_insn (gen_rtx_USE (VOIDmode, gotreg));
+  s390_load_got (false);
+  emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
   DONE;
-}")
+})
 
 (define_expand "builtin_longjmp"
-  [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
+  [(match_operand 0 "register_operand" "")]
   ""
-  "
 {
   /* The elements of the buffer are, in order:  */
   rtx fp = gen_rtx_MEM (Pmode, operands[0]);
@@ -6876,7 +7090,7 @@
   rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
   rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
   rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
-  rtx jmp = gen_rtx_REG (Pmode, 14);
+  rtx jmp = gen_reg_rtx (Pmode);
 
   emit_move_insn (jmp, lab);
   emit_move_insn (basereg, base);
@@ -6888,7 +7102,7 @@
   emit_insn (gen_rtx_USE (VOIDmode, basereg));
   emit_indirect_jump (jmp);
   DONE;
-}")
+})
 
 
 ;; These patterns say how to save and restore the stack pointer.  We need not
@@ -6918,17 +7132,15 @@
    (set (match_dup 0) (match_operand 1 "register_operand" ""))
    (set (match_dup 3) (match_dup 2))]
   ""
-  "
 {
   operands[2] = gen_reg_rtx (Pmode);
   operands[3] = gen_rtx_MEM (Pmode, operands[0]);
-}")
+})
 
 (define_expand "save_stack_nonlocal"
   [(match_operand 0 "memory_operand" "")
    (match_operand 1 "register_operand" "")]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (Pmode);
 
@@ -6941,13 +7153,12 @@
                  TARGET_64BIT ? TImode : DImode),
                  operands[1]);
   DONE;
-}")
+})
 
 (define_expand "restore_stack_nonlocal"
   [(match_operand 0 "register_operand" "")
    (match_operand 1 "memory_operand" "")]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (Pmode);
 
@@ -6960,7 +7171,7 @@
                  TARGET_64BIT ? TImode : DImode));
   emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
   DONE;
-}")
+})
 
 
 ;
@@ -6970,7 +7181,7 @@
 (define_insn "nop"
   [(const_int 0)]
   ""
-  "lr\\t0,0"
+  "lr\t0,0"
   [(set_attr "op_type" "RR")])
 
 
@@ -6978,144 +7189,97 @@
 ; Special literal pool access instruction pattern(s).
 ;
 
-(define_insn "consttable_qi"
-  [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)]
+(define_insn "*pool_entry"
+  [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
+                    UNSPECV_POOL_ENTRY)]
   ""
-  "*
 {
-  assemble_integer (operands[0], 1, BITS_PER_UNIT, 1);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "1")])
-
-(define_insn "consttable_hi"
-  [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)]
-  ""
-  "*
-{
-  assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "2")])
-
-(define_insn "consttable_si"
-  [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)]
-  ""
-  "*
-{
-  if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0]))
-    return \".long\\t%0\";
-
-  assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "4")])
-
-(define_insn "consttable_di"
-  [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)]
-  ""
-  "*
-{
-  assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "8")])
-
-(define_insn "consttable_sf"
-  [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)]
-  ""
-  "*
-{
-  REAL_VALUE_TYPE r;
-
-  if (GET_CODE (operands[0]) != CONST_DOUBLE)
-    abort ();
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
-  assemble_real (r, SFmode, 4*BITS_PER_UNIT);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "4")])
-
-(define_insn "consttable_df"
-  [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)]
-  ""
-  "*
-{
-  REAL_VALUE_TYPE r;
-
-  if (GET_CODE (operands[0]) != CONST_DOUBLE)
-    abort ();
-
-  REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
-  assemble_real (r, DFmode, 8*BITS_PER_UNIT);
-  return \"\";
-}"
-  [(set_attr "op_type"  "NN")
-   (set_attr "length"   "8")])
+  enum machine_mode mode = GET_MODE (PATTERN (insn));
+  unsigned int align = GET_MODE_BITSIZE (mode);
+  s390_output_pool_entry (asm_out_file, operands[0], mode, align);
+  return "";
+}
+  [(set_attr "op_type" "NN")
+   (set (attr "length") 
+        (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
 
 (define_insn "pool_start_31"
-  [(unspec_volatile [(const_int 0)] 206)]
-  "!TARGET_64BIT"
-  ".align\\t4"
+  [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
+  "!TARGET_CPU_ZARCH"
+  ".align\t4"
   [(set_attr "op_type"  "NN")
    (set_attr "length"   "2")])
 
 (define_insn "pool_end_31"
-  [(unspec_volatile [(const_int 0)] 207)]
-  "!TARGET_64BIT"
-  ".align\\t2"
+  [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
+  "!TARGET_CPU_ZARCH"
+  ".align\t2"
   [(set_attr "op_type"  "NN")
    (set_attr "length"   "2")])
 
 (define_insn "pool_start_64"
-  [(unspec_volatile [(const_int 0)] 206)]
-  "TARGET_64BIT"
-  ".section\\t.rodata\;.align\\t8"
+  [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)]
+  "TARGET_CPU_ZARCH"
+  ".section\t.rodata\;.align\t8"
   [(set_attr "op_type"  "NN")
    (set_attr "length"   "0")])
 
 (define_insn "pool_end_64"
-  [(unspec_volatile [(const_int 0)] 207)]
-  "TARGET_64BIT"
+  [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)]
+  "TARGET_CPU_ZARCH"
   ".previous"
   [(set_attr "op_type"  "NN")
    (set_attr "length"   "0")])
 
+(define_insn "main_base_31_small"
+  [(set (match_operand 0 "register_operand" "=a")
+        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
+  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+  "basr\t%0,0"
+  [(set_attr "op_type" "RR")
+   (set_attr "type"    "la")])
+
+(define_insn "main_base_31_large"
+  [(set (match_operand 0 "register_operand" "=a")
+        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
+   (set (pc) (label_ref (match_operand 2 "" "")))]
+  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+  "bras\t%0,%2"
+  [(set_attr "op_type" "RI")])
+
+(define_insn "main_base_64"
+  [(set (match_operand 0 "register_operand" "=a")
+        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
+  "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+  "larl\t%0,%1"
+  [(set_attr "op_type" "RIL")
+   (set_attr "type"    "larl")])
+
+(define_insn "main_pool"
+  [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)]
+  ""
+  "* abort ();"
+  [(set_attr "op_type" "NN")])
+
 (define_insn "reload_base_31"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-        (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))]
-  "!TARGET_64BIT"
-  "basr\\t%0,0\;la\\t%0,%1-.(%0)"
+  [(set (match_operand 0 "register_operand" "=a")
+        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
+  "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+  "basr\t%0,0\;la\t%0,%1-.(%0)"
   [(set_attr "op_type" "NN")
    (set_attr "type"    "la")
    (set_attr "length"  "6")])
 
 (define_insn "reload_base_64"
-  [(set (match_operand:DI 0 "register_operand" "=a")
-        (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))]
-  "TARGET_64BIT"
-  "larl\\t%0,%1"
+  [(set (match_operand 0 "register_operand" "=a")
+        (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
+  "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
+  "larl\t%0,%1"
   [(set_attr "op_type" "RIL")
    (set_attr "type"    "larl")])
 
-(define_insn "reload_anchor"
-  [(set (match_operand:SI 0 "register_operand" "=a")
-        (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))]
-  "!TARGET_64BIT"
-  "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
-  [(set_attr "op_type" "NN")
-   (set_attr "type"    "la")
-   (set_attr "atype"   "agen")
-   (set_attr "length"  "8")])
-
 (define_insn "pool"
-  [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)]
+  [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
   ""
   "* abort ();"
   [(set_attr "op_type" "NN")
@@ -7129,78 +7293,33 @@
 (define_expand "prologue"
   [(use (const_int 0))]
   ""
-  "
-{
-      s390_emit_prologue ();
-      DONE;
-}")
+  "s390_emit_prologue (); DONE;")
 
 (define_expand "epilogue"
   [(use (const_int 1))]
   ""
-  "
-{
-      s390_emit_epilogue ();
-      DONE;
-}")
+  "s390_emit_epilogue (); DONE;")
 
-
-(define_insn "*return_si"
+(define_insn "*return"
   [(return)
-   (use (match_operand:SI 0 "register_operand" "a"))]
-  "!TARGET_64BIT"
-  "br\\t%0"
+   (use (match_operand 0 "register_operand" "a"))]
+  "GET_MODE (operands[0]) == Pmode"
+  "br\t%0"
   [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")		
+   (set_attr "type"    "jsr")
    (set_attr "atype"   "agen")])
 
-(define_insn "*return_di"
-  [(return)
-   (use (match_operand:DI 0 "register_operand" "a"))]
-  "TARGET_64BIT"
-  "br\\t%0"
-  [(set_attr "op_type" "RR")
-   (set_attr "type"    "jsr")		
-   (set_attr "atype"   "agen")])
 
-(define_insn "literal_pool_31"
-  [(unspec_volatile [(const_int 0)] 300)
-   (set (match_operand:SI 0 "register_operand" "=a") 
-        (label_ref (match_operand 1 "" "")))	
-   (use (label_ref (match_operand 2 "" "")))]
-  ""
-{
-   if (s390_nr_constants) 
-     {
-       output_asm_insn ("bras\\t%0,%2", operands);
-       s390_output_constant_pool (operands[1], operands[2]);
-     } 
-   else if (flag_pic)
-     {
-        /* We need the anchor label in any case.  */
-        (*targetm.asm_out.internal_label) (asm_out_file, "L",
-                                           CODE_LABEL_NUMBER (operands[1]));
-     }
-
-   return "";	
-}
-  [(set_attr "op_type" "NN")
-   (set_attr "type"    "larl")])
+;; Instruction definition to extend a 31-bit pointer into a 64-bit
+;; pointer. This is used for compatability.
 
-(define_insn "literal_pool_64"
-  [(unspec_volatile [(const_int 0)] 300)
-   (set (match_operand:DI 0 "register_operand" "=a") 
-        (label_ref (match_operand 1 "" "")))	
-   (use (label_ref (match_operand 2 "" "")))]
-  ""
+(define_expand "ptr_extend"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (match_operand:SI 1 "register_operand" "r"))]
+  "TARGET_64BIT"
 {
-   if (s390_nr_constants) 
-     {
-       output_asm_insn ("larl\\t%0,%1", operands);
-       s390_output_constant_pool (operands[1], operands[2]);
-     }
-
-   return "";	
-}
-  [(set_attr "op_type" "NN")
-   (set_attr "type"    "larl")])
+  emit_insn (gen_anddi3 (operands[0],
+			 gen_lowpart (DImode, operands[1]),
+			 GEN_INT (0x7fffffff)));
+  DONE;
+})
diff --git a/gcc/config/sh/embed-elf.h b/gcc/config/sh/embed-elf.h
index 3d8fd59c204..e96de90b860 100644
--- a/gcc/config/sh/embed-elf.h
+++ b/gcc/config/sh/embed-elf.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH 
    non-Linux embedded targets.
-   Copyright (C) 2002 Free Software Foundation, Inc.
+   Copyright (C) 2002, 2003 Free Software Foundation, Inc.
    Contributed by J"orn Rennecke <joern.rennecke@superh.com>
 
 This file is part of GNU CC.
@@ -20,8 +20,6 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#include "sh/elf.h"
-
 #undef USER_LABEL_PREFIX
 #define USER_LABEL_PREFIX "_"
 
diff --git a/gcc/config/sh/lib1funcs.asm b/gcc/config/sh/lib1funcs.asm
index 4173d8043f6..eebce2ecf96 100644
--- a/gcc/config/sh/lib1funcs.asm
+++ b/gcc/config/sh/lib1funcs.asm
@@ -1638,6 +1638,7 @@ LOCAL(large_divisor):
 	.section	.text..SHmedia32,"ax"
 	.align	2
 	.global	GLOBAL(udivdi3)
+	FUNC(GLOBAL(udivdi3))
 GLOBAL(udivdi3):
 	shlri r3,1,r4
 	nsb r4,r22
@@ -1745,6 +1746,7 @@ LOCAL(no_lo_adj):
 	cmpgtu r5,r2,r5
 	sub r8,r5,r2
 	blink tr0,r63
+	ENDFUNC(GLOBAL(udivdi3))
 /* Note 1: To shift the result of the second divide stage so that the result
    always fits into 32 bits, yet we still reduce the rest sufficiently
    would require a lot of instructions to do the shifts just right.  Using
@@ -1763,6 +1765,7 @@ LOCAL(no_lo_adj):
 	.section	.text..SHmedia32,"ax"
 	.align	2
 	.global	GLOBAL(divdi3)
+	FUNC(GLOBAL(divdi3))
 GLOBAL(divdi3):
 	pta GLOBAL(udivdi3),tr0
 	shari r2,63,r22
@@ -1776,6 +1779,7 @@ GLOBAL(divdi3):
 	blink tr0,r18
 	sub r63,r2,r2
 	blink tr1,r63
+	ENDFUNC(GLOBAL(divdi3))
 #endif /* __SHMEDIA__ */
 #endif /* L_divdi3 */
 
@@ -1785,6 +1789,7 @@ GLOBAL(divdi3):
 	.section	.text..SHmedia32,"ax"
 	.align	2
 	.global	GLOBAL(umoddi3)
+	FUNC(GLOBAL(umoddi3))
 GLOBAL(umoddi3):
 	shlri r3,1,r4
 	nsb r4,r22
@@ -1893,6 +1898,7 @@ LOCAL(no_lo_adj):
 	sub r2,r5,r2
 	shlrd r2,r22,r2
 	blink tr0,r63
+	ENDFUNC(GLOBAL(umoddi3))
 /* Note 1: To shift the result of the second divide stage so that the result
    always fits into 32 bits, yet we still reduce the rest sufficiently
    would require a lot of instructions to do the shifts just right.  Using
@@ -1911,6 +1917,7 @@ LOCAL(no_lo_adj):
 	.section	.text..SHmedia32,"ax"
 	.align	2
 	.global	GLOBAL(moddi3)
+	FUNC(GLOBAL(moddi3))
 GLOBAL(moddi3):
 	pta GLOBAL(umoddi3),tr0
 	shari r2,63,r22
@@ -1924,6 +1931,7 @@ GLOBAL(moddi3):
 	blink tr0,r18
 	sub r63,r2,r2
 	blink tr1,r63
+	ENDFUNC(GLOBAL(moddi3))
 #endif /* __SHMEDIA__ */
 #endif /* L_moddi3 */
 
@@ -1936,7 +1944,17 @@ GLOBAL(moddi3):
 	FUNC(GLOBAL(set_fpscr))
 GLOBAL(set_fpscr):
 	lds r4,fpscr
+#ifdef __PIC__
+	mov.l	r12,@-r15
+	mova	LOCAL(set_fpscr_L0),r0
+	mov.l	LOCAL(set_fpscr_L0),r12
+	add	r0,r12
+	mov.l	LOCAL(set_fpscr_L1),r0
+	mov.l	@(r0,r12),r1
+	mov.l	@r15+,r12
+#else
 	mov.l LOCAL(set_fpscr_L1),r1
+#endif
 	swap.w r4,r0
 	or #24,r0
 #ifndef FMOVD_WORKS
@@ -1964,8 +1982,15 @@ GLOBAL(set_fpscr):
 	mov.l r3,@(4,r1)
 #endif
 	.align 2
+#ifdef __PIC__
+LOCAL(set_fpscr_L0):
+	.long _GLOBAL_OFFSET_TABLE_
+LOCAL(set_fpscr_L1):
+	.long GLOBAL(fpscr_values@GOT)
+#else
 LOCAL(set_fpscr_L1):
 	.long GLOBAL(fpscr_values)
+#endif
 
 	ENDFUNC(GLOBAL(set_fpscr))
 #ifndef NO_FPSCR_VALUES
@@ -1983,6 +2008,7 @@ LOCAL(set_fpscr_L1):
 	.section	.text..SHmedia32,"ax"
 	.align	2
 	.global	GLOBAL(init_trampoline)
+	FUNC(GLOBAL(init_trampoline))
 GLOBAL(init_trampoline):
 	st.l	r0,8,r2
 #ifdef __LITTLE_ENDIAN__
@@ -1999,6 +2025,7 @@ GLOBAL(init_trampoline):
 	st.q	r0,0,r20
 	st.l	r0,12,r3
 	.global	GLOBAL(ic_invalidate)
+	FUNC(GLOBAL(ic_invalidate))
 GLOBAL(ic_invalidate):
 	ocbwb	r0,0
 	synco
@@ -2006,6 +2033,9 @@ GLOBAL(ic_invalidate):
 	ptabs	r18, tr0
 	synci
 	blink	tr0, r63
+
+	ENDFUNC(GLOBAL(ic_invalidate))
+	ENDFUNC(GLOBAL(init_trampoline))
 #elif defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__)
 	.global GLOBAL(ic_invalidate)
 	FUNC(GLOBAL(ic_invalidate))
diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
index 78a40e5e3b5..f6a9d7c6449 100644
--- a/gcc/config/sh/linux.h
+++ b/gcc/config/sh/linux.h
@@ -73,15 +73,16 @@ do { \
   "%{shared:-shared} \
    %{!static: \
      %{rdynamic:-export-dynamic} \
-     %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2} \
-     %{!rpath:-rpath /lib}} \
+     %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.2}} \
    %{static:-static}"
 
 #undef LIB_SPEC
 #define LIB_SPEC \
-  "%{shared: -lc} \
+  "%{pthread:-lpthread} \
+   %{shared: -lc} \
    %{!static:-rpath-link %R/lib:%R/usr/lib} \
-   %{!shared: %{pthread:-lthread} \
+   %{!shared: \
+     %{mieee-fp:-lieee} \
      %{profile:-lc_p} %{!profile: -lc}}"
 
 #if defined(HAVE_LD_EH_FRAME_HDR)
@@ -104,6 +105,9 @@ do { \
 #define ENDFILE_SPEC \
   "%{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Output assembler code to STREAM to call the profiler.  */
 
 #undef FUNCTION_PROFILER
@@ -170,11 +174,11 @@ do { \
 #define SH_DWARF_FRAME_FPSCR	24
 #endif /* defined (__SH5__) */
 
-#if defined (__SH5__) && __SH5__ != 32
+#if defined (__SH5__)
 /* MD_FALLBACK_FRAME_STATE_FOR is not yet defined for SHMEDIA.  */
-#else /* defined (__SH5__) && __SH5__ != 32 */
+#else /* defined (__SH5__) */
 
-#if defined (__SH3E__) || defined (__SH4__) || defined (__SH5__)
+#if defined (__SH3E__) || defined (__SH4__)
 #define SH_FALLBACK_FRAME_FLOAT_STATE(SC, FS, CFA)			\
   do {									\
     int i_, r_;								\
@@ -274,5 +278,16 @@ do { \
     goto SUCCESS;							\
   } while (0)
 
-#endif /* defined (__SH5__) && __SH5__ != 32 */
+#endif /* defined (__SH5__) */
 #endif /* IN_LIBGCC2 */
+
+/* For SH3 and SH4, we use a slot of the unwind frame which correspond
+   to a fake register number 16 as a placeholder for the return address
+   in MD_FALLBACK_FRAME_STATE_FOR and its content will be read with
+   _Unwind_GetGR which uses dwarf_reg_size_table to get the size of
+   the register.  So the entry of dwarf_reg_size_table corresponding to
+   this slot must be set.  To do this, we redefine DBX_REGISTER_NUMBER
+   so as to return itself for 16.  */
+#undef DBX_REGISTER_NUMBER
+#define DBX_REGISTER_NUMBER(REGNO) \
+  ((! TARGET_SH5 && (REGNO) == 16) ? 16 : SH_DBX_REGISTER_NUMBER (REGNO))
diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
index 10ef2e4a591..b87aecd0181 100644
--- a/gcc/config/sh/sh-protos.h
+++ b/gcc/config/sh/sh-protos.h
@@ -25,7 +25,6 @@ Boston, MA 02111-1307, USA.  */
 #define GCC_SH_PROTOS_H
 
 #ifdef RTX_CODE
-extern struct rtx_def *sh_builtin_saveregs PARAMS ((void));
 extern struct rtx_def *prepare_scc_operands PARAMS ((enum rtx_code));
 
 /* Declare functions defined in sh.c and used in templates.  */
@@ -121,6 +120,8 @@ extern int fldi_ok PARAMS ((void));
 extern int sh_pr_n_sets PARAMS ((void));
 extern int sh_hard_regno_rename_ok PARAMS ((unsigned int, unsigned int));
 extern int sh_cfun_interrupt_handler_p PARAMS ((void));
+extern int sh_attr_renesas_p PARAMS ((tree));
+extern int sh_cfun_attr_renesas_p PARAMS ((void));
 extern void sh_initialize_trampoline PARAMS ((rtx, rtx, rtx));
 extern bool sh_cannot_change_mode_class
 	      PARAMS ((enum machine_mode, enum machine_mode, enum reg_class));
@@ -136,5 +137,10 @@ extern void sh_pr_interrupt PARAMS ((struct cpp_reader *));
 extern void sh_pr_trapa PARAMS ((struct cpp_reader *));
 extern void sh_pr_nosave_low_regs PARAMS ((struct cpp_reader *));
 extern rtx function_symbol (const char *);
+extern rtx sh_get_pr_initial_val (void);
+
+extern rtx sh_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern void sh_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
+extern int sh_pass_in_reg_p (CUMULATIVE_ARGS *, enum machine_mode, tree);
 
 #endif /* ! GCC_SH_PROTOS_H */
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index e1c81c9c178..a266471b063 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -108,7 +108,7 @@ rtx sh_compare_op1;
 /* Provides the class number of the smallest class containing
    reg number.  */
 
-int regno_reg_class[FIRST_PSEUDO_REGISTER] =
+enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
 {
   R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
   GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
@@ -190,7 +190,7 @@ static rtx find_barrier PARAMS ((int, rtx, rtx));
 static int noncall_uses_reg PARAMS ((rtx, rtx, rtx *));
 static rtx gen_block_redirect PARAMS ((rtx, int, int));
 static void sh_reorg PARAMS ((void));
-static void output_stack_adjust PARAMS ((int, rtx, int, rtx (*) (rtx)));
+static void output_stack_adjust (int, rtx, int, HARD_REG_SET *);
 static rtx frame_insn PARAMS ((rtx));
 static rtx push PARAMS ((int));
 static void pop PARAMS ((int));
@@ -203,6 +203,7 @@ const struct attribute_spec sh_attribute_table[];
 static tree sh_handle_interrupt_handler_attribute PARAMS ((tree *, tree, tree, int, bool *));
 static tree sh_handle_sp_switch_attribute PARAMS ((tree *, tree, tree, int, bool *));
 static tree sh_handle_trap_exit_attribute PARAMS ((tree *, tree, tree, int, bool *));
+static tree sh_handle_renesas_attribute PARAMS ((tree *, tree, tree, int, bool *));
 static void sh_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
 static void sh_insert_attributes PARAMS ((tree, tree *));
 static int sh_adjust_cost PARAMS ((rtx, rtx, rtx, int));
@@ -234,6 +235,19 @@ static int sh_address_cost PARAMS ((rtx));
 static int shmedia_target_regs_stack_space (HARD_REG_SET *);
 static int shmedia_reserve_space_for_target_registers_p (int, HARD_REG_SET *);
 static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
+static int scavenge_reg (HARD_REG_SET *s);
+struct save_schedule_s;
+static struct save_entry_s *sh5_schedule_saves (HARD_REG_SET *,
+						struct save_schedule_s *, int);
+
+static bool sh_promote_prototypes PARAMS ((tree));
+static rtx sh_struct_value_rtx PARAMS ((tree, int));
+static bool sh_return_in_memory PARAMS ((tree, tree));
+static rtx sh_builtin_saveregs PARAMS ((void));
+static void sh_setup_incoming_varargs PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int));
+static bool sh_strict_argument_naming PARAMS ((CUMULATIVE_ARGS *));
+static bool sh_pretend_outgoing_varargs_named PARAMS ((CUMULATIVE_ARGS *));
+
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ATTRIBUTE_TABLE
@@ -311,6 +325,27 @@ static int shmedia_target_regs_stack_adjust (HARD_REG_SET *);
 #define TARGET_HAVE_TLS true
 #endif
 
+#undef TARGET_PROMOTE_PROTOTYPES
+#define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
+#undef TARGET_PROMOTE_FUNCTION_ARGS
+#define TARGET_PROMOTE_FUNCTION_ARGS sh_promote_prototypes
+#undef TARGET_PROMOTE_FUNCTION_RETURN
+#define TARGET_PROMOTE_FUNCTION_RETURN sh_promote_prototypes
+
+#undef TARGET_STRUCT_VALUE_RTX
+#define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
+#undef TARGET_RETURN_IN_MEMORY
+#define TARGET_RETURN_IN_MEMORY sh_return_in_memory
+
+#undef TARGET_EXPAND_BUILTIN_SAVEREGS
+#define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
+#undef TARGET_SETUP_INCOMING_VARARGS
+#define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
+#undef TARGET_STRICT_ARGUMENT_NAMING
+#define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
+#undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
+#define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Print the operand address in x to the stream.  */
@@ -4558,17 +4593,16 @@ output_jump_label_table ()
 
 static int extra_push;
 
-/* Adjust the stack by SIZE bytes.  REG holds the rtl of the register
-  to be adjusted, and TEMP, if nonnegative, holds the register number
-  of a general register that we may clobber.  */
+/* Adjust the stack by SIZE bytes.  REG holds the rtl of the register to be
+   adjusted.  If epilogue_p is zero, this is for a prologue; otherwise, it's
+   for an epilogue.  If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET
+   of all the registers that are about to be restored, and hence dead.  */
 
 static void
-output_stack_adjust (size, reg, temp, emit_fn)
-     int size;
-     rtx reg;
-     int temp;
-     rtx (*emit_fn) PARAMS ((rtx));
+output_stack_adjust (int size, rtx reg, int epilogue_p,
+		     HARD_REG_SET *live_regs_mask)
 {
+  rtx (*emit_fn) (rtx) = epilogue_p ? &emit_insn : &frame_insn;
   if (size)
     {
       HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
@@ -4591,10 +4625,43 @@ output_stack_adjust (size, reg, temp, emit_fn)
 	{
 	  rtx const_reg;
 	  rtx insn;
+	  int temp = epilogue_p ? 7 : (TARGET_SH5 ? 0 : 1);
+	  int i;
 
 	  /* If TEMP is invalid, we could temporarily save a general
 	     register to MACL.  However, there is currently no need
 	     to handle this case, so just abort when we see it.  */
+	  if (current_function_interrupt
+	      || ! call_used_regs[temp] || fixed_regs[temp])
+	    temp = -1;
+	  if (temp < 0 && ! current_function_interrupt)
+	    {
+	      HARD_REG_SET temps;
+	      COPY_HARD_REG_SET (temps, call_used_reg_set);
+	      AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
+	      if (epilogue_p)
+		{
+		  for (i = 0; i < HARD_REGNO_NREGS (FIRST_RET_REG, DImode); i++)
+		    CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
+		  if (current_function_calls_eh_return)
+		    {
+		      CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
+		      for (i = 0; i <= 3; i++)
+			CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
+		    }
+		}
+	      else
+		{
+		  for (i = FIRST_PARM_REG;
+		       i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
+		    CLEAR_HARD_REG_BIT (temps, i);
+		  if (current_function_needs_context)
+		    CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
+		}
+	      temp = scavenge_reg (&temps);
+	    }
+	  if (temp < 0 && live_regs_mask)
+	    temp = scavenge_reg (live_regs_mask);
 	  if (temp < 0)
 	    abort ();
 	  const_reg = gen_rtx_REG (GET_MODE (reg), temp);
@@ -4612,7 +4679,7 @@ output_stack_adjust (size, reg, temp, emit_fn)
 	      emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
 	      insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
 	    }
-	  if (emit_fn == frame_insn)
+	  if (! epilogue_p)
 	    REG_NOTES (insn)
 	      = (gen_rtx_EXPR_LIST
 		 (REG_FRAME_RELATED_EXPR,
@@ -4789,12 +4856,11 @@ calc_live_regs (live_regs_mask)
   int reg;
   int count;
   int interrupt_handler;
-  int pr_live;
+  int pr_live, has_call;
 
   interrupt_handler = sh_cfun_interrupt_handler_p ();
 
-  for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
-    CLEAR_HARD_REG_SET (*live_regs_mask);
+  CLEAR_HARD_REG_SET (*live_regs_mask);
   if (TARGET_SH4 && TARGET_FMOVD && interrupt_handler
       && regs_ever_live[FPSCR_REG])
     target_flags &= ~FPU_SINGLE_BIT;
@@ -4813,7 +4879,9 @@ calc_live_regs (live_regs_mask)
      the initial value can become the PR_MEDIA_REG hard register, as seen for
      execute/20010122-1.c:test9.  */
   if (TARGET_SHMEDIA)
-    pr_live = regs_ever_live[PR_MEDIA_REG];
+    /* ??? this function is called from initial_elimination_offset, hence we
+       can't use the result of sh_media_register_for_return here.  */
+    pr_live = sh_pr_n_sets ();
   else
     {
       rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
@@ -4821,6 +4889,10 @@ calc_live_regs (live_regs_mask)
 		 ? (GET_CODE (pr_initial) != REG
 		    || REGNO (pr_initial) != (PR_REG))
 		 : regs_ever_live[PR_REG]);
+      /* For Shcompact, if not optimizing, we end up with a memory reference
+	 using the return address pointer for __builtin_return_address even
+	 though there is no actual need to put the PR register on the stack.  */
+      pr_live |= regs_ever_live[RETURN_ADDRESS_POINTER_REGNUM];
     }
   /* Force PR to be live if the prologue has to call the SHmedia
      argument decoder or register saver.  */
@@ -4829,6 +4901,7 @@ calc_live_regs (live_regs_mask)
 	   & ~ CALL_COOKIE_RET_TRAMP (1))
 	  || current_function_has_nonlocal_label))
     pr_live = 1;
+  has_call = TARGET_SHMEDIA ? ! leaf_function_p () : pr_live;
   for (count = 0, reg = FIRST_PSEUDO_REGISTER - 1; reg >= 0; reg--)
     {
       if (reg == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
@@ -4838,7 +4911,9 @@ calc_live_regs (live_regs_mask)
 	     (regs_ever_live[reg]
 	      || (call_used_regs[reg]
 		  && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG)
-		  && pr_live))
+		  && has_call)
+	      || (has_call && REGISTER_NATURAL_MODE (reg) == SImode
+		  && (GENERAL_REGISTER_P (reg) || TARGET_REGISTER_P (reg))))
 	     && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
 	     && reg != RETURN_ADDRESS_POINTER_REGNUM
 	     && reg != T_REG && reg != GBR_REG
@@ -4848,13 +4923,17 @@ calc_live_regs (live_regs_mask)
 	     (TARGET_SHCOMPACT
 	      && flag_pic
 	      && current_function_args_info.call_cookie
-	      && reg == PIC_OFFSET_TABLE_REGNUM)
+	      && reg == (int) PIC_OFFSET_TABLE_REGNUM)
 	     || (regs_ever_live[reg] && ! call_used_regs[reg])
 	     || (current_function_calls_eh_return
-		 && (reg == EH_RETURN_DATA_REGNO (0)
-		     || reg == EH_RETURN_DATA_REGNO (1)
-		     || reg == EH_RETURN_DATA_REGNO (2)
-		     || reg == EH_RETURN_DATA_REGNO (3)))))
+		 && (reg == (int) EH_RETURN_DATA_REGNO (0)
+		     || reg == (int) EH_RETURN_DATA_REGNO (1)
+		     || reg == (int) EH_RETURN_DATA_REGNO (2)
+		     || reg == (int) EH_RETURN_DATA_REGNO (3)))
+	     || ((reg == MACL_REG || reg == MACH_REG)
+		 && regs_ever_live[reg]
+		 && sh_cfun_attr_renesas_p ())
+	     ))
 	{
 	  SET_HARD_REG_BIT (*live_regs_mask, reg);
 	  count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
@@ -4891,6 +4970,19 @@ calc_live_regs (live_regs_mask)
 	  SET_HARD_REG_BIT (*live_regs_mask, reg);
 	  count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
 	}
+  /* If this is an interrupt handler, we don't have any call-clobbered
+     registers we can conveniently use for target register save/restore.
+     Make sure we save at least one general purpose register when we need
+     to save target registers.  */
+  if (interrupt_handler
+      && hard_regs_intersect_p (live_regs_mask,
+				&reg_class_contents[TARGET_REGS])
+      && ! hard_regs_intersect_p (live_regs_mask,
+				  &reg_class_contents[GENERAL_REGS]))
+    {
+      SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
+      count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
+    }
 
   return count;
 }
@@ -4921,6 +5013,9 @@ sh_media_register_for_return ()
 
   if (! current_function_is_leaf)
     return -1;
+  if (lookup_attribute ("interrupt_handler",
+			DECL_ATTRIBUTES (current_function_decl)))
+    return -1;
 
   tr0_used = flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM];
 
@@ -4931,6 +5026,130 @@ sh_media_register_for_return ()
   return -1;
 }
 
+/* The maximum registers we need to save are:
+   - 62 general purpose registers (r15 is stack pointer, r63 is zero)
+   - 32 floating point registers (for each pair, we save none,
+         one single precision value, or a double precision value).
+   -  8 target registers
+   -  add 1 entry for a delimiter.  */
+#define MAX_SAVED_REGS (62+32+8)
+
+typedef struct save_entry_s
+{
+  unsigned char reg;
+  unsigned char mode;
+  short offset;
+} save_entry;
+
+#define MAX_TEMPS 4
+
+/* There will be a delimiter entry with VOIDmode both at the start and the
+   end of a filled in schedule.  The end delimiter has the offset of the
+   save with the smallest (i.e. most negative) offset.  */
+typedef struct save_schedule_s
+{
+  save_entry entries[MAX_SAVED_REGS + 2];
+  int temps[MAX_TEMPS+1];
+} save_schedule;
+
+/* Fill in SCHEDULE according to LIVE_REGS_MASK.  If RESTORE is nonzero,
+   use reverse order.  Returns the last entry written to (not counting
+   the delimiter).  OFFSET_BASE is a number to be added to all offset
+   entries.  */
+   
+static save_entry *
+sh5_schedule_saves (HARD_REG_SET *live_regs_mask, save_schedule *schedule,
+		    int offset_base)
+{
+  int align, i;
+  save_entry *entry = schedule->entries;
+  int tmpx = 0;
+  int offset;
+
+  if (! current_function_interrupt)
+    for (i = FIRST_GENERAL_REG; tmpx < MAX_TEMPS && i <= LAST_GENERAL_REG; i++)
+      if (call_used_regs[i] && ! fixed_regs[i] && i != PR_MEDIA_REG
+	  && ! FUNCTION_ARG_REGNO_P (i)
+	  && i != FIRST_RET_REG
+	  && ! (current_function_needs_context && i == STATIC_CHAIN_REGNUM)
+	  && ! (current_function_calls_eh_return
+		&& (i == EH_RETURN_STACKADJ_REGNO
+		    || ((unsigned)i <= EH_RETURN_DATA_REGNO (0)
+			&& (unsigned)i >= EH_RETURN_DATA_REGNO (3)))))
+	schedule->temps[tmpx++] = i;
+  entry->reg = -1;
+  entry->mode = VOIDmode;
+  entry->offset = offset_base;
+  entry++;
+  /* We loop twice: first, we save 8-byte aligned registers in the
+     higher addresses, that are known to be aligned.  Then, we
+     proceed to saving 32-bit registers that don't need 8-byte
+     alignment.
+     If this is an interrupt function, all registers that need saving
+     need to be saved in full.  moreover, we need to postpone saving
+     target registers till we have saved some general purpose registers
+     we can then use as scratch registers.  */
+  offset = offset_base;
+  for (align = 1; align >= 0; align--)
+    {
+      for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
+	if (TEST_HARD_REG_BIT (*live_regs_mask, i))
+	  {
+	    enum machine_mode mode = REGISTER_NATURAL_MODE (i);
+	    int reg = i;
+
+	    if (current_function_interrupt)
+	      {
+		if (TARGET_REGISTER_P (i))
+		  continue;
+		if (GENERAL_REGISTER_P (i))
+		  mode = DImode;
+	      }
+	    if (mode == SFmode && (i % 2) == 1
+		&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
+		&& (TEST_HARD_REG_BIT (*live_regs_mask, (i ^ 1))))
+	      {
+		mode = DFmode;
+		i--;
+		reg--;
+	      }
+
+	    /* If we're doing the aligned pass and this is not aligned,
+	       or we're doing the unaligned pass and this is aligned,
+	       skip it.  */
+	    if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT) == 0)
+		!= align)
+	      continue;
+
+	    if (current_function_interrupt
+		&& GENERAL_REGISTER_P (i)
+		&& tmpx < MAX_TEMPS)
+	      schedule->temps[tmpx++] = i;
+
+	    offset -= GET_MODE_SIZE (mode);
+	    entry->reg = i;
+	    entry->mode = mode;
+	    entry->offset = offset;
+	    entry++;
+	  }
+      if (align && current_function_interrupt)
+	for (i = LAST_TARGET_REG; i >= FIRST_TARGET_REG; i--)
+	  if (TEST_HARD_REG_BIT (*live_regs_mask, i))
+	    {
+	      offset -= GET_MODE_SIZE (DImode);
+	      entry->reg = i;
+	      entry->mode = DImode;
+	      entry->offset = offset;
+	      entry++;
+	    }
+    }
+  entry->reg = -1;
+  entry->mode = VOIDmode;
+  entry->offset = offset;
+  schedule->temps[tmpx] = -1;
+  return entry - 1;
+}
+
 void
 sh_expand_prologue ()
 {
@@ -4945,7 +5164,7 @@ sh_expand_prologue ()
      and partially on the stack, e.g. a large structure.  */
   output_stack_adjust (-current_function_pretend_args_size
 		       - current_function_args_info.stack_regs * 8,
-		       stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
+		       stack_pointer_rtx, 0, NULL);
 
   extra_push = 0;
 
@@ -4991,6 +5210,9 @@ sh_expand_prologue ()
 	  rtx insn = emit_move_insn (gen_rtx_REG (DImode, tr),
 				     gen_rtx_REG (DImode, PR_MEDIA_REG));
 
+	  /* ??? We should suppress saving pr when we don't need it, but this
+	     is tricky because of builtin_return_address.  */
+
 	  /* If this function only exits with sibcalls, this copy
 	     will be flagged as dead.  */
 	  REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
@@ -5003,7 +5225,8 @@ sh_expand_prologue ()
   if (current_function_stdarg)
     {
       /* This is not used by the SH2E calling convention  */
-      if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 && ! TARGET_HITACHI)
+      if (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5
+	  && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
 	{
 	  /* Push arg regs as if they'd been provided by caller in stack.  */
 	  for (i = 0; i < NPARM_REGS(SImode); i++)
@@ -5034,14 +5257,19 @@ sh_expand_prologue ()
     
   if (TARGET_SH5)
     {
-      int i;
-      int offset;
-      int align;
-      rtx r0 = gen_rtx_REG (Pmode, R0_REG);
+      int offset_base, offset;
+      rtx r0 = NULL_RTX;
       int offset_in_r0 = -1;
       int sp_in_r0 = 0;
       int tregs_space = shmedia_target_regs_stack_adjust (&live_regs_mask);
       int total_size, save_size;
+      save_schedule schedule;
+      save_entry *entry;
+      int *tmp_pnt;
+
+      if (call_used_regs[R0_REG] && ! fixed_regs[R0_REG]
+	  && ! current_function_interrupt)
+	r0 = gen_rtx_REG (Pmode, R0_REG);
 
       /* D is the actual number of bytes that we need for saving registers,
 	 however, in initial_elimination_offset we have committed to using
@@ -5067,146 +5295,153 @@ sh_expand_prologue ()
 		  && total_size <= 2044)))
 	d_rounding = total_size - save_size;
 
-      offset = d + d_rounding;
+      offset_base = d + d_rounding;
 
       output_stack_adjust (-(save_size + d_rounding), stack_pointer_rtx,
-			   1, frame_insn);
-
-      /* We loop twice: first, we save 8-byte aligned registers in the
-	 higher addresses, that are known to be aligned.  Then, we
-	 proceed to saving 32-bit registers that don't need 8-byte
-	 alignment.  */
-      /* Note that if you change this code in a way that affects where
-	 the return register is saved, you have to update not only
-	 sh_expand_epilogue, but also sh_set_return_address.  */
-      for (align = 1; align >= 0; align--)
-	for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
-	  if (TEST_HARD_REG_BIT (live_regs_mask, i))
-	    {
-	      enum machine_mode mode = REGISTER_NATURAL_MODE (i);
-	      int reg = i;
-	      rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
+			   0, NULL);
 
-	      if (mode == SFmode && (i % 2) == 1
-		  && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
-		  && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
-		{
-		  mode = DFmode;
-		  i--;
-		  reg--;
-		}
-		
-	      /* If we're doing the aligned pass and this is not aligned,
-		 or we're doing the unaligned pass and this is aligned,
-		 skip it.  */
-	      if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
-		   == 0) != align)
-		continue;
+      sh5_schedule_saves (&live_regs_mask, &schedule, offset_base);
+      tmp_pnt = schedule.temps;
+      for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
+        {
+	  enum machine_mode mode = entry->mode;
+	  int reg = entry->reg;
+	  rtx reg_rtx, mem_rtx, pre_dec = NULL_RTX;
 
-	      offset -= GET_MODE_SIZE (mode);
+	  offset = entry->offset;
 
-	      reg_rtx = gen_rtx_REG (mode, reg);
+	  reg_rtx = gen_rtx_REG (mode, reg);
 
-	      mem_rtx = gen_rtx_MEM (mode,
-				     gen_rtx_PLUS (Pmode,
-						   stack_pointer_rtx,
-						   GEN_INT (offset)));
+	  mem_rtx = gen_rtx_MEM (mode,
+				 gen_rtx_PLUS (Pmode,
+					       stack_pointer_rtx,
+					       GEN_INT (offset)));
 
-	      GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
+	  GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_pre_dec);
 
-	      mem_rtx = NULL_RTX;
+	  if (! r0)
+	    abort ();
+	  mem_rtx = NULL_RTX;
 
-	    try_pre_dec:
-	      do
-		if (HAVE_PRE_DECREMENT
-		    && (offset_in_r0 - offset == GET_MODE_SIZE (mode)
-			|| mem_rtx == NULL_RTX
-			|| i == PR_REG || SPECIAL_REGISTER_P (i)))
-		  {
-		    pre_dec = gen_rtx_MEM (mode,
-					   gen_rtx_PRE_DEC (Pmode, r0));
+	try_pre_dec:
+	  do
+	    if (HAVE_PRE_DECREMENT
+		&& (offset_in_r0 - offset == GET_MODE_SIZE (mode)
+		    || mem_rtx == NULL_RTX
+		    || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
+	      {
+		pre_dec = gen_rtx_MEM (mode,
+				       gen_rtx_PRE_DEC (Pmode, r0));
 
-		    GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
-					      pre_dec_ok);
+		GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (pre_dec, 0),
+					  pre_dec_ok);
 
-		    pre_dec = NULL_RTX;
+		pre_dec = NULL_RTX;
 
-		    break;
+		break;
 
-		  pre_dec_ok:
-		    mem_rtx = NULL_RTX;
-		    offset += GET_MODE_SIZE (mode);
-		  }
-	      while (0);
+	      pre_dec_ok:
+		mem_rtx = NULL_RTX;
+		offset += GET_MODE_SIZE (mode);
+	      }
+	  while (0);
 
-	      if (mem_rtx != NULL_RTX)
-		goto addr_ok;
+	  if (mem_rtx != NULL_RTX)
+	    goto addr_ok;
 
-	      if (offset_in_r0 == -1)
-		{
-		  emit_move_insn (r0, GEN_INT (offset));
-		  offset_in_r0 = offset;
-		}
-	      else if (offset != offset_in_r0)
+	  if (offset_in_r0 == -1)
+	    {
+	      emit_move_insn (r0, GEN_INT (offset));
+	      offset_in_r0 = offset;
+	    }
+	  else if (offset != offset_in_r0)
+	    {
+	      emit_move_insn (r0,
+			      gen_rtx_PLUS
+			      (Pmode, r0,
+			       GEN_INT (offset - offset_in_r0)));
+	      offset_in_r0 += offset - offset_in_r0;
+	    }
+					      
+	  if (pre_dec != NULL_RTX)
+	    {
+	      if (! sp_in_r0)
 		{
 		  emit_move_insn (r0,
 				  gen_rtx_PLUS
-				  (Pmode, r0,
-				   GEN_INT (offset - offset_in_r0)));
-		  offset_in_r0 += offset - offset_in_r0;
+				  (Pmode, r0, stack_pointer_rtx));
+		  sp_in_r0 = 1;
 		}
-						  
-	      if (pre_dec != NULL_RTX)
-		{
-		  if (! sp_in_r0)
-		    {
-		      emit_move_insn (r0,
-				      gen_rtx_PLUS
-				      (Pmode, r0, stack_pointer_rtx));
-		      sp_in_r0 = 1;
-		    }
 
-		  offset -= GET_MODE_SIZE (mode);
-		  offset_in_r0 -= GET_MODE_SIZE (mode);
+	      offset -= GET_MODE_SIZE (mode);
+	      offset_in_r0 -= GET_MODE_SIZE (mode);
 
-		  mem_rtx = pre_dec;
-		}
-	      else if (sp_in_r0)
-		mem_rtx = gen_rtx_MEM (mode, r0);
-	      else
-		mem_rtx = gen_rtx_MEM (mode,
-				       gen_rtx_PLUS (Pmode,
-						     stack_pointer_rtx,
-						     r0));
-
-	      /* We must not use an r0-based address for target-branch
-		 registers or for special registers without pre-dec
-		 memory addresses, since we store their values in r0
-		 first.  */
-	      if (TARGET_REGISTER_P (i)
-		  || ((i == PR_REG || SPECIAL_REGISTER_P (i))
-		      && mem_rtx != pre_dec))
-		abort ();
-
-	    addr_ok:
-	      if (TARGET_REGISTER_P (i)
-		  || ((i == PR_REG || SPECIAL_REGISTER_P (i))
-		      && mem_rtx != pre_dec))
-		{
-		  rtx r0mode = gen_rtx_REG (GET_MODE (reg_rtx), R0_REG);
+	      mem_rtx = pre_dec;
+	    }
+	  else if (sp_in_r0)
+	    mem_rtx = gen_rtx_MEM (mode, r0);
+	  else
+	    mem_rtx = gen_rtx_MEM (mode,
+				   gen_rtx_PLUS (Pmode,
+						 stack_pointer_rtx,
+						 r0));
+
+	  /* We must not use an r0-based address for target-branch
+	     registers or for special registers without pre-dec
+	     memory addresses, since we store their values in r0
+	     first.  */
+	  if (TARGET_REGISTER_P (reg)
+	      || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
+		  && mem_rtx != pre_dec))
+	    abort ();
 
-		  emit_move_insn (r0mode, reg_rtx);
+	addr_ok:
+	  if (TARGET_REGISTER_P (reg)
+	      || ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
+		  && mem_rtx != pre_dec))
+	    {
+	      rtx tmp_reg = gen_rtx_REG (GET_MODE (reg_rtx), *tmp_pnt);
+
+	      emit_move_insn (tmp_reg, reg_rtx);
 
+	      if (REGNO (tmp_reg) == R0_REG)
+		{
 		  offset_in_r0 = -1;
 		  sp_in_r0 = 0;
-
-		  reg_rtx = r0mode;
+		  if (refers_to_regno_p (R0_REG, R0_REG+1, mem_rtx, (rtx *) 0))
+		    abort ();
 		}
 
-	      emit_move_insn (mem_rtx, reg_rtx);
+	      if (*++tmp_pnt <= 0)
+		tmp_pnt = schedule.temps;
+
+	      reg_rtx = tmp_reg;
 	    }
+	  {
+	    rtx insn;
+
+	    /* Mark as interesting for dwarf cfi generator */
+	    insn = emit_move_insn (mem_rtx, reg_rtx);
+	    RTX_FRAME_RELATED_P (insn) = 1;
 
-      if (offset != d_rounding)
+	    if (TARGET_SHCOMPACT && (offset_in_r0 != -1)) 
+	      {
+		rtx reg_rtx = gen_rtx_REG (mode, reg);
+		rtx set, note_rtx;
+		rtx mem_rtx = gen_rtx_MEM (mode,
+					   gen_rtx_PLUS (Pmode,
+							 stack_pointer_rtx,
+							 GEN_INT (offset)));
+
+		set = gen_rtx_SET (VOIDmode, mem_rtx, reg_rtx);
+		note_rtx = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, set,
+					      REG_NOTES (insn));
+		REG_NOTES (insn) = note_rtx;
+	      }
+	  }
+	}
+
+      if (entry->offset != d_rounding)
 	abort ();
     }
   else
@@ -5258,7 +5493,7 @@ sh_expand_prologue ()
   target_flags = save_flags;
 
   output_stack_adjust (-rounded_frame_size (d) + d_rounding,
-		       stack_pointer_rtx, TARGET_SH5 ? 0 : 1, frame_insn);
+		       stack_pointer_rtx, 0, NULL);
 
   if (frame_pointer_needed)
     frame_insn (GEN_MOV (frame_pointer_rtx, stack_pointer_rtx));
@@ -5318,7 +5553,7 @@ sh_expand_epilogue ()
 
   if (frame_pointer_needed)
     {
-      output_stack_adjust (frame_size, frame_pointer_rtx, 7, emit_insn);
+      output_stack_adjust (frame_size, frame_pointer_rtx, 1, &live_regs_mask);
 
       /* We must avoid moving the stack pointer adjustment past code
 	 which reads from the local frame, else an interrupt could
@@ -5334,7 +5569,7 @@ sh_expand_epilogue ()
 	 occur after the SP adjustment and clobber data in the local
 	 frame.  */
       emit_insn (gen_blockage ());
-      output_stack_adjust (frame_size, stack_pointer_rtx, 7, emit_insn);
+      output_stack_adjust (frame_size, stack_pointer_rtx, 1, &live_regs_mask);
     }
 
   if (SHMEDIA_REGS_STACK_ADJUST ())
@@ -5355,143 +5590,129 @@ sh_expand_epilogue ()
     emit_insn (gen_toggle_sz ());
   if (TARGET_SH5)
     {
-      int offset = d_rounding;
+      int offset_base, offset;
       int offset_in_r0 = -1;
       int sp_in_r0 = 0;
-      int align;
       rtx r0 = gen_rtx_REG (Pmode, R0_REG);
-      int tmp_regno = R20_REG;
-      
-      /* We loop twice: first, we save 8-byte aligned registers in the
-	 higher addresses, that are known to be aligned.  Then, we
-	 proceed to saving 32-bit registers that don't need 8-byte
-	 alignment.  */
-      for (align = 0; align <= 1; align++)
-	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	  if (TEST_HARD_REG_BIT (live_regs_mask, i))
-	    {
-	      enum machine_mode mode = REGISTER_NATURAL_MODE (i);
-	      int reg = i;
-	      rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
+      save_schedule schedule;
+      save_entry *entry;
+      int *tmp_pnt;
+
+      entry = sh5_schedule_saves (&live_regs_mask, &schedule, d_rounding);
+      offset_base = -entry[1].offset + d_rounding;
+      tmp_pnt = schedule.temps;
+      for (; entry->mode != VOIDmode; entry--)
+	{
+	  enum machine_mode mode = entry->mode;
+	  int reg = entry->reg;
+	  rtx reg_rtx, mem_rtx, post_inc = NULL_RTX, insn;
 
-	      if (mode == SFmode && (i % 2) == 0
-		  && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
-		  && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
-		{
-		  mode = DFmode;
-		  i++;
-		}
+	  offset = offset_base + entry->offset;
+	  reg_rtx = gen_rtx_REG (mode, reg);
 
-	      /* If we're doing the aligned pass and this is not aligned,
-		 or we're doing the unaligned pass and this is aligned,
-		 skip it.  */
-	      if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
-		   == 0) != align)
-		continue;
+	  mem_rtx = gen_rtx_MEM (mode,
+				 gen_rtx_PLUS (Pmode,
+					       stack_pointer_rtx,
+					       GEN_INT (offset)));
 
-	      reg_rtx = gen_rtx_REG (mode, reg);
+	  GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
 
-	      mem_rtx = gen_rtx_MEM (mode,
-				     gen_rtx_PLUS (Pmode,
-						   stack_pointer_rtx,
-						   GEN_INT (offset)));
+	  mem_rtx = NULL_RTX;
 
-	      GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (mem_rtx, 0), try_post_inc);
-
-	      mem_rtx = NULL_RTX;
+	try_post_inc:
+	  do
+	    if (HAVE_POST_INCREMENT
+		&& (offset == offset_in_r0
+		    || (offset + GET_MODE_SIZE (mode) != d + d_rounding
+			&& mem_rtx == NULL_RTX)
+		    || reg == PR_REG || SPECIAL_REGISTER_P (reg)))
+	      {
+		post_inc = gen_rtx_MEM (mode,
+					gen_rtx_POST_INC (Pmode, r0));
 
-	    try_post_inc:
-	      do
-		if (HAVE_POST_INCREMENT
-		    && (offset == offset_in_r0
-			|| (offset + GET_MODE_SIZE (mode) != d + d_rounding
-			    && mem_rtx == NULL_RTX)
-			|| i == PR_REG || SPECIAL_REGISTER_P (i)))
-		  {
-		    post_inc = gen_rtx_MEM (mode,
-					    gen_rtx_POST_INC (Pmode, r0));
+		GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
+					  post_inc_ok);
 
-		    GO_IF_LEGITIMATE_ADDRESS (mode, XEXP (post_inc, 0),
-					      post_inc_ok);
+		post_inc = NULL_RTX;
 
-		    post_inc = NULL_RTX;
+		break;
+		
+	      post_inc_ok:
+		mem_rtx = NULL_RTX;
+	      }
+	  while (0);
+	  
+	  if (mem_rtx != NULL_RTX)
+	    goto addr_ok;
 
-		    break;
-		    
-		  post_inc_ok:
-		    mem_rtx = NULL_RTX;
-		  }
-	      while (0);
+	  if (offset_in_r0 == -1)
+	    {
+	      emit_move_insn (r0, GEN_INT (offset));
+	      offset_in_r0 = offset;
+	    }
+	  else if (offset != offset_in_r0)
+	    {
+	      emit_move_insn (r0,
+			      gen_rtx_PLUS
+			      (Pmode, r0,
+			       GEN_INT (offset - offset_in_r0)));
+	      offset_in_r0 += offset - offset_in_r0;
+	    }
 	      
-	      if (mem_rtx != NULL_RTX)
-		goto addr_ok;
-
-	      if (offset_in_r0 == -1)
-		{
-		  emit_move_insn (r0, GEN_INT (offset));
-		  offset_in_r0 = offset;
-		}
-	      else if (offset != offset_in_r0)
+	  if (post_inc != NULL_RTX)
+	    {
+	      if (! sp_in_r0)
 		{
 		  emit_move_insn (r0,
 				  gen_rtx_PLUS
-				  (Pmode, r0,
-				   GEN_INT (offset - offset_in_r0)));
-		  offset_in_r0 += offset - offset_in_r0;
+				  (Pmode, r0, stack_pointer_rtx));
+		  sp_in_r0 = 1;
 		}
-		  
-	      if (post_inc != NULL_RTX)
-		{
-		  if (! sp_in_r0)
-		    {
-		      emit_move_insn (r0,
-				      gen_rtx_PLUS
-				      (Pmode, r0, stack_pointer_rtx));
-		      sp_in_r0 = 1;
-		    }
-		  
-		  mem_rtx = post_inc;
+	      
+	      mem_rtx = post_inc;
 
-		  offset_in_r0 += GET_MODE_SIZE (mode);
-		}
-	      else if (sp_in_r0)
-		mem_rtx = gen_rtx_MEM (mode, r0);
-	      else
-		mem_rtx = gen_rtx_MEM (mode,
-				       gen_rtx_PLUS (Pmode,
-						     stack_pointer_rtx,
-						     r0));
-
-	      if ((i == PR_REG || SPECIAL_REGISTER_P (i))
-		  && mem_rtx != post_inc)
-		abort ();
-
-	    addr_ok:
-	      if ((i == PR_REG || SPECIAL_REGISTER_P (i))
-		  && mem_rtx != post_inc)
-		{
-		  insn = emit_move_insn (r0, mem_rtx);
-		  mem_rtx = r0;
-		}
-	      else if (TARGET_REGISTER_P (i))
-		{
-		  rtx tmp_reg = gen_rtx_REG (mode, tmp_regno);
-
-		  /* Give the scheduler a bit of freedom by using R20..R23
-		     in a round-robin fashion.  Don't use R1 here because
-		     we want to use it for EH_RETURN_STACKADJ_RTX.  */
-		  insn = emit_move_insn (tmp_reg, mem_rtx);
-		  mem_rtx = tmp_reg;
-		  if (++tmp_regno > R23_REG)
-		    tmp_regno = R20_REG;
-		}
+	      offset_in_r0 += GET_MODE_SIZE (mode);
+	    }
+	  else if (sp_in_r0)
+	    mem_rtx = gen_rtx_MEM (mode, r0);
+	  else
+	    mem_rtx = gen_rtx_MEM (mode,
+				   gen_rtx_PLUS (Pmode,
+						 stack_pointer_rtx,
+						 r0));
 
-	      insn = emit_move_insn (reg_rtx, mem_rtx);
+	  if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
+	      && mem_rtx != post_inc)
+	    abort ();
 
-	      offset += GET_MODE_SIZE (mode);
+	addr_ok:
+	  if ((reg == PR_REG || SPECIAL_REGISTER_P (reg))
+	      && mem_rtx != post_inc)
+	    {
+	      insn = emit_move_insn (r0, mem_rtx);
+	      mem_rtx = r0;
 	    }
+	  else if (TARGET_REGISTER_P (reg))
+	    {
+	      rtx tmp_reg = gen_rtx_REG (mode, *tmp_pnt);
+
+	      /* Give the scheduler a bit of freedom by using up to
+		 MAX_TEMPS registers in a round-robin fashion.  */
+	      insn = emit_move_insn (tmp_reg, mem_rtx);
+	      mem_rtx = tmp_reg;
+	      if (*++tmp_pnt < 0)
+		tmp_pnt = schedule.temps;
+	    }
+
+	  insn = emit_move_insn (reg_rtx, mem_rtx);
+	  if (reg == PR_MEDIA_REG && sh_media_register_for_return () >= 0)
+	    /* This is dead, unless we return with a sibcall.  */
+	    REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
+						  const0_rtx,
+						  REG_NOTES (insn));
+	}
 
-      if (offset != d + d_rounding)
+      if (entry->offset + offset_base != d + d_rounding)
 	abort ();
     }
   else /* ! TARGET_SH5 */
@@ -5521,7 +5742,7 @@ sh_expand_epilogue ()
   output_stack_adjust (extra_push + current_function_pretend_args_size
 		       + save_size + d_rounding
 		       + current_function_args_info.stack_regs * 8,
-		       stack_pointer_rtx, 7, emit_insn);
+		       stack_pointer_rtx, 1, NULL);
 
   if (current_function_calls_eh_return)
     emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
@@ -5566,7 +5787,6 @@ sh_set_return_address (ra, tmp)
 {
   HARD_REG_SET live_regs_mask;
   int d;
-  int d_rounding = 0;
   int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
   int pr_offset;
 
@@ -5598,56 +5818,26 @@ sh_set_return_address (ra, tmp)
 
   if (TARGET_SH5)
     {
-      int i;
       int offset;
-      int align;
+      save_schedule schedule;
+      save_entry *entry;
       
-      if (d % (STACK_BOUNDARY / BITS_PER_UNIT))
-	d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
-		      - d % (STACK_BOUNDARY / BITS_PER_UNIT));
-
-      offset = 0;
-
-      /* We loop twice: first, we save 8-byte aligned registers in the
-	 higher addresses, that are known to be aligned.  Then, we
-	 proceed to saving 32-bit registers that don't need 8-byte
-	 alignment.  */
-      for (align = 0; align <= 1; align++)
-	for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
-	  if (TEST_HARD_REG_BIT (live_regs_mask, i))
-	    {
-	      enum machine_mode mode = REGISTER_NATURAL_MODE (i);
-
-	      if (mode == SFmode && (i % 2) == 0
-		  && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
-		  && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
-		{
-		  mode = DFmode;
-		  i++;
-		}
-
-	      /* If we're doing the aligned pass and this is not aligned,
-		 or we're doing the unaligned pass and this is aligned,
-		 skip it.  */
-	      if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
-		   == 0) != align)
-		continue;
-
-	      if (i == pr_reg)
-		goto found;
-
-	      offset += GET_MODE_SIZE (mode);
-	    }
+      entry = sh5_schedule_saves (&live_regs_mask, &schedule, 0);
+      offset = entry[1].offset;
+      for (; entry->mode != VOIDmode; entry--)
+	if (entry->reg == pr_reg)
+	  goto found;
 
       /* We can't find pr register.  */
       abort ();
 
     found:
-      pr_offset = (rounded_frame_size (d) - d_rounding + offset
+      offset = entry->offset - offset;
+      pr_offset = (rounded_frame_size (d) + offset
 		   + SHMEDIA_REGS_STACK_ADJUST ());
     }
   else
-    pr_offset = rounded_frame_size (d) - d_rounding;
+    pr_offset = rounded_frame_size (d);
 
   emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
   emit_insn (GEN_ADD3 (tmp, tmp, frame_pointer_rtx));
@@ -5668,7 +5858,7 @@ sh_output_function_epilogue (file, size)
   sp_switch = NULL_RTX;
 }
 
-rtx
+static rtx
 sh_builtin_saveregs ()
 {
   /* First unnamed integer register.  */
@@ -5818,7 +6008,8 @@ sh_build_va_list ()
   tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
   tree record;
 
-  if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
+  if (TARGET_SH5 || (! TARGET_SH2E && ! TARGET_SH4)
+      || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
     return ptr_type_node;
 
   record = make_node (RECORD_TYPE);
@@ -5872,7 +6063,8 @@ sh_va_start (valist, nextarg)
       return;
     }
 
-  if ((! TARGET_SH2E && ! TARGET_SH4) || TARGET_HITACHI)
+  if ((! TARGET_SH2E && ! TARGET_SH4)
+      || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
     {
       std_expand_builtin_va_start (valist, nextarg);
       return;
@@ -5951,7 +6143,8 @@ sh_va_arg (valist, type)
   if (pass_by_ref)
     type = build_pointer_type (type);
 
-  if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4) && ! TARGET_HITACHI)
+  if (! TARGET_SH5 && (TARGET_SH2E || TARGET_SH4)
+      && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
     {
       tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
       tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
@@ -6135,6 +6328,343 @@ sh_va_arg (valist, type)
   return result;
 }
 
+static bool
+sh_promote_prototypes (type)
+     tree type;
+{
+  if (TARGET_HITACHI)
+    return 0;
+  if (! type)
+    return 1;
+  return ! sh_attr_renesas_p (type);
+}
+
+/* Define where to put the arguments to a function.
+   Value is zero to push the argument on the stack,
+   or a hard register in which to store the argument.
+
+   MODE is the argument's machine mode.
+   TYPE is the data type of the argument (as a tree).
+    This is null for libcalls where that information may
+    not be available.
+   CUM is a variable of type CUMULATIVE_ARGS which gives info about
+    the preceding args and about the function being called.
+   NAMED is nonzero if this argument is a named parameter
+    (otherwise it is an extra parameter matching an ellipsis).
+
+   On SH the first args are normally in registers
+   and the rest are pushed.  Any arg that starts within the first
+   NPARM_REGS words is at least partially passed in a register unless
+   its data type forbids.  */
+
+
+rtx
+sh_function_arg (ca, mode, type, named)
+     CUMULATIVE_ARGS *ca;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+  if (! TARGET_SH5 && mode == VOIDmode)
+    return GEN_INT (ca->renesas_abi ? 1 : 0);
+
+  if (! TARGET_SH5
+      && PASS_IN_REG_P (*ca, mode, type)
+      && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
+    {
+      int regno;
+
+      if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
+	  && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG (*ca, mode) & 1)))
+	{
+	  rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
+				      gen_rtx_REG (SFmode,
+						   BASE_ARG_REG (mode)
+						   + (ROUND_REG (*ca, mode) ^ 1)),
+				      const0_rtx);
+	  rtx r2 = gen_rtx_EXPR_LIST(VOIDmode,
+				     gen_rtx_REG (SFmode,
+						  BASE_ARG_REG (mode)
+						  + ((ROUND_REG (*ca, mode) + 1) ^ 1)),
+				     GEN_INT (4));
+	  return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
+	}
+
+     /* If the alignment of a DF value causes an SF register to be
+	skipped, we will use that skipped register for the next SF
+	value.  */
+      if ((TARGET_HITACHI || ca->renesas_abi)
+	  && ca->free_single_fp_reg
+	  && mode == SFmode)
+	return gen_rtx_REG (mode, ca->free_single_fp_reg);
+
+      regno = (BASE_ARG_REG (mode) + ROUND_REG (*ca, mode))
+	       ^ (mode == SFmode && TARGET_SH4
+		  && TARGET_LITTLE_ENDIAN != 0
+		  && ! TARGET_HITACHI && ! ca->renesas_abi);
+      return gen_rtx_REG (mode, regno);
+
+    }
+  
+  if (TARGET_SH5)
+    {
+      if (mode == VOIDmode && TARGET_SHCOMPACT)
+	return GEN_INT (ca->call_cookie);
+
+      /* The following test assumes unnamed arguments are promoted to
+	 DFmode.  */
+      if (mode == SFmode && ca->free_single_fp_reg)
+	return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode, ca->free_single_fp_reg);
+
+      if ((GET_SH_ARG_CLASS (mode) == SH_ARG_FLOAT)
+	  && (named || ! ca->prototype_p)
+	  && ca->arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))
+	{
+	  if (! ca->prototype_p && TARGET_SHMEDIA)
+	    return SH5_PROTOTYPELESS_FLOAT_ARG (*ca, mode);
+
+	  return SH5_PROTOTYPED_FLOAT_ARG (*ca, mode,
+					   FIRST_FP_PARM_REG
+					   + ca->arg_count[(int) SH_ARG_FLOAT]);
+	}
+
+      if (ca->arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)
+	  && (! TARGET_SHCOMPACT
+	      || (! SHCOMPACT_FORCE_ON_STACK (mode, type)
+		  && ! SH5_WOULD_BE_PARTIAL_NREGS (*ca, mode,
+						   type, named))))
+	{
+	  return gen_rtx_REG (mode, (FIRST_PARM_REG
+				       + ca->arg_count[(int) SH_ARG_INT]));
+	}
+
+      return 0;
+    }
+
+  return 0;
+}
+ 
+/* Update the data in CUM to advance over an argument
+   of mode MODE and data type TYPE.
+   (TYPE is null for libcalls where that information may not be
+   available.)  */
+
+void
+sh_function_arg_advance (ca, mode, type, named)
+     CUMULATIVE_ARGS *ca;
+     enum machine_mode mode;
+     tree type;
+     int named;
+{
+ if (ca->force_mem)
+   ca->force_mem = 0;
+ else if (TARGET_SH5)
+   {
+     tree type2 = (ca->byref && type
+		   ? TREE_TYPE (type)
+ 		   : type);
+     enum machine_mode mode2 = (ca->byref && type
+				? TYPE_MODE (type2)
+				: mode);
+     int dwords = ((ca->byref
+		    ? ca->byref
+		    : mode2 == BLKmode
+		    ? int_size_in_bytes (type2)
+		    : GET_MODE_SIZE (mode2)) + 7) / 8;
+     int numregs = MIN (dwords, NPARM_REGS (SImode)
+			- ca->arg_count[(int) SH_ARG_INT]);
+
+     if (numregs)
+       {
+	 ca->arg_count[(int) SH_ARG_INT] += numregs;
+	 if (TARGET_SHCOMPACT
+	     && SHCOMPACT_FORCE_ON_STACK (mode2, type2))
+	   {
+	     ca->call_cookie
+	       |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
+				       - numregs, 1);
+	     /* N.B. We want this also for outgoing.   */
+	     ca->stack_regs += numregs;
+	   }
+	 else if (ca->byref)
+	   {
+	     if (! ca->outgoing)
+	       ca->stack_regs += numregs;
+	     ca->byref_regs += numregs;
+	     ca->byref = 0;
+	     do
+	       ca->call_cookie
+		 |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
+					 - numregs, 2);
+	     while (--numregs);
+	     ca->call_cookie
+	       |= CALL_COOKIE_INT_REG (ca->arg_count[(int) SH_ARG_INT]
+				       - 1, 1);
+	   }
+	 else if (dwords > numregs)
+	   {
+	     int pushregs = numregs;
+
+	     if (TARGET_SHCOMPACT)
+	       ca->stack_regs += numregs;
+	     while (pushregs < NPARM_REGS (SImode) - 1
+		    && (CALL_COOKIE_INT_REG_GET
+			(ca->call_cookie,
+			NPARM_REGS (SImode) - pushregs)
+			== 1))
+	       {
+		 ca->call_cookie
+		   &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode)
+					     - pushregs, 1);
+		 pushregs++;
+	       }
+	     if (numregs == NPARM_REGS (SImode))
+	       ca->call_cookie
+		 |= CALL_COOKIE_INT_REG (0, 1)
+		    | CALL_COOKIE_STACKSEQ (numregs - 1);
+	     else
+	       ca->call_cookie
+		 |= CALL_COOKIE_STACKSEQ (numregs);
+	   }
+       }
+     if (GET_SH_ARG_CLASS (mode2) == SH_ARG_FLOAT
+	 && (named || ! ca->prototype_p))
+       {
+	 if (mode2 == SFmode && ca->free_single_fp_reg)
+	   ca->free_single_fp_reg = 0;
+	 else if (ca->arg_count[(int) SH_ARG_FLOAT]
+ 		  < NPARM_REGS (SFmode))
+	   {
+	     int numfpregs
+	       = MIN ((GET_MODE_SIZE (mode2) + 7) / 8 * 2,
+		      NPARM_REGS (SFmode)
+		      - ca->arg_count[(int) SH_ARG_FLOAT]);
+
+	     ca->arg_count[(int) SH_ARG_FLOAT] += numfpregs;
+
+	     if (TARGET_SHCOMPACT && ! ca->prototype_p)
+	       {
+		 if (ca->outgoing && numregs > 0)
+		   do
+		     {
+		       ca->call_cookie
+			 |= (CALL_COOKIE_INT_REG
+			     (ca->arg_count[(int) SH_ARG_INT]
+			      - numregs + ((numfpregs - 2) / 2),
+			      4 + (ca->arg_count[(int) SH_ARG_FLOAT]
+				   - numfpregs) / 2));
+		     }
+		   while (numfpregs -= 2);
+	       }
+	     else if (mode2 == SFmode && (named)
+		      && (ca->arg_count[(int) SH_ARG_FLOAT]
+			  < NPARM_REGS (SFmode)))
+	       ca->free_single_fp_reg
+		 = FIRST_FP_PARM_REG - numfpregs
+		 + ca->arg_count[(int) SH_ARG_FLOAT] + 1;
+	   }
+       }
+     return;
+   }
+
+ if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
+   {
+     /* Note that we've used the skipped register.  */
+     if (mode == SFmode && ca->free_single_fp_reg)
+       {
+	 ca->free_single_fp_reg = 0;
+	 return;
+       }
+     /* When we have a DF after an SF, there's an SF register that get
+	skipped in order to align the DF value.  We note this skipped
+	register, because the next SF value will use it, and not the
+	SF that follows the DF.  */
+     if (mode == DFmode
+	 && ROUND_REG (*ca, DFmode) != ROUND_REG (*ca, SFmode))
+       {
+	 ca->free_single_fp_reg = (ROUND_REG (*ca, SFmode)
+				     + BASE_ARG_REG (mode));
+       }
+   }
+
+ if (! (TARGET_SH4 || ca->renesas_abi)
+     || PASS_IN_REG_P (*ca, mode, type))
+   (ca->arg_count[(int) GET_SH_ARG_CLASS (mode)]
+    = (ROUND_REG (*ca, mode)
+       + (mode == BLKmode
+	  ? ROUND_ADVANCE (int_size_in_bytes (type))
+	  : ROUND_ADVANCE (GET_MODE_SIZE (mode)))));
+}
+
+/* If the structure value address is not passed in a register, define
+   `STRUCT_VALUE' as an expression returning an RTX for the place
+   where the address is passed.  If it returns 0, the address is
+   passed as an "invisible" first argument.  */
+/* The Renesas calling convention doesn't quite fit into this scheme since
+   the address is passed like an invisible argument, but one that is always
+   passed in memory.  */
+static rtx
+sh_struct_value_rtx (fndecl, incoming)
+     tree fndecl;
+     int incoming ATTRIBUTE_UNUSED;
+{
+  if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
+    return 0;
+  return gen_rtx_REG (Pmode, 2);
+}
+
+static bool
+sh_return_in_memory (type, fndecl)
+     tree type;
+     tree fndecl;
+{
+  if (TARGET_SH5)
+    {
+      if (TYPE_MODE (type) == BLKmode)
+	return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type)) > 8;
+      else
+	return GET_MODE_SIZE (TYPE_MODE (type)) > 8;
+    }
+  else
+    {
+      return (TYPE_MODE (type) == BLKmode
+	      || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
+		  && TREE_CODE (type) == RECORD_TYPE));
+    }
+}
+
+/* We actually emit the code in sh_expand_prologue.  We used to use
+   a static variable to flag that we need to emit this code, but that
+   doesn't when inlining, when functions are deferred and then emitted
+   later.  Fortunately, we already have two flags that are part of struct
+   function that tell if a function uses varargs or stdarg.  */
+static void
+sh_setup_incoming_varargs (ca, mode, type, pretend_arg_size, second_time)
+     CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+     tree type ATTRIBUTE_UNUSED;
+     int *pretend_arg_size ATTRIBUTE_UNUSED;
+     int second_time ATTRIBUTE_UNUSED;
+{
+  if (! current_function_stdarg)
+    abort ();
+}
+
+static bool
+sh_strict_argument_naming (ca)
+     CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED;
+{
+  return TARGET_SH5;
+}
+
+static bool
+sh_pretend_outgoing_varargs_named (ca)
+     CUMULATIVE_ARGS *ca;
+{
+  return ! (TARGET_HITACHI || ca->renesas_abi) && ! TARGET_SH5;
+}
+
+
 /* Define the offset between two registers, one to be eliminated, and
    the other its replacement, at the start of a routine.  */
 
@@ -6188,9 +6718,10 @@ initial_elimination_offset (from, to)
     {
       if (TARGET_SH5)
 	{
-	  int i, n = total_saved_regs_space;
-	  int align;
+	  int n = total_saved_regs_space;
 	  int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
+	  save_schedule schedule;
+	  save_entry *entry;
 	  
 	  n += total_auto_space;
 
@@ -6200,40 +6731,13 @@ initial_elimination_offset (from, to)
 
 	  target_flags = copy_flags;
 
-	  /* We loop twice: first, check 8-byte aligned registers,
-	     that are stored in the higher addresses, that are known
-	     to be aligned.  Then, check 32-bit registers that don't
-	     need 8-byte alignment.  */
-	  for (align = 1; align >= 0; align--)
-	    for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
-	      if (TEST_HARD_REG_BIT (live_regs_mask, i))
-		{
-		  enum machine_mode mode = REGISTER_NATURAL_MODE (i);
-
-		  if (mode == SFmode && (i % 2) == 1
-		      && ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
-		      && TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1)))
-		    {
-		      mode = DFmode;
-		      i--;
-		    }
-		
-		  /* If we're doing the aligned pass and this is not aligned,
-		     or we're doing the unaligned pass and this is aligned,
-		     skip it.  */
-		  if ((GET_MODE_SIZE (mode) % (STACK_BOUNDARY / BITS_PER_UNIT)
-		       == 0) != align)
-		    continue;
-
-		  n -= GET_MODE_SIZE (mode);
-
-		  if (i == pr_reg)
-		    {
-		      target_flags = save_flags;
-		      return n;
-		    }
-		}
-
+	  sh5_schedule_saves (&live_regs_mask, &schedule, n);
+	  for (entry = &schedule.entries[1]; entry->mode != VOIDmode; entry++)
+	    if (entry->reg == pr_reg)
+	      {
+		target_flags = save_flags;
+		return entry->offset;
+	      }
 	  abort ();
 	}
       else
@@ -6296,7 +6800,12 @@ sh_insert_attributes (node, attributes)
    to run on.
 
    trap_exit -- use a trapa to exit an interrupt function instead of
-   an rte instruction.  */
+   an rte instruction.
+
+   renesas -- use Renesas calling/layout conventions (functions and
+   structures).
+
+*/
 
 const struct attribute_spec sh_attribute_table[] =
 {
@@ -6304,6 +6813,7 @@ const struct attribute_spec sh_attribute_table[] =
   { "interrupt_handler", 0, 0, true,  false, false, sh_handle_interrupt_handler_attribute },
   { "sp_switch",         1, 1, true,  false, false, sh_handle_sp_switch_attribute },
   { "trap_exit",         1, 1, true,  false, false, sh_handle_trap_exit_attribute },
+  { "renesas",           0, 0, false, true, false, sh_handle_renesas_attribute },
   { NULL,                0, 0, false, false, false, NULL }
 };
 
@@ -6409,6 +6919,40 @@ sh_handle_trap_exit_attribute (node, name, args, flags, no_add_attrs)
   return NULL_TREE;
 }
 
+static tree
+sh_handle_renesas_attribute (node, name, args, flags, no_add_attrs)
+     tree *node ATTRIBUTE_UNUSED;
+     tree name ATTRIBUTE_UNUSED;
+     tree args ATTRIBUTE_UNUSED;
+     int flags ATTRIBUTE_UNUSED;
+     bool *no_add_attrs ATTRIBUTE_UNUSED;
+{
+  return NULL_TREE;
+}
+
+/* True if __attribute__((renesas)) or -mrenesas.  */
+int
+sh_attr_renesas_p (td)
+     tree td;
+{
+  if (TARGET_HITACHI)
+    return 1;
+  if (td == 0)
+    return 0;
+  if (DECL_P (td))
+    td = TREE_TYPE (td);
+  return (lookup_attribute ("renesas", TYPE_ATTRIBUTES (td))
+	  != NULL_TREE);
+}
+
+/* True if __attribute__((renesas)) or -mrenesas, for the current
+   function.  */
+int
+sh_cfun_attr_renesas_p ()
+{
+  return sh_attr_renesas_p (current_function_decl);
+}
+
 int
 sh_cfun_interrupt_handler_p ()
 {
@@ -7872,7 +8416,7 @@ static bool
 sh_ms_bitfield_layout_p (record_type)
      tree record_type ATTRIBUTE_UNUSED;
 {
-  return TARGET_SH5;
+  return (TARGET_SH5 || TARGET_HITACHI || sh_attr_renesas_p (record_type));
 }
 
 /* 
@@ -8226,7 +8770,7 @@ sh_media_init_builtins ()
   const struct builtin_description *d;
 
   memset (shared, 0, sizeof shared);
-  for (d = bdesc; d - bdesc < (int) (sizeof bdesc / sizeof bdesc[0]); d++)
+  for (d = bdesc; d - bdesc < (int) ARRAY_SIZE (bdesc); d++)
     {
       tree type, arg_type;
       int signature = d->signature;
@@ -8555,10 +9099,10 @@ sh_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
      comes first, in which case "this" comes second.  */
   INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0);
 #ifndef PCC_STATIC_STRUCT_RETURN
-  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     structure_value_byref = 1;
 #endif /* not PCC_STATIC_STRUCT_RETURN */
-  if (structure_value_byref && struct_value_rtx == 0)
+  if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
     { 
       tree ptype = build_pointer_type (TREE_TYPE (funtype));
 
@@ -8705,4 +9249,47 @@ function_symbol (const char *name)
   return sym;
 }
 
+/* Find the number of a general purpose register in S.  */
+static int
+scavenge_reg (HARD_REG_SET *s)
+{
+  int r;
+  for (r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
+    if (TEST_HARD_REG_BIT (*s, r))
+      return r;
+  return -1;
+}
+
+rtx
+sh_get_pr_initial_val (void)
+{
+  rtx val;
+
+  /* ??? Unfortunately, get_hard_reg_initial_val doesn't always work for the
+     PR register on SHcompact, because it might be clobbered by the prologue.
+     We check first if that is known to be the case.  */
+  if (TARGET_SHCOMPACT
+      && ((current_function_args_info.call_cookie
+	   & ~ CALL_COOKIE_RET_TRAMP (1))
+	  || current_function_has_nonlocal_label))
+    return gen_rtx_MEM (SImode, return_address_pointer_rtx);
+
+  /* If we haven't finished rtl generation, there might be a nonlocal label
+     that we haven't seen yet.
+     ??? get_hard_reg_initial_val fails if it is called while no_new_pseudos
+     is set, unless it has been called before for the same register.  And even
+     then, we end in trouble if we didn't use the register in the same
+     basic block before.  So call get_hard_reg_initial_val now and wrap it
+     in an unspec if we might need to replace it.  */
+  /* ??? We also must do this for TARGET_SH1 in general, because otherwise
+     combine can put the pseudo returned by get_hard_reg_initial_val into
+     instructions that need a general purpose registers, which will fail to
+     be recognized when the pseudo becomes allocated to PR.  */
+  val
+    = get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
+  if (TARGET_SH1)
+    return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
+  return val;
+}
+
 #include "gt-sh.h"
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 9ab647aff5d..3ccfdf9c898 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -319,6 +319,7 @@ extern int target_flags;
   {"dalign",  	DALIGN_BIT, "Aligns doubles at 64-bit boundaries" },		\
   {"fmovd",  	FMOVD_BIT, "" },		\
   {"hitachi",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" },		\
+  {"renesas",	HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" },		\
   {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" },		\
   {"ieee",  	IEEE_BIT, "Increase the IEEE compliance for floating-point code" },			\
   {"isize", 	ISIZE_BIT, "" },		\
@@ -591,6 +592,13 @@ do {									\
 #define UNITS_PER_WORD	(TARGET_SHMEDIA ? 8 : 4)
 #define MIN_UNITS_PER_WORD 4
 
+/* Scaling factor for Dwarf data offsets for CFI information.
+   The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
+   SHmedia; however, since we do partial register saves for the registers
+   visible to SHcompact, and for target registers for SHMEDIA32, we have
+   to allow saves that are only 4-byte aligned.  */
+#define DWARF_CIE_DATA_ALIGNMENT -4
+
 /* Width in bits of a pointer.
    See also the macro `Pmode' defined below.  */
 #define POINTER_SIZE  (TARGET_SHMEDIA64 ? 64 : 32)
@@ -639,8 +647,8 @@ do {									\
 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
   ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
     || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
-   ? MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
-   : ALIGN)
+   ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
+   : (unsigned) ALIGN)
 
 /* Make arrays of chars word-aligned for the same reasons.  */
 #define DATA_ALIGNMENT(TYPE, ALIGN)		\
@@ -816,16 +824,18 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
 #define LAST_TARGET_REG  (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
 
 #define GENERAL_REGISTER_P(REGNO) \
-  IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
+  IN_RANGE ((REGNO), \
+	    (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
+	    (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
 
 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
   (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
 
 #define FP_REGISTER_P(REGNO) \
-  ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
+  ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
 
 #define XD_REGISTER_P(REGNO) \
-  ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
+  ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
 
 #define FP_OR_XD_REGISTER_P(REGNO) \
   (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
@@ -838,7 +848,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
    || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
 
 #define TARGET_REGISTER_P(REGNO) \
-  ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
+  ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
 
 #define SHMEDIA_REGISTER_P(REGNO) \
   (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
@@ -917,7 +927,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
      Only the lower 32bits of R10-R14 are guaranteed to be preserved	\
      across SH5 function calls.  */					\
   0,      0,      0,      0,      0,      0,      0,      1,		\
-  1,      1,      0,      1,      1,      1,      1,      1,		\
+  1,      1,      1,      1,      1,      1,      1,      1,		\
   1,      1,      1,      1,      0,      0,      0,      0,		\
   0,      0,      0,      0,      1,      1,      1,      1,		\
   1,      1,      1,      1,      0,      0,      0,      0,		\
@@ -937,7 +947,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
 /* XD registers.  */							\
   1,      1,      1,      1,      1,      1,      0,      0,		\
 /*"gbr",  "ap",	  "pr",   "t",    "mach", "macl", "fpul", "fpscr", */	\
-  1,      1,      0,      1,      1,      1,      1,      1,		\
+  1,      1,      1,      1,      1,      1,      1,      1,		\
 /*"rap" */								\
   1,									\
 }
@@ -951,7 +961,8 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
   (TARGET_SHMEDIA32 \
    && GET_MODE_SIZE (MODE) > 4 \
    && (((REGNO) >= FIRST_GENERAL_REG + 10 \
-        && (REGNO) <= FIRST_GENERAL_REG + 14) \
+        && (REGNO) <= FIRST_GENERAL_REG + 15) \
+       || TARGET_REGISTER_P (REGNO) \
        || (REGNO) == PR_MEDIA_REG))
 
 /* Return number of consecutive hard regs needed starting at reg REGNO
@@ -1008,7 +1019,7 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
    ? (MODE) == DFmode \
    : TARGET_REGISTER_P (REGNO) \
    ? ((MODE) == DImode || (MODE) == SImode) \
-   : (REGNO) == PR_REG ? 0			\
+   : (REGNO) == PR_REG ? (MODE) == SImode \
    : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
    : 1)
 
@@ -1116,29 +1127,6 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
 /* Register in which the static-chain is passed to a function.  */
 #define STATIC_CHAIN_REGNUM	(TARGET_SH5 ? 1 : 3)
 
-/* The register in which a struct value address is passed.  */
-
-#define STRUCT_VALUE_REGNUM 2
-
-/* If the structure value address is not passed in a register, define
-   `STRUCT_VALUE' as an expression returning an RTX for the place
-   where the address is passed.  If it returns 0, the address is
-   passed as an "invisible" first argument.  */
-
-/* The Renesas calling convention doesn't quite fit into this scheme since
-   the address is passed like an invisible argument, but one that is always
-   passed in memory.  */
-#define STRUCT_VALUE \
-  (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
-
-#define RETURN_IN_MEMORY(TYPE) \
-  (TARGET_SH5 \
-   ? ((TYPE_MODE (TYPE) == BLKmode \
-       ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
-       : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
-   : (TYPE_MODE (TYPE) == BLKmode \
-      || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
-
 /* Don't default to pcc-struct-return, because we have already specified
    exactly how to return structures in the RETURN_IN_MEMORY macro.  */
 
@@ -1273,7 +1261,7 @@ enum reg_class
    reg number REGNO.  This could be a conditional expression
    or could index an array.  */
 
-extern int regno_reg_class[FIRST_PSEUDO_REGISTER];
+extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
 
 /* When defined, the compiler allows registers explicitly used in the
@@ -1363,7 +1351,9 @@ extern enum reg_class reg_class_from_letter[];
 #define CONSTRAINT_LEN(C,STR) \
   (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
     || (C) == 'Y' \
-    || ((C) == 'I' && (((STR)[1] != '0' && (STR)[1] != '1') || ! isdigit ((STR)[2]))) \
+    || ((C) == 'I' \
+        && (((STR)[1] != '0' && (STR)[1] != '1') \
+	    || (STR)[2] < '0' || (STR)[2] > '9')) \
     || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
     || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
     || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
@@ -1667,12 +1657,15 @@ extern enum reg_class reg_class_from_letter[];
    || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
 
 /* 1 if N is a possible register number for function argument passing.  */
+/* ??? There are some callers that pass REGNO as int, and others that pass
+   it as unsigned.  We get warnings unless we do casts everywhere.  */
 #define FUNCTION_ARG_REGNO_P(REGNO) \
-  (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG		\
-					    + NPARM_REGS (SImode)))	\
+  (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG			\
+    && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
    || (TARGET_FPU_ANY                                                   \
-       && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG	\
-						     + NPARM_REGS (SFmode))))
+       && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG		\
+       && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG		\
+					   + NPARM_REGS (SFmode))))
 
 /* Define a data type for recording info about an argument list
    during the scan of that argument list.  This data type should
@@ -1782,6 +1775,10 @@ struct sh_args {
 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
   (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
     long call_cookie;
+
+  /* This is set to nonzero when the call in question must use the Renesas ABI,
+     even without the -mrenesas option.  */
+    int renesas_abi;
 };
 
 #define CUMULATIVE_ARGS  struct sh_args
@@ -1824,17 +1821,18 @@ struct sh_args {
 
    For TARGET_HITACHI, the structure value pointer is passed in memory.  */
 
-#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
+#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL) \
   do {								\
     (CUM).arg_count[(int) SH_ARG_INT] = 0;			\
     (CUM).arg_count[(int) SH_ARG_FLOAT] = 0;			\
+    (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0;	\
     (CUM).force_mem						\
-      = (TARGET_HITACHI && FNTYPE				\
-	 && aggregate_value_p (TREE_TYPE (FNTYPE)));		\
+      = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE)	\
+	 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL)));	\
     (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE);	\
     (CUM).arg_count[(int) SH_ARG_INT]				\
       = (TARGET_SH5 && (FNTYPE)					\
-	 && aggregate_value_p (TREE_TYPE (FNTYPE)));		\
+	 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL)));	\
     (CUM).free_single_fp_reg = 0;				\
     (CUM).outgoing = 1;						\
     (CUM).stack_regs = 0;					\
@@ -1866,128 +1864,11 @@ struct sh_args {
     INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0);	\
     (CUM).outgoing = 0;						\
   } while (0)
- 
-/* Update the data in CUM to advance over an argument
-   of mode MODE and data type TYPE.
-   (TYPE is null for libcalls where that information may not be
-   available.)  */
 
 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)	\
- if ((CUM).force_mem)					\
-   (CUM).force_mem = 0;					\
- else if (TARGET_SH5)					\
-   {							\
-     tree TYPE_ = ((CUM).byref && (TYPE)		\
-		   ? TREE_TYPE (TYPE)			\
- 		   : (TYPE));				\
-     enum machine_mode MODE_ = ((CUM).byref && (TYPE)	\
-				? TYPE_MODE (TYPE_)	\
-				: (MODE));		\
-     int dwords = (((CUM).byref				\
-		    ? (CUM).byref			\
-		    : (MODE_) == BLKmode		\
-		    ? int_size_in_bytes (TYPE_)		\
-		    : GET_MODE_SIZE (MODE_)) + 7) / 8;	\
-     int numregs = MIN (dwords, NPARM_REGS (SImode)	\
-			- (CUM).arg_count[(int) SH_ARG_INT]); \
-							\
-     if (numregs)					\
-       {						\
-	 (CUM).arg_count[(int) SH_ARG_INT] += numregs;	\
-	 if (TARGET_SHCOMPACT				\
-	     && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
-	   {						\
-	     (CUM).call_cookie 				\
-	       |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
-					- numregs), 1);	\
-	     /* N.B. We want this also for outgoing.   */\
-	     (CUM).stack_regs += numregs;		\
-	   }						\
-	 else if ((CUM).byref)				\
-	   {						\
-	     if (! (CUM).outgoing)			\
-	       (CUM).stack_regs += numregs;		\
-	     (CUM).byref_regs += numregs;		\
-	     (CUM).byref = 0;				\
-	     do						\
-	       (CUM).call_cookie			\
-		 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
-					  - numregs), 2); \
-	     while (--numregs);				\
-	     (CUM).call_cookie				\
-	       |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
-				        - 1), 1); \
-	   }						\
-	 else if (dwords > numregs)			\
-	   {						\
-	     int pushregs = numregs;			\
-							\
-	     if (TARGET_SHCOMPACT)			\
-	       (CUM).stack_regs += numregs;		\
-	     while (pushregs < NPARM_REGS (SImode) - 1	\
-		    && (CALL_COOKIE_INT_REG_GET		\
-			((CUM).call_cookie,		\
-			NPARM_REGS (SImode) - pushregs) \
-			== 1))				\
-	       {					\
-		 (CUM).call_cookie			\
-		   &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
-					     - pushregs, 1); \
-		 pushregs++;				\
-	       }					\
-	     if (numregs == NPARM_REGS (SImode))	\
-	       (CUM).call_cookie 			\
-		 |= CALL_COOKIE_INT_REG (0, 1)		\
-		    | CALL_COOKIE_STACKSEQ (numregs - 1); \
-	     else					\
-	       (CUM).call_cookie			\
-		 |= CALL_COOKIE_STACKSEQ (numregs);	\
-	   }						\
-       }						\
-     if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT	\
-	 && ((NAMED) || ! (CUM).prototype_p))		\
-       {						\
-	 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
-	   (CUM).free_single_fp_reg = 0;		\
-	 else if ((CUM).arg_count[(int) SH_ARG_FLOAT]	\
- 		  < NPARM_REGS (SFmode))		\
-	   {					        \
-	     int numfpregs		 		\
-	       = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
-		      NPARM_REGS (SFmode)		\
-		      - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
-		 					\
-	     (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
-							\
-	     if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
-	       {					\
-		 if ((CUM).outgoing && numregs > 0)	\
-		   do					\
-		     {					\
-		       (CUM).call_cookie		\
-			 |= (CALL_COOKIE_INT_REG	\
-			     ((CUM).arg_count[(int) SH_ARG_INT] \
-			      - numregs + ((numfpregs - 2) / 2), \
-			      4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
-				   - numfpregs) / 2));	\
-		     }					\
-		   while (numfpregs -= 2);		\
-	       }					\
-	     else if ((MODE_) == SFmode && (NAMED)	\
-		      && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
-			  < NPARM_REGS (SFmode)))	\
-	       (CUM).free_single_fp_reg			\
-		 = FIRST_FP_PARM_REG - numfpregs	\
-		 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
-	   }						\
-       }						\
-   }							\
- else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
-   ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)]	\
-    = (ROUND_REG ((CUM), (MODE))			\
-       + ((MODE) == BLKmode				\
-	  ? ROUND_ADVANCE (int_size_in_bytes (TYPE))	\
-	  : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
+	sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
+#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED)	\
+	sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
 
 /* Return boolean indicating arg of mode MODE will be passed in a reg.
    This macro is only used in this file.  */
@@ -1995,7 +1876,11 @@ struct sh_args {
 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
   (((TYPE) == 0 \
     || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
-	&& (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
+	&& (! (TARGET_HITACHI || (CUM).renesas_abi) \
+	    || ! (AGGREGATE_TYPE_P (TYPE) \
+		  || (!TARGET_FPU_ANY \
+		      && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
+			  && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
    && ! (CUM).force_mem \
    && (TARGET_SH2E \
        ? ((MODE) == BLKmode \
@@ -2025,75 +1910,6 @@ struct sh_args {
    foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7  */
 #define FUNCTION_ARG_SCmode_WART 1
 
-/* Define where to put the arguments to a function.
-   Value is zero to push the argument on the stack,
-   or a hard register in which to store the argument.
-
-   MODE is the argument's machine mode.
-   TYPE is the data type of the argument (as a tree).
-    This is null for libcalls where that information may
-    not be available.
-   CUM is a variable of type CUMULATIVE_ARGS which gives info about
-    the preceding args and about the function being called.
-   NAMED is nonzero if this argument is a named parameter
-    (otherwise it is an extra parameter matching an ellipsis).
-
-   On SH the first args are normally in registers
-   and the rest are pushed.  Any arg that starts within the first
-   NPARM_REGS words is at least partially passed in a register unless
-   its data type forbids.  */
-
-#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-  ((! TARGET_SH5 \
-    && PASS_IN_REG_P ((CUM), (MODE), (TYPE))				\
-    && ((NAMED) || !TARGET_HITACHI))					\
-   ? (((MODE) == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN		\
-       && (! FUNCTION_ARG_SCmode_WART || (ROUND_REG ((CUM), (MODE)) & 1)))\
-      ? (gen_rtx_PARALLEL						\
-	 (SCmode,							\
-	  (gen_rtvec							\
-	   (2, 								\
-	    (gen_rtx_EXPR_LIST						\
-	     (VOIDmode,							\
-	      gen_rtx_REG (SFmode,					\
-			   BASE_ARG_REG (MODE)				\
-			   + ROUND_REG ((CUM), (MODE)) ^ 1),		\
-	      const0_rtx)),						\
-	    (gen_rtx_EXPR_LIST						\
-	     (VOIDmode,							\
-	      gen_rtx_REG (SFmode,					\
-			   BASE_ARG_REG (MODE)				\
-			   + (ROUND_REG ((CUM), (MODE)) + 1) ^ 1),	\
-	      GEN_INT (4)))))))						\
-      : gen_rtx_REG ((MODE),						\
-		     ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
-		      ^ ((MODE) == SFmode && TARGET_SH4			\
-			 && TARGET_LITTLE_ENDIAN != 0))))		\
-   : TARGET_SH5								\
-   ? ((MODE) == VOIDmode && TARGET_SHCOMPACT				\
-      ? GEN_INT ((CUM).call_cookie)					\
-      /* The following test assumes unnamed arguments are promoted to	\
-	 DFmode.  */							\
-      : (MODE) == SFmode && (CUM).free_single_fp_reg			\
-      ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
-      : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT			\
-         && ((NAMED) || ! (CUM).prototype_p)				\
-         && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode))	\
-      ? ((! (CUM).prototype_p && TARGET_SHMEDIA)			\
-	 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE))			\
-	 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE),			\
-				     FIRST_FP_PARM_REG			\
-				     + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
-      : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode)	\
-	 && (! TARGET_SHCOMPACT						\
-	     || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE))		\
-	         && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE),	\
-						  (TYPE), (NAMED)))))	\
-      ? gen_rtx_REG ((MODE), (FIRST_PARM_REG				\
- 			      + (CUM).arg_count[(int) SH_ARG_INT]))	\
-      : 0)								\
-   : 0)
-
 /* Whether an argument must be passed by reference.  On SHcompact, we
    pretend arguments wider than 32-bits that would have been passed in
    registers are passed by reference, so that an SHmedia trampoline
@@ -2188,10 +2004,6 @@ struct sh_args {
 							  (REG)),	\
 				   const0_rtx))))
 
-#define STRICT_ARGUMENT_NAMING TARGET_SH5
-
-#define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
-
 /* For an arg passed partly in registers and partly in memory,
    this is the number of registers used.
    For args passed entirely in registers or entirely in memory, zero.
@@ -2223,16 +2035,6 @@ struct sh_args {
 /* Perform any needed actions needed for a function that is receiving a
    variable number of arguments.  */
 
-/* We actually emit the code in sh_expand_prologue.  We used to use
-   a static variable to flag that we need to emit this code, but that
-   doesn't when inlining, when functions are deferred and then emitted
-   later.  Fortunately, we already have two flags that are part of struct
-   function that tell if a function uses varargs or stdarg.  */
-#define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST)  do \
-  if (! current_function_stdarg) \
-    abort (); \
-while (0)
-
 /* Define the `__builtin_va_list' type for the ABI.  */
 #define BUILD_VA_LIST_TYPE(VALIST) \
   (VALIST) = sh_build_va_list ()
@@ -2311,9 +2113,7 @@ while (0)
    can ignore COUNT.  */
 
 #define RETURN_ADDR_RTX(COUNT, FRAME)	\
-  (((COUNT) == 0)				\
-   ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
-   : (rtx) 0)
+  (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
 
 /* A C expression whose value is RTL representing the location of the
    incoming return address at the beginning of any function, before the
@@ -2323,9 +2123,6 @@ while (0)
 #define INCOMING_RETURN_ADDR_RTX \
   gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
 
-/* Generate necessary RTL for __builtin_saveregs().  */
-#define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
-
 /* Addressing modes, and classification of registers for them.  */
 #define HAVE_POST_INCREMENT  TARGET_SH1
 #define HAVE_PRE_DECREMENT   TARGET_SH1
@@ -2906,9 +2703,6 @@ while (0)
    but a CALL with constant address is cheap.  */
 /*#define NO_FUNCTION_CSE 1*/
 
-/* Chars and shorts should be passed as ints.  */
-#define PROMOTE_PROTOTYPES 1
-
 /* The machine modes of pointers and functions.  */
 #define Pmode  (TARGET_SHMEDIA64 ? DImode : SImode)
 #define FUNCTION_MODE  Pmode
@@ -3083,20 +2877,32 @@ while (0)
    register exists, so we should return -1 for invalid register numbers.  */
 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
 
+/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
+   used to use the encodings 245..260, but that doesn't make sense:
+   PR_REG and PR_MEDIA_REG are actually the same register, and likewise
+   the FP registers stay the same when switching between compact and media
+   mode.  Hence, we also need to use the same dwarf frame coloumns.
+   Likewise, we need to support unwind information for SHmedia registers
+   even in compact code.  */
 #define SH_DBX_REGISTER_NUMBER(REGNO) \
-  (GENERAL_REGISTER_P (REGNO) \
-   ? ((REGNO) - FIRST_GENERAL_REG) \
-   : FP_REGISTER_P (REGNO) \
-   ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
-					      : 77) : 25)) \
+  (IN_RANGE ((REGNO), \
+	     (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
+	     FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
+   ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
+  : ((int) (REGNO) >= FIRST_FP_REG \
+     && ((int) (REGNO) \
+	 <= (FIRST_FP_REG + \
+	     ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
+   ? ((unsigned) (REGNO) - FIRST_FP_REG \
+      + (TARGET_SH5 ? 77 : 25)) \
    : XD_REGISTER_P (REGNO) \
-   ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
+   ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
    : TARGET_REGISTER_P (REGNO) \
-   ? ((REGNO) - FIRST_TARGET_REG + 68) \
+   ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
    : (REGNO) == PR_REG \
-   ? (TARGET_SH5 ? 241 : 17) \
+   ? (TARGET_SH5 ? 18 : 17) \
    : (REGNO) == PR_MEDIA_REG \
-   ? (TARGET_SH5 ? 18 : -1) \
+   ? (TARGET_SH5 ? 18 : (unsigned) -1) \
    : (REGNO) == T_REG \
    ? (TARGET_SH5 ? 242 : 18) \
    : (REGNO) == GBR_REG \
@@ -3107,7 +2913,7 @@ while (0)
    ? (TARGET_SH5 ? 240 : 21) \
    : (REGNO) == FPUL_REG \
    ? (TARGET_SH5 ? 244 : 23) \
-   : -1)
+   : (unsigned) -1)
 
 /* This is how to output a reference to a symbol_ref.  On SH5,
    references to non-code symbols must be preceded by `datalabel'.  */
@@ -3449,9 +3255,31 @@ extern int rtx_equal_function_value_matters;
   (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
 
 #define EH_RETURN_DATA_REGNO(N)	\
-  ((N) < 4 ? (N) + (TARGET_SH5 ? 2 : 4) : INVALID_REGNUM)
-
-#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)
+  ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
+
+#define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
+#define EH_RETURN_STACKADJ_RTX	gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
+
+/* We have to distinguish between code and data, so that we apply
+   datalabel where and only where appropriate.  Use textrel for code.  */
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
+ ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
+  | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
+
+/* Handle special EH pointer encodings.  Absolute, pc-relative, and
+   indirect are handled automatically.  */
+#define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
+  do { \
+    if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
+      { \
+	encoding &= ~DW_EH_PE_textrel; \
+	encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
+	if (GET_CODE (ADDR) != SYMBOL_REF) \
+	  abort (); \
+	SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
+	if (0) goto DONE; \
+      } \
+  } while (0)
 
 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
 /* SH constant pool breaks the devices in crtstuff.c to control section
@@ -3468,8 +3296,13 @@ extern int rtx_equal_function_value_matters;
 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
 
 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
-  (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
-   ? (current_function_is_leaf && ! sh_pr_n_sets () \
+  (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
+   ? (current_function_is_leaf \
+      && ! sh_pr_n_sets () \
+      && ! (TARGET_SHCOMPACT \
+	    && ((current_function_args_info.call_cookie \
+		 & ~ CALL_COOKIE_RET_TRAMP (1)) \
+		|| current_function_has_nonlocal_label)) \
       ? (hard_reg) \
       : gen_rtx_MEM (Pmode, TARGET_SH5 \
 			    ? (plus_constant (arg_pointer_rtx, \
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 2af568b772c..c5c55c76bf2 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -142,6 +142,7 @@
   (UNSPEC_DTPOFF	23)
   (UNSPEC_GOTTPOFF	24)
   (UNSPEC_TPOFF		25)
+  (UNSPEC_RA		26)
 
   ;; These are used with unspec_volatile.
   (UNSPECV_BLOCKAGE	0)
@@ -2052,7 +2053,7 @@
 "
 {
   enum machine_mode inmode = GET_MODE (operands[1]);
-  int regno, offset = 0;
+  int offset = 0;
 
   if (GET_CODE (operands[0]) == SUBREG)
     {
@@ -3471,6 +3472,19 @@
 	fake	%1,%0"
   [(set_attr "type" "pcload,move,load,move,prget,move,store,pcload")])
 
+(define_insn_and_split "load_ra"
+  [(set (match_operand:SI 0 "general_movdst_operand" "")
+	(unspec:SI [(match_operand 1 "register_operand" "")] UNSPEC_RA))]
+  "TARGET_SH1"
+  "#"
+  "&& ! rtx_equal_function_value_matters"
+  [(set (match_dup 0) (match_dup 1))]
+  "
+{
+  if (TARGET_SHCOMPACT && current_function_has_nonlocal_label)
+    operands[1] = gen_rtx_MEM (SImode, return_address_pointer_rtx);
+}")
+
 (define_insn "*movsi_media"
   [(set (match_operand:SI 0 "general_movdst_operand"
 	        "=r,r,r,r,m,f,m,f,r,f,*b,r,b")
@@ -5855,7 +5869,10 @@
       DONE;
     }
   else
+  {
     operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+    operands[1] = operands[2];
+  }
 
   emit_call_insn (gen_calli (operands[0], operands[1]));
   DONE;
@@ -6163,6 +6180,7 @@
 (define_insn "sibcall_media"
   [(call (mem:DI (match_operand:DI 0 "target_reg_operand" "k"))
 	 (match_operand 1 "" ""))
+   (use (reg:SI PR_MEDIA_REG))
    (return)]
   "TARGET_SHMEDIA"
   "blink	%0, r63"
@@ -7247,6 +7265,8 @@ mov.l\\t1f,r0\\n\\
     {
       rtx r18 = gen_rtx_REG (DImode, PR_MEDIA_REG);
 
+      if (! call_used_regs[TR0_REG] || fixed_regs[TR0_REG])
+	abort ();
       tr_regno = TR0_REG;
       tr = gen_rtx_REG (DImode, tr_regno);
       emit_move_insn (tr, r18);
diff --git a/gcc/config/sol2.h b/gcc/config/sol2.h
index 950472d77ac..49dc1ce2ae4 100644
--- a/gcc/config/sol2.h
+++ b/gcc/config/sol2.h
@@ -1,6 +1,6 @@
 /* Operating system specific defines to be used when targeting GCC for any
    Solaris 2 system.
-   Copyright 2002 Free Software Foundation, Inc.
+   Copyright 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -76,6 +76,9 @@ Boston, MA 02111-1307, USA.  */
 	TARGET_SUB_OS_CPP_BUILTINS();			\
     } while (0)
 
+/* The system headers under Solaris 2 are C++-aware since 2.0.  */
+#define NO_IMPLICIT_EXTERN_C
+
 /* The sun bundled assembler doesn't accept -Yd, (and neither does gas).
    It's safe to pass -s always, even if -g is not used.  */
 #undef ASM_SPEC
@@ -166,13 +169,9 @@ Boston, MA 02111-1307, USA.  */
  *
  */
 
-/* This declares mprotect (used in TRANSFER_FROM_TRAMPOLINE) for
-   libgcc2.c.  */
-/* We don't want to include this because sys/mman.h is not present on
-   some non-Solaris configurations that use sol2.h.  */
-#if 0 /* def L_trampoline */
-#include <sys/mman.h>
-#endif
+/* sys/mman.h is not present on some non-Solaris configurations
+   that use sol2.h, so TRANSFER_FROM_TRAMPOLINE must use a magic
+   number instead of the appropriate PROT_* flags.  */
 
 #define TRANSFER_FROM_TRAMPOLINE					\
 									\
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
index a7a48e60c2d..cf943907d22 100644
--- a/gcc/config/sparc/linux.h
+++ b/gcc/config/sparc/linux.h
@@ -1,5 +1,6 @@
 /* Definitions for SPARC running Linux-based GNU systems with ELF.
-   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1996, 1997, 1998, 1999, 2000, 2002, 2003
+   Free Software Foundation, Inc.
    Contributed by Eddie C. Dost (ecd@skynet.be)
 
 This file is part of GCC.
@@ -30,8 +31,6 @@ Boston, MA 02111-1307, USA.  */
     }						\
   while (0)
 
-#define LINUX_DEFAULT_ELF
-
 /* Don't assume anything about the header files.  */
 #define NO_IMPLICIT_EXTERN_C
 
@@ -154,15 +153,6 @@ Boston, MA 02111-1307, USA.  */
 
 #undef  LINK_SPEC
 #ifdef USE_GNULIBC_1
-#ifndef LINUX_DEFAULT_ELF
-#define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
-  %{!shared: \
-    %{!ibcs: \
-      %{!static: \
-        %{rdynamic:-export-dynamic} \
-        %{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \
-        %{!rpath:-rpath /lib/elf/}} %{static:-static}}}"
-#else
 #define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
   %{!shared: \
     %{!ibcs: \
@@ -170,7 +160,6 @@ Boston, MA 02111-1307, USA.  */
         %{rdynamic:-export-dynamic} \
         %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \
         %{static:-static}}}"
-#endif
 #else
 #define LINK_SPEC "-m elf32_sparc -Y P,/usr/lib %{shared:-shared} \
   %{!mno-relax:%{!r:-relax}} \
@@ -244,6 +233,13 @@ do {									\
 #define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
 #endif
 
+#ifdef HAVE_AS_TLS
+#undef TARGET_SUN_TLS
+#undef TARGET_GNU_TLS
+#define TARGET_SUN_TLS 0
+#define TARGET_GNU_TLS 1
+#endif
+
 /* Don't be different from other Linux platforms in this regard.  */
 #define HANDLE_PRAGMA_PACK_PUSH_POP
 
@@ -253,6 +249,9 @@ do {									\
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Do code reading to identify a signal frame, and set the frame
    state data appropriately.  See unwind-dw2.c for the structs.  */
 
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index 10c83960b38..c3ecfaf1dee 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -1,5 +1,5 @@
 /* Definitions for 64-bit SPARC running Linux-based GNU systems with ELF.
-   Copyright 1996, 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2002, 2003 Free Software Foundation, Inc.
    Contributed by David S. Miller (davem@caip.rutgers.edu)
 
 This file is part of GCC.
@@ -31,8 +31,6 @@ Boston, MA 02111-1307, USA.  */
     }						\
   while (0)
 
-#define LINUX_DEFAULT_ELF
-
 /* Don't assume anything about the header files.  */
 #define NO_IMPLICIT_EXTERN_C
 
@@ -317,6 +315,13 @@ do {									\
 #define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
 #endif
 
+#ifdef HAVE_AS_TLS
+#undef TARGET_SUN_TLS
+#undef TARGET_GNU_TLS
+#define TARGET_SUN_TLS 0
+#define TARGET_GNU_TLS 1
+#endif
+
 /* Don't be different from other Linux platforms in this regard.  */
 #define HANDLE_PRAGMA_PACK_PUSH_POP
 
@@ -326,6 +331,9 @@ do {									\
 
 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
 
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Do code reading to identify a signal frame, and set the frame
    state data appropriately.  See unwind-dw2.c for the structs.  */
 
diff --git a/gcc/config/sparc/openbsd.h b/gcc/config/sparc/openbsd.h
index 6717e222151..e36f51eb602 100644
--- a/gcc/config/sparc/openbsd.h
+++ b/gcc/config/sparc/openbsd.h
@@ -1,5 +1,5 @@
 /* Configuration file for sparc OpenBSD target.
-   Copyright (C) 1999, 2002 Free Software Foundation, Inc.
+   Copyright (C) 1999, 2002, 2003 Free Software Foundation, Inc.
 
 This file is part of GCC.
 
@@ -18,10 +18,6 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-/* Get generic OpenBSD definitions.  */
-#define OBSD_OLD_GAS
-#include <openbsd.h>
-
 /* Target OS builtins.  */
 #define TARGET_OS_CPP_BUILTINS()		\
   do						\
diff --git a/gcc/config/sparc/sol2-c1.asm b/gcc/config/sparc/sol2-c1.asm
index 894a8c34c08..a1cc68d6756 100644
--- a/gcc/config/sparc/sol2-c1.asm
+++ b/gcc/config/sparc/sol2-c1.asm
@@ -92,6 +92,10 @@ _start:
 	! access those data anyway.  Instead, go straight to main:
 	mov	%l0, %o0	! argc
 	mov	%l1, %o1	! argv
+#ifdef GCRT1
+	setn(___Argv, %o4, %o3)
+	stn	%o1, [%o3]      ! *___Argv
+#endif
 	! Skip argc words past argv, to env:
 	sll	%l0, CPTRSHIFT, %o2
 	add	%o2, CPTRSIZE, %o2
diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
index 0de1e128551..4b9582d96b8 100644
--- a/gcc/config/sparc/sparc-protos.h
+++ b/gcc/config/sparc/sparc-protos.h
@@ -27,99 +27,104 @@ Boston, MA 02111-1307, USA.  */
 extern bool sparc_emitting_epilogue;
 
 #ifdef TREE_CODE
-extern struct rtx_def *function_value PARAMS ((tree, enum machine_mode, int));
-extern void function_arg_advance PARAMS ((CUMULATIVE_ARGS *,
-					  enum machine_mode, tree, int));
-extern struct rtx_def *function_arg PARAMS ((const CUMULATIVE_ARGS *,
-					     enum machine_mode,
-					     tree, int, int));
-extern int function_arg_partial_nregs  PARAMS ((const CUMULATIVE_ARGS *,
-						enum machine_mode,
-						tree, int));
-extern int function_arg_pass_by_reference PARAMS ((const CUMULATIVE_ARGS *,
-						   enum machine_mode,
-						   tree, int));
-extern struct rtx_def *sparc_builtin_saveregs PARAMS ((void));
+extern struct rtx_def *function_value (tree, enum machine_mode, int);
+extern void function_arg_advance (CUMULATIVE_ARGS *,
+				  enum machine_mode, tree, int);
+extern struct rtx_def *function_arg (const CUMULATIVE_ARGS *,
+				     enum machine_mode, tree, int, int);
+extern int function_arg_partial_nregs (const CUMULATIVE_ARGS *,
+				       enum machine_mode, tree, int);
+extern int function_arg_pass_by_reference (const CUMULATIVE_ARGS *,
+					   enum machine_mode, tree, int);
+extern struct rtx_def *sparc_builtin_saveregs (void);
 #ifdef RTX_CODE
-extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, tree));
-extern void sparc_va_start PARAMS ((tree, rtx));
+extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
+extern void sparc_va_start (tree, rtx);
 #endif
-extern struct rtx_def *sparc_va_arg PARAMS ((tree, tree));
-extern unsigned long sparc_type_code PARAMS ((tree));
+extern struct rtx_def *sparc_va_arg (tree, tree);
+extern unsigned long sparc_type_code (tree);
 #ifdef ARGS_SIZE_RTX
 /* expr.h defines ARGS_SIZE_RTX and `enum direction' */
-extern enum direction function_arg_padding PARAMS ((enum machine_mode, tree));
+extern enum direction function_arg_padding (enum machine_mode, tree);
 #endif /* ARGS_SIZE_RTX */
 #endif /* TREE_CODE */
 
-extern void load_pic_register PARAMS ((void));
-extern void order_regs_for_local_alloc PARAMS ((void));
-extern int compute_frame_size PARAMS ((int, int));
-extern int check_pic PARAMS ((int));
-extern int short_branch PARAMS ((int, int));
-extern int sparc_flat_epilogue_delay_slots PARAMS ((void));
-extern unsigned long sparc_flat_compute_frame_size PARAMS ((int));
-extern void sparc_profile_hook PARAMS ((int));
-extern void sparc_override_options PARAMS ((void));
-extern int leaf_return_peephole_ok PARAMS ((void));
-extern void sparc_output_scratch_registers PARAMS ((FILE *));
-extern void sparc_flat_save_restore PARAMS ((FILE *, const char *,
-					     unsigned int, unsigned long,
-					     unsigned long, const char *,
-					     const char *, unsigned long));
+extern void load_pic_register (void);
+extern void order_regs_for_local_alloc (void);
+extern int compute_frame_size (int, int);
+extern int check_pic (int);
+extern int short_branch (int, int);
+extern int sparc_flat_epilogue_delay_slots (void);
+extern unsigned long sparc_flat_compute_frame_size (int);
+extern void sparc_profile_hook (int);
+extern void sparc_override_options (void);
+extern int leaf_return_peephole_ok (void);
+extern void sparc_output_scratch_registers (FILE *);
+extern void sparc_flat_save_restore (FILE *, const char *,
+				     unsigned int, unsigned long,
+				     unsigned long, const char *,
+				     const char *, unsigned long);
 
 #ifdef RTX_CODE
-extern enum machine_mode select_cc_mode PARAMS ((enum rtx_code, rtx, rtx));
+extern enum machine_mode select_cc_mode (enum rtx_code, rtx, rtx);
 /* Define the function that build the compare insn for scc and bcc.  */
-extern rtx gen_compare_reg PARAMS ((enum rtx_code code, rtx, rtx));
-extern void sparc_emit_float_lib_cmp PARAMS ((rtx, rtx, enum rtx_code));
-extern void sparc_emit_floatunsdi PARAMS ((rtx [2]));
-extern void emit_tfmode_binop PARAMS ((enum rtx_code, rtx *));
-extern void emit_tfmode_unop PARAMS ((enum rtx_code, rtx *));
-extern void emit_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
+extern rtx gen_compare_reg (enum rtx_code code, rtx, rtx);
+extern void sparc_emit_float_lib_cmp (rtx, rtx, enum rtx_code);
+extern void sparc_emit_floatunsdi (rtx [2]);
+extern void emit_tfmode_binop (enum rtx_code, rtx *);
+extern void emit_tfmode_unop (enum rtx_code, rtx *);
+extern void emit_tfmode_cvt (enum rtx_code, rtx *);
 /* This function handles all v9 scc insns */
-extern int gen_v9_scc PARAMS ((enum rtx_code, rtx *));
-extern void sparc_initialize_trampoline PARAMS ((rtx, rtx, rtx));
-extern void sparc64_initialize_trampoline PARAMS ((rtx, rtx, rtx));
-extern rtx legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx));
-extern void sparc_defer_case_vector PARAMS ((rtx, rtx, int));
-extern void sparc_emit_set_const32 PARAMS ((rtx, rtx));
-extern void sparc_emit_set_const64 PARAMS ((rtx, rtx));
-extern void sparc_emit_set_symbolic_const64 PARAMS ((rtx, rtx, rtx));
-extern int sparc_splitdi_legitimate PARAMS ((rtx, rtx));
-extern int sparc_absnegfloat_split_legitimate PARAMS ((rtx, rtx));
-extern char *output_cbranch PARAMS ((rtx, rtx, int, int, int, int, rtx));
-extern const char *output_sibcall PARAMS ((rtx, rtx));
-extern char *output_v9branch PARAMS ((rtx, rtx, int, int, int, int, int,
-				      rtx));
-extern void emit_v9_brxx_insn PARAMS ((enum rtx_code, rtx, rtx));
-extern void print_operand PARAMS ((FILE *, rtx, int));
-extern int mems_ok_for_ldd_peep PARAMS ((rtx, rtx, rtx));
-extern int arith_double_4096_operand PARAMS ((rtx, enum machine_mode));
-extern int arith_4096_operand PARAMS ((rtx, enum machine_mode));
-extern int zero_operand PARAMS ((rtx, enum machine_mode));
-extern int fp_zero_operand PARAMS ((rtx, enum machine_mode));
-extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode));
-extern int empty_delay_slot PARAMS ((rtx));
-extern int eligible_for_epilogue_delay PARAMS ((rtx, int));
-extern int eligible_for_sibcall_delay PARAMS ((rtx));
-extern int emit_move_sequence PARAMS ((rtx, enum machine_mode));
-extern int fp_sethi_p PARAMS ((rtx));
-extern int fp_mov_p PARAMS ((rtx));
-extern int fp_high_losum_p PARAMS ((rtx));
-extern int mem_min_alignment PARAMS ((rtx, int));
-extern int pic_address_needs_scratch PARAMS ((rtx));
-extern int reg_unused_after PARAMS ((rtx, rtx));
-extern int register_ok_for_ldd PARAMS ((rtx));
-extern int registers_ok_for_ldd_peep PARAMS ((rtx, rtx));
-extern int sparc_flat_eligible_for_epilogue_delay PARAMS ((rtx, int));
-extern int v9_regcmp_p PARAMS ((enum rtx_code));
-extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *));
+extern int gen_v9_scc (enum rtx_code, rtx *);
+extern void sparc_initialize_trampoline (rtx, rtx, rtx);
+extern void sparc64_initialize_trampoline (rtx, rtx, rtx);
+extern bool legitimate_constant_p (rtx);
+extern bool constant_address_p (rtx);
+extern bool legitimate_pic_operand_p (rtx);
+extern int legitimate_address_p (enum machine_mode, rtx, int);
+extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
+extern rtx legitimize_tls_address (rtx);
+extern rtx legitimize_address (rtx, rtx, enum machine_mode);
+extern void sparc_defer_case_vector (rtx, rtx, int);
+extern void sparc_emit_set_const32 (rtx, rtx);
+extern void sparc_emit_set_const64 (rtx, rtx);
+extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx);
+extern int sparc_splitdi_legitimate (rtx, rtx);
+extern int sparc_absnegfloat_split_legitimate (rtx, rtx);
+extern char *output_cbranch (rtx, rtx, int, int, int, int, rtx);
+extern const char *output_sibcall (rtx, rtx);
+extern char *output_v9branch (rtx, rtx, int, int, int, int, int, rtx);
+extern void emit_v9_brxx_insn (enum rtx_code, rtx, rtx);
+extern void print_operand (FILE *, rtx, int);
+extern int mems_ok_for_ldd_peep (rtx, rtx, rtx);
+extern int arith_double_4096_operand (rtx, enum machine_mode);
+extern int arith_4096_operand (rtx, enum machine_mode);
+extern int zero_operand (rtx, enum machine_mode);
+extern int fp_zero_operand (rtx, enum machine_mode);
+extern int reg_or_0_operand (rtx, enum machine_mode);
+extern int tls_symbolic_operand (rtx);
+extern int empty_delay_slot (rtx);
+extern int eligible_for_epilogue_delay (rtx, int);
+extern int eligible_for_sibcall_delay (rtx);
+extern int tls_call_delay (rtx);
+extern int emit_move_sequence (rtx, enum machine_mode);
+extern int fp_sethi_p (rtx);
+extern int fp_mov_p (rtx);
+extern int fp_high_losum_p (rtx);
+extern int mem_min_alignment (rtx, int);
+extern int pic_address_needs_scratch (rtx);
+extern int reg_unused_after (rtx, rtx);
+extern int register_ok_for_ldd (rtx);
+extern int registers_ok_for_ldd_peep (rtx, rtx);
+extern int sparc_flat_eligible_for_epilogue_delay (rtx, int);
+extern int v9_regcmp_p (enum rtx_code);
+extern char *sparc_v8plus_shift (rtx *, rtx, const char *);
 /* Function used for V8+ code generation.  Returns 1 if the high
    32 bits of REG are 0 before INSN.  */   
-extern int sparc_check_64 PARAMS ((rtx, rtx));
-extern rtx gen_df_reg PARAMS ((rtx, int));
-extern int sparc_extra_constraint_check PARAMS ((rtx, int, int));
+extern int sparc_check_64 (rtx, rtx);
+extern rtx gen_df_reg (rtx, int);
+extern int sparc_extra_constraint_check (rtx, int, int);
+extern void sparc_output_dwarf_dtprel (FILE*, int, rtx);
 #endif /* RTX_CODE */
 
 #endif /* __SPARC_PROTOS_H__ */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 617a964b619..8441783261a 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -120,6 +120,12 @@ char sparc_leaf_regs[] =
   1, 1, 1, 1, 1, 1, 1, 1,
   1, 1, 1, 1, 1};
 
+struct machine_function GTY(())
+{
+  /* Some local-dynamic TLS symbol name.  */
+  const char *some_ld_name;
+};
+
 /* Name of where we pretend to think the frame pointer points.
    Normally, this is "%fp", but if we are in a leaf procedure,
    this is "%sp+something".  We record "something" separately as it may be
@@ -128,60 +134,61 @@ char sparc_leaf_regs[] =
 static const char *frame_base_name;
 static int frame_base_offset;
 
-static void sparc_init_modes	PARAMS ((void));
-static int save_regs		PARAMS ((FILE *, int, int, const char *,
-				       int, int, int));
-static int restore_regs		PARAMS ((FILE *, int, int, const char *, int, int));
-static void build_big_number	PARAMS ((FILE *, int, const char *));
-static int function_arg_slotno	PARAMS ((const CUMULATIVE_ARGS *,
-				       enum machine_mode, tree, int, int,
-				       int *, int *));
-
-static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-
-static void sparc_output_addr_vec PARAMS ((rtx));
-static void sparc_output_addr_diff_vec PARAMS ((rtx));
-static void sparc_output_deferred_case_vectors PARAMS ((void));
-static int check_return_regs PARAMS ((rtx));
-static int epilogue_renumber PARAMS ((rtx *, int));
-static bool sparc_assemble_integer PARAMS ((rtx, unsigned int, int));
-static int set_extends PARAMS ((rtx));
-static void output_restore_regs PARAMS ((FILE *, int));
-static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void sparc_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void sparc_flat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
-static void sparc_flat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void sparc_nonflat_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT,
-						     int));
-static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
-						     int));
+static void sparc_init_modes (void);
+static int save_regs (FILE *, int, int, const char *, int, int, int);
+static int restore_regs (FILE *, int, int, const char *, int, int);
+static void build_big_number (FILE *, int, const char *);
+static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
+				tree, int, int, int *, int *);
+
+static int supersparc_adjust_cost (rtx, rtx, rtx, int);
+static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
+
+static void sparc_output_addr_vec (rtx);
+static void sparc_output_addr_diff_vec (rtx);
+static void sparc_output_deferred_case_vectors (void);
+static int check_return_regs (rtx);
+static int epilogue_renumber (rtx *, int);
+static bool sparc_assemble_integer (rtx, unsigned int, int);
+static int set_extends (rtx);
+static void output_restore_regs (FILE *, int);
+static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
+static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
+static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
+static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
+static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
 #ifdef OBJECT_FORMAT_ELF
-static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
+static void sparc_elf_asm_named_section (const char *, unsigned int);
 #endif
-static void sparc_aout_select_section PARAMS ((tree, int,
-					       unsigned HOST_WIDE_INT))
+static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
      ATTRIBUTE_UNUSED;
-static void sparc_aout_select_rtx_section PARAMS ((enum machine_mode, rtx,
-						   unsigned HOST_WIDE_INT))
+static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
+					   unsigned HOST_WIDE_INT)
      ATTRIBUTE_UNUSED;
 
-static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int sparc_issue_rate PARAMS ((void));
-static void sparc_sched_init PARAMS ((FILE *, int, int));
-static int sparc_use_dfa_pipeline_interface PARAMS ((void));
-static int sparc_use_sched_lookahead PARAMS ((void));
-
-static void emit_soft_tfmode_libcall PARAMS ((const char *, int, rtx *));
-static void emit_soft_tfmode_binop PARAMS ((enum rtx_code, rtx *));
-static void emit_soft_tfmode_unop PARAMS ((enum rtx_code, rtx *));
-static void emit_soft_tfmode_cvt PARAMS ((enum rtx_code, rtx *));
-static void emit_hard_tfmode_operation PARAMS ((enum rtx_code, rtx *));
-
-static bool sparc_function_ok_for_sibcall PARAMS ((tree, tree));
-static void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					   HOST_WIDE_INT, tree));
-static bool sparc_rtx_costs PARAMS ((rtx, int, int, int *));
+static int sparc_adjust_cost (rtx, rtx, rtx, int);
+static int sparc_issue_rate (void);
+static void sparc_sched_init (FILE *, int, int);
+static int sparc_use_dfa_pipeline_interface (void);
+static int sparc_use_sched_lookahead (void);
+
+static void emit_soft_tfmode_libcall (const char *, int, rtx *);
+static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
+static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
+static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
+static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
+
+static bool sparc_function_ok_for_sibcall (tree, tree);
+static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+				   HOST_WIDE_INT, tree);
+static struct machine_function * sparc_init_machine_status (void);
+static bool sparc_cannot_force_const_mem (rtx);
+static rtx sparc_tls_get_addr (void);
+static rtx sparc_tls_got (void);
+static const char *get_some_local_dynamic_name (void);
+static int get_some_local_dynamic_name_1 (rtx *, void *);
+static bool sparc_rtx_costs (rtx, int, int, int *);
 
 /* Option handling.  */
 
@@ -245,6 +252,13 @@ enum processor_type sparc_cpu;
 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
 
+#ifdef HAVE_AS_TLS
+#undef TARGET_HAVE_TLS
+#define TARGET_HAVE_TLS true
+#endif
+#undef TARGET_CANNOT_FORCE_CONST_MEM
+#define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
+
 #undef TARGET_ASM_OUTPUT_MI_THUNK
 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
@@ -261,7 +275,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
    initialization.  */
 
 void
-sparc_override_options ()
+sparc_override_options (void)
 {
   static struct code_model {
     const char *const name;
@@ -453,6 +467,9 @@ sparc_override_options ()
 
   /* Do various machine dependent initializations.  */
   sparc_init_modes ();
+
+  /* Set up function hooks.  */
+  init_machine_status = sparc_init_machine_status;
 }
 
 /* Miscellaneous utilities.  */
@@ -461,8 +478,7 @@ sparc_override_options ()
    or branch on register contents instructions.  */
 
 int
-v9_regcmp_p (code)
-     enum rtx_code code;
+v9_regcmp_p (enum rtx_code code)
 {
   return (code == EQ || code == NE || code == GE || code == LT
 	  || code == LE || code == GT);
@@ -475,9 +491,7 @@ v9_regcmp_p (code)
    or const0_rtx.  */
 
 int
-reg_or_0_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+reg_or_0_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -495,9 +509,7 @@ reg_or_0_operand (op, mode)
 /* Return nonzero only if OP is const1_rtx.  */
 
 int
-const1_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return op == const1_rtx;
 }
@@ -505,9 +517,7 @@ const1_operand (op, mode)
 /* Nonzero if OP is a floating point value with value 0.0.  */
 
 int
-fp_zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fp_zero_operand (rtx op, enum machine_mode mode)
 {
   if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
     return 0;
@@ -517,9 +527,7 @@ fp_zero_operand (op, mode)
 /* Nonzero if OP is a register operand in floating point register.  */
 
 int
-fp_register_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fp_register_operand (rtx op, enum machine_mode mode)
 {
   if (! register_operand (op, mode))
     return 0;
@@ -533,8 +541,7 @@ fp_register_operand (op, mode)
    sethi instruction.  */
 
 int
-fp_sethi_p (op)
-     rtx op;
+fp_sethi_p (rtx op)
 {
   if (GET_CODE (op) == CONST_DOUBLE)
     {
@@ -558,8 +565,7 @@ fp_sethi_p (op)
    mov instruction.  */
 
 int
-fp_mov_p (op)
-     rtx op;
+fp_mov_p (rtx op)
 {
   if (GET_CODE (op) == CONST_DOUBLE)
     {
@@ -583,8 +589,7 @@ fp_mov_p (op)
    instruction sequence.  */
 
 int
-fp_high_losum_p (op)
-     rtx op;
+fp_high_losum_p (rtx op)
 {
   /* The constraints calling this should only be in
      SFmode move insns, so any constant which cannot
@@ -610,9 +615,7 @@ fp_high_losum_p (op)
 /* Nonzero if OP is an integer register.  */
 
 int
-intreg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (register_operand (op, SImode)
 	  || (TARGET_ARCH64 && register_operand (op, DImode)));
@@ -621,9 +624,7 @@ intreg_operand (op, mode)
 /* Nonzero if OP is a floating point condition code register.  */
 
 int
-fcc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fcc_reg_operand (rtx op, enum machine_mode mode)
 {
   /* This can happen when recog is called from combine.  Op may be a MEM.
      Fail instead of calling abort in this case.  */
@@ -648,9 +649,7 @@ fcc_reg_operand (op, mode)
 /* Nonzero if OP is a floating point condition code fcc0 register.  */
 
 int
-fcc0_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+fcc0_reg_operand (rtx op, enum machine_mode mode)
 {
   /* This can happen when recog is called from combine.  Op may be a MEM.
      Fail instead of calling abort in this case.  */
@@ -669,9 +668,7 @@ fcc0_reg_operand (op, mode)
 /* Nonzero if OP is an integer or floating point condition code register.  */
 
 int
-icc_or_fcc_reg_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
     {
@@ -688,9 +685,7 @@ icc_or_fcc_reg_operand (op, mode)
 
 /* Nonzero if OP can appear as the dest of a RESTORE insn.  */
 int
-restore_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+restore_operand (rtx op, enum machine_mode mode)
 {
   return (GET_CODE (op) == REG && GET_MODE (op) == mode
 	  && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
@@ -700,9 +695,7 @@ restore_operand (op, mode)
    memory address.  */
 
 int
-call_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+call_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) != MEM)
     abort ();
@@ -711,20 +704,51 @@ call_operand (op, mode)
 }
 
 int
-call_operand_address (op, mode)
-     rtx op;
-     enum machine_mode mode;
+call_operand_address (rtx op, enum machine_mode mode)
 {
   return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
 }
 
+/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
+   otherwise return 0.  */
+
+int
+tls_symbolic_operand (rtx op)
+{
+  if (GET_CODE (op) != SYMBOL_REF)
+    return 0;
+  return SYMBOL_REF_TLS_MODEL (op);
+}
+
+int
+tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
+}
+
+int
+tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
+}
+
+int
+tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
+}
+
+int
+tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
+{
+  return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
+}
+
 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
    reference and a constant.  */
 
 int
-symbolic_operand (op, mode)
-     register rtx op;
-     enum machine_mode mode;
+symbolic_operand (register rtx op, enum machine_mode mode)
 {
   enum machine_mode omode = GET_MODE (op);
 
@@ -734,12 +758,15 @@ symbolic_operand (op, mode)
   switch (GET_CODE (op))
     {
     case SYMBOL_REF:
+      return !SYMBOL_REF_TLS_MODEL (op);
+
     case LABEL_REF:
       return 1;
 
     case CONST:
       op = XEXP (op, 0);
-      return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+      return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+		&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
 	       || GET_CODE (XEXP (op, 0)) == LABEL_REF)
 	      && GET_CODE (XEXP (op, 1)) == CONST_INT);
 
@@ -752,25 +779,22 @@ symbolic_operand (op, mode)
    operand of mode MODE.  */
 
 int
-symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == SUBREG)
     op = SUBREG_REG (op);
   if (GET_CODE (op) != MEM)
     return 0;
   op = XEXP (op, 0);
-  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
-	  || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
+  return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
+	  || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
+	  || GET_CODE (op) == LABEL_REF);
 }
 
 /* Return truth value of statement that OP is a LABEL_REF of mode MODE.  */
 
 int
-label_ref_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+label_ref_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) != LABEL_REF)
     return 0;
@@ -783,9 +807,7 @@ label_ref_operand (op, mode)
    in either the medium/low or medium/anywhere code models of sparc64.  */
 
 int
-sp64_medium_pic_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   /* Check for (const (minus (symbol_ref:GOT)
                              (const (minus (label) (pc))))).  */
@@ -810,9 +832,7 @@ sp64_medium_pic_operand (op, mode)
    are accessed with EMBMEDANY_BASE_REG.  */
 
 int
-data_segment_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -832,9 +852,7 @@ data_segment_operand (op, mode)
    This is needed in the medium/anywhere code model on v9.  */
 
 int
-text_segment_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   switch (GET_CODE (op))
     {
@@ -856,9 +874,7 @@ text_segment_operand (op, mode)
    not symbolic.  */
 
 int
-reg_or_nonsymb_mem_operand (op, mode)
-    register rtx op;
-    enum machine_mode mode;
+reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -870,9 +886,8 @@ reg_or_nonsymb_mem_operand (op, mode)
 }
 
 int
-splittable_symbolic_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+splittable_symbolic_memory_operand (rtx op,
+				    enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != MEM)
     return 0;
@@ -882,9 +897,8 @@ splittable_symbolic_memory_operand (op, mode)
 }
 
 int
-splittable_immediate_memory_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+splittable_immediate_memory_operand (rtx op,
+				     enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != MEM)
     return 0;
@@ -896,9 +910,7 @@ splittable_immediate_memory_operand (op, mode)
 /* Return truth value of whether OP is EQ or NE.  */
 
 int
-eq_or_neq (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
 }
@@ -907,9 +919,7 @@ eq_or_neq (op, mode)
    or LTU for non-floating-point.  We handle those specially.  */
 
 int
-normal_comp_operator (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -927,9 +937,7 @@ normal_comp_operator (op, mode)
    MATCH_OPERATOR to recognize all the branch insns.  */
 
 int
-noov_compare_op (op, mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
+noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -947,9 +955,7 @@ noov_compare_op (op, mode)
    MATCH_OPERATOR to recognize all the branch insns.  */
 
 int
-noov_compare64_op (op, mode)
-    register rtx op;
-    enum machine_mode mode ATTRIBUTE_UNUSED;
+noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -969,9 +975,7 @@ noov_compare64_op (op, mode)
    conditional move or branch on register contents instructions.  */
 
 int
-v9_regcmp_op (op, mode)
-     register rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   enum rtx_code code = GET_CODE (op);
 
@@ -984,9 +988,7 @@ v9_regcmp_op (op, mode)
 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation.  */
 
 int
-extend_op (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
 }
@@ -996,9 +998,7 @@ extend_op (op, mode)
    because these require CC_NOOVmode, which we handle explicitly.  */
 
 int
-cc_arithop (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) == AND
       || GET_CODE (op) == IOR
@@ -1012,9 +1012,7 @@ cc_arithop (op, mode)
    complement its second operand and set the condition codes explicitly.  */
 
 int
-cc_arithopn (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   /* XOR is not here because combine canonicalizes (xor (not ...) ...)
      and (xor ... (not ...)) to (not (xor ...)).  */
@@ -1027,9 +1025,7 @@ cc_arithopn (op, mode)
    most 3 address instructions.  */
 
 int
-arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_operand (rtx op, enum machine_mode mode)
 {
   if (register_operand (op, mode))
     return 1;
@@ -1041,9 +1037,7 @@ arith_operand (op, mode)
 /* Return true if OP is a constant 4096  */
 
 int
-arith_4096_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   if (GET_CODE (op) != CONST_INT)
     return 0;
@@ -1054,9 +1048,7 @@ arith_4096_operand (op, mode)
 /* Return true if OP is suitable as second operand for add/sub */
 
 int
-arith_add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_add_operand (rtx op, enum machine_mode mode)
 {
   return arith_operand (op, mode) || arith_4096_operand (op, mode);
 }
@@ -1065,9 +1057,7 @@ arith_add_operand (op, mode)
    immediate field of OR and XOR instructions.  Used for 64-bit
    constant formation patterns.  */
 int
-const64_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ((GET_CODE (op) == CONST_INT
 	   && SPARC_SIMM13_P (INTVAL (op)))
@@ -1083,9 +1073,7 @@ const64_operand (op, mode)
 
 /* The same, but only for sethi instructions.  */
 int
-const64_high_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+const64_high_operand (rtx op, enum machine_mode mode)
 {
   return ((GET_CODE (op) == CONST_INT
 	   && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
@@ -1102,9 +1090,7 @@ const64_high_operand (op, mode)
    the movcc instructions.  */
 
 int
-arith11_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith11_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
@@ -1115,9 +1101,7 @@ arith11_operand (op, mode)
    the movrcc instructions.  */
 
 int
-arith10_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith10_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
@@ -1131,9 +1115,7 @@ arith10_operand (op, mode)
    for most 3 address instructions.  */
 
 int
-arith_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_double_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
@@ -1153,9 +1135,7 @@ arith_double_operand (op, mode)
 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
 
 int
-arith_double_4096_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (TARGET_ARCH64 &&
   	  ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
@@ -1167,9 +1147,7 @@ arith_double_4096_operand (op, mode)
 /* Return true if OP is suitable as second operand for add/sub in DImode */
 
 int
-arith_double_add_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith_double_add_operand (rtx op, enum machine_mode mode)
 {
   return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
 }
@@ -1180,9 +1158,7 @@ arith_double_add_operand (op, mode)
 /* ??? Replace with arith11_operand?  */
 
 int
-arith11_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith11_double_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_DOUBLE
@@ -1203,9 +1179,7 @@ arith11_double_operand (op, mode)
 /* ??? Replace with arith10_operand?  */
 
 int
-arith10_double_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+arith10_double_operand (rtx op, enum machine_mode mode)
 {
   return (register_operand (op, mode)
 	  || (GET_CODE (op) == CONST_DOUBLE
@@ -1225,17 +1199,13 @@ arith10_double_operand (op, mode)
    which have a 13 bit immediate field.  */
 
 int
-small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
 }
 
 int
-small_int_or_double (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
 	  || (GET_CODE (op) == CONST_DOUBLE
@@ -1248,9 +1218,7 @@ small_int_or_double (op, mode)
    interprets the extended result as an unsigned number.  */
 
 int
-uns_small_int (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
 #if HOST_BITS_PER_WIDE_INT > 32
   /* All allowed constants will fit a CONST_INT.  */
@@ -1267,18 +1235,14 @@ uns_small_int (op, mode)
 }
 
 int
-uns_arith_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+uns_arith_operand (rtx op, enum machine_mode mode)
 {
   return register_operand (op, mode) || uns_small_int (op, mode);
 }
 
 /* Return truth value of statement that OP is a call-clobbered register.  */
 int
-clobbered_register (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
+clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
 {
   return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
 }
@@ -1286,9 +1250,7 @@ clobbered_register (op, mode)
 /* Return 1 if OP is a valid operand for the source of a move insn.  */
 
 int
-input_operand (op, mode)
-     rtx op;
-     enum machine_mode mode;
+input_operand (rtx op, enum machine_mode mode)
 {
   /* If both modes are non-void they must be the same.  */
   if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
@@ -1370,9 +1332,7 @@ input_operand (op, mode)
 /* We know it can't be done in one insn when we get here,
    the movsi expander guarantees this.  */
 void
-sparc_emit_set_const32 (op0, op1)
-     rtx op0;
-     rtx op1;
+sparc_emit_set_const32 (rtx op0, rtx op1)
 {
   enum machine_mode mode = GET_MODE (op0);
   rtx temp;
@@ -1428,10 +1388,7 @@ sparc_emit_set_const32 (op0, op1)
 
 /* SPARC-v9 code-model support.  */
 void
-sparc_emit_set_symbolic_const64 (op0, op1, temp1)
-     rtx op0;
-     rtx op1;
-     rtx temp1;
+sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp1)
 {
   rtx ti_temp1 = 0;
 
@@ -1571,10 +1528,10 @@ sparc_emit_set_symbolic_const64 (op0, op1, temp1)
 /* These avoid problems when cross compiling.  If we do not
    go through all this hair then the optimizer will see
    invalid REG_EQUAL notes or in some cases none at all.  */
-static void sparc_emit_set_safe_HIGH64 PARAMS ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_SET64 PARAMS ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_OR64 PARAMS ((rtx, HOST_WIDE_INT));
-static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
+static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
+static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
+static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
+static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
 
 #if HOST_BITS_PER_WIDE_INT == 64
 #define GEN_HIGHINT64(__x)		GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
@@ -1593,33 +1550,25 @@ static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
    during CSE.  We mask out the non-HIGH bits, and matches
    a plain movdi, to alleviate this problem.  */
 static void
-sparc_emit_set_safe_HIGH64 (dest, val)
-     rtx dest;
-     HOST_WIDE_INT val;
+sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
 {
   emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
 }
 
 static rtx
-gen_safe_SET64 (dest, val)
-     rtx dest;
-     HOST_WIDE_INT val;
+gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
 {
   return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
 }
 
 static rtx
-gen_safe_OR64 (src, val)
-     rtx src;
-     HOST_WIDE_INT val;
+gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
 {
   return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
 }
 
 static rtx
-gen_safe_XOR64 (src, val)
-     rtx src;
-     HOST_WIDE_INT val;
+gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
 {
   return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
 }
@@ -1632,15 +1581,12 @@ gen_safe_XOR64 (src, val)
    Without doing this, the optimizer cannot see such
    opportunities.  */
 
-static void sparc_emit_set_const64_quick1
-	PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, int));
+static void sparc_emit_set_const64_quick1 (rtx, rtx,
+					   unsigned HOST_WIDE_INT, int);
 
 static void
-sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
-  rtx op0;
-  rtx temp;
-  unsigned HOST_WIDE_INT low_bits;
-  int is_neg;
+sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
+			       unsigned HOST_WIDE_INT low_bits, int is_neg)
 {
   unsigned HOST_WIDE_INT high_bits;
 
@@ -1675,17 +1621,14 @@ sparc_emit_set_const64_quick1 (op0, temp, low_bits, is_neg)
     }
 }
 
-static void sparc_emit_set_const64_quick2
-	PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT,
-	       unsigned HOST_WIDE_INT, int));
+static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
+					   unsigned HOST_WIDE_INT, int);
 
 static void
-sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
-  rtx op0;
-  rtx temp;
-  unsigned HOST_WIDE_INT high_bits;
-  unsigned HOST_WIDE_INT low_immediate;
-  int shift_count;
+sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
+			       unsigned HOST_WIDE_INT high_bits,
+			       unsigned HOST_WIDE_INT low_immediate,
+			       int shift_count)
 {
   rtx temp2 = op0;
 
@@ -1716,17 +1659,15 @@ sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_immediate, shift_count)
 			    gen_safe_OR64 (op0, low_immediate)));
 }
 
-static void sparc_emit_set_const64_longway
-	PARAMS ((rtx, rtx, unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
+static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
+					    unsigned HOST_WIDE_INT);
 
 /* Full 64-bit constant decomposition.  Even though this is the
    'worst' case, we still optimize a few things away.  */
 static void
-sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
-     rtx op0;
-     rtx temp;
-     unsigned HOST_WIDE_INT high_bits;
-     unsigned HOST_WIDE_INT low_bits;
+sparc_emit_set_const64_longway (rtx op0, rtx temp,
+				unsigned HOST_WIDE_INT high_bits,
+				unsigned HOST_WIDE_INT low_bits)
 {
   rtx sub_temp;
 
@@ -1824,15 +1765,14 @@ sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits)
 }
 
 /* Analyze a 64-bit constant for certain properties.  */
-static void analyze_64bit_constant
-	PARAMS ((unsigned HOST_WIDE_INT,
-	       unsigned HOST_WIDE_INT,
-	       int *, int *, int *));
+static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
+				    unsigned HOST_WIDE_INT,
+				    int *, int *, int *);
 
 static void
-analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
-     int *hbsp, *lbsp, *abbasp;
+analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
+			unsigned HOST_WIDE_INT low_bits,
+			int *hbsp, int *lbsp, int *abbasp)
 {
   int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
   int i;
@@ -1893,12 +1833,11 @@ analyze_64bit_constant (high_bits, low_bits, hbsp, lbsp, abbasp)
   *abbasp = all_bits_between_are_set;
 }
 
-static int const64_is_2insns
-	PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT));
+static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
 
 static int
-const64_is_2insns (high_bits, low_bits)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
+const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
+		   unsigned HOST_WIDE_INT low_bits)
 {
   int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
 
@@ -1921,14 +1860,14 @@ const64_is_2insns (high_bits, low_bits)
   return 0;
 }
 
-static unsigned HOST_WIDE_INT create_simple_focus_bits
-	PARAMS ((unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT,
-	       int, int));
+static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
+							unsigned HOST_WIDE_INT,
+							int, int);
 
 static unsigned HOST_WIDE_INT
-create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
-     unsigned HOST_WIDE_INT high_bits, low_bits;
-     int lowest_bit_set, shift;
+create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
+			  unsigned HOST_WIDE_INT low_bits,
+			  int lowest_bit_set, int shift)
 {
   HOST_WIDE_INT hi, lo;
 
@@ -1952,9 +1891,7 @@ create_simple_focus_bits (high_bits, low_bits, lowest_bit_set, shift)
    insn sequence possible.  Detection of all the 1-insn cases
    has been done already.  */
 void
-sparc_emit_set_const64 (op0, op1)
-     rtx op0;
-     rtx op1;
+sparc_emit_set_const64 (rtx op0, rtx op1)
 {
   unsigned HOST_WIDE_INT high_bits, low_bits;
   int lowest_bit_set, highest_bit_set;
@@ -2232,10 +2169,7 @@ sparc_emit_set_const64 (op0, op1)
    processing is needed.  */
 
 enum machine_mode
-select_cc_mode (op, x, y)
-     enum rtx_code op;
-     rtx x;
-     rtx y ATTRIBUTE_UNUSED;
+select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
 {
   if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
     {
@@ -2284,9 +2218,7 @@ select_cc_mode (op, x, y)
    return the rtx for the cc reg in the proper mode.  */
 
 rtx
-gen_compare_reg (code, x, y)
-     enum rtx_code code;
-     rtx x, y;
+gen_compare_reg (enum rtx_code code, rtx x, rtx y)
 {
   enum machine_mode mode = SELECT_CC_MODE (code, x, y);
   rtx cc_reg;
@@ -2367,9 +2299,7 @@ gen_compare_reg (code, x, y)
    sparc_compare_op1.  */
 
 int
-gen_v9_scc (compare_code, operands)
-     enum rtx_code compare_code;
-     register rtx *operands;
+gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
 {
   rtx temp, op0, op1;
 
@@ -2457,9 +2387,7 @@ gen_v9_scc (compare_code, operands)
    This function exists to take advantage of the v9 brxx insns.  */
 
 void
-emit_v9_brxx_insn (code, op0, label)
-     enum rtx_code code;
-     rtx op0, label;
+emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
 {
   emit_jump_insn (gen_rtx_SET (VOIDmode,
 			   pc_rtx,
@@ -2475,9 +2403,7 @@ emit_v9_brxx_insn (code, op0, label)
    low 64bit of the register and 0 otherwise.
  */
 rtx
-gen_df_reg (reg, low)
-     rtx reg;
-     int low;
+gen_df_reg (rtx reg, int low)
 {
   int regno = REGNO (reg);
 
@@ -2491,10 +2417,7 @@ gen_df_reg (reg, low)
    assumed that no more than 3 operands are required.  */
 
 static void
-emit_soft_tfmode_libcall (func_name, nargs, operands)
-     const char *func_name;
-     int nargs;
-     rtx *operands;
+emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
 {
   rtx ret_slot = NULL, arg[3], func_sym;
   int i;
@@ -2579,9 +2502,7 @@ emit_soft_tfmode_libcall (func_name, nargs, operands)
 /* Expand soft-float TFmode calls to sparc abi routines.  */
 
 static void
-emit_soft_tfmode_binop (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
 {
   const char *func;
 
@@ -2607,9 +2528,7 @@ emit_soft_tfmode_binop (code, operands)
 }
 
 static void
-emit_soft_tfmode_unop (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
 {
   const char *func;
 
@@ -2626,9 +2545,7 @@ emit_soft_tfmode_unop (code, operands)
 }
 
 static void
-emit_soft_tfmode_cvt (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
 {
   const char *func;
 
@@ -2729,9 +2646,7 @@ emit_soft_tfmode_cvt (code, operands)
    registers.  */
 
 static void
-emit_hard_tfmode_operation (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
 {
   rtx op, dest;
 
@@ -2760,9 +2675,7 @@ emit_hard_tfmode_operation (code, operands)
 }
 
 void
-emit_tfmode_binop (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_tfmode_binop (enum rtx_code code, rtx *operands)
 {
   if (TARGET_HARD_QUAD)
     emit_hard_tfmode_operation (code, operands);
@@ -2771,9 +2684,7 @@ emit_tfmode_binop (code, operands)
 }
 
 void
-emit_tfmode_unop (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_tfmode_unop (enum rtx_code code, rtx *operands)
 {
   if (TARGET_HARD_QUAD)
     emit_hard_tfmode_operation (code, operands);
@@ -2782,9 +2693,7 @@ emit_tfmode_unop (code, operands)
 }
 
 void
-emit_tfmode_cvt (code, operands)
-     enum rtx_code code;
-     rtx *operands;
+emit_tfmode_cvt (enum rtx_code code, rtx *operands)
 {
   if (TARGET_HARD_QUAD)
     emit_hard_tfmode_operation (code, operands);
@@ -2795,7 +2704,7 @@ emit_tfmode_cvt (code, operands)
 /* Return nonzero if a return peephole merging return with
    setting of output register is ok.  */
 int
-leaf_return_peephole_ok ()
+leaf_return_peephole_ok (void)
 {
   return (actual_fsize == 0);
 }
@@ -2804,8 +2713,7 @@ leaf_return_peephole_ok ()
    nop into its delay slot.  */
 
 int
-empty_delay_slot (insn)
-     rtx insn;
+empty_delay_slot (rtx insn)
 {
   rtx seq;
 
@@ -2824,9 +2732,7 @@ empty_delay_slot (insn)
    delay slot.  SLOT is the slot we are trying to fill.  */
 
 int
-eligible_for_epilogue_delay (trial, slot)
-     rtx trial;
-     int slot;
+eligible_for_epilogue_delay (rtx trial, int slot)
 {
   rtx pat, src;
 
@@ -2948,12 +2854,37 @@ eligible_for_epilogue_delay (trial, slot)
   return 0;
 }
 
+/* Return nonzero if TRIAL can go into the call delay slot.  */
+int
+tls_call_delay (rtx trial)
+{
+  rtx pat, unspec;
+
+  /* Binutils allows
+     call __tls_get_addr, %tgd_call (foo)
+      add %l7, %o0, %o0, %tgd_add (foo)
+     while Sun as/ld does not.  */
+  if (TARGET_GNU_TLS || !TARGET_TLS)
+    return 1;
+
+  pat = PATTERN (trial);
+  if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
+    return 1;
+
+  unspec = XEXP (SET_DEST (pat), 1);
+  if (GET_CODE (unspec) != UNSPEC
+      || (XINT (unspec, 1) != UNSPEC_TLSGD
+	  && XINT (unspec, 1) != UNSPEC_TLSLDM))
+    return 1;
+
+  return 0;
+}
+
 /* Return nonzero if TRIAL can go into the sibling call
    delay slot.  */
 
 int
-eligible_for_sibcall_delay (trial)
-     rtx trial;
+eligible_for_sibcall_delay (rtx trial)
 {
   rtx pat, src;
 
@@ -3043,8 +2974,7 @@ eligible_for_sibcall_delay (trial)
 }
 
 static int
-check_return_regs (x)
-     rtx x;
+check_return_regs (rtx x)
 {
   switch (GET_CODE (x))
     {
@@ -3078,8 +3008,7 @@ check_return_regs (x)
 }
 
 int
-short_branch (uid1, uid2)
-     int uid1, uid2;
+short_branch (int uid1, int uid2)
 {
   int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
 
@@ -3094,9 +3023,7 @@ short_branch (uid1, uid2)
    We assume REG is a reload reg, and therefore does
    not live past labels or calls or jumps.  */
 int
-reg_unused_after (reg, insn)
-     rtx reg;
-     rtx insn;
+reg_unused_after (rtx reg, rtx insn)
 {
   enum rtx_code code, prev_code = UNKNOWN;
 
@@ -3125,6 +3052,45 @@ reg_unused_after (reg, insn)
   return 1;
 }
 
+/* Determine if it's legal to put X into the constant pool.  This
+   is not possible if X contains the address of a symbol that is
+   not constant (TLS) or not known at final link time (PIC).  */
+
+static bool
+sparc_cannot_force_const_mem (rtx x)
+{
+  switch (GET_CODE (x))
+    {
+    case CONST_INT:
+    case CONST_DOUBLE:
+      /* Accept all non-symbolic constants.  */
+      return false;
+
+    case LABEL_REF:
+      /* Labels are OK iff we are non-PIC.  */
+      return flag_pic != 0;
+
+    case SYMBOL_REF:
+      /* 'Naked' TLS symbol references are never OK,
+	 non-TLS symbols are OK iff we are non-PIC.  */
+      if (SYMBOL_REF_TLS_MODEL (x))
+	return true;
+      else
+	return flag_pic != 0;
+
+    case CONST:
+      return sparc_cannot_force_const_mem (XEXP (x, 0));
+    case PLUS:
+    case MINUS:
+      return sparc_cannot_force_const_mem (XEXP (x, 0))
+         || sparc_cannot_force_const_mem (XEXP (x, 1));
+    case UNSPEC:
+      return true;
+    default:
+      abort ();
+    }
+}
+
 /* The table we use to reference PIC data.  */
 static GTY(()) rtx global_offset_table;
 
@@ -3135,8 +3101,7 @@ static char get_pc_symbol_name[256];
 /* Ensure that we are not using patterns that are not OK with PIC.  */
 
 int
-check_pic (i)
-     int i;
+check_pic (int i)
 {
   switch (flag_pic)
     {
@@ -3159,8 +3124,7 @@ check_pic (i)
    reloaded while generating PIC code.  */
 
 int
-pic_address_needs_scratch (x)
-     rtx x;
+pic_address_needs_scratch (rtx x)
 {
   /* An address which is a symbolic plus a non SMALL_INT needs a temp reg.  */
   if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
@@ -3172,16 +3136,399 @@ pic_address_needs_scratch (x)
   return 0;
 }
 
+/* Determine if a given RTX is a valid constant.  We already know this
+   satisfies CONSTANT_P.  */
+
+bool
+legitimate_constant_p (rtx x)
+{
+  rtx inner;
+
+  switch (GET_CODE (x))
+    {
+    case SYMBOL_REF:
+      /* TLS symbols are not constant.  */
+      if (SYMBOL_REF_TLS_MODEL (x))
+	return false;
+      break;
+
+    case CONST:
+      inner = XEXP (x, 0);
+
+      /* Offsets of TLS symbols are never valid.
+	 Discourage CSE from creating them.  */
+      if (GET_CODE (inner) == PLUS
+	  && tls_symbolic_operand (XEXP (inner, 0)))
+	return false;
+      break;
+
+    case CONST_DOUBLE:
+      if (GET_MODE (x) == VOIDmode)
+        return true;
+
+      /* Floating point constants are generally not ok.
+	 The only exception is 0.0 in VIS.  */
+      if (TARGET_VIS
+	  && (GET_MODE (x) == SFmode
+	      || GET_MODE (x) == DFmode
+	      || GET_MODE (x) == TFmode)
+	  && fp_zero_operand (x, GET_MODE (x)))
+	return true;
+
+      return false;
+
+    default:
+      break;
+    }
+
+  return true;
+}
+
+/* Determine if a given RTX is a valid constant address.  */
+
+bool
+constant_address_p (rtx x)
+{
+  switch (GET_CODE (x))
+    {
+    case LABEL_REF:
+    case CONST_INT:
+    case HIGH:
+      return true;
+
+    case CONST:
+      if (flag_pic && pic_address_needs_scratch (x))
+	return false;
+      return legitimate_constant_p (x);
+
+    case SYMBOL_REF:
+      return !flag_pic && legitimate_constant_p (x);
+
+    default:
+      return false;
+    }
+}
+
+/* Nonzero if the constant value X is a legitimate general operand
+   when generating PIC code.  It is given that flag_pic is on and
+   that X satisfies CONSTANT_P or is a CONST_DOUBLE.  */
+
+bool
+legitimate_pic_operand_p (rtx x)
+{
+  if (pic_address_needs_scratch (x))
+    return false;
+  if (tls_symbolic_operand (x)
+      || (GET_CODE (x) == CONST
+	  && GET_CODE (XEXP (x, 0)) == PLUS
+	  && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
+    return false;
+  return true;
+}
+
+/* Return nonzero if ADDR is a valid memory address.
+   STRICT specifies whether strict register checking applies.  */
+   
+int
+legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
+{
+  rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
+
+  if (REG_P (addr) || GET_CODE (addr) == SUBREG)
+    rs1 = addr;
+  else if (GET_CODE (addr) == PLUS)
+    {
+      rs1 = XEXP (addr, 0);
+      rs2 = XEXP (addr, 1);
+
+      /* Canonicalize.  REG comes first, if there are no regs,
+	 LO_SUM comes first.  */
+      if (!REG_P (rs1)
+	  && GET_CODE (rs1) != SUBREG
+	  && (REG_P (rs2)
+	      || GET_CODE (rs2) == SUBREG
+	      || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
+	{
+	  rs1 = XEXP (addr, 1);
+	  rs2 = XEXP (addr, 0);
+	}
+
+      if ((flag_pic == 1
+	   && rs1 == pic_offset_table_rtx
+	   && !REG_P (rs2)
+	   && GET_CODE (rs2) != SUBREG
+	   && GET_CODE (rs2) != LO_SUM
+	   && GET_CODE (rs2) != MEM
+	   && !tls_symbolic_operand (rs2)
+	   && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
+	   && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
+	  || ((REG_P (rs1)
+	       || GET_CODE (rs1) == SUBREG)
+	      && RTX_OK_FOR_OFFSET_P (rs2)))
+	{
+	  imm1 = rs2;
+	  rs2 = NULL;
+	}
+      else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
+	       && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
+	{
+	  /* We prohibit REG + REG for TFmode when there are no instructions
+	     which accept REG+REG instructions.  We do this because REG+REG
+	     is not an offsetable address.  If we get the situation in reload
+	     where source and destination of a movtf pattern are both MEMs with
+	     REG+REG address, then only one of them gets converted to an
+	     offsetable address.  */
+	  if (mode == TFmode
+	      && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
+		   && TARGET_HARD_QUAD))
+	    return 0;
+
+	  /* We prohibit REG + REG on ARCH32 if not optimizing for
+	     DFmode/DImode because then mem_min_alignment is likely to be zero
+	     after reload and the  forced split would lack a matching splitter
+	     pattern.  */
+	  if (TARGET_ARCH32 && !optimize
+	      && (mode == DFmode || mode == DImode))
+	    return 0;
+	}
+      else if (USE_AS_OFFSETABLE_LO10
+	       && GET_CODE (rs1) == LO_SUM
+	       && TARGET_ARCH64
+	       && ! TARGET_CM_MEDMID
+	       && RTX_OK_FOR_OLO10_P (rs2))
+	{
+	  imm2 = rs2;
+	  rs2 = NULL;
+	  imm1 = XEXP (rs1, 1);
+	  rs1 = XEXP (rs1, 0);
+	  if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
+	    return 0;
+	}
+    }
+  else if (GET_CODE (addr) == LO_SUM)
+    {
+      rs1 = XEXP (addr, 0);
+      imm1 = XEXP (addr, 1);
+
+      if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
+	return 0;
+
+      /* We can't allow TFmode, because an offset greater than or equal to the
+         alignment (8) may cause the LO_SUM to overflow if !v9.  */
+      if (mode == TFmode && !TARGET_V9)
+	return 0;
+    }
+  else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
+    return 1;
+  else
+    return 0;
+
+  if (GET_CODE (rs1) == SUBREG)
+    rs1 = SUBREG_REG (rs1);
+  if (!REG_P (rs1))
+    return 0;
+
+  if (rs2)
+    {
+      if (GET_CODE (rs2) == SUBREG)
+	rs2 = SUBREG_REG (rs2);
+      if (!REG_P (rs2))
+	return 0;
+    }
+
+  if (strict)
+    {
+      if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
+	  || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
+	return 0;
+    }
+  else
+    {
+      if ((REGNO (rs1) >= 32
+	   && REGNO (rs1) != FRAME_POINTER_REGNUM
+	   && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
+	  || (rs2
+	      && (REGNO (rs2) >= 32
+		  && REGNO (rs2) != FRAME_POINTER_REGNUM
+		  && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
+	return 0;
+    }
+  return 1;
+}
+
+/* Construct the SYMBOL_REF for the tls_get_offset function.  */
+
+static GTY(()) rtx sparc_tls_symbol;
+static rtx
+sparc_tls_get_addr (void)
+{
+  if (!sparc_tls_symbol)
+    sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
+
+  return sparc_tls_symbol;
+}
+
+static rtx
+sparc_tls_got (void)
+{
+  rtx temp;
+  if (flag_pic)
+    {
+      current_function_uses_pic_offset_table = 1;
+      return pic_offset_table_rtx;
+    }
+
+  if (!global_offset_table)
+    global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
+  temp = gen_reg_rtx (Pmode);
+  emit_move_insn (temp, global_offset_table);
+  return temp;
+}
+
+
+/* ADDR contains a thread-local SYMBOL_REF.  Generate code to compute
+   this (thread-local) address.  */
+
+rtx
+legitimize_tls_address (rtx addr)
+{
+  rtx temp1, temp2, temp3, ret, o0, got, insn;
+
+  if (no_new_pseudos)
+    abort ();
+
+  if (GET_CODE (addr) == SYMBOL_REF)
+    switch (SYMBOL_REF_TLS_MODEL (addr))
+      {
+      case TLS_MODEL_GLOBAL_DYNAMIC:
+	start_sequence ();
+	temp1 = gen_reg_rtx (SImode);
+	temp2 = gen_reg_rtx (SImode);
+	ret = gen_reg_rtx (Pmode);
+	o0 = gen_rtx_REG (Pmode, 8);
+	got = sparc_tls_got ();
+	emit_insn (gen_tgd_hi22 (temp1, addr));
+	emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
+	if (TARGET_ARCH32)
+	  {
+	    emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
+	    insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
+						   addr, const1_rtx));
+	  }
+	else
+	  {
+	    emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
+	    insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
+						   addr, const1_rtx));
+	  }
+        CALL_INSN_FUNCTION_USAGE (insn)
+	  = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
+			       CALL_INSN_FUNCTION_USAGE (insn));
+	insn = get_insns ();
+	end_sequence ();
+	emit_libcall_block (insn, ret, o0, addr);
+	break;
+
+      case TLS_MODEL_LOCAL_DYNAMIC:
+	start_sequence ();
+	temp1 = gen_reg_rtx (SImode);
+	temp2 = gen_reg_rtx (SImode);
+	temp3 = gen_reg_rtx (Pmode);
+	ret = gen_reg_rtx (Pmode);
+	o0 = gen_rtx_REG (Pmode, 8);
+	got = sparc_tls_got ();
+	emit_insn (gen_tldm_hi22 (temp1));
+	emit_insn (gen_tldm_lo10 (temp2, temp1));
+	if (TARGET_ARCH32)
+	  {
+	    emit_insn (gen_tldm_add32 (o0, got, temp2));
+	    insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
+						    const1_rtx));
+	  }
+	else
+	  {
+	    emit_insn (gen_tldm_add64 (o0, got, temp2));
+	    insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
+						    const1_rtx));
+	  }
+        CALL_INSN_FUNCTION_USAGE (insn)
+	  = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
+			       CALL_INSN_FUNCTION_USAGE (insn));
+	insn = get_insns ();
+	end_sequence ();
+	emit_libcall_block (insn, temp3, o0,
+			    gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
+					    UNSPEC_TLSLD_BASE));
+	temp1 = gen_reg_rtx (SImode);
+	temp2 = gen_reg_rtx (SImode);
+	emit_insn (gen_tldo_hix22 (temp1, addr));
+	emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
+	if (TARGET_ARCH32)
+	  emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
+	else
+	  emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
+	break;
+
+      case TLS_MODEL_INITIAL_EXEC:
+	temp1 = gen_reg_rtx (SImode);
+	temp2 = gen_reg_rtx (SImode);
+	temp3 = gen_reg_rtx (Pmode);
+	got = sparc_tls_got ();
+	emit_insn (gen_tie_hi22 (temp1, addr));
+	emit_insn (gen_tie_lo10 (temp2, temp1, addr));
+	if (TARGET_ARCH32)
+	  emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
+	else
+	  emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
+        if (TARGET_SUN_TLS)
+	  {
+	    ret = gen_reg_rtx (Pmode);
+	    if (TARGET_ARCH32)
+	      emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
+					temp3, addr));
+	    else
+	      emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
+					temp3, addr));
+	  }
+	else
+	  ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
+	break;
+
+      case TLS_MODEL_LOCAL_EXEC:
+	temp1 = gen_reg_rtx (Pmode);
+	temp2 = gen_reg_rtx (Pmode);
+	if (TARGET_ARCH32)
+	  {
+	    emit_insn (gen_tle_hix22_sp32 (temp1, addr));
+	    emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
+	  }
+	else
+	  {
+	    emit_insn (gen_tle_hix22_sp64 (temp1, addr));
+	    emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
+	  }
+	ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
+	break;
+
+      default:
+	abort ();
+      }
+
+  else
+    abort ();  /* for now ... */
+
+  return ret;
+}
+
+
 /* Legitimize PIC addresses.  If the address is already position-independent,
    we return ORIG.  Newly generated position-independent addresses go into a
    reg.  This is REG if nonzero, otherwise we allocate register(s) as
    necessary.  */
 
 rtx
-legitimize_pic_address (orig, mode, reg)
-     rtx orig;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-     rtx reg;
+legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
+			rtx reg)
 {
   if (GET_CODE (orig) == SYMBOL_REF)
     {
@@ -3281,10 +3628,56 @@ legitimize_pic_address (orig, mode, reg)
   return orig;
 }
 
+/* Try machine-dependent ways of modifying an illegitimate address X
+   to be legitimate.  If we find one, return the new, valid address.
+
+   OLDX is the address as it was before break_out_memory_refs was called.
+   In some cases it is useful to look at this to decide what needs to be done.
+
+   MODE is the mode of the operand pointed to by X.  */
+
+rtx
+legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
+{
+  rtx orig_x = x;
+
+  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
+    x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
+		      force_operand (XEXP (x, 0), NULL_RTX));
+  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
+    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
+		      force_operand (XEXP (x, 1), NULL_RTX));
+  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
+    x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
+		      XEXP (x, 1));
+  if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
+    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
+		      force_operand (XEXP (x, 1), NULL_RTX));
+
+  if (x != orig_x && legitimate_address_p (mode, x, FALSE))
+    return x;
+
+  if (tls_symbolic_operand (x))
+    x = legitimize_tls_address (x);
+  else if (flag_pic)
+    x = legitimize_pic_address (x, mode, 0);
+  else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
+    x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
+		      copy_to_mode_reg (Pmode, XEXP (x, 1)));
+  else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
+    x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
+		      copy_to_mode_reg (Pmode, XEXP (x, 0)));
+  else if (GET_CODE (x) == SYMBOL_REF
+	   || GET_CODE (x) == CONST
+           || GET_CODE (x) == LABEL_REF)
+    x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
+  return x;
+}
+
 /* Emit special PIC prologues.  */
 
 void
-load_pic_register ()
+load_pic_register (void)
 {
   /* Labels to get the PC in the prologue of this function.  */
   int orig_flag_pic = flag_pic;
@@ -3329,9 +3722,7 @@ load_pic_register ()
    least a DESIRED byte boundary.  */
 
 int
-mem_min_alignment (mem, desired)
-     rtx mem;
-     int desired;
+mem_min_alignment (rtx mem, int desired)
 {
   rtx addr, base, offset;
 
@@ -3524,7 +3915,7 @@ int sparc_mode_class [NUM_MACHINE_MODES];
 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
 
 static void
-sparc_init_modes ()
+sparc_init_modes (void)
 {
   int i;
 
@@ -3602,13 +3993,8 @@ sparc_init_modes ()
    v9 int regs as it simplifies the code.  */
 
 static int
-save_regs (file, low, high, base, offset, n_regs, real_offset)
-     FILE *file;
-     int low, high;
-     const char *base;
-     int offset;
-     int n_regs;
-     int real_offset;
+save_regs (FILE *file, int low, int high, const char *base,
+	   int offset, int n_regs, int real_offset)
 {
   int i;
 
@@ -3675,12 +4061,8 @@ save_regs (file, low, high, base, offset, n_regs, real_offset)
    v9 int regs as it simplifies the code.  */
 
 static int
-restore_regs (file, low, high, base, offset, n_regs)
-     FILE *file;
-     int low, high;
-     const char *base;
-     int offset;
-     int n_regs;
+restore_regs (FILE *file, int low, int high, const char *base,
+	      int offset, int n_regs)
 {
   int i;
 
@@ -3720,9 +4102,7 @@ restore_regs (file, low, high, base, offset, n_regs)
    during the reload pass and also by output_function_prologue().  */
 
 int
-compute_frame_size (size, leaf_function)
-     int size;
-     int leaf_function;
+compute_frame_size (int size, int leaf_function)
 {
   int n_regs = 0, i;
   int outgoing_args_size = (current_function_outgoing_args_size
@@ -3780,10 +4160,7 @@ compute_frame_size (size, leaf_function)
 /* ??? We may be able to use the set macro here too.  */
 
 static void
-build_big_number (file, num, reg)
-     FILE *file;
-     int num;
-     const char *reg;
+build_big_number (FILE *file, int num, const char *reg)
 {
   if (num >= 0 || ! TARGET_ARCH64)
     {
@@ -3809,8 +4186,7 @@ build_big_number (file, num, reg)
 
 /* Output any necessary .register pseudo-ops.  */
 void
-sparc_output_scratch_registers (file)
-     FILE *file ATTRIBUTE_UNUSED;
+sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
 {
 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
   int i;
@@ -3850,9 +4226,7 @@ sparc_output_scratch_registers (file)
    to do this is made in regclass.c.  */
 
 static void
-sparc_output_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size;
+sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
 {
   if (TARGET_FLAT)
     sparc_flat_function_prologue (file, size);
@@ -3864,10 +4238,8 @@ sparc_output_function_prologue (file, size)
 /* Output code for the function prologue.  */
 
 static void
-sparc_nonflat_function_prologue (file, size, leaf_function)
-     FILE *file;
-     HOST_WIDE_INT size;
-     int leaf_function;
+sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
+				 int leaf_function)
 {
   sparc_output_scratch_registers (file);
 
@@ -3982,9 +4354,7 @@ sparc_nonflat_function_prologue (file, size, leaf_function)
 /* Output code to restore any call saved registers.  */
 
 static void
-output_restore_regs (file, leaf_function)
-     FILE *file;
-     int leaf_function ATTRIBUTE_UNUSED;
+output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
 {
   int offset, n_regs;
   const char *base;
@@ -4015,9 +4385,7 @@ output_restore_regs (file, leaf_function)
    before returning.  */
 
 static void
-sparc_output_function_epilogue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size;
+sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
 {
   if (TARGET_FLAT)
     sparc_flat_function_epilogue (file, size);
@@ -4029,10 +4397,9 @@ sparc_output_function_epilogue (file, size)
 /* Output code for the function epilogue.  */
 
 static void
-sparc_nonflat_function_epilogue (file, size, leaf_function)
-     FILE *file;
-     HOST_WIDE_INT size ATTRIBUTE_UNUSED;
-     int leaf_function;
+sparc_nonflat_function_epilogue (FILE *file,
+				 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
+				 int leaf_function)
 {
   const char *ret;
 
@@ -4046,11 +4413,19 @@ sparc_nonflat_function_epilogue (file, size, leaf_function)
 	 of a function were call foo; dslot; this can make the return
 	 PC of foo (ie. address of call instruction plus 8) point to
 	 the first instruction in the next function.  */
-      rtx insn;
-
-      fputs("\tnop\n", file);
+      rtx insn, last_real_insn;
 
       insn = get_last_insn ();
+
+      last_real_insn = prev_real_insn (insn);
+      if (last_real_insn
+	  && GET_CODE (last_real_insn) == INSN
+	  && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
+	last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
+
+      if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
+	fputs("\tnop\n", file);
+
       if (GET_CODE (insn) == NOTE)
 	      insn = prev_nonnote_insn (insn);
       if (insn && GET_CODE (insn) == BARRIER)
@@ -4161,8 +4536,7 @@ sparc_nonflat_function_epilogue (file, size, leaf_function)
 /* Output a sibling call.  */
 
 const char *
-output_sibcall (insn, call_operand)
-     rtx insn, call_operand;
+output_sibcall (rtx insn, rtx call_operand)
 {
   int leaf_regs = current_function_uses_only_leaf_regs;
   rtx operands[3];
@@ -4364,11 +4738,9 @@ output_sibcall (insn, call_operand)
    For a library call, FNTYPE is 0.  */
 
 void
-init_cumulative_args (cum, fntype, libname, fndecl)
-     CUMULATIVE_ARGS *cum;
-     tree fntype;
-     rtx libname ATTRIBUTE_UNUSED;
-     tree fndecl ATTRIBUTE_UNUSED;
+init_cumulative_args (struct sparc_args *cum, tree fntype,
+		      rtx libname ATTRIBUTE_UNUSED,
+		      tree fndecl ATTRIBUTE_UNUSED)
 {
   cum->words = 0;
   cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
@@ -4391,14 +4763,9 @@ init_cumulative_args (cum, fntype, libname, fndecl)
    *PPADDING records the amount of padding needed in words.  */
 
 static int
-function_arg_slotno (cum, mode, type, named, incoming_p, pregno, ppadding)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     int incoming_p;
-     int *pregno;
-     int *ppadding;
+function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
+		     tree type, int named, int incoming_p,
+		     int *pregno, int *ppadding)
 {
   int regbase = (incoming_p
 		 ? SPARC_INCOMING_INT_ARG_FIRST
@@ -4541,24 +4908,19 @@ struct function_arg_record_value_parms
 };
 
 static void function_arg_record_value_3
-	PARAMS ((HOST_WIDE_INT, struct function_arg_record_value_parms *));
+ (HOST_WIDE_INT, struct function_arg_record_value_parms *);
 static void function_arg_record_value_2
-	PARAMS ((tree, HOST_WIDE_INT,
-		 struct function_arg_record_value_parms *));
+ (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
 static void function_arg_record_value_1
-        PARAMS ((tree, HOST_WIDE_INT,
-		 struct function_arg_record_value_parms *));
-static rtx function_arg_record_value
-	PARAMS ((tree, enum machine_mode, int, int, int));
+ (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *);
+static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
 
 /* A subroutine of function_arg_record_value.  Traverse the structure
    recursively and determine how many registers will be required.  */
 
 static void
-function_arg_record_value_1 (type, startbitpos, parms)
-     tree type;
-     HOST_WIDE_INT startbitpos;
-     struct function_arg_record_value_parms *parms;
+function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
+			     struct function_arg_record_value_parms *parms)
 {
   tree field;
 
@@ -4642,9 +5004,8 @@ function_arg_record_value_1 (type, startbitpos, parms)
    structure between parms->intoffset and bitpos to integer registers.  */
 
 static void 
-function_arg_record_value_3 (bitpos, parms)
-     HOST_WIDE_INT bitpos;
-     struct function_arg_record_value_parms *parms;
+function_arg_record_value_3 (HOST_WIDE_INT bitpos,
+			     struct function_arg_record_value_parms *parms)
 {
   enum machine_mode mode;
   unsigned int regno;
@@ -4700,10 +5061,8 @@ function_arg_record_value_3 (bitpos, parms)
    to make that happen.  */
 
 static void
-function_arg_record_value_2 (type, startbitpos, parms)
-     tree type;
-     HOST_WIDE_INT startbitpos;
-     struct function_arg_record_value_parms *parms;
+function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
+			     struct function_arg_record_value_parms *parms)
 {
   tree field;
   int packed_p = 0;
@@ -4795,10 +5154,8 @@ function_arg_record_value_2 (type, startbitpos, parms)
    REGBASE is the regno of the base register for the parameter array.  */
    
 static rtx
-function_arg_record_value (type, mode, slotno, named, regbase)
-     tree type;
-     enum machine_mode mode;
-     int slotno, named, regbase;
+function_arg_record_value (tree type, enum machine_mode mode,
+			   int slotno, int named, int regbase)
 {
   HOST_WIDE_INT typesize = int_size_in_bytes (type);
   struct function_arg_record_value_parms parms;
@@ -4900,12 +5257,8 @@ function_arg_record_value (type, mode, slotno, named, regbase)
    INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.  */
 
 rtx
-function_arg (cum, mode, type, named, incoming_p)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
-     int incoming_p;
+function_arg (const struct sparc_args *cum, enum machine_mode mode,
+	      tree type, int named, int incoming_p)
 {
   int regbase = (incoming_p
 		 ? SPARC_INCOMING_INT_ARG_FIRST
@@ -5036,11 +5389,8 @@ function_arg (cum, mode, type, named, incoming_p)
    mode] will be split between that reg and memory.  */
 
 int
-function_arg_partial_nregs (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
+function_arg_partial_nregs (const struct sparc_args *cum,
+			    enum machine_mode mode, tree type, int named)
 {
   int slotno, regno, padding;
 
@@ -5107,11 +5457,9 @@ function_arg_partial_nregs (cum, mode, type, named)
    For Pascal, also pass arrays by reference.  */
 
 int
-function_arg_pass_by_reference (cum, mode, type, named)
-     const CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED;
-     enum machine_mode mode;
-     tree type;
-     int named ATTRIBUTE_UNUSED;
+function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
+				enum machine_mode mode, tree type,
+				int named ATTRIBUTE_UNUSED)
 {
   if (TARGET_ARCH32)
     {
@@ -5135,11 +5483,8 @@ function_arg_pass_by_reference (cum, mode, type, named)
    TYPE is null for libcalls where that information may not be available.  */
 
 void
-function_arg_advance (cum, mode, type, named)
-     CUMULATIVE_ARGS *cum;
-     enum machine_mode mode;
-     tree type;
-     int named;
+function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
+		      tree type, int named)
 {
   int slotno, regno, padding;
 
@@ -5191,21 +5536,13 @@ function_arg_advance (cum, mode, type, named)
    argument slot.  */
 
 enum direction
-function_arg_padding (mode, type)
-     enum machine_mode mode;
-     tree type;
+function_arg_padding (enum machine_mode mode, tree type)
 {
   if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
     return upward;
 
-  /* This is the default definition.  */
-  return (! BYTES_BIG_ENDIAN
-	  ? upward
-	  : ((mode == BLKmode
-	      ? (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
-		 && int_size_in_bytes (type) < (PARM_BOUNDARY / BITS_PER_UNIT))
-	      : GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
-	     ? downward : upward));
+  /* Fall back to the default.  */
+  return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
 }
 
 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
@@ -5213,10 +5550,7 @@ function_arg_padding (mode, type)
    except that up to 32-bytes may be returned in registers.  */
 
 rtx
-function_value (type, mode, incoming_p)
-     tree type;
-     enum machine_mode mode;
-     int incoming_p;
+function_value (tree type, enum machine_mode mode, int incoming_p)
 {
   int regno;
   int regbase = (incoming_p
@@ -5267,7 +5601,7 @@ function_value (type, mode, incoming_p)
    the first unnamed parameter.  */
 
 rtx
-sparc_builtin_saveregs ()
+sparc_builtin_saveregs (void)
 {
   int first_reg = current_function_args_info.words;
   rtx address;
@@ -5294,9 +5628,7 @@ sparc_builtin_saveregs ()
 /* Implement `va_start' for varargs and stdarg.  */
 
 void
-sparc_va_start (valist, nextarg)
-     tree valist;
-     rtx nextarg;
+sparc_va_start (tree valist, rtx nextarg)
 {
   nextarg = expand_builtin_saveregs ();
   std_expand_builtin_va_start (valist, nextarg);
@@ -5305,8 +5637,7 @@ sparc_va_start (valist, nextarg)
 /* Implement `va_arg'.  */
 
 rtx
-sparc_va_arg (valist, type)
-     tree valist, type;
+sparc_va_arg (tree valist, tree type)
 {
   HOST_WIDE_INT size, rsize, align;
   tree addr, incr;
@@ -5430,11 +5761,8 @@ sparc_va_arg (valist, type)
    INSN, if set, is the insn.  */
 
 char *
-output_cbranch (op, dest, label, reversed, annul, noop, insn)
-     rtx op, dest;
-     int label;
-     int reversed, annul, noop;
-     rtx insn;
+output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
+		int noop, rtx insn)
 {
   static char string[50];
   enum rtx_code code = GET_CODE (op);
@@ -5678,9 +6006,7 @@ output_cbranch (op, dest, label, reversed, annul, noop, insn)
    values as arguments instead of the TFmode registers themselves,
    that's why we cannot call emit_float_lib_cmp.  */
 void
-sparc_emit_float_lib_cmp (x, y, comparison)
-     rtx x, y;
-     enum rtx_code comparison;
+sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
 {
   const char *qpfunc;
   rtx slot0, slot1, result, tem, tem2;
@@ -5817,8 +6143,7 @@ sparc_emit_float_lib_cmp (x, y, comparison)
    optabs would emit if we didn't have TFmode patterns.  */
 
 void
-sparc_emit_floatunsdi (operands)
-     rtx operands[2];
+sparc_emit_floatunsdi (rtx *operands)
 {
   rtx neglab, donelab, i0, i1, f0, in, out;
   enum machine_mode mode;
@@ -5861,11 +6186,8 @@ sparc_emit_floatunsdi (operands)
    NOOP is nonzero if we have to follow this branch by a noop.  */
 
 char *
-output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
-     rtx op, dest;
-     int reg, label;
-     int reversed, annul, noop;
-     rtx insn;
+output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
+		 int annul, int noop, rtx insn)
 {
   static char string[50];
   enum rtx_code code = GET_CODE (op);
@@ -6005,9 +6327,7 @@ output_v9branch (op, dest, reg, label, reversed, annul, noop, insn)
  */
 
 static int
-epilogue_renumber (where, test)
-     register rtx *where;
-     int test;
+epilogue_renumber (register rtx *where, int test)
 {
   register const char *fmt;
   register int i;
@@ -6091,7 +6411,7 @@ static const int *const reg_alloc_orders[] = {
   reg_nonleaf_alloc_order};
 
 void
-order_regs_for_local_alloc ()
+order_regs_for_local_alloc (void)
 {
   static int last_order_nonleaf = 1;
 
@@ -6108,9 +6428,7 @@ order_regs_for_local_alloc ()
    mem<-->reg splits to be run.  */
 
 int
-sparc_splitdi_legitimate (reg, mem)
-     rtx reg;
-     rtx mem;
+sparc_splitdi_legitimate (rtx reg, rtx mem)
 {
   /* Punt if we are here by mistake.  */
   if (! reload_completed)
@@ -6135,8 +6453,7 @@ sparc_splitdi_legitimate (reg, mem)
    run after reload.  */
 
 int
-sparc_absnegfloat_split_legitimate (x, y)
-     rtx x, y;
+sparc_absnegfloat_split_legitimate (rtx x, rtx y)
 {
   if (GET_CODE (x) != REG)
     return 0;
@@ -6153,8 +6470,7 @@ sparc_absnegfloat_split_legitimate (x, y)
    Note reg1 and reg2 *must* be hard registers.  */
 
 int
-registers_ok_for_ldd_peep (reg1, reg2)
-     rtx reg1, reg2;
+registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
 {
   /* We might have been passed a SUBREG.  */
   if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 
@@ -6202,8 +6518,7 @@ registers_ok_for_ldd_peep (reg1, reg2)
    NULL_RTX.  */
 
 int
-mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
-      rtx mem1, mem2, dependent_reg_rtx;
+mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
 {
   rtx addr1, addr2;
   unsigned int reg1;
@@ -6277,8 +6592,7 @@ mems_ok_for_ldd_peep (mem1, mem2, dependent_reg_rtx)
    ldd and std insns.  */
 
 int
-register_ok_for_ldd (reg)
-     rtx reg;
+register_ok_for_ldd (rtx reg)
 {
   /* We might have been passed a SUBREG.  */
   if (GET_CODE (reg) != REG) 
@@ -6295,10 +6609,7 @@ register_ok_for_ldd (reg)
    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
 
 void
-print_operand (file, x, code)
-     FILE *file;
-     rtx x;
-     int code;
+print_operand (FILE *file, rtx x, int code)
 {
   switch (code)
     {
@@ -6335,6 +6646,10 @@ print_operand (file, x, code)
       /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
       fprintf (file, "%s+%d", frame_base_name, frame_base_offset);
       return;
+    case '&':
+      /* Print some local dynamic TLS name.  */
+      assemble_name (file, get_some_local_dynamic_name ());
+      return;
     case 'Y':
       /* Adjust the operand to take into account a RESTORE operation.  */
       if (GET_CODE (x) == CONST_INT)
@@ -6583,10 +6898,7 @@ print_operand (file, x, code)
    special handling for aligned DI-mode objects.  */
 
 static bool
-sparc_assemble_integer (x, size, aligned_p)
-     rtx x;
-     unsigned int size;
-     int aligned_p;
+sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
 {
   /* ??? We only output .xword's for symbols and only then in environments
      where the assembler can handle them.  */
@@ -6641,8 +6953,7 @@ sparc_assemble_integer (x, size, aligned_p)
 #endif
 
 unsigned long
-sparc_type_code (type)
-     register tree type;
+sparc_type_code (register tree type)
 {
   register unsigned long qualifiers = 0;
   register unsigned shift;
@@ -6766,8 +7077,7 @@ sparc_type_code (type)
    Emit enough FLUSH insns to synchronize the data and instruction caches.  */
 
 void
-sparc_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
+sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
 {
   /* SPARC 32 bit trampoline:
 
@@ -6828,8 +7138,7 @@ sparc_initialize_trampoline (tramp, fnaddr, cxt)
    we can read the PC without clobbering a register.  */
 
 void
-sparc64_initialize_trampoline (tramp, fnaddr, cxt)
-     rtx tramp, fnaddr, cxt;
+sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
 {
 #ifdef TRANSFER_FROM_TRAMPOLINE
   emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
@@ -6960,8 +7269,8 @@ struct sparc_frame_info zero_frame_info;
    stack pointer.  */
 
 unsigned long
-sparc_flat_compute_frame_size (size)
-     int size;			/* # of var. bytes allocated.  */
+sparc_flat_compute_frame_size (int size)
+              			/* # of var. bytes allocated.  */
 {
   int regno;
   unsigned long total_size;	/* # bytes that the entire frame takes up.  */
@@ -7079,16 +7388,11 @@ sparc_flat_compute_frame_size (size)
    DOUBLEWORD_OP is either "std" for save, "ldd" for restore.  */
 
 void
-sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
-			 doubleword_op, base_offset)
-     FILE *file;
-     const char *base_reg;
-     unsigned int offset;
-     unsigned long gmask;
-     unsigned long fmask;
-     const char *word_op;
-     const char *doubleword_op;
-     unsigned long base_offset;
+sparc_flat_save_restore (FILE *file, const char *base_reg,
+			 unsigned int offset, long unsigned int gmask,
+			 long unsigned int fmask, const char *word_op,
+			 const char *doubleword_op,
+			 long unsigned int base_offset)
 {
   int regno;
 
@@ -7183,9 +7487,7 @@ sparc_flat_save_restore (file, base_reg, offset, gmask, fmask, word_op,
 /* Set up the stack and frame (if desired) for the function.  */
 
 static void
-sparc_flat_function_prologue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size;
+sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
 {
   const char *sp_str = reg_names[STACK_POINTER_REGNUM];
   unsigned long gmask = current_frame_info.gmask;
@@ -7371,9 +7673,7 @@ sparc_flat_function_prologue (file, size)
    and regs.  */
 
 static void
-sparc_flat_function_epilogue (file, size)
-     FILE *file;
-     HOST_WIDE_INT size;
+sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
 {
   rtx epilogue_delay = current_function_epilogue_delay_list;
   int noepilogue = FALSE;
@@ -7518,7 +7818,7 @@ sparc_flat_function_epilogue (file, size)
    or the only register saved is the return register.  */
 
 int
-sparc_flat_epilogue_delay_slots ()
+sparc_flat_epilogue_delay_slots (void)
 {
   if (!current_frame_info.initialized)
     (void) sparc_flat_compute_frame_size (get_frame_size ());
@@ -7534,9 +7834,7 @@ sparc_flat_epilogue_delay_slots ()
    pointer is OK.  */
 
 int
-sparc_flat_eligible_for_epilogue_delay (trial, slot)
-     rtx trial;
-     int slot ATTRIBUTE_UNUSED;
+sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
 {
   rtx pat = PATTERN (trial);
 
@@ -7554,11 +7852,7 @@ sparc_flat_eligible_for_epilogue_delay (trial, slot)
    a dependency LINK or INSN on DEP_INSN.  COST is the current cost.  */
 
 static int
-supersparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
+supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 {
   enum attr_type insn_type;
 
@@ -7619,11 +7913,7 @@ supersparc_adjust_cost (insn, link, dep_insn, cost)
 }
 
 static int
-hypersparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
+hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
 {
   enum attr_type insn_type, dep_type;
   rtx pat = PATTERN(insn);
@@ -7700,11 +7990,7 @@ hypersparc_adjust_cost (insn, link, dep_insn, cost)
 }
 
 static int
-sparc_adjust_cost(insn, link, dep, cost)
-     rtx insn;
-     rtx link;
-     rtx dep;
-     int cost;
+sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
 {
   switch (sparc_cpu)
     {
@@ -7722,15 +8008,14 @@ sparc_adjust_cost(insn, link, dep, cost)
 }
 
 static void
-sparc_sched_init (dump, sched_verbose, max_ready)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     int max_ready ATTRIBUTE_UNUSED;
+sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
+		  int sched_verbose ATTRIBUTE_UNUSED,
+		  int max_ready ATTRIBUTE_UNUSED)
 {
 }
   
 static int
-sparc_use_dfa_pipeline_interface ()
+sparc_use_dfa_pipeline_interface (void)
 {
   if ((1 << sparc_cpu) &
       ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
@@ -7742,7 +8027,7 @@ sparc_use_dfa_pipeline_interface ()
 }
 
 static int
-sparc_use_sched_lookahead ()
+sparc_use_sched_lookahead (void)
 {
   if (sparc_cpu == PROCESSOR_ULTRASPARC
       || sparc_cpu == PROCESSOR_ULTRASPARC3)
@@ -7755,7 +8040,7 @@ sparc_use_sched_lookahead ()
 }
 
 static int
-sparc_issue_rate ()
+sparc_issue_rate (void)
 {
   switch (sparc_cpu)
     {
@@ -7776,8 +8061,7 @@ sparc_issue_rate ()
 }
 
 static int
-set_extends (insn)
-     rtx insn;
+set_extends (rtx insn)
 {
   register rtx pat = PATTERN (insn);
 
@@ -7844,9 +8128,7 @@ static GTY(()) rtx sparc_addr_diff_list;
 static GTY(()) rtx sparc_addr_list;
 
 void
-sparc_defer_case_vector (lab, vec, diff)
-     rtx lab, vec;
-     int diff;
+sparc_defer_case_vector (rtx lab, rtx vec, int diff)
 {
   vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
   if (diff)
@@ -7857,8 +8139,7 @@ sparc_defer_case_vector (lab, vec, diff)
 }
 
 static void 
-sparc_output_addr_vec (vec)
-     rtx vec;
+sparc_output_addr_vec (rtx vec)
 {
   rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
   int idx, vlen = XVECLEN (body, 0);
@@ -7886,8 +8167,7 @@ sparc_output_addr_vec (vec)
 }
 
 static void 
-sparc_output_addr_diff_vec (vec)
-     rtx vec;
+sparc_output_addr_diff_vec (rtx vec)
 {
   rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
   rtx base = XEXP (XEXP (body, 0), 0);
@@ -7919,7 +8199,7 @@ sparc_output_addr_diff_vec (vec)
 }
 
 static void
-sparc_output_deferred_case_vectors ()
+sparc_output_deferred_case_vectors (void)
 {
   rtx t;
   int align;
@@ -7947,8 +8227,7 @@ sparc_output_deferred_case_vectors ()
    unknown.  Return 1 if the high bits are zero, -1 if the register is
    sign extended.  */
 int
-sparc_check_64 (x, insn)
-     rtx x, insn;
+sparc_check_64 (rtx x, rtx insn)
 {
   /* If a register is set only once it is safe to ignore insns this
      code does not know how to handle.  The loop will either recognize
@@ -8008,10 +8287,7 @@ sparc_check_64 (x, insn)
 /* Returns assembly code to perform a DImode shift using
    a 64-bit global or out register on SPARC-V8+.  */
 char *
-sparc_v8plus_shift (operands, insn, opcode)
-     rtx *operands;
-     rtx insn;
-     const char *opcode;
+sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
 {
   static char asm_code[60];
 
@@ -8020,6 +8296,10 @@ sparc_v8plus_shift (operands, insn, opcode)
   if (which_alternative != 2)
     operands[3] = operands[0];
 
+  /* We can only shift by constants <= 63. */
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+
   if (GET_CODE (operands[1]) == CONST_INT)
     {
       output_asm_insn ("mov\t%1, %3", operands);
@@ -8044,8 +8324,7 @@ sparc_v8plus_shift (operands, insn, opcode)
    for profiling a function entry.  */
 
 void
-sparc_profile_hook (labelno)
-     int labelno;
+sparc_profile_hook (int labelno)
 {
   char buf[32];
   rtx lab, fun;
@@ -8059,9 +8338,7 @@ sparc_profile_hook (labelno)
 
 #ifdef OBJECT_FORMAT_ELF
 static void
-sparc_elf_asm_named_section (name, flags)
-     const char *name;
-     unsigned int flags;
+sparc_elf_asm_named_section (const char *name, unsigned int flags)
 {
   if (flags & SECTION_MERGE)
     {
@@ -8103,9 +8380,7 @@ sparc_elf_asm_named_section (name, flags)
    void) and then nothing else happens.  Such a sibling call would look
    valid without the added check here.  */
 static bool
-sparc_function_ok_for_sibcall (decl, exp)
-     tree decl;
-     tree exp ATTRIBUTE_UNUSED;
+sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
 {
   return (decl
 	  && ! TARGET_FLAT
@@ -8117,10 +8392,7 @@ sparc_function_ok_for_sibcall (decl, exp)
    pretending PIC always on), but that's what the old code did.  */
 
 static void
-sparc_aout_select_section (t, reloc, align)
-     tree t;
-     int reloc;
-     unsigned HOST_WIDE_INT align;
+sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
 {
   default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
 }
@@ -8129,10 +8401,8 @@ sparc_aout_select_section (t, reloc, align)
    that offers.  */
 
 static void
-sparc_aout_select_rtx_section (mode, x, align)
-     enum machine_mode mode;
-     rtx x;
-     unsigned HOST_WIDE_INT align;
+sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
+			       unsigned HOST_WIDE_INT align)
 {
   if (align <= MAX_TEXT_ALIGN
       && ! (flag_pic && (symbolic_operand (x, mode)
@@ -8143,10 +8413,7 @@ sparc_aout_select_rtx_section (mode, x, align)
 }
 
 int
-sparc_extra_constraint_check (op, c, strict)
-     rtx op;
-     int c;
-     int strict;
+sparc_extra_constraint_check (rtx op, int c, int strict)
 {
   int reload_ok_mem;
 
@@ -8209,9 +8476,7 @@ sparc_extra_constraint_check (op, c, strict)
    ??? the latencies and then CSE will just use that.  */
 
 static bool
-sparc_rtx_costs (x, code, outer_code, total)
-     rtx x;
-     int code, outer_code, *total;
+sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
 {
   switch (code)
     {
@@ -8579,12 +8844,10 @@ sparc_rtx_costs (x, code, outer_code, total)
    Used for C++ multiple inheritance.  */
 
 static void
-sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk_fndecl ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
-     tree function;
+sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+		       HOST_WIDE_INT delta,
+		       HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+		       tree function)
 {
   rtx this, insn, funexp, delta_rtx, tmp;
 
@@ -8597,7 +8860,7 @@ sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
 
   /* Find the "this" pointer.  Normally in %o0, but in ARCH64 if the function
      returns a structure, the structure return pointer is there instead.  */
-  if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
   else
     this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
@@ -8646,4 +8909,68 @@ sparc_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
   no_new_pseudos = 0;
 }
 
+/* How to allocate a 'struct machine_function'.  */
+
+static struct machine_function *
+sparc_init_machine_status (void)
+{
+  return ggc_alloc_cleared (sizeof (struct machine_function));
+}
+
+/* Locate some local-dynamic symbol still in use by this function
+   so that we can print its name in local-dynamic base patterns.  */
+
+static const char *
+get_some_local_dynamic_name (void)
+{
+  rtx insn;
+
+  if (cfun->machine->some_ld_name)
+    return cfun->machine->some_ld_name;
+
+  for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
+    if (INSN_P (insn)
+	&& for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
+      return cfun->machine->some_ld_name;
+
+  abort ();
+}
+
+static int
+get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
+{
+  rtx x = *px;
+
+  if (x
+      && GET_CODE (x) == SYMBOL_REF
+      && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
+    {
+      cfun->machine->some_ld_name = XSTR (x, 0);
+      return 1;
+    }
+
+  return 0;
+}
+
+/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
+   We need to emit DTP-relative relocations.  */
+
+void
+sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
+{
+  switch (size)
+    {
+    case 4:
+      fputs ("\t.word\t%r_tls_dtpoff32(", file);
+      break;
+    case 8:
+      fputs ("\t.xword\t%r_tls_dtpoff64(", file);
+      break;
+    default:
+      abort ();
+    }
+  output_addr_const (file, x);
+  fputs (")", file);
+}
+
 #include "gt-sparc.h"
diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h
index 9235f66bf53..a997602daff 100644
--- a/gcc/config/sparc/sparc.h
+++ b/gcc/config/sparc/sparc.h
@@ -2099,27 +2099,18 @@ do {									\
    When PIC, we do not accept an address that would require a scratch reg
    to load into a register.  */
 
-#define CONSTANT_ADDRESS_P(X)   \
-  (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
-   || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH			\
-   || (GET_CODE (X) == CONST						\
-       && ! (flag_pic && pic_address_needs_scratch (X))))
+#define CONSTANT_ADDRESS_P(X) constant_address_p (X)
 
 /* Define this, so that when PIC, reload won't try to reload invalid
    addresses which require two reload registers.  */
 
-#define LEGITIMATE_PIC_OPERAND_P(X)  (! pic_address_needs_scratch (X))
+#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
 
 /* Nonzero if the constant value X is a legitimate general operand.
    Anything can be made to work except floating point constants.
    If TARGET_VIS, 0.0 can be made to work as well.  */
 
-#define LEGITIMATE_CONSTANT_P(X) 					\
-  (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode || 		\
-   (TARGET_VIS &&							\
-    (GET_MODE (X) == SFmode || GET_MODE (X) == DFmode ||		\
-     GET_MODE (X) == TFmode) &&						\
-    fp_zero_operand (X, GET_MODE (X))))
+#define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
    and check its validity for a certain class.
@@ -2226,110 +2217,19 @@ do {									\
 #define RTX_OK_FOR_OLO10_P(X)						\
   (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
 
+#ifdef REG_OK_STRICT
 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
-{ if (RTX_OK_FOR_BASE_P (X))				\
+{							\
+  if (legitimate_address_p (MODE, X, 1))		\
     goto ADDR;						\
-  else if (GET_CODE (X) == PLUS)			\
-    {							\
-      register rtx op0 = XEXP (X, 0);			\
-      register rtx op1 = XEXP (X, 1);			\
-      if (flag_pic && op0 == pic_offset_table_rtx)	\
-	{						\
-	  if (RTX_OK_FOR_BASE_P (op1))			\
-	    goto ADDR;					\
-	  else if (flag_pic == 1			\
-		   && GET_CODE (op1) != REG		\
-		   && GET_CODE (op1) != LO_SUM		\
-		   && GET_CODE (op1) != MEM		\
-		   && (! SYMBOLIC_CONST (op1)		\
-		       || MODE == Pmode)		\
-		   && (GET_CODE (op1) != CONST_INT	\
-		       || SMALL_INT (op1)))		\
-	    goto ADDR;					\
-	}						\
-      else if (RTX_OK_FOR_BASE_P (op0))			\
-	{						\
-	  if ((RTX_OK_FOR_INDEX_P (op1)			\
- 	      /* We prohibit REG + REG for TFmode when	\
-		 there are no instructions which accept	\
-		 REG+REG instructions.  We do this	\
-		 because REG+REG is not an offsetable	\
-		 address.  If we get the situation	\
-		 in reload where source and destination	\
-		 of a movtf pattern are both MEMs with	\
-		 REG+REG address, then only one of them	\
-		 gets converted to an offsetable	\
-		 address.  */				\
- 	       && (MODE != TFmode			\
-		   || (TARGET_FPU && TARGET_ARCH64	\
-		       && TARGET_V9			\
-		       && TARGET_HARD_QUAD))		\
-	      /* We prohibit REG + REG on ARCH32 if	\
-		 not optimizing for DFmode/DImode	\
-		 because then mem_min_alignment is	\
-		 likely to be zero after reload and the \
-		 forced split would lack a matching	\
-		 splitter pattern.  */			\
-	       && (TARGET_ARCH64 || optimize		\
-		   || (MODE != DFmode			\
-		       && MODE != DImode)))		\
-	      || RTX_OK_FOR_OFFSET_P (op1))		\
-	    goto ADDR;					\
-	}						\
-      else if (RTX_OK_FOR_BASE_P (op1))			\
-	{						\
-	  if ((RTX_OK_FOR_INDEX_P (op0)			\
- 	      /* See the previous comment.  */		\
- 	       && (MODE != TFmode			\
-		  || (TARGET_FPU && TARGET_ARCH64	\
-		      && TARGET_V9			\
-		      && TARGET_HARD_QUAD))		\
-	       && (TARGET_ARCH64 || optimize		\
-		   || (MODE != DFmode			\
-		       && MODE != DImode)))		\
-	      || RTX_OK_FOR_OFFSET_P (op0))		\
-	    goto ADDR;					\
-	}						\
-      else if (USE_AS_OFFSETABLE_LO10			\
-	       && GET_CODE (op0) == LO_SUM		\
-	       && TARGET_ARCH64				\
-	       && ! TARGET_CM_MEDMID			\
-	       && RTX_OK_FOR_OLO10_P (op1))		\
-	{						\
-	  register rtx op00 = XEXP (op0, 0);		\
-	  register rtx op01 = XEXP (op0, 1);		\
-	  if (RTX_OK_FOR_BASE_P (op00)			\
-	      && CONSTANT_P (op01))			\
-	    goto ADDR;					\
-	}						\
-      else if (USE_AS_OFFSETABLE_LO10			\
-	       && GET_CODE (op1) == LO_SUM		\
-	       && TARGET_ARCH64				\
-	       && ! TARGET_CM_MEDMID			\
-	       && RTX_OK_FOR_OLO10_P (op0))		\
-	{						\
-	  register rtx op10 = XEXP (op1, 0);		\
-	  register rtx op11 = XEXP (op1, 1);		\
-	  if (RTX_OK_FOR_BASE_P (op10)			\
-	      && CONSTANT_P (op11))			\
-	    goto ADDR;					\
-	}						\
-    }							\
-  else if (GET_CODE (X) == LO_SUM)			\
-    {							\
-      register rtx op0 = XEXP (X, 0);			\
-      register rtx op1 = XEXP (X, 1);			\
-      if (RTX_OK_FOR_BASE_P (op0)			\
-	  && CONSTANT_P (op1)				\
-	  /* We can't allow TFmode, because an offset	\
-	     greater than or equal to the alignment (8)	\
-	     may cause the LO_SUM to overflow if !v9.  */\
-	  && (MODE != TFmode || TARGET_V9))		\
-	goto ADDR;					\
-    }							\
-  else if (GET_CODE (X) == CONST_INT && SMALL_INT (X))	\
+}
+#else
+#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)		\
+{							\
+  if (legitimate_address_p (MODE, X, 0))		\
     goto ADDR;						\
 }
+#endif
 
 /* Go to LABEL if ADDR (a legitimate address expression)
    has an effect that depends on the machine mode it is used for.
@@ -2374,33 +2274,11 @@ do {									\
 
 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG.  */
 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN)	\
-{ rtx sparc_x = (X);						\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1),			\
-			force_operand (XEXP (X, 0), NULL_RTX));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-			force_operand (XEXP (X, 1), NULL_RTX));	\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS)	\
-    (X) = gen_rtx_PLUS (Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
-			XEXP (X, 1));				\
-  if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS)	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-			force_operand (XEXP (X, 1), NULL_RTX));	\
-  if (sparc_x != (X) && memory_address_p (MODE, X))		\
-    goto WIN;							\
-  if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0);	\
-  else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 0),			\
-			copy_to_mode_reg (Pmode, XEXP (X, 1)));	\
-  else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0)))	\
-    (X) = gen_rtx_PLUS (Pmode, XEXP (X, 1),			\
-			copy_to_mode_reg (Pmode, XEXP (X, 0)));	\
-  else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST	\
-	   || GET_CODE (X) == LABEL_REF)			\
-    (X) = copy_to_suggested_reg (X, NULL_RTX, Pmode); 		\
-  if (memory_address_p (MODE, X))				\
-    goto WIN; }
+{						\
+  (X) = legitimize_address (X, OLDX, MODE);	\
+  if (memory_address_p (MODE, X))		\
+    goto WIN;					\
+}
 
 /* Try a machine-dependent way of reloading an illegitimate address
    operand.  If we find one, push the reload and jump to WIN.  This
@@ -2845,8 +2723,16 @@ do {									\
 #define ASM_OUTPUT_IDENT(FILE, NAME) \
   fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
 
+/* Emit a dtp-relative reference to a TLS variable.  */
+
+#ifdef HAVE_AS_TLS
+#define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \
+  sparc_output_dwarf_dtprel (FILE, SIZE, X)
+#endif
+
 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
-  ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
+  ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^'		\
+   || (CHAR) == '(' || (CHAR) == '_' || (CHAR) == '&')
 
 /* Print operand X (an rtx) in assembler syntax to file FILE.
    CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
@@ -2933,6 +2819,14 @@ do {									\
     }								\
 }
 
+#ifdef HAVE_AS_TLS
+#define TARGET_TLS 1
+#else
+#define TARGET_TLS 0
+#endif
+#define TARGET_SUN_TLS TARGET_TLS
+#define TARGET_GNU_TLS 0
+
 /* Define the codes that are matched by predicates in sparc.c.  */
 
 #define PREDICATE_CODES							\
@@ -2980,7 +2874,11 @@ do {									\
 {"clobbered_register", {REG}},						\
 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
 {"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
-{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
+{"const64_high_operand", {CONST_INT, CONST_DOUBLE}},			\
+{"tgd_symbolic_operand", {SYMBOL_REF}},					\
+{"tld_symbolic_operand", {SYMBOL_REF}},					\
+{"tie_symbolic_operand", {SYMBOL_REF}},					\
+{"tle_symbolic_operand", {SYMBOL_REF}},
 
 /* The number of Pmode words for the setjmp buffer.  */
 #define JMP_BUF_SIZE 12
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 07ce71874c6..a987041af81 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -38,6 +38,13 @@
    (UNSPEC_EMB_TEXTHI		14)
    (UNSPEC_EMB_TEXTULO		15)
    (UNSPEC_EMB_SETHM		18)
+
+   (UNSPEC_TLSGD		30)
+   (UNSPEC_TLSLDM		31)
+   (UNSPEC_TLSLDO		32)
+   (UNSPEC_TLSIE		33)
+   (UNSPEC_TLSLE		34)
+   (UNSPEC_TLSLD_BASE		35)
   ])
 
 (define_constants
@@ -195,6 +202,9 @@
 
 ;; Attributes for instruction and branch scheduling
 
+(define_attr "tls_call_delay" "false,true"
+  (symbol_ref "tls_call_delay (insn)"))
+
 (define_attr "in_call_delay" "false,true"
   (cond [(eq_attr "type" "uncond_branch,branch,call,sibcall,call_no_delay_slot,multi")
 	 	(const_string "false")
@@ -202,7 +212,8 @@
 	 	(if_then_else (eq_attr "length" "1")
 			      (const_string "true")
 			      (const_string "false"))]
-	(if_then_else (eq_attr "length" "1")
+	(if_then_else (and (eq_attr "length" "1")
+			   (eq_attr "tls_call_delay" "true"))
 		      (const_string "true")
 		      (const_string "false"))))
 
@@ -1681,6 +1692,10 @@
 	}
     }
 
+  /* Fixup TLS cases.  */
+  if (tls_symbolic_operand (operands [1]))
+    operands[1] = legitimize_tls_address (operands[1]);
+
   /* Fixup PIC cases.  */
   if (flag_pic)
     {
@@ -1740,6 +1755,10 @@
 	}
     }
 
+  /* Fixup TLS cases.  */
+  if (tls_symbolic_operand (operands [1]))
+    operands[1] = legitimize_tls_address (operands[1]);
+
   /* Fixup PIC cases.  */
   if (flag_pic)
     {
@@ -1822,6 +1841,10 @@
 	}
     }
 
+  /* Fixup TLS cases.  */
+  if (tls_symbolic_operand (operands [1]))
+    operands[1] = legitimize_tls_address (operands[1]);
+
   /* Fixup PIC cases.  */
   if (flag_pic)
     {
@@ -1998,6 +2021,10 @@
 	}
     }
 
+  /* Fixup TLS cases.  */
+  if (tls_symbolic_operand (operands [1]))
+    operands[1] = legitimize_tls_address (operands[1]);
+
   if (flag_pic)
     {
       if (CONSTANT_P (operands[1])
@@ -6881,6 +6908,8 @@
 {
   if (operands[2] == const1_rtx)
     return "add\t%1, %1, %0";
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
   return "sll\t%1, %2, %0";
 }
   [(set (attr "type")
@@ -6910,6 +6939,8 @@
 {
   if (operands[2] == const1_rtx)
     return "add\t%1, %1, %0";
+  if (GET_CODE (operands[2]) == CONST_INT)
+    operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
   return "sllx\t%1, %2, %0";
 }
   [(set (attr "type")
@@ -6969,7 +7000,11 @@
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
-  "sra\t%1, %2, %0"
+  {
+     if (GET_CODE (operands[2]) == CONST_INT)
+       operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+     return "sra\t%1, %2, %0";
+  }
   [(set_attr "type" "shift")])
 
 (define_insn "*ashrsi3_extend"
@@ -7016,12 +7051,17 @@
     }
 })
 
-(define_insn ""
+(define_insn "*ashrdi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
-  "srax\t%1, %2, %0"
+  
+  {
+    if (GET_CODE (operands[2]) == CONST_INT)
+      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+    return "srax\t%1, %2, %0";
+  }
   [(set_attr "type" "shift")])
 
 ;; XXX
@@ -7040,7 +7080,11 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   ""
-  "srl\t%1, %2, %0"
+  {
+    if (GET_CODE (operands[2]) == CONST_INT)
+      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
+    return "srl\t%1, %2, %0";
+  }
   [(set_attr "type" "shift")])
 
 ;; This handles the case where
@@ -7097,12 +7141,16 @@
     }
 })
 
-(define_insn ""
+(define_insn "*lshrdi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_ARCH64"
-  "srlx\t%1, %2, %0"
+  {
+    if (GET_CODE (operands[2]) == CONST_INT)
+      operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
+    return "srlx\t%1, %2, %0";
+  }
   [(set_attr "type" "shift")])
 
 ;; XXX
@@ -8366,3 +8414,566 @@
   "TARGET_V9"
   "t%C0\t%%xcc, %1"
   [(set_attr "type" "trap")])
+
+;; TLS support
+(define_insn "tgd_hi22"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (high:SI (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")]
+			    UNSPEC_TLSGD)))]
+  "TARGET_TLS"
+  "sethi\\t%%tgd_hi22(%a1), %0")
+
+(define_insn "tgd_lo10"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (unspec:SI [(match_operand 2 "tgd_symbolic_operand" "")]
+			      UNSPEC_TLSGD)))]
+  "TARGET_TLS"
+  "add\\t%1, %%tgd_lo10(%a2), %0")
+
+(define_insn "tgd_add32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r")
+		 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+			     (match_operand 3 "tgd_symbolic_operand" "")]
+			    UNSPEC_TLSGD)))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "add\\t%1, %2, %0, %%tgd_add(%a3)")
+
+(define_insn "tgd_add64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+			     (match_operand 3 "tgd_symbolic_operand" "")]
+			    UNSPEC_TLSGD)))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "add\\t%1, %2, %0, %%tgd_add(%a3)")
+
+(define_insn "tgd_call32"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")
+				  (match_operand 2 "tgd_symbolic_operand" "")]
+				 UNSPEC_TLSGD))
+	      (match_operand 3 "" "")))
+   (clobber (reg:SI 15))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "call\t%a1, %%tgd_call(%a2)%#"
+  [(set_attr "type" "call")])
+
+(define_insn "tgd_call64"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")
+				  (match_operand 2 "tgd_symbolic_operand" "")]
+				 UNSPEC_TLSGD))
+	      (match_operand 3 "" "")))
+   (clobber (reg:DI 15))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "call\t%a1, %%tgd_call(%a2)%#"
+  [(set_attr "type" "call")])
+
+(define_insn "tldm_hi22"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (high:SI (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
+  "TARGET_TLS"
+  "sethi\\t%%tldm_hi22(%&), %0")
+
+(define_insn "tldm_lo10"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		    (unspec:SI [(const_int 0)] UNSPEC_TLSLDM)))]
+  "TARGET_TLS"
+  "add\\t%1, %%tldm_lo10(%&), %0")
+
+(define_insn "tldm_add32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r")
+		 (unspec:SI [(match_operand:SI 2 "register_operand" "r")]
+			    UNSPEC_TLSLDM)))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "add\\t%1, %2, %0, %%tldm_add(%&)")
+
+(define_insn "tldm_add64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:SI 2 "register_operand" "r")]
+			    UNSPEC_TLSLDM)))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "add\\t%1, %2, %0, %%tldm_add(%&)")
+
+(define_insn "tldm_call32"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:SI (unspec:SI [(match_operand:SI 1 "symbolic_operand" "s")]
+				 UNSPEC_TLSLDM))
+	      (match_operand 2 "" "")))
+   (clobber (reg:SI 15))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "call\t%a1, %%tldm_call(%&)%#"
+  [(set_attr "type" "call")])
+
+(define_insn "tldm_call64"
+  [(set (match_operand 0 "register_operand" "=r")
+	(call (mem:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "s")]
+				 UNSPEC_TLSLDM))
+	      (match_operand 2 "" "")))
+   (clobber (reg:DI 15))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "call\t%a1, %%tldm_call(%&)%#"
+  [(set_attr "type" "call")])
+
+(define_insn "tldo_hix22"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (high:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
+			    UNSPEC_TLSLDO)))]
+  "TARGET_TLS"
+  "sethi\\t%%tldo_hix22(%a1), %0")
+
+(define_insn "tldo_lox10"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (unspec:SI [(match_operand 2 "tld_symbolic_operand" "")]
+			      UNSPEC_TLSLDO)))]
+  "TARGET_TLS"
+  "xor\\t%1, %%tldo_lox10(%a2), %0")
+
+(define_insn "tldo_add32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r")
+		 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+			     (match_operand 3 "tld_symbolic_operand" "")]
+			    UNSPEC_TLSLDO)))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "add\\t%1, %2, %0, %%tldo_add(%a3)")
+
+(define_insn "tldo_add64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+			     (match_operand 3 "tld_symbolic_operand" "")]
+			    UNSPEC_TLSLDO)))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "add\\t%1, %2, %0, %%tldo_add(%a3)")
+
+(define_insn "tie_hi22"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (high:SI (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")]
+			    UNSPEC_TLSIE)))]
+  "TARGET_TLS"
+  "sethi\\t%%tie_hi22(%a1), %0")
+
+(define_insn "tie_lo10"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (unspec:SI [(match_operand 2 "tie_symbolic_operand" "")]
+			      UNSPEC_TLSIE)))]
+  "TARGET_TLS"
+  "add\\t%1, %%tie_lo10(%a2), %0")
+
+(define_insn "tie_ld32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(unspec:SI [(match_operand:SI 1 "register_operand" "r")
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand 3 "tie_symbolic_operand" "")]
+		   UNSPEC_TLSIE))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ld\\t[%1 + %2], %0, %%tie_ld(%a3)"
+  [(set_attr "type" "load")])
+
+(define_insn "tie_ld64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(unspec:DI [(match_operand:DI 1 "register_operand" "r")
+		    (match_operand:SI 2 "register_operand" "r")
+		    (match_operand 3 "tie_symbolic_operand" "")]
+		   UNSPEC_TLSIE))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldx\\t[%1 + %2], %0, %%tie_ldx(%a3)"
+  [(set_attr "type" "load")])
+
+(define_insn "tie_add32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(plus:SI (match_operand:SI 1 "register_operand" "r")
+		 (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+			     (match_operand 3 "tld_symbolic_operand" "")]
+			    UNSPEC_TLSIE)))]
+  "TARGET_SUN_TLS && TARGET_ARCH32"
+  "add\\t%1, %2, %0, %%tie_add(%a3)")
+
+(define_insn "tie_add64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(plus:DI (match_operand:DI 1 "register_operand" "r")
+		 (unspec:DI [(match_operand:DI 2 "register_operand" "r")
+			     (match_operand 3 "tld_symbolic_operand" "")]
+			    UNSPEC_TLSIE)))]
+  "TARGET_SUN_TLS && TARGET_ARCH64"
+  "add\\t%1, %2, %0, %%tie_add(%a3)")
+
+(define_insn "tle_hix22_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (high:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
+			    UNSPEC_TLSLE)))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "sethi\\t%%tle_hix22(%a1), %0")
+
+(define_insn "tle_lox10_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (unspec:SI [(match_operand 2 "tle_symbolic_operand" "")]
+			      UNSPEC_TLSLE)))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "xor\\t%1, %%tle_lox10(%a2), %0")
+
+(define_insn "tle_hix22_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (high:DI (unspec:DI [(match_operand 1 "tle_symbolic_operand" "")]
+			    UNSPEC_TLSLE)))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "sethi\\t%%tle_hix22(%a1), %0")
+
+(define_insn "tle_lox10_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(lo_sum:DI (match_operand:DI 1 "register_operand" "r")
+		   (unspec:DI [(match_operand 2 "tle_symbolic_operand" "")]
+			      UNSPEC_TLSLE)))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "xor\\t%1, %%tle_lox10(%a2), %0")
+
+;; Now patterns combinding tldo_add{32,64} with some integer loads or stores
+(define_insn "*tldo_ldub_sp32"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub1_sp32"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(zero_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub2_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsb1_sp32"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsb2_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub_sp64"
+  [(set (match_operand:QI 0 "register_operand" "=r")
+	(mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub1_sp64"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(zero_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub2_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldub3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldub\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsb1_sp64"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(sign_extend:HI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsb2_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsb3_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsb\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduh_sp32"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduh1_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsh1_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:SI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduh_sp64"
+  [(set (match_operand:HI 0 "register_operand" "=r")
+	(mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduh1_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(zero_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduh2_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "lduh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsh1_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(sign_extend:SI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldsh2_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsh\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_lduw_sp32"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "ld\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")])
+
+(define_insn "*tldo_lduw_sp64"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")])
+
+(define_insn "*tldo_lduw1_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(zero_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "lduw\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")])
+
+(define_insn "*tldo_ldsw1_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(sign_extend:DI (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+						     (match_operand 3 "tld_symbolic_operand" "")]
+						    UNSPEC_TLSLDO)
+					 (match_operand:DI 1 "register_operand" "r")))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldsw\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "sload")
+   (set_attr "us3load_type" "3cycle")])
+
+(define_insn "*tldo_ldx_sp64"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r"))))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "ldx\t[%1 + %2], %0, %%tldo_add(%3)"
+  [(set_attr "type" "load")])
+
+(define_insn "*tldo_stb_sp32"
+  [(set (mem:QI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r")))
+	(match_operand:QI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "stb\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_stb_sp64"
+  [(set (mem:QI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r")))
+	(match_operand:QI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "stb\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_sth_sp32"
+  [(set (mem:HI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r")))
+	(match_operand:HI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "sth\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_sth_sp64"
+  [(set (mem:HI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r")))
+	(match_operand:HI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "sth\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_stw_sp32"
+  [(set (mem:SI (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:SI 1 "register_operand" "r")))
+	(match_operand:SI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH32"
+  "st\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_stw_sp64"
+  [(set (mem:SI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r")))
+	(match_operand:SI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "stw\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
+
+(define_insn "*tldo_stx_sp64"
+  [(set (mem:DI (plus:DI (unspec:DI [(match_operand:SI 2 "register_operand" "r")
+				     (match_operand 3 "tld_symbolic_operand" "")]
+				    UNSPEC_TLSLDO)
+			 (match_operand:DI 1 "register_operand" "r")))
+	(match_operand:DI 0 "register_operand" "=r"))]
+  "TARGET_TLS && TARGET_ARCH64"
+  "stx\t%0, [%1 + %2], %%tldo_add(%3)"
+  [(set_attr "type" "store")])
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index 8ce526f90d2..d493b7ce797 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -1562,7 +1562,7 @@ xstormy16_asm_output_mi_thunk (file, thunk_fndecl, delta,
   int regnum = FIRST_ARGUMENT_REGISTER;
   
   /* There might be a hidden first argument for a returned structure.  */
-  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+  if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
     regnum += 1;
   
   fprintf (file, "\tadd %s,#0x%x\n", reg_names[regnum], (int) delta & 0xFFFF);
diff --git a/gcc/config/stormy16/stormy16.h b/gcc/config/stormy16/stormy16.h
index c6d1596a4d9..3d1ab50756f 100644
--- a/gcc/config/stormy16/stormy16.h
+++ b/gcc/config/stormy16/stormy16.h
@@ -540,11 +540,7 @@ enum reg_class
    The obvious choice would be `float'--but that won't work with traditional C
    compilers that expect all arguments declared as `float' to arrive as
    `double'.  To avoid this conversion, the library routines ask for the value
-   as some other type and then treat it as a `float'.
-
-   On some systems, no other type will work for this.  For these systems, you
-   must use `LIBGCC_NEEDS_DOUBLE' instead, to force conversion of the values
-   `double' before they are passed.  */
+   as some other type and then treat it as a `float'.  */
 /* #define FLOAT_ARG_TYPE */
 
 /* Define this macro to override the way library routines redesignate a `float'
diff --git a/gcc/config/v850/t-v850 b/gcc/config/v850/t-v850
index 75c3b4695bd..4890ee3a9ff 100644
--- a/gcc/config/v850/t-v850
+++ b/gcc/config/v850/t-v850
@@ -81,12 +81,17 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
 	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
 
 # Create target-specific versions of the libraries
-MULTILIB_OPTIONS  = mv850/mv850e
-MULTILIB_DIRNAMES = v850 v850e
+MULTILIB_OPTIONS  = mv850e
+MULTILIB_DIRNAMES = v850e
 INSTALL_LIBGCC    = install-multilib
+MULTILIB_MATCHES  = mv850e=mv850e1
 
 TCFLAGS = -mno-app-regs -msmall-sld -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
 
 v850-c.o: $(srcdir)/config/v850/v850-c.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
   $(TM_H) $(CPPLIB_H) $(TREE_H) c-pragma.h toplev.h $(GGC_H) $(TM_P_H)
 	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/v850/v850-c.c 
+
+# Local Variables:
+# mode: Makefile
+# End:
diff --git a/gcc/config/v850/t-v850e b/gcc/config/v850/t-v850e
new file mode 100644
index 00000000000..97724e58109
--- /dev/null
+++ b/gcc/config/v850/t-v850e
@@ -0,0 +1,96 @@
+LIB1ASMSRC = v850/lib1funcs.asm
+LIB1ASMFUNCS	= _mulsi3 \
+		  _divsi3 \
+		  _udivsi3 \
+		  _modsi3 \
+		  _umodsi3 \
+		  _save_2 \
+		  _save_20 \
+		  _save_21 \
+		  _save_22 \
+		  _save_23 \
+		  _save_24 \
+		  _save_25 \
+		  _save_26 \
+		  _save_27 \
+		  _save_28 \
+		  _save_29 \
+		  _save_2c \
+		  _save_20c \
+		  _save_21c \
+		  _save_22c \
+		  _save_23c \
+		  _save_24c \
+		  _save_25c \
+		  _save_26c \
+		  _save_27c \
+		  _save_28c \
+		  _save_29c \
+		  _save_31c \
+		  _save_varargs \
+		  _save_interrupt \
+		  _save_all_interrupt \
+                  _callt_save_20 \
+		  _callt_save_21 \
+		  _callt_save_22 \
+		  _callt_save_23 \
+		  _callt_save_24 \
+		  _callt_save_25 \
+		  _callt_save_26 \
+		  _callt_save_27 \
+		  _callt_save_28 \
+		  _callt_save_29 \
+		  _callt_save_20c \
+		  _callt_save_21c \
+		  _callt_save_22c \
+		  _callt_save_23c \
+		  _callt_save_24c \
+		  _callt_save_25c \
+		  _callt_save_26c \
+		  _callt_save_27c \
+		  _callt_save_28c \
+		  _callt_save_29c \
+		  _callt_save_31c \
+		  _callt_save_varargs \
+		  _callt_save_interrupt \
+		  _callt_save_all_interrupt \
+		  _callt_save_r2_r29 \
+		  _callt_save_r2_r31 \
+		  _callt_save_r6_r9 \
+		  _negdi2 \
+		  _cmpdi2 \
+		  _ucmpdi2 \
+		  _muldi3
+
+# We want fine grained libraries, so use the new code to build the
+# floating point emulation libraries.
+FPBIT = fp-bit.c
+DPBIT = dp-bit.c
+
+dp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' > dp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>dp-bit.c
+	echo '#endif' 		>> dp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> dp-bit.c
+
+fp-bit.c: $(srcdir)/config/fp-bit.c
+	echo '#define FLOAT' > fp-bit.c
+	echo '#ifdef __LITTLE_ENDIAN__' >> fp-bit.c
+	echo '#define FLOAT_BIT_ORDER_MISMATCH' >>fp-bit.c
+	echo '#endif' 		>> fp-bit.c
+	cat $(srcdir)/config/fp-bit.c >> fp-bit.c
+
+# Create target-specific versions of the libraries
+MULTILIB_OPTIONS  = mv850
+MULTILIB_DIRNAMES = v850
+INSTALL_LIBGCC    = install-multilib
+
+TCFLAGS = -mno-app-regs -msmall-sld -Wa,-mwarn-signed-overflow -Wa,-mwarn-unsigned-overflow
+
+v850-c.o: $(srcdir)/config/v850/v850-c.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
+  $(TM_H) $(CPPLIB_H) $(TREE_H) c-pragma.h toplev.h $(GGC_H) $(TM_P_H)
+	$(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/v850/v850-c.c 
+
+# Local Variables:
+# mode: Makefile
+# End:
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 4db79a99d3b..3c40da1815c 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -2257,8 +2257,8 @@ v850_handle_data_area_attribute (node, name, args, flags, no_add_attrs)
     case VAR_DECL:
       if (current_function_decl != NULL_TREE)
 	{
-	  error_with_decl (decl, "\
-a data area attribute cannot be specified for local variables");
+          error ("%Jdata area attributes cannot be specified for "
+                 "local variables", decl, decl);
 	  *no_add_attrs = true;
 	}
 
@@ -2268,8 +2268,8 @@ a data area attribute cannot be specified for local variables");
       area = v850_get_data_area (decl);
       if (area != DATA_AREA_NORMAL && data_area != area)
 	{
-	  error_with_decl (decl, "\
-data area of '%s' conflicts with previous declaration");
+	  error ("%Jdata area of '%D' conflicts with previous declaration",
+                 decl, decl);
 	  *no_add_attrs = true;
 	}
       break;
diff --git a/gcc/config/v850/v850.h b/gcc/config/v850/v850.h
index 52e631334e5..7ebf12d6693 100644
--- a/gcc/config/v850/v850.h
+++ b/gcc/config/v850/v850.h
@@ -32,6 +32,7 @@
 
 #define TARGET_CPU_generic 	1
 #define TARGET_CPU_v850e   	2
+#define TARGET_CPU_v850e1  	3
 
 #ifndef TARGET_CPU_DEFAULT
 #define TARGET_CPU_DEFAULT	TARGET_CPU_generic
@@ -56,6 +57,17 @@
 #define TARGET_VERSION 		fprintf (stderr, " (NEC V850E)");
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_v850e1
+#undef  MASK_DEFAULT
+#define MASK_DEFAULT            MASK_V850E	/* No practical difference.  */
+#undef  SUBTARGET_ASM_SPEC
+#define SUBTARGET_ASM_SPEC 	"%{!mv*:-mv850e1}"
+#undef  SUBTARGET_CPP_SPEC
+#define SUBTARGET_CPP_SPEC 	"%{!mv*:-D__v850e1__} %{mv850e1:-D__v850e1__}"
+#undef  TARGET_VERSION
+#define TARGET_VERSION 		fprintf (stderr, " (NEC V850E1)");
+#endif
+
 #define ASM_SPEC "%{mv*:-mv%*}"
 #define CPP_SPEC		"%{mv850e:-D__v850e__} %{mv850:-D__v850__} %(subtarget_cpp_spec)"
 
@@ -176,6 +188,8 @@ extern int target_flags;
    { "v850",		 	 MASK_V850,				\
                                 N_("Compile for the v850 processor") },	\
    { "v850",		 	 -(MASK_V850 ^ MASK_CPU), "" },		\
+   { "v850e1",			 MASK_V850E, N_("Compile for v850e1 processor") }, \
+   { "v850e1",		        -(MASK_V850E ^ MASK_CPU), "" }, /* Make sure that the other bits are cleared.  */ \
    { "v850e",			 MASK_V850E, N_("Compile for v850e processor") }, \
    { "v850e",		        -(MASK_V850E ^ MASK_CPU), "" }, /* Make sure that the other bits are cleared.  */ \
    { "small-sld",		 MASK_SMALL_SLD, N_("Enable the use of the short load instructions") },	\
diff --git a/gcc/config/vax/vax-protos.h b/gcc/config/vax/vax-protos.h
index 199db19af55..978083b48c5 100644
--- a/gcc/config/vax/vax-protos.h
+++ b/gcc/config/vax/vax-protos.h
@@ -18,16 +18,16 @@ along with GCC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-extern void override_options PARAMS ((void));
+extern void override_options (void);
 
 #ifdef RTX_CODE
-extern const char *rev_cond_name PARAMS ((rtx));
-extern void split_quadword_operands PARAMS ((rtx *, rtx *, int));
-extern void print_operand_address PARAMS ((FILE *, rtx));
-extern int vax_float_literal PARAMS ((rtx));
+extern const char *rev_cond_name (rtx);
+extern void split_quadword_operands (rtx *, rtx *, int);
+extern void print_operand_address (FILE *, rtx);
+extern int vax_float_literal (rtx);
 #endif /* RTX_CODE */
 
 #ifdef REAL_VALUE_TYPE
-extern int check_float_value PARAMS ((enum machine_mode, REAL_VALUE_TYPE *, int));
+extern int check_float_value (enum machine_mode, REAL_VALUE_TYPE *, int);
 #endif /* REAL_VALUE_TYPE */
 
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
index 1b94beef01d..ad40e982fec 100644
--- a/gcc/config/vax/vax.c
+++ b/gcc/config/vax/vax.c
@@ -41,14 +41,14 @@ Boston, MA 02111-1307, USA.  */
 #include "target.h"
 #include "target-def.h"
 
-static void vax_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
-static void vax_file_start PARAMS ((void));
-static void vax_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
-					 HOST_WIDE_INT, tree));
-static int vax_address_cost_1 PARAMS ((rtx));
-static int vax_address_cost PARAMS ((rtx));
-static int vax_rtx_costs_1 PARAMS ((rtx, enum rtx_code, enum rtx_code));
-static bool vax_rtx_costs PARAMS ((rtx, int, int, int *));
+static void vax_output_function_prologue (FILE *, HOST_WIDE_INT);
+static void vax_file_start (void);
+static void vax_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+				 HOST_WIDE_INT, tree);
+static int vax_address_cost_1 (rtx);
+static int vax_address_cost (rtx);
+static int vax_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code);
+static bool vax_rtx_costs (rtx, int, int, int *);
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
@@ -77,7 +77,7 @@ struct gcc_target targetm = TARGET_INITIALIZER;
 /* Set global variables as needed for the options enabled.  */
 
 void
-override_options ()
+override_options (void)
 {
   /* We're VAX floating point, not IEEE floating point.  */
   memset (real_format_for_mode, 0, sizeof real_format_for_mode);
@@ -96,9 +96,7 @@ override_options ()
    which registers should not be saved even if used.  */
 
 static void
-vax_output_function_prologue (file, size)
-     FILE * file;
-     HOST_WIDE_INT size;
+vax_output_function_prologue (FILE * file, HOST_WIDE_INT size)
 {
   register int regno;
   register int mask = 0;
@@ -135,7 +133,7 @@ vax_output_function_prologue (file, size)
    so that gas can distinguish between D_float and G_float prior to
    processing the .stabs directive identifying type double.  */
 static void
-vax_file_start ()
+vax_file_start (void)
 {
   default_file_start ();
 
@@ -146,9 +144,7 @@ vax_file_start ()
 /* This is like nonimmediate_operand with a restriction on the type of MEM.  */
 
 void
-split_quadword_operands (operands, low, n)
-     rtx *operands, *low;
-     int n ATTRIBUTE_UNUSED;
+split_quadword_operands (rtx * operands, rtx * low, int n ATTRIBUTE_UNUSED)
 {
   int i;
   /* Split operands.  */
@@ -178,9 +174,7 @@ split_quadword_operands (operands, low, n)
 }
 
 void
-print_operand_address (file, addr)
-     FILE *file;
-     register rtx addr;
+print_operand_address (FILE * file, register rtx addr)
 {
   register rtx reg1, breg, ireg;
   rtx offset;
@@ -361,8 +355,7 @@ print_operand_address (file, addr)
 }
 
 const char *
-rev_cond_name (op)
-     rtx op;
+rev_cond_name (rtx op)
 {
   switch (GET_CODE (op))
     {
@@ -393,8 +386,7 @@ rev_cond_name (op)
 }
 
 int
-vax_float_literal(c)
-    register rtx c;
+vax_float_literal(register rtx c)
 {
   register enum machine_mode mode;
   REAL_VALUE_TYPE r, s;
@@ -440,8 +432,7 @@ vax_float_literal(c)
 
 
 static int
-vax_address_cost_1 (addr)
-    register rtx addr;
+vax_address_cost_1 (register rtx addr)
 {
   int reg = 0, indexed = 0, indir = 0, offset = 0, predec = 0;
   rtx plus_op0 = 0, plus_op1 = 0;
@@ -509,8 +500,7 @@ vax_address_cost_1 (addr)
 }
 
 static int
-vax_address_cost (x)
-     rtx x;
+vax_address_cost (rtx x)
 {
   return (1 + (GET_CODE (x) == REG ? 0 : vax_address_cost_1 (x)));
 }
@@ -520,9 +510,7 @@ vax_address_cost (x)
    other models.  */
 
 static int
-vax_rtx_costs_1 (x, code, outer_code)
-    register rtx x;
-    enum rtx_code code, outer_code;
+vax_rtx_costs_1 (register rtx x, enum rtx_code code, enum rtx_code outer_code)
 {
   enum machine_mode mode = GET_MODE (x);
   register int c;
@@ -745,10 +733,7 @@ vax_rtx_costs_1 (x, code, outer_code)
 }
 
 static bool
-vax_rtx_costs (x, code, outer_code, total)
-    rtx x;
-    int code, outer_code;
-    int *total;
+vax_rtx_costs (rtx x, int code, int outer_code, int * total)
 {
   *total = vax_rtx_costs_1 (x, code, outer_code);
   return true;
@@ -762,12 +747,11 @@ vax_rtx_costs (x, code, outer_code, total)
 */
 
 static void
-vax_output_mi_thunk (file, thunk, delta, vcall_offset, function)
-     FILE *file;
-     tree thunk ATTRIBUTE_UNUSED;
-     HOST_WIDE_INT delta;
-     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
-     tree function;
+vax_output_mi_thunk (FILE * file,
+                     tree thunk ATTRIBUTE_UNUSED, 
+                     HOST_WIDE_INT delta,
+                     HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
+                     tree function)
 {
   fprintf (file, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC, delta);
   asm_fprintf (file, ",4(%Rap)\n");
diff --git a/gcc/config/xtensa/crti.asm b/gcc/config/xtensa/crti.asm
index 8019ed1c3db..8e5cbe23fbd 100644
--- a/gcc/config/xtensa/crti.asm
+++ b/gcc/config/xtensa/crti.asm
@@ -29,16 +29,28 @@
 # .init sections.  Users may put any desired instructions in those
 # sections.
 
+#include "xtensa-config.h"
+
 	.section .init
 	.globl _init
 	.type _init,@function
 	.align	4
 _init:
-	entry	sp, 40
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	entry	sp, 64
+#else
+	addi	sp, sp, -32
+	s32i	a0, sp, 0
+#endif
 
 	.section .fini
 	.globl _fini
 	.type _fini,@function
 	.align	4
 _fini:
-	entry	sp, 40
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	entry	sp, 64
+#else
+	addi	sp, sp, -32
+	s32i	a0, sp, 0
+#endif
diff --git a/gcc/config/xtensa/crtn.asm b/gcc/config/xtensa/crtn.asm
index b4bdad93fe4..9ccf2e61ab0 100644
--- a/gcc/config/xtensa/crtn.asm
+++ b/gcc/config/xtensa/crtn.asm
@@ -29,8 +29,22 @@
 # fact return.  Users may put any desired instructions in those sections.
 # This file is the last thing linked into any executable.
 
+#include "xtensa-config.h"
+
 	.section .init
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
 	retw
+#else
+	l32i	a0, sp, 0
+	addi	sp, sp, 32
+	ret
+#endif
 
 	.section .fini
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
 	retw
+#else
+	l32i	a0, sp, 0
+	addi	sp, sp, 32
+	ret
+#endif
diff --git a/gcc/config/xtensa/elf.h b/gcc/config/xtensa/elf.h
index 65b0f6eb337..849be87edb0 100644
--- a/gcc/config/xtensa/elf.h
+++ b/gcc/config/xtensa/elf.h
@@ -43,13 +43,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #define WCHAR_TYPE_SIZE 16
 
 #undef ASM_SPEC
-#define ASM_SPEC "%{v} %{mno-density:--no-density} \
-                  %{mtext-section-literals:--text-section-literals} \
-                  %{mno-text-section-literals:--no-text-section-literals} \
-		  %{mtarget-align:--target-align} \
-		  %{mno-target-align:--no-target-align} \
-		  %{mlongcalls:--longcalls} \
-		  %{mno-longcalls:--no-longcalls}"
+#define ASM_SPEC \
+ "%{v} \
+  %{mtext-section-literals:--text-section-literals} \
+  %{mno-text-section-literals:--no-text-section-literals} \
+  %{mtarget-align:--target-align} \
+  %{mno-target-align:--no-target-align} \
+  %{mlongcalls:--longcalls} \
+  %{mno-longcalls:--no-longcalls}"
 
 #undef LIB_SPEC
 #define LIB_SPEC "-lc -lsim -lc -lhandlers-sim -lhal"
diff --git a/gcc/config/xtensa/lib1funcs.asm b/gcc/config/xtensa/lib1funcs.asm
index 72cd958841b..2df00218a5a 100644
--- a/gcc/config/xtensa/lib1funcs.asm
+++ b/gcc/config/xtensa/lib1funcs.asm
@@ -30,8 +30,13 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 
 #include "xtensa-config.h"
 
-	# Define macros for the ABS and ADDX* instructions to handle cases
-	# where they are not included in the Xtensa processor configuration.
+# Note: These functions use a minimum stack frame size of 32.  This is
+# necessary for Xtensa configurations that only support a fixed register
+# window size of 8, where even leaf functions (such as these) need to
+# allocate space for a 4-word "extra save area".
+
+# Define macros for the ABS and ADDX* instructions to handle cases
+# where they are not included in the Xtensa processor configuration.
 
 	.macro	do_abs dst, src, tmp
 #if XCHAL_HAVE_ABS
@@ -70,19 +75,41 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #endif
 	.endm
 
+# Define macros for function entry and return, supporting either the
+# standard register windowed ABI or the non-windowed call0 ABI.  These
+# macros do not allocate any extra stack space, so they only work for
+# leaf functions that do not need to spill anything to the stack.
+
+	.macro abi_entry reg, size
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	entry \reg, \size
+#else
+	/* do nothing */
+#endif
+	.endm
+
+	.macro abi_return
+#if XCHAL_HAVE_WINDOWED && !__XTENSA_CALL0_ABI__
+	retw
+#else
+	ret
+#endif
+	.endm
+
+
 #ifdef L_mulsi3
 	.align	4
 	.global	__mulsi3
 	.type	__mulsi3,@function
 __mulsi3:
-	entry	sp, 16
+	abi_entry sp, 32
 
 #if XCHAL_HAVE_MUL16
 	or	a4, a2, a3
 	srai	a4, a4, 16
 	bnez	a4, .LMUL16
 	mul16u	a2, a2, a3
-	retw
+	abi_return
 .LMUL16:
 	srai	a4, a2, 16
 	srai	a5, a3, 16
@@ -138,7 +165,7 @@ __mulsi3:
 	bgeui	a3, 16, .Lmult_main_loop
 	neg	a3, a2
 	movltz	a2, a3, a5
-	retw
+	abi_return
 
 	.align	4
 .Lmult_main_loop:
@@ -168,17 +195,17 @@ __mulsi3:
 
 #endif /* !XCHAL_HAVE_MUL16 && !XCHAL_HAVE_MAC16 */
 
-	retw
+	abi_return
 	.size	__mulsi3,.-__mulsi3
 
 #endif /* L_mulsi3 */
 
 
-	# Define a macro for the NSAU (unsigned normalize shift amount)
-	# instruction, which computes the number of leading zero bits,
-	# to handle cases where it is not included in the Xtensa processor
-	# configuration.
-	
+# Define a macro for the NSAU (unsigned normalize shift amount)
+# instruction, which computes the number of leading zero bits,
+# to handle cases where it is not included in the Xtensa processor
+# configuration.
+
 	.macro	do_nsau cnt, val, tmp, a
 #if XCHAL_HAVE_NSA
 	nsau	\cnt, \val
@@ -237,7 +264,7 @@ __nsau_data:
 	.global	__udivsi3
 	.type	__udivsi3,@function
 __udivsi3:
-	entry	sp, 16
+	abi_entry sp, 32
 	bltui	a3, 2, .Lle_one	# check if the divisor <= 1
 
 	mov	a6, a2		# keep dividend in a6
@@ -270,7 +297,7 @@ __udivsi3:
 	bltu	a6, a3, .Lreturn
 	addi	a2, a2, 1	# increment quotient if dividend >= divisor
 .Lreturn:
-	retw
+	abi_return
 
 .Lspecial:
 	# return dividend >= divisor
@@ -278,14 +305,14 @@ __udivsi3:
 	bltu	a6, a3, .Lreturn2
 	movi	a2, 1
 .Lreturn2:
-	retw
+	abi_return
 
 .Lle_one:
 	beqz	a3, .Lerror	# if divisor == 1, return the dividend
-	retw
+	abi_return
 .Lerror:
 	movi	a2, 0		# just return 0; could throw an exception
-	retw
+	abi_return
 	.size	__udivsi3,.-__udivsi3
 
 #endif /* L_udivsi3 */
@@ -296,7 +323,7 @@ __udivsi3:
 	.global	__divsi3
 	.type	__divsi3,@function
 __divsi3:
-	entry	sp, 16
+	abi_entry sp, 32
 	xor	a7, a2, a3	# sign = dividend ^ divisor
 	do_abs	a6, a2, a4	# udividend = abs(dividend)
 	do_abs	a3, a3, a4	# udivisor = abs(divisor)
@@ -332,7 +359,7 @@ __divsi3:
 .Lreturn:
 	neg	a5, a2
 	movltz	a2, a5, a7	# return (sign < 0) ? -quotient : quotient
-	retw
+	abi_return
 
 .Lspecial:
 	movi	a2, 0
@@ -341,16 +368,16 @@ __divsi3:
 	movi	a4, -1
 	movltz	a2, a4, a7	# else return (sign < 0) ? -1 :	 1 
 .Lreturn2:
-	retw
+	abi_return
 
 .Lle_one:
 	beqz	a3, .Lerror
 	neg	a2, a6		# if udivisor == 1, then return...
 	movgez	a2, a6, a7	# (sign < 0) ? -udividend : udividend
-	retw
+	abi_return
 .Lerror:
 	movi	a2, 0		# just return 0; could throw an exception
-	retw
+	abi_return
 	.size	__divsi3,.-__divsi3
 
 #endif /* L_divsi3 */
@@ -361,7 +388,7 @@ __divsi3:
 	.global	__umodsi3
 	.type	__umodsi3,@function
 __umodsi3:
-	entry	sp, 16
+	abi_entry sp, 32
 	bltui	a3, 2, .Lle_one	# check if the divisor is <= 1
 
 	do_nsau	a5, a2, a6, a7	# dividend_shift = nsau(dividend)
@@ -390,19 +417,19 @@ __umodsi3:
 	bltu	a2, a3, .Lreturn
 	sub	a2, a2, a3	# subtract once more if dividend >= divisor
 .Lreturn:
-	retw
+	abi_return
 
 .Lspecial:
 	bltu	a2, a3, .Lreturn2
 	sub	a2, a2, a3	# subtract once if dividend >= divisor
 .Lreturn2:
-	retw
+	abi_return
 
 .Lle_one:
 	# the divisor is either 0 or 1, so just return 0.
 	# someday we may want to throw an exception if the divisor is 0.
 	movi	a2, 0
-	retw
+	abi_return
 	.size	__umodsi3,.-__umodsi3
 
 #endif /* L_umodsi3 */
@@ -413,7 +440,7 @@ __umodsi3:
 	.global	__modsi3
 	.type	__modsi3,@function
 __modsi3:
-	entry	sp, 16
+	abi_entry sp, 32
 	mov	a7, a2		# save original (signed) dividend
 	do_abs	a2, a2, a4	# udividend = abs(dividend)
 	do_abs	a3, a3, a4	# udivisor = abs(divisor)
@@ -447,7 +474,7 @@ __modsi3:
 	bgez	a7, .Lpositive
 	neg	a2, a2		# if (dividend < 0), return -udividend
 .Lpositive:	
-	retw
+	abi_return
 
 .Lspecial:
 	bltu	a2, a3, .Lreturn2
@@ -456,13 +483,13 @@ __modsi3:
 	bgez	a7, .Lpositive2
 	neg	a2, a2		# if (dividend < 0), return -udividend
 .Lpositive2:	
-	retw
+	abi_return
 
 .Lle_one:
 	# udivisor is either 0 or 1, so just return 0.
 	# someday we may want to throw an exception if udivisor is 0.
 	movi	a2, 0
-	retw
+	abi_return
 	.size	__modsi3,.-__modsi3
 
 #endif /* L_modsi3 */
diff --git a/gcc/config/xtensa/lib2funcs.S b/gcc/config/xtensa/lib2funcs.S
index d06e1222ae8..80f5f0bcb48 100644
--- a/gcc/config/xtensa/lib2funcs.S
+++ b/gcc/config/xtensa/lib2funcs.S
@@ -150,7 +150,7 @@ __xtensa_nonlocal_goto:
    be touched by the trampoline.  An ISYNC instruction is also needed to
    make sure that the modified instructions are loaded into the instruction
    fetch buffer. */
-	
+
 #define TRAMPOLINE_SIZE 59
 
 	.text
diff --git a/gcc/config/xtensa/linux.h b/gcc/config/xtensa/linux.h
index d8b230f2337..ef5aae04f63 100644
--- a/gcc/config/xtensa/linux.h
+++ b/gcc/config/xtensa/linux.h
@@ -40,13 +40,14 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 #define WCHAR_TYPE_SIZE 32
 
 #undef ASM_SPEC
-#define ASM_SPEC "%{v} %{mno-density:--no-density} \
-                  %{mtext-section-literals:--text-section-literals} \
-                  %{mno-text-section-literals:--no-text-section-literals} \
-		  %{mtarget-align:--target-align} \
-		  %{mno-target-align:--no-target-align} \
-		  %{mlongcalls:--longcalls} \
-		  %{mno-longcalls:--no-longcalls}"
+#define ASM_SPEC \
+ "%{v} \
+  %{mtext-section-literals:--text-section-literals} \
+  %{mno-text-section-literals:--no-text-section-literals} \
+  %{mtarget-align:--target-align} \
+  %{mno-target-align:--no-target-align} \
+  %{mlongcalls:--longcalls} \
+  %{mno-longcalls:--no-longcalls}"
 
 #undef LINK_SPEC
 #define LINK_SPEC \
diff --git a/gcc/config/xtensa/t-xtensa b/gcc/config/xtensa/t-xtensa
index 5597650273a..d39f7fe0e0f 100644
--- a/gcc/config/xtensa/t-xtensa
+++ b/gcc/config/xtensa/t-xtensa
@@ -17,11 +17,11 @@ LIB1ASMFUNCS = _mulsi3 _nsau _divsi3 _modsi3 _udivsi3 _umodsi3
 LIB2FUNCS_EXTRA += $(srcdir)/config/xtensa/lib2funcs.S
 
 $(T)crti.o: $(srcdir)/config/xtensa/crti.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crti.o \
-	  -x assembler-with-cpp $(srcdir)/config/xtensa/crti.asm
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/xtensa/crti.asm
 $(T)crtn.o: $(srcdir)/config/xtensa/crtn.asm $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) -c -o $(T)crtn.o \
-	  -x assembler-with-cpp $(srcdir)/config/xtensa/crtn.asm
+	$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
+	-c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/xtensa/crtn.asm
 
 $(out_object_file): gt-xtensa.h
 gt-xtensa.h : s-gtype ; @true
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 3c382d96ca5..32d5030c239 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -200,7 +200,7 @@ static struct machine_function * xtensa_init_machine_status PARAMS ((void));
 static void printx PARAMS ((FILE *, signed int));
 static void xtensa_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
 static unsigned int xtensa_multibss_section_type_flags
-  PARAMS ((tree, const char *, int));
+  PARAMS ((tree, const char *, int)) ATTRIBUTE_UNUSED;
 static void xtensa_select_rtx_section
   PARAMS ((enum machine_mode, rtx, unsigned HOST_WIDE_INT));
 static bool xtensa_rtx_costs PARAMS ((rtx, int, int, int *));
@@ -581,8 +581,37 @@ call_insn_operand (op, mode)
   if (CONSTANT_ADDRESS_P (op))
     {
       /* Direct calls only allowed to static functions with PIC.  */
-      return (!flag_pic
-	      || (GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)));
+      if (flag_pic)
+	{
+	  tree callee, callee_sec, caller_sec;
+
+	  if (GET_CODE (op) != SYMBOL_REF || !SYMBOL_REF_LOCAL_P (op))
+	    return FALSE;
+
+	  /* Don't attempt a direct call if the callee is known to be in
+	     a different section, since there's a good chance it will be
+	     out of range.  */
+
+	  if (flag_function_sections
+	      || DECL_ONE_ONLY (current_function_decl))
+	    return FALSE;
+	  caller_sec = DECL_SECTION_NAME (current_function_decl);
+	  callee = SYMBOL_REF_DECL (op);
+	  if (callee)
+	    {
+	      if (DECL_ONE_ONLY (callee))
+		return FALSE;
+	      callee_sec = DECL_SECTION_NAME (callee);
+	      if (((caller_sec == NULL_TREE) ^ (callee_sec == NULL_TREE))
+		  || (caller_sec != NULL_TREE
+		      && strcmp (TREE_STRING_POINTER (caller_sec),
+				 TREE_STRING_POINTER (callee_sec)) != 0))
+		return FALSE;
+	    }
+	  else if (caller_sec != NULL_TREE)
+	    return FALSE;
+	}
+      return TRUE;
     }
 
   return FALSE;
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 5f5e112cd85..621dd5fbbb6 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -42,148 +42,43 @@ extern struct rtx_def * branch_cmp[2];	/* operands for compare */
 extern enum cmp_type branch_type;	/* what type of branch to use */
 extern unsigned xtensa_current_frame_size;
 
-/* Run-time compilation parameters selecting different hardware subsets.  */
-
-#define MASK_BIG_ENDIAN		0x00000001	/* big or little endian */
-#define MASK_DENSITY		0x00000002	/* code density option */
-#define MASK_MAC16		0x00000004	/* MAC16 option */
-#define MASK_MUL16		0x00000008	/* 16-bit integer multiply */
-#define MASK_MUL32		0x00000010	/* integer multiply/divide */
-#define MASK_DIV32		0x00000020	/* integer multiply/divide */
-#define MASK_NSA		0x00000040	/* nsa instruction option */
-#define MASK_MINMAX		0x00000080	/* min/max instructions */
-#define MASK_SEXT		0x00000100	/* sign extend insn option */
-#define MASK_BOOLEANS		0x00000200	/* boolean register option */
-#define MASK_HARD_FLOAT		0x00000400	/* floating-point option */
-#define MASK_HARD_FLOAT_DIV	0x00000800	/* floating-point divide */
-#define MASK_HARD_FLOAT_RECIP	0x00001000	/* floating-point reciprocal */
-#define MASK_HARD_FLOAT_SQRT	0x00002000	/* floating-point sqrt */
-#define MASK_HARD_FLOAT_RSQRT	0x00004000	/* floating-point recip sqrt */
-#define MASK_NO_FUSED_MADD	0x00008000	/* avoid f-p mul/add */
-#define MASK_CONST16		0x00010000	/* use CONST16 instruction */
-#define MASK_ABS		0x00020000	/* use ABS instruction */
-#define MASK_ADDX		0x00040000	/* use ADDX* and SUBX* */
-
-/* Macros used in the machine description to test the flags.  */
-
-#define TARGET_BIG_ENDIAN	(target_flags & MASK_BIG_ENDIAN)
-#define TARGET_DENSITY		(target_flags & MASK_DENSITY)
-#define TARGET_MAC16		(target_flags & MASK_MAC16)
-#define TARGET_MUL16		(target_flags & MASK_MUL16)
-#define TARGET_MUL32		(target_flags & MASK_MUL32)
-#define TARGET_DIV32		(target_flags & MASK_DIV32)
-#define TARGET_NSA		(target_flags & MASK_NSA)
-#define TARGET_MINMAX		(target_flags & MASK_MINMAX)
-#define TARGET_SEXT		(target_flags & MASK_SEXT)
-#define TARGET_BOOLEANS		(target_flags & MASK_BOOLEANS)
-#define TARGET_HARD_FLOAT	(target_flags & MASK_HARD_FLOAT)
-#define TARGET_HARD_FLOAT_DIV	(target_flags & MASK_HARD_FLOAT_DIV)
-#define TARGET_HARD_FLOAT_RECIP	(target_flags & MASK_HARD_FLOAT_RECIP)
-#define TARGET_HARD_FLOAT_SQRT	(target_flags & MASK_HARD_FLOAT_SQRT)
-#define TARGET_HARD_FLOAT_RSQRT	(target_flags & MASK_HARD_FLOAT_RSQRT)
+/* Masks for the -m switches */
+#define MASK_NO_FUSED_MADD	0x00000001	/* avoid f-p mul/add */
+#define MASK_CONST16		0x00000002	/* use CONST16 instruction */
+
+/* Macros used in the machine description to select various Xtensa
+   configuration options.  */
+#define TARGET_BIG_ENDIAN	XCHAL_HAVE_BE
+#define TARGET_DENSITY		XCHAL_HAVE_DENSITY
+#define TARGET_MAC16		XCHAL_HAVE_MAC16
+#define TARGET_MUL16		XCHAL_HAVE_MUL16
+#define TARGET_MUL32		XCHAL_HAVE_MUL32
+#define TARGET_DIV32		XCHAL_HAVE_DIV32
+#define TARGET_NSA		XCHAL_HAVE_NSA
+#define TARGET_MINMAX		XCHAL_HAVE_MINMAX
+#define TARGET_SEXT		XCHAL_HAVE_SEXT
+#define TARGET_BOOLEANS		XCHAL_HAVE_BOOLEANS
+#define TARGET_HARD_FLOAT	XCHAL_HAVE_FP
+#define TARGET_HARD_FLOAT_DIV	XCHAL_HAVE_FP_DIV
+#define TARGET_HARD_FLOAT_RECIP	XCHAL_HAVE_FP_RECIP
+#define TARGET_HARD_FLOAT_SQRT	XCHAL_HAVE_FP_SQRT
+#define TARGET_HARD_FLOAT_RSQRT	XCHAL_HAVE_FP_RSQRT
+#define TARGET_ABS		XCHAL_HAVE_ABS
+#define TARGET_ADDX		XCHAL_HAVE_ADDX
+
+/* Macros controlled by command-line options.  */
 #define TARGET_NO_FUSED_MADD	(target_flags & MASK_NO_FUSED_MADD)
 #define TARGET_CONST16		(target_flags & MASK_CONST16)
-#define TARGET_ABS		(target_flags & MASK_ABS)
-#define TARGET_ADDX		(target_flags & MASK_ADDX)
-
-/* Default target_flags if no switches are specified  */
 
 #define TARGET_DEFAULT (						\
-  (XCHAL_HAVE_BE	? MASK_BIG_ENDIAN : 0) |			\
-  (XCHAL_HAVE_DENSITY	? MASK_DENSITY : 0) |				\
-  (XCHAL_HAVE_L32R	? 0 : MASK_CONST16) |				\
-  (XCHAL_HAVE_ABS	? MASK_ABS : 0) |				\
-  (XCHAL_HAVE_ADDX	? MASK_ADDX : 0) |				\
-  (XCHAL_HAVE_MAC16	? MASK_MAC16 : 0) |				\
-  (XCHAL_HAVE_MUL16	? MASK_MUL16 : 0) |				\
-  (XCHAL_HAVE_MUL32	? MASK_MUL32 : 0) |				\
-  (XCHAL_HAVE_DIV32	? MASK_DIV32 : 0) |				\
-  (XCHAL_HAVE_NSA	? MASK_NSA : 0) |				\
-  (XCHAL_HAVE_MINMAX	? MASK_MINMAX : 0) |				\
-  (XCHAL_HAVE_SEXT	? MASK_SEXT : 0) |				\
-  (XCHAL_HAVE_BOOLEANS	? MASK_BOOLEANS : 0) |				\
-  (XCHAL_HAVE_FP	? MASK_HARD_FLOAT : 0) |			\
-  (XCHAL_HAVE_FP_DIV	? MASK_HARD_FLOAT_DIV : 0) |			\
-  (XCHAL_HAVE_FP_RECIP	? MASK_HARD_FLOAT_RECIP : 0) |			\
-  (XCHAL_HAVE_FP_SQRT	? MASK_HARD_FLOAT_SQRT : 0) |			\
-  (XCHAL_HAVE_FP_RSQRT	? MASK_HARD_FLOAT_RSQRT : 0))
-
-/* Macro to define tables used to set the flags.  */
+  (XCHAL_HAVE_L32R	? 0 : MASK_CONST16))
 
 #define TARGET_SWITCHES							\
 {									\
-  {"big-endian",		MASK_BIG_ENDIAN,			\
-    N_("Use big-endian byte order")},					\
-  {"little-endian",		-MASK_BIG_ENDIAN,			\
-    N_("Use little-endian byte order")},				\
-  {"density",			MASK_DENSITY,				\
-    N_("Use the Xtensa code density option")},				\
-  {"no-density",		-MASK_DENSITY,				\
-    N_("Do not use the Xtensa code density option")},			\
   {"const16",			MASK_CONST16,				\
     N_("Use CONST16 instruction to load constants")},			\
   {"no-const16",		-MASK_CONST16,				\
     N_("Use PC-relative L32R instruction to load constants")},		\
-  {"abs",			MASK_ABS,				\
-    N_("Use the Xtensa ABS instruction")},				\
-  {"no-abs",			-MASK_ABS,				\
-    N_("Do not use the Xtensa ABS instruction")},			\
-  {"addx",			MASK_ADDX,				\
-    N_("Use the Xtensa ADDX and SUBX instructions")},			\
-  {"no-addx",			-MASK_ADDX,				\
-    N_("Do not use the Xtensa ADDX and SUBX instructions")},		\
-  {"mac16",			MASK_MAC16,				\
-    N_("Use the Xtensa MAC16 option")},					\
-  {"no-mac16",			-MASK_MAC16,				\
-    N_("Do not use the Xtensa MAC16 option")},				\
-  {"mul16",			MASK_MUL16,				\
-    N_("Use the Xtensa MUL16 option")},					\
-  {"no-mul16",			-MASK_MUL16,				\
-    N_("Do not use the Xtensa MUL16 option")},				\
-  {"mul32",			MASK_MUL32,				\
-    N_("Use the Xtensa MUL32 option")},					\
-  {"no-mul32",			-MASK_MUL32,				\
-    N_("Do not use the Xtensa MUL32 option")},				\
-  {"div32",			MASK_DIV32,				\
-    0 /* undocumented */},						\
-  {"no-div32",			-MASK_DIV32,				\
-    0 /* undocumented */},						\
-  {"nsa",			MASK_NSA,				\
-    N_("Use the Xtensa NSA option")},					\
-  {"no-nsa",			-MASK_NSA,				\
-    N_("Do not use the Xtensa NSA option")},				\
-  {"minmax",			MASK_MINMAX,				\
-    N_("Use the Xtensa MIN/MAX option")},				\
-  {"no-minmax",			-MASK_MINMAX,				\
-    N_("Do not use the Xtensa MIN/MAX option")},			\
-  {"sext",			MASK_SEXT,				\
-    N_("Use the Xtensa SEXT option")},					\
-  {"no-sext",			-MASK_SEXT,				\
-    N_("Do not use the Xtensa SEXT option")},				\
-  {"booleans",			MASK_BOOLEANS,				\
-    N_("Use the Xtensa boolean register option")},			\
-  {"no-booleans",		-MASK_BOOLEANS,				\
-    N_("Do not use the Xtensa boolean register option")},		\
-  {"hard-float",		MASK_HARD_FLOAT,			\
-    N_("Use the Xtensa floating-point unit")},				\
-  {"soft-float",		-MASK_HARD_FLOAT,			\
-    N_("Do not use the Xtensa floating-point unit")},			\
-  {"hard-float-div",		MASK_HARD_FLOAT_DIV,			\
-    0 /* undocumented */},						\
-  {"no-hard-float-div",		-MASK_HARD_FLOAT_DIV,			\
-    0 /* undocumented */},						\
-  {"hard-float-recip",		MASK_HARD_FLOAT_RECIP,			\
-    0 /* undocumented */},						\
-  {"no-hard-float-recip",	-MASK_HARD_FLOAT_RECIP,			\
-    0 /* undocumented */},						\
-  {"hard-float-sqrt",		MASK_HARD_FLOAT_SQRT,			\
-    0 /* undocumented */},						\
-  {"no-hard-float-sqrt",	-MASK_HARD_FLOAT_SQRT,			\
-    0 /* undocumented */},						\
-  {"hard-float-rsqrt",		MASK_HARD_FLOAT_RSQRT,			\
-    0 /* undocumented */},						\
-  {"no-hard-float-rsqrt",	-MASK_HARD_FLOAT_RSQRT,			\
-    0 /* undocumented */},						\
   {"no-fused-madd",		MASK_NO_FUSED_MADD,			\
     N_("Disable fused multiply/add and multiply/subtract FP instructions")}, \
   {"fused-madd",		-MASK_NO_FUSED_MADD,			\
@@ -1207,7 +1102,7 @@ typedef struct xtensa_args {
    operand on the target machine when generating position independent
    code.  */
 #define LEGITIMATE_PIC_OPERAND_P(X)					\
-  ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_FLAG (X))			\
+  ((GET_CODE (X) != SYMBOL_REF || SYMBOL_REF_LOCAL_P (X))		\
    && GET_CODE (X) != LABEL_REF						\
    && GET_CODE (X) != CONST)
 
@@ -1482,3 +1377,13 @@ typedef struct xtensa_args {
 /* Exception handling TODO!! */
 #define DWARF_UNWIND_INFO 0
 
+/* Xtensa constant pool breaks the devices in crtstuff.c to control
+   section in where code resides.  We have to write it as asm code.  Use
+   a MOVI and let the assembler relax it -- for the .init and .fini
+   sections, the assembler knows to put the literal in the right
+   place.  */
+#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
+    asm (SECTION_OP "\n\
+	movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
+	callx8\ta8\n" \
+	TEXT_SECTION_ASM_OP);
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 26bad87cf7f..01ec40d63a7 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -19,13 +19,6 @@
 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 ;; 02111-1307, USA.
 
-;;
-;; ....................
-;;
-;;	CONSTANTS
-;;
-;; ....................
-;;
 
 (define_constants [
   (A0_REG		0)
@@ -41,13 +34,8 @@
   (UNSPECV_ENTRY	2)
 ])
 
-;;
-;; ....................
-;;
-;;	ATTRIBUTES
-;;
-;; ....................
-;;
+
+;; Attributes.
 
 (define_attr "type"
   "unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fdiv,fsqrt,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr"
@@ -63,14 +51,8 @@
 (define_asm_attributes
   [(set_attr "type" "multi")])
 
-
-;;
-;; ....................
-;;
-;;	FUNCTIONAL UNITS
-;;
-;; ....................
-;;
+
+;; Functional units.
 
 (define_function_unit "memory" 1 0 (eq_attr "type" "load,fload") 2 0)
 
@@ -84,21 +66,14 @@
 
 (define_function_unit "fpconv" 1 0 (eq_attr "type" "fconv") 2 0)
 
-
-;;
-;;  ....................
-;;
-;;	ADDITION
-;;
-;;  ....................
-;;
+
+;; Addition.
 
 (define_expand "adddi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(plus:DI (match_operand:DI 1 "register_operand" "")
 		 (match_operand:DI 2 "register_operand" "")))]
   ""
-  "
 {
   rtx srclo;
   rtx dstlo = gen_lowpart (SImode, operands[0]);
@@ -125,7 +100,7 @@
   emit_insn (gen_addsi3 (dsthi, src1hi, src2hi));
   emit_insn (gen_adddi_carry (dsthi, dstlo, srclo));
   DONE;
-}")
+})
 
 ;; Represent the add-carry operation as an atomic operation instead of
 ;; expanding it to a conditional branch.  Otherwise, the edge
@@ -138,7 +113,7 @@
 			 (match_operand:SI 2 "register_operand" "r"))
 		 (match_dup 0)))]
   ""
-  "bgeu\\t%1, %2, 0f\;addi\\t%0, %0, 1\;0:"
+  "bgeu\t%1, %2, 0f\;addi\t%0, %0, 1\;0:"
   [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"6")])
@@ -149,11 +124,11 @@
 		 (match_operand:SI 2 "add_operand" "d,O,r,J,N")))]
   ""
   "@
-   add.n\\t%0, %1, %2
-   addi.n\\t%0, %1, %d2
-   add\\t%0, %1, %2
-   addi\\t%0, %1, %d2
-   addmi\\t%0, %1, %x2"
+   add.n\t%0, %1, %2
+   addi.n\t%0, %1, %d2
+   add\t%0, %1, %2
+   addi\t%0, %1, %d2
+   addmi\t%0, %1, %x2"
   [(set_attr "type"	"arith,arith,arith,arith,arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"2,2,3,3,3")])
@@ -164,7 +139,7 @@
 			  (const_int 2))
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "addx2\\t%0, %1, %2"
+  "addx2\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -175,7 +150,7 @@
 			  (const_int 4))
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "addx4\\t%0, %1, %2"
+  "addx4\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -186,7 +161,7 @@
 			  (const_int 8))
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "addx8\\t%0, %1, %2"
+  "addx8\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -196,26 +171,19 @@
 	(plus:SF (match_operand:SF 1 "register_operand" "%f")
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "add.s\\t%0, %1, %2"
+  "add.s\t%0, %1, %2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	SUBTRACTION
-;;
-;;  ....................
-;;
+
+;; Subtraction.
 
 (define_expand "subdi3"
   [(set (match_operand:DI 0 "register_operand" "")
 	(minus:DI (match_operand:DI 1 "register_operand" "")
 		  (match_operand:DI 2 "register_operand" "")))]
   ""
-  "
 {
   rtx dstlo = gen_lowpart (SImode, operands[0]);
   rtx src1lo = gen_lowpart (SImode, operands[1]);
@@ -229,7 +197,7 @@
   emit_insn (gen_subdi_carry (dsthi, src1lo, src2lo));
   emit_insn (gen_subsi3 (dstlo, src1lo, src2lo));
   DONE;
-}")
+})
 
 (define_insn "subdi_carry"
   [(set (match_operand:SI 0 "register_operand" "+a")
@@ -237,7 +205,7 @@
 		  (ltu:SI (match_operand:SI 1 "register_operand" "r")
 			  (match_operand:SI 2 "register_operand" "r"))))]
   ""
-  "bgeu\\t%1, %2, 0f\;addi\\t%0, %0, -1\;0:"
+  "bgeu\t%1, %2, 0f\;addi\t%0, %0, -1\;0:"
   [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"6")])
@@ -247,7 +215,7 @@
         (minus:SI (match_operand:SI 1 "register_operand" "r")
 		  (match_operand:SI 2 "register_operand" "r")))]
   ""
-  "sub\\t%0, %1, %2"
+  "sub\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -258,7 +226,7 @@
 			   (const_int 2))
 		  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "subx2\\t%0, %1, %2"
+  "subx2\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -269,7 +237,7 @@
 			   (const_int 4))
 		  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "subx4\\t%0, %1, %2"
+  "subx4\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -280,7 +248,7 @@
 			   (const_int 8))
 		  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_ADDX"
-  "subx8\\t%0, %1, %2"
+  "subx8\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -290,26 +258,20 @@
 	(minus:SF (match_operand:SF 1 "register_operand" "f")
 		  (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "sub.s\\t%0, %1, %2"
+  "sub.s\t%0, %1, %2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	MULTIPLICATION
-;;
-;;  ....................
-;;
+
+;; Multiplication.
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(mult:SI (match_operand:SI 1 "register_operand" "%r")
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_MUL32"
-  "mull\\t%0, %1, %2"
+  "mull\t%0, %1, %2"
   [(set_attr "type"	"mul32")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -322,8 +284,8 @@
 		  (match_operand:HI 2 "register_operand" "r,r"))))]
   "TARGET_MUL16 || TARGET_MAC16"
   "@
-   mul16s\\t%0, %1, %2
-   mul.aa.ll\\t%1, %2"
+   mul16s\t%0, %1, %2
+   mul.aa.ll\t%1, %2"
   [(set_attr "type"	"mul16,mac16")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -336,8 +298,8 @@
 		  (match_operand:HI 2 "register_operand" "r,r"))))]
   "TARGET_MUL16 || TARGET_MAC16"
   "@
-   mul16u\\t%0, %1, %2
-   umul.aa.ll\\t%1, %2"
+   mul16u\t%0, %1, %2
+   umul.aa.ll\t%1, %2"
   [(set_attr "type"	"mul16,mac16")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -350,7 +312,7 @@
 			   (match_operand:HI 2 "register_operand" "r")))
 		 (match_operand:SI 3 "register_operand" "0")))]
   "TARGET_MAC16"
-  "mula.aa.ll\\t%1, %2"
+  "mula.aa.ll\t%1, %2"
   [(set_attr "type"	"mac16")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -363,7 +325,7 @@
 			   (sign_extend:SI
 			    (match_operand:HI 3 "register_operand" "r")))))]
   "TARGET_MAC16"
-  "muls.aa.ll\\t%2, %3"
+  "muls.aa.ll\t%2, %3"
   [(set_attr "type"	"mac16")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -373,7 +335,7 @@
 	(mult:SF (match_operand:SF 1 "register_operand" "%f")
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "mul.s\\t%0, %1, %2"
+  "mul.s\t%0, %1, %2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -384,7 +346,7 @@
 			  (match_operand:SF 2 "register_operand" "f"))
 		 (match_operand:SF 3 "register_operand" "0")))]
   "TARGET_HARD_FLOAT && !TARGET_NO_FUSED_MADD"
-  "madd.s\\t%0, %1, %2"
+  "madd.s\t%0, %1, %2"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -395,26 +357,20 @@
 		  (mult:SF (match_operand:SF 2 "register_operand" "%f")
 			   (match_operand:SF 3 "register_operand" "f"))))]
   "TARGET_HARD_FLOAT && !TARGET_NO_FUSED_MADD"
-  "msub.s\\t%0, %2, %3"
+  "msub.s\t%0, %2, %3"
   [(set_attr "type"	"fmadd")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	DIVISION
-;;
-;;  ....................
-;;
+
+;; Division.
 
 (define_insn "divsi3"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(div:SI (match_operand:SI 1 "register_operand" "r")
 		(match_operand:SI 2 "register_operand" "r")))]
   "TARGET_DIV32"
-  "quos\\t%0, %1, %2"
+  "quos\t%0, %1, %2"
   [(set_attr "type"	"div32")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -424,7 +380,7 @@
 	(udiv:SI (match_operand:SI 1 "register_operand" "r")
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_DIV32"
-  "quou\\t%0, %1, %2"
+  "quou\t%0, %1, %2"
   [(set_attr "type"	"div32")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -434,7 +390,7 @@
 	(div:SF (match_operand:SF 1 "register_operand" "f")
 		(match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT_DIV"
-  "div.s\\t%0, %1, %2"
+  "div.s\t%0, %1, %2"
   [(set_attr "type"	"fdiv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -444,26 +400,20 @@
 	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
 		(match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT_RECIP && flag_unsafe_math_optimizations"
-  "recip.s\\t%0, %2"
+  "recip.s\t%0, %2"
   [(set_attr "type"	"fdiv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	REMAINDER
-;;
-;;  ....................
-;;
+
+;; Remainders.
 
 (define_insn "modsi3"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(mod:SI (match_operand:SI 1 "register_operand" "r")
 		(match_operand:SI 2 "register_operand" "r")))]
   "TARGET_DIV32"
-  "rems\\t%0, %1, %2"
+  "rems\t%0, %1, %2"
   [(set_attr "type"	"div32")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -473,25 +423,19 @@
 	(umod:SI (match_operand:SI 1 "register_operand" "r")
 		 (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_DIV32"
-  "remu\\t%0, %1, %2"
+  "remu\t%0, %1, %2"
   [(set_attr "type"	"div32")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	SQUARE ROOT
-;;
-;;  ....................
-;;
+
+;; Square roots.
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT_SQRT"
-  "sqrt.s\\t%0, %1"
+  "sqrt.s\t%0, %1"
   [(set_attr "type"	"fsqrt")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -501,25 +445,19 @@
 	(div:SF (match_operand:SF 1 "const_float_1_operand" "")
 		(sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
   "TARGET_HARD_FLOAT_RSQRT && flag_unsafe_math_optimizations"
-  "rsqrt.s\\t%0, %2"
+  "rsqrt.s\t%0, %2"
   [(set_attr "type"	"fsqrt")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	ABSOLUTE VALUE
-;;
-;;  ....................
-;;
+
+;; Absolute value.
 
 (define_insn "abssi2"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(abs:SI (match_operand:SI 1 "register_operand" "r")))]
   "TARGET_ABS"
-  "abs\\t%0, %1"
+  "abs\t%0, %1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -528,26 +466,20 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "abs.s\\t%0, %1"
+  "abs.s\t%0, %1"
   [(set_attr "type"	"farith")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	MIN AND MAX INSTRUCTIONS
-;;
-;;  ....................
-;;
+
+;; Min and max.
 
 (define_insn "sminsi3"
   [(set (match_operand:SI 0 "register_operand" "=a")
         (smin:SI (match_operand:SI 1 "register_operand" "%r")
                  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_MINMAX"
-  "min\\t%0, %1, %2"
+  "min\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -557,7 +489,7 @@
         (umin:SI (match_operand:SI 1 "register_operand" "%r")
                  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_MINMAX"
-  "minu\\t%0, %1, %2"
+  "minu\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -567,7 +499,7 @@
         (smax:SI (match_operand:SI 1 "register_operand" "%r")
                  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_MINMAX"
-  "max\\t%0, %1, %2"
+  "max\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -577,25 +509,18 @@
         (umax:SI (match_operand:SI 1 "register_operand" "%r")
                  (match_operand:SI 2 "register_operand" "r")))]
   "TARGET_MINMAX"
-  "maxu\\t%0, %1, %2"
+  "maxu\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	FIND FIRST BIT INSTRUCTION
-;;
-;;  ....................
-;;
+
+;; Find first bit.
 
 (define_expand "ffssi2"
   [(set (match_operand:SI 0 "register_operand" "")
 	(ffs:SI (match_operand:SI 1 "register_operand" "")))]
   "TARGET_NSA"
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   emit_insn (gen_negsi2 (temp, operands[1]));
@@ -604,32 +529,26 @@
   emit_insn (gen_negsi2 (temp, temp));
   emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (32)));
   DONE;
-}")
+})
 
-;; there is no RTL operator corresponding to NSAU
+;; There is no RTL operator corresponding to NSAU.
 (define_insn "nsau"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "r")] UNSPEC_NSAU))]
   "TARGET_NSA"
-  "nsau\\t%0, %1"
+  "nsau\t%0, %1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	NEGATION and ONE'S COMPLEMENT
-;;
-;;  ....................
-;;
+
+;; Negation and one's complement.
 
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
   ""
-  "neg\\t%0, %1"
+  "neg\t%0, %1"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -638,31 +557,24 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(not:SI (match_operand:SI 1 "register_operand" "")))]
   ""
-  "
 {
   rtx temp = gen_reg_rtx (SImode);
   emit_insn (gen_movsi (temp, constm1_rtx));
   emit_insn (gen_xorsi3 (operands[0], temp, operands[1]));
   DONE;
-}")
+})
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "neg.s\\t%0, %1"
+  "neg.s\t%0, %1"
   [(set_attr "type"	"farith")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	LOGICAL
-;;
-;;  ....................
-;;
+
+;; Logical instructions.
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
@@ -670,8 +582,8 @@
 		(match_operand:SI 2 "mask_operand" "P,r")))]
   ""
   "@
-   extui\\t%0, %1, 0, %K2
-   and\\t%0, %1, %2"
+   extui\t%0, %1, 0, %K2
+   and\t%0, %1, %2"
   [(set_attr "type"	"arith,arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -681,7 +593,7 @@
 	(ior:SI (match_operand:SI 1 "register_operand" "%r")
 		(match_operand:SI 2 "register_operand" "r")))]
   ""
-  "or\\t%0, %1, %2"
+  "or\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -691,27 +603,21 @@
 	(xor:SI (match_operand:SI 1 "register_operand" "%r")
 		(match_operand:SI 2 "register_operand" "r")))]
   ""
-  "xor\\t%0, %1, %2"
+  "xor\t%0, %1, %2"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	ZERO EXTENSION
-;;
-;;  ....................
-;;
+
+;; Zero-extend instructions.
 
 (define_insn "zero_extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
 	(zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
   ""
   "@
-   extui\\t%0, %1, 0, 16
-   l16ui\\t%0, %1"
+   extui\t%0, %1, 0, 16
+   l16ui\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -721,41 +627,34 @@
 	(zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
   ""
   "@
-   extui\\t%0, %1, 0, 8
-   l8ui\\t%0, %1"
+   extui\t%0, %1, 0, 8
+   l8ui\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
 
-
-;;
-;;  ....................
-;;
-;;	SIGN EXTENSION
-;;
-;;  ....................
-;;
+
+;; Sign-extend instructions.
 
 (define_expand "extendhisi2"
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
   ""
-  "
 {
   if (sext_operand (operands[1], HImode))
     emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));
   else
     xtensa_extend_reg (operands[0], operands[1]);
   DONE;
-}")
+})
 
 (define_insn "extendhisi2_internal"
   [(set (match_operand:SI 0 "register_operand" "=B,a")
 	(sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
   ""
   "@
-   sext\\t%0, %1, 15
-   l16si\\t%0, %1"
+   sext\t%0, %1, 15
+   l16si\t%0, %1"
   [(set_attr "type"	"arith,load")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -764,34 +663,25 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
   ""
-  "
 {
   if (TARGET_SEXT)
-    {
-      emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
-      DONE;
-    }
-  xtensa_extend_reg (operands[0], operands[1]);
+    emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
+  else
+    xtensa_extend_reg (operands[0], operands[1]);
   DONE;
-}")
+})
 
 (define_insn "extendqisi2_internal"
   [(set (match_operand:SI 0 "register_operand" "=B")
 	(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
   "TARGET_SEXT"
-  "sext\\t%0, %1, 7"
+  "sext\t%0, %1, 7"
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	FIELD EXTRACT
-;;
-;;  ....................
-;;
+
+;; Field extract instructions.
 
 (define_expand "extv"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -799,16 +689,19 @@
 			 (match_operand:SI 2 "const_int_operand" "")
 			 (match_operand:SI 3 "const_int_operand" "")))]
   "TARGET_SEXT"
-  "
 {
-  if (!sext_fldsz_operand (operands[2], SImode)) FAIL;
-  /* we could expand to a right shift followed by sext but that's
-     no better than the standard left and right shift sequence */
-  if (!lsbitnum_operand (operands[3], SImode)) FAIL;
+  if (!sext_fldsz_operand (operands[2], SImode))
+    FAIL;
+
+  /* We could expand to a right shift followed by SEXT but that's
+     no better than the standard left and right shift sequence.  */
+  if (!lsbitnum_operand (operands[3], SImode))
+    FAIL;
+
   emit_insn (gen_extv_internal (operands[0], operands[1],
 				operands[2], operands[3]));
   DONE;
-}")
+})
 
 (define_insn "extv_internal"
   [(set (match_operand:SI 0 "register_operand" "=a")
@@ -816,12 +709,11 @@
 			 (match_operand:SI 2 "sext_fldsz_operand" "i")
 			 (match_operand:SI 3 "lsbitnum_operand" "i")))]
   "TARGET_SEXT"
-  "*
 {
   int fldsz = INTVAL (operands[2]);
   operands[2] = GEN_INT (fldsz - 1);
-  return \"sext\\t%0, %1, %2\";
-}"
+  return "sext\t%0, %1, %2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -832,13 +724,13 @@
 			 (match_operand:SI 2 "const_int_operand" "")
 			 (match_operand:SI 3 "const_int_operand" "")))]
   ""
-  "
 {
-  if (!extui_fldsz_operand (operands[2], SImode)) FAIL;
+  if (!extui_fldsz_operand (operands[2], SImode))
+    FAIL;
   emit_insn (gen_extzv_internal (operands[0], operands[1],
 				 operands[2], operands[3]));
   DONE;
-}")
+})
 
 (define_insn "extzv_internal"
   [(set (match_operand:SI 0 "register_operand" "=a")
@@ -846,7 +738,6 @@
 			 (match_operand:SI 2 "extui_fldsz_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i")))]
   ""
-  "*
 {
   int shift;
   if (BITS_BIG_ENDIAN)
@@ -854,26 +745,20 @@
   else
     shift = INTVAL (operands[3]) & 0x1f;
   operands[3] = GEN_INT (shift);
-  return \"extui\\t%0, %1, %3, %2\";
-}"
+  return "extui\t%0, %1, %3, %2";
+}
   [(set_attr "type"	"arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	CONVERSIONS
-;;
-;;  ....................
-;;
+
+;; Conversions.
 
 (define_insn "fix_truncsfsi2"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "trunc.s\\t%0, %1, 0"
+  "trunc.s\t%0, %1, 0"
   [(set_attr "type"	"fconv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -882,7 +767,7 @@
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "utrunc.s %0, %1, 0"
+  "utrunc.s\t%0, %1, 0"
   [(set_attr "type"	"fconv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -891,7 +776,7 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(float:SF (match_operand:SI 1 "register_operand" "a")))]
   "TARGET_HARD_FLOAT"
-  "float.s\\t%0, %1, 0"
+  "float.s\t%0, %1, 0"
   [(set_attr "type"	"fconv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -900,19 +785,13 @@
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(unsigned_float:SF (match_operand:SI 1 "register_operand" "a")))]
   "TARGET_HARD_FLOAT"
-  "ufloat.s %0, %1, 0"
+  "ufloat.s\t%0, %1, 0"
   [(set_attr "type"	"fconv")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	DATA MOVEMENT
-;;
-;;  ....................
-;;
+
+;; Data movement instructions.
 
 ;; 64-bit Integer moves
 
@@ -920,7 +799,6 @@
   [(set (match_operand:DI 0 "nonimmed_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
   ""
-  "
 {
   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
     operands[1] = force_const_mem (DImode, operands[1]);
@@ -931,7 +809,7 @@
 
   if (xtensa_copy_incoming_a7 (operands, DImode))
     DONE;
-}")
+})
 
 (define_insn_and_split "movdi_internal"
   [(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
@@ -952,39 +830,37 @@
     }
 })
 
-
 ;; 32-bit Integer moves
 
 (define_expand "movsi"
   [(set (match_operand:SI 0 "nonimmed_operand" "")
 	(match_operand:SI 1 "general_operand" ""))]
   ""
-  "
 {
   if (xtensa_emit_move_sequence (operands, SImode))
     DONE;
-}")
+})
 
 (define_insn "movsi_internal"
   [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,W,a,a,U,*a,*A")
 	(match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,i,T,U,r,*A,*r"))]
   "xtensa_valid_move (SImode, operands)"
   "@
-   movi.n\\t%0, %x1
-   mov.n\\t%0, %1
-   mov.n\\t%0, %1
-   %v1l32i.n\\t%0, %1
-   %v0s32i.n\\t%1, %0
-   %v0s32i.n\\t%1, %0
-   mov\\t%0, %1
-   movsp\\t%0, %1
-   movi\\t%0, %x1
-   const16\\t%0, %t1\;const16\\t%0, %b1
-   %v1l32r\\t%0, %1
-   %v1l32i\\t%0, %1
-   %v0s32i\\t%1, %0
-   rsr\\t%0, 16 # ACCLO
-   wsr\\t%1, 16 # ACCLO"
+   movi.n\t%0, %x1
+   mov.n\t%0, %1
+   mov.n\t%0, %1
+   %v1l32i.n\t%0, %1
+   %v0s32i.n\t%1, %0
+   %v0s32i.n\t%1, %0
+   mov\t%0, %1
+   movsp\t%0, %1
+   movi\t%0, %x1
+   const16\t%0, %t1\;const16\t%0, %b1
+   %v1l32r\t%0, %1
+   %v1l32i\t%0, %1
+   %v0s32i\t%1, %0
+   rsr\t%0, 16 # ACCLO
+   wsr\t%1, 16 # ACCLO"
   [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,load,load,store,rsr,wsr")
    (set_attr "mode"	"SI")
    (set_attr "length"	"2,2,2,2,2,2,3,3,3,6,3,3,3,3,3")])
@@ -995,25 +871,24 @@
   [(set (match_operand:HI 0 "nonimmed_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
   ""
-  "
 {
   if (xtensa_emit_move_sequence (operands, HImode))
     DONE;
-}")
+})
 
 (define_insn "movhi_internal"
   [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 	(match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
   "xtensa_valid_move (HImode, operands)"
   "@
-   movi.n\\t%0, %x1
-   mov.n\\t%0, %1
-   mov\\t%0, %1
-   movi\\t%0, %x1
-   %v1l16ui\\t%0, %1
-   %v0s16i\\t%1, %0
-   rsr\\t%0, 16 # ACCLO
-   wsr\\t%1, 16 # ACCLO"
+   movi.n\t%0, %x1
+   mov.n\t%0, %1
+   mov\t%0, %1
+   movi\t%0, %x1
+   %v1l16ui\t%0, %1
+   %v0s16i\t%1, %0
+   rsr\t%0, 16 # ACCLO
+   wsr\t%1, 16 # ACCLO"
   [(set_attr "type"	"move,move,move,move,load,store,rsr,wsr")
    (set_attr "mode"	"HI")
    (set_attr "length"	"2,2,3,3,3,3,3,3")])
@@ -1024,25 +899,24 @@
   [(set (match_operand:QI 0 "nonimmed_operand" "")
 	(match_operand:QI 1 "general_operand" ""))]
   ""
-  "
 {
   if (xtensa_emit_move_sequence (operands, QImode))
     DONE;
-}")
+})
 
 (define_insn "movqi_internal"
   [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 	(match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
   "xtensa_valid_move (QImode, operands)"
   "@
-   movi.n\\t%0, %x1
-   mov.n\\t%0, %1
-   mov\\t%0, %1
-   movi\\t%0, %x1
-   %v1l8ui\\t%0, %1
-   %v0s8i\\t%1, %0
-   rsr\\t%0, 16 # ACCLO
-   wsr\\t%1, 16 # ACCLO"
+   movi.n\t%0, %x1
+   mov.n\t%0, %1
+   mov\t%0, %1
+   movi\t%0, %x1
+   %v1l8ui\t%0, %1
+   %v0s8i\t%1, %0
+   rsr\t%0, 16 # ACCLO
+   wsr\t%1, 16 # ACCLO"
   [(set_attr "type"	"move,move,move,move,load,store,rsr,wsr")
    (set_attr "mode"	"QI")
    (set_attr "length"	"2,2,3,3,3,3,3,3")])
@@ -1053,7 +927,6 @@
   [(set (match_operand:SF 0 "nonimmed_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
   ""
-  "
 {
   if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
     operands[1] = force_const_mem (SFmode, operands[1]);
@@ -1070,7 +943,7 @@
       if (xtensa_copy_incoming_a7 (operands, SFmode))
 	DONE;
     }
-}")
+})
 
 (define_insn "movsf_internal"
   [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,W,a,a,U")
@@ -1080,19 +953,19 @@
     && !(FP_REG_P (xt_true_regnum (operands[0]))
          && (constantpool_mem_p (operands[1]) || CONSTANT_P (operands[1]))))"
   "@
-   mov.s\\t%0, %1
-   %v1lsi\\t%0, %1
-   %v0ssi\\t%1, %0
-   mov.n\\t%0, %1
-   %v1l32i.n\\t%0, %1
-   %v0s32i.n\\t%1, %0
-   mov\\t%0, %1
-   wfr\\t%0, %1
-   rfr\\t%0, %1
-   const16\\t%0, %t1\;const16\\t%0, %b1
-   %v1l32r\\t%0, %1
-   %v1l32i\\t%0, %1
-   %v0s32i\\t%1, %0"
+   mov.s\t%0, %1
+   %v1lsi\t%0, %1
+   %v0ssi\t%1, %0
+   mov.n\t%0, %1
+   %v1l32i.n\t%0, %1
+   %v0s32i.n\t%1, %0
+   mov\t%0, %1
+   wfr\t%0, %1
+   rfr\t%0, %1
+   const16\t%0, %t1\;const16\t%0, %b1
+   %v1l32r\t%0, %1
+   %v1l32i\t%0, %1
+   %v0s32i\t%1, %0"
   [(set_attr "type"	"farith,fload,fstore,move,load,store,move,farith,farith,move,load,load,store")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3,3,3,2,2,2,3,3,3,6,3,3,3")])
@@ -1104,12 +977,11 @@
    (set (match_dup 1)
 	(plus:SI (match_dup 1) (match_dup 2)))]
   "TARGET_HARD_FLOAT"
-  "*
 {
   if (volatile_refs_p (PATTERN (insn)))
-    output_asm_insn (\"memw\", operands);
-  return \"lsiu\\t%0, %1, %2\";
-}"
+    output_asm_insn ("memw", operands);
+  return "lsiu\t%0, %1, %2";
+}
   [(set_attr "type"	"fload")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -1121,12 +993,11 @@
    (set (match_dup 0)
 	(plus:SI (match_dup 0) (match_dup 1)))]
   "TARGET_HARD_FLOAT"
-  "*
 {
   if (volatile_refs_p (PATTERN (insn)))
-    output_asm_insn (\"memw\", operands);
-  return \"ssiu\\t%2, %0, %1\";
-}"
+    output_asm_insn ("memw", operands);
+  return "ssiu\t%2, %0, %1";
+}
   [(set_attr "type"	"fstore")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3")])
@@ -1137,7 +1008,6 @@
   [(set (match_operand:DF 0 "nonimmed_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
   ""
-  "
 {
   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
     operands[1] = force_const_mem (DFmode, operands[1]);
@@ -1148,7 +1018,7 @@
 
   if (xtensa_copy_incoming_a7 (operands, DFmode))
     DONE;
-}")
+})
 
 (define_insn_and_split "movdf_internal"
   [(set (match_operand:DF 0 "nonimmed_operand" "=a,W,a,a,U")
@@ -1168,7 +1038,6 @@
       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
     }
 })
- 
 
 ;; Block moves
 
@@ -1178,11 +1047,11 @@
 	      (use (match_operand:SI 2 "arith_operand" ""))
 	      (use (match_operand:SI 3 "const_int_operand" ""))])]
   ""
-  "
 {
-  if (!xtensa_expand_block_move (operands)) FAIL;
+  if (!xtensa_expand_block_move (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_insn "movstrsi_internal"
   [(set (match_operand:BLK 0 "memory_operand" "=U")
@@ -1192,26 +1061,19 @@
    (clobber (match_scratch:SI 4 "=&r"))
    (clobber (match_scratch:SI 5 "=&r"))]
   ""
-  "*
 {
   rtx tmpregs[2];
   tmpregs[0] = operands[4];
   tmpregs[1] = operands[5];
   xtensa_emit_block_move (operands, tmpregs, 1);
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"multi")
    (set_attr "mode"	"none")
    (set_attr "length"	"300")])
 
-
-;;
-;;  ....................
-;;
-;;	SHIFTS
-;;
-;;  ....................
-;;
+
+;; Shift instructions.
 
 (define_insn "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
@@ -1219,8 +1081,8 @@
 		   (match_operand:SI 2 "arith_operand" "J,r")))]
   ""      
   "@
-   slli\\t%0, %1, %R2
-   ssl\\t%2\;sll\\t%0, %1"
+   slli\t%0, %1, %R2
+   ssl\t%2\;sll\t%0, %1"
   [(set_attr "type"	"arith,arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
@@ -1231,8 +1093,8 @@
 		     (match_operand:SI 2 "arith_operand" "J,r")))]
   ""
   "@
-   srai\\t%0, %1, %R2
-   ssr\\t%2\;sra\\t%0, %1"
+   srai\t%0, %1, %R2
+   ssr\t%2\;sra\t%0, %1"
   [(set_attr "type"	"arith,arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
@@ -1242,17 +1104,16 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
 		     (match_operand:SI 2 "arith_operand" "J,r")))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
       if ((INTVAL (operands[2]) & 0x1f) < 16)
-        return \"srli\\t%0, %1, %R2\";
+        return "srli\t%0, %1, %R2";
       else
-      	return \"extui\\t%0, %1, %R2, %L2\";
+      	return "extui\t%0, %1, %R2, %L2";
     }
-  return \"ssr\\t%2\;srl\\t%0, %1\";
-}"
+  return "ssr\t%2\;srl\t%0, %1";
+}
   [(set_attr "type"	"arith,arith")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,6")])
@@ -1263,8 +1124,8 @@
 		     (match_operand:SI 2 "arith_operand" "J,r")))]
   ""
   "@
-   ssai\\t%L2\;src\\t%0, %1, %1
-   ssl\\t%2\;src\\t%0, %1, %1"
+   ssai\t%L2\;src\t%0, %1, %1
+   ssl\t%2\;src\t%0, %1, %1"
   [(set_attr "type"	"multi,multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"6,6")])
@@ -1275,71 +1136,55 @@
 		     (match_operand:SI 2 "arith_operand" "J,r")))]
   ""
   "@
-   ssai\\t%R2\;src\\t%0, %1, %1
-   ssr\\t%2\;src\\t%0, %1, %1"
+   ssai\t%R2\;src\t%0, %1, %1
+   ssr\t%2\;src\t%0, %1, %1"
   [(set_attr "type"	"multi,multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"6,6")])
 
+
+;; Comparisons.
 
-;;
-;;  ....................
-;;
-;;	COMPARISONS
-;;
-;;  ....................
-;;
-
-;; Like the md files for MIPS and SPARC, we handle comparisons by stashing
-;; away the operands and then using that information in the subsequent
-;; conditional branch.
+;; Handle comparisons by stashing away the operands and then using that
+;; information in the subsequent conditional branch.
 
 (define_expand "cmpsi"
   [(set (cc0)
 	(compare:CC (match_operand:SI 0 "register_operand" "")
 		    (match_operand:SI 1 "nonmemory_operand" "")))]
   ""
-  "
 {
   branch_cmp[0] = operands[0];
   branch_cmp[1] = operands[1];
   branch_type = CMP_SI;
   DONE;
-}")
+})
 
 (define_expand "tstsi"
   [(set (cc0)
 	(match_operand:SI 0 "register_operand" ""))]
   ""
-  "
 {
   branch_cmp[0] = operands[0];
   branch_cmp[1] = const0_rtx;
   branch_type = CMP_SI;
   DONE;
-}")
+})
 
 (define_expand "cmpsf"
   [(set (cc0)
 	(compare:CC (match_operand:SF 0 "register_operand" "")
 		    (match_operand:SF 1 "register_operand" "")))]
   "TARGET_HARD_FLOAT"
-  "
 {
   branch_cmp[0] = operands[0];
   branch_cmp[1] = operands[1];
   branch_type = CMP_SF;
   DONE;
-}")
-
+})
 
-;;
-;;  ....................
-;;
-;;	CONDITIONAL BRANCHES
-;;
-;;  ....................
-;;
+
+;; Conditional branches.
 
 (define_expand "beq"
   [(set (pc)
@@ -1347,11 +1192,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, EQ);
   DONE;
-}")
+})
 
 (define_expand "bne"
   [(set (pc)
@@ -1359,11 +1203,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, NE);
   DONE;
-}")
+})
 
 (define_expand "bgt"
   [(set (pc)
@@ -1371,11 +1214,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, GT);
   DONE;
-}")
+})
 
 (define_expand "bge"
   [(set (pc)
@@ -1383,11 +1225,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, GE);
   DONE;
-}")
+})
 
 (define_expand "blt"
   [(set (pc)
@@ -1395,11 +1236,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, LT);
   DONE;
-}")
+})
 
 (define_expand "ble"
   [(set (pc)
@@ -1407,11 +1247,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, LE);
   DONE;
-}")
+})
 
 (define_expand "bgtu"
   [(set (pc)
@@ -1419,11 +1258,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, GTU);
   DONE;
-}")
+})
 
 (define_expand "bgeu"
   [(set (pc)
@@ -1431,11 +1269,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, GEU);
   DONE;
-}")
+})
 
 (define_expand "bltu"
   [(set (pc)
@@ -1443,11 +1280,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, LTU);
   DONE;
-}")
+})
 
 (define_expand "bleu"
   [(set (pc)
@@ -1455,11 +1291,10 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "
 {
   xtensa_expand_conditional_branch (operands, LEU);
   DONE;
-}")
+})
 
 ;; Branch patterns for standard integer comparisons
 
@@ -1471,16 +1306,15 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   if (which_alternative == 1)
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"beq\\t%0, %1, %2\";
-	case NE:	return \"bne\\t%0, %1, %2\";
-	case LT:	return \"blt\\t%0, %1, %2\";
-	case GE:	return \"bge\\t%0, %1, %2\";
+	case EQ:	return "beq\t%0, %1, %2";
+	case NE:	return "bne\t%0, %1, %2";
+	case LT:	return "blt\t%0, %1, %2";
+	case GE:	return "bge\t%0, %1, %2";
 	default:	break;
 	}
     }
@@ -1489,13 +1323,13 @@
       switch (GET_CODE (operands[3]))
 	{
 	case EQ:	return (TARGET_DENSITY
-				? \"beqz.n\\t%0, %2\"
-				: \"beqz\\t%0, %2\");
+				? "beqz.n\t%0, %2"
+				: "beqz\t%0, %2");
 	case NE:	return (TARGET_DENSITY
-				? \"bnez.n\\t%0, %2\"
-				: \"bnez\\t%0, %2\");
-	case LT:	return \"bltz\\t%0, %2\";
-	case GE:	return \"bgez\\t%0, %2\";
+				? "bnez.n\t%0, %2"
+				: "bnez\t%0, %2");
+	case LT:	return "bltz\t%0, %2";
+	case GE:	return "bgez\t%0, %2";
 	default:	break;
 	}
     }
@@ -1503,16 +1337,16 @@
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"beqi\\t%0, %d1, %2\";
-	case NE:	return \"bnei\\t%0, %d1, %2\";
-	case LT:	return \"blti\\t%0, %d1, %2\";
-	case GE:	return \"bgei\\t%0, %d1, %2\";
+	case EQ:	return "beqi\t%0, %d1, %2";
+	case NE:	return "bnei\t%0, %d1, %2";
+	case LT:	return "blti\t%0, %d1, %2";
+	case GE:	return "bgei\t%0, %d1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump,jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3,3")])
@@ -1525,16 +1359,15 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   if (which_alternative == 1)
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"bne\\t%0, %1, %2\";
-	case NE:	return \"beq\\t%0, %1, %2\";
-	case LT:	return \"bge\\t%0, %1, %2\";
-	case GE:	return \"blt\\t%0, %1, %2\";
+	case EQ:	return "bne\t%0, %1, %2";
+	case NE:	return "beq\t%0, %1, %2";
+	case LT:	return "bge\t%0, %1, %2";
+	case GE:	return "blt\t%0, %1, %2";
 	default:	break;
 	}
     }
@@ -1543,13 +1376,13 @@
       switch (GET_CODE (operands[3]))
 	{
 	case EQ:	return (TARGET_DENSITY
-				? \"bnez.n\\t%0, %2\"
-				: \"bnez\\t%0, %2\");
+				? "bnez.n\t%0, %2"
+				: "bnez\t%0, %2");
 	case NE:	return (TARGET_DENSITY
-				? \"beqz.n\\t%0, %2\"
-				: \"beqz\\t%0, %2\");
-	case LT:	return \"bgez\\t%0, %2\";
-	case GE:	return \"bltz\\t%0, %2\";
+				? "beqz.n\t%0, %2"
+				: "beqz\t%0, %2");
+	case LT:	return "bgez\t%0, %2";
+	case GE:	return "bltz\t%0, %2";
 	default:	break;
 	}
     }
@@ -1557,16 +1390,16 @@
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"bnei\\t%0, %d1, %2\";
-	case NE:	return \"beqi\\t%0, %d1, %2\";
-	case LT:	return \"bgei\\t%0, %d1, %2\";
-	case GE:	return \"blti\\t%0, %d1, %2\";
+	case EQ:	return "bnei\t%0, %d1, %2";
+	case NE:	return "beqi\t%0, %d1, %2";
+	case LT:	return "bgei\t%0, %d1, %2";
+	case GE:	return "blti\t%0, %d1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump,jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3,3")])
@@ -1579,14 +1412,13 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   if (which_alternative == 1)
     {
       switch (GET_CODE (operands[3]))
 	{
-	case LTU:	return \"bltu\\t%0, %1, %2\";
-	case GEU:	return \"bgeu\\t%0, %1, %2\";
+	case LTU:	return "bltu\t%0, %1, %2";
+	case GEU:	return "bgeu\t%0, %1, %2";
 	default:	break;
 	}
     }
@@ -1594,14 +1426,14 @@
     {
       switch (GET_CODE (operands[3]))
 	{
-	case LTU:	return \"bltui\\t%0, %d1, %2\";
-	case GEU:	return \"bgeui\\t%0, %d1, %2\";
+	case LTU:	return "bltui\t%0, %d1, %2";
+	case GEU:	return "bgeui\t%0, %d1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump,jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3,3")])
@@ -1614,14 +1446,13 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   if (which_alternative == 1)
     {
       switch (GET_CODE (operands[3]))
 	{
-	case LTU:	return \"bgeu\\t%0, %1, %2\";
-	case GEU:	return \"bltu\\t%0, %1, %2\";
+	case LTU:	return "bgeu\t%0, %1, %2";
+	case GEU:	return "bltu\t%0, %1, %2";
 	default:	break;
 	}
     }
@@ -1629,14 +1460,14 @@
     {
       switch (GET_CODE (operands[3]))
 	{
-	case LTU:	return \"bgeui\\t%0, %d1, %2\";
-	case GEU:	return \"bltui\\t%0, %d1, %2\";
+	case LTU:	return "bgeui\t%0, %d1, %2";
+	case GEU:	return "bltui\t%0, %d1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump,jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3,3")])
@@ -1654,7 +1485,6 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
@@ -1662,8 +1492,8 @@
       operands[1] = GEN_INT(bitnum);
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"bbci\\t%0, %d1, %2\";
-	case NE:	return \"bbsi\\t%0, %d1, %2\";
+	case EQ:	return "bbci\t%0, %d1, %2";
+	case NE:	return "bbsi\t%0, %d1, %2";
 	default:	break;
 	}
     }
@@ -1671,14 +1501,14 @@
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"bbc\\t%0, %1, %2\";
-	case NE:	return \"bbs\\t%0, %1, %2\";
+	case EQ:	return "bbc\t%0, %1, %2";
+	case NE:	return "bbs\t%0, %1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -1694,7 +1524,6 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
@@ -1702,23 +1531,23 @@
       operands[1] = GEN_INT (bitnum);
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:    return \"bbsi\\t%0, %d1, %2\";
-	case NE:    return \"bbci\\t%0, %d1, %2\";
-	default:    break;
+	case EQ:	return "bbsi\t%0, %d1, %2";
+	case NE:	return "bbci\t%0, %d1, %2";
+	default:	break;
 	}
     }
   else
     {
       switch (GET_CODE (operands[3]))
 	{
-	case EQ:	return \"bbs\\t%0, %1, %2\";
-	case NE:	return \"bbc\\t%0, %1, %2\";
+	case EQ:	return "bbs\t%0, %1, %2";
+	case NE:	return "bbc\t%0, %1, %2";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -1732,17 +1561,16 @@
 		      (label_ref (match_operand 2 "" ""))
 		      (pc)))]
   ""
-  "*
 {
   switch (GET_CODE (operands[3]))
     {
-    case EQ:	return \"bnone\\t%0, %1, %2\";
-    case NE:	return \"bany\\t%0, %1, %2\";
-    default:	break;
+    case EQ:		return "bnone\t%0, %1, %2";
+    case NE:		return "bany\t%0, %1, %2";
+    default:		break;
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -1756,138 +1584,127 @@
 		      (pc)
 		      (label_ref (match_operand 2 "" ""))))]
   ""
-  "*
 {
   switch (GET_CODE (operands[3]))
     {
-    case EQ:	return \"bany\\t%0, %1, %2\";
-    case NE:	return \"bnone\\t%0, %1, %2\";
-    default:	break;
+    case EQ:		return "bany\t%0, %1, %2";
+    case NE:		return "bnone\t%0, %1, %2";
+    default:		break;
     }
-  fatal_insn (\"unexpected branch operator\", operands[3]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
 
 
-;; Define the loop insns that is used by bct optimization to represent the
-;; start and end of a zero-overhead loop (in loop.c). This start template
-;; generates the loop insn, the end template doesn't generate any instructions
-;; since since loop end is handled in hardware.
+;; Define the loop insns used by bct optimization to represent the
+;; start and end of a zero-overhead loop (in loop.c).  This start
+;; template generates the loop insn; the end template doesn't generate
+;; any instructions since loop end is handled in hardware.
 
 (define_insn "zero_cost_loop_start"
-  [(set (pc) (if_then_else (eq (match_operand:SI 0 "register_operand" "a")
-			       (const_int 0))
-			   (label_ref (match_operand 1 "" ""))
-			   (pc)))
+  [(set (pc)
+	(if_then_else (eq (match_operand:SI 0 "register_operand" "a")
+			  (const_int 0))
+		      (label_ref (match_operand 1 "" ""))
+		      (pc)))
    (set (reg:SI 19)
 	(plus:SI (match_dup 0) (const_int -1)))]
   ""
-  "loopnez %0, %l1"
+  "loopnez\t%0, %l1"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
 
 (define_insn "zero_cost_loop_end"
-  [(set (pc) (if_then_else (ne (reg:SI 19) (const_int 0))
-			   (label_ref (match_operand 0 "" ""))
-			   (pc)))
+  [(set (pc)
+	(if_then_else (ne (reg:SI 19) (const_int 0))
+		      (label_ref (match_operand 0 "" ""))
+		      (pc)))
    (set (reg:SI 19)
 	(plus:SI (reg:SI 19) (const_int -1)))]
   ""
-  "*
+{
     xtensa_emit_loop_end (insn, operands);
-    return \"\";
-  "
+    return "";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"0")])
 
-
-;;
-;;  ....................
-;;
-;;	SETTING A REGISTER FROM A COMPARISON
-;;
-;;  ....................
-;;
+
+;; Setting a register from a comparison.
 
 (define_expand "seq"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (EQ, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "sne"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (NE, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "sgt"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (GT, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "sge"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (GE, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "slt"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (LT, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "sle"
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_dup 1))]
   ""
-  "
 {
   operands[1] = gen_rtx (LE, SImode, branch_cmp[0], branch_cmp[1]);
-  if (!xtensa_expand_scc (operands)) FAIL;
+  if (!xtensa_expand_scc (operands))
+    FAIL;
   DONE;
-}")
-
+})
 
-;;
-;;  ....................
-;;
-;;	CONDITIONAL MOVES
-;;
-;;  ....................
-;;
+
+;; Conditional moves.
 
 (define_expand "movsicc"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -1895,11 +1712,11 @@
 			 (match_operand:SI 2 "register_operand" "")
 			 (match_operand:SI 3 "register_operand" "")))]
   ""
-  "
 {
-  if (!xtensa_expand_conditional_move (operands, 0)) FAIL;
+  if (!xtensa_expand_conditional_move (operands, 0))
+    FAIL;
   DONE;
-}")
+})
 
 (define_expand "movsfcc"
   [(set (match_operand:SF 0 "register_operand" "")
@@ -1907,11 +1724,11 @@
 			 (match_operand:SF 2 "register_operand" "")
 			 (match_operand:SF 3 "register_operand" "")))]
   ""
-  "
 {
-  if (!xtensa_expand_conditional_move (operands, 1)) FAIL;
+  if (!xtensa_expand_conditional_move (operands, 1))
+    FAIL;
   DONE;
-}")
+})
 
 (define_insn "movsicc_internal0"
   [(set (match_operand:SI 0 "register_operand" "=a,a")
@@ -1921,16 +1738,15 @@
 			 (match_operand:SI 2 "register_operand" "r,0")
 			 (match_operand:SI 3 "register_operand" "0,r")))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"moveqz\\t%0, %2, %1\";
-	case NE:	return \"movnez\\t%0, %2, %1\";
-	case LT:	return \"movltz\\t%0, %2, %1\";
-	case GE:	return \"movgez\\t%0, %2, %1\";
+	case EQ:	return "moveqz\t%0, %2, %1";
+	case NE:	return "movnez\t%0, %2, %1";
+	case LT:	return "movltz\t%0, %2, %1";
+	case GE:	return "movgez\t%0, %2, %1";
 	default:	break;
 	}
     }
@@ -1938,16 +1754,16 @@
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"movnez\\t%0, %3, %1\";
-	case NE:	return \"moveqz\\t%0, %3, %1\";
-	case LT:	return \"movgez\\t%0, %3, %1\";
-	case GE:	return \"movltz\\t%0, %3, %1\";
+	case EQ:	return "movnez\t%0, %3, %1";
+	case NE:	return "moveqz\t%0, %3, %1";
+	case LT:	return "movgez\t%0, %3, %1";
+	case GE:	return "movltz\t%0, %3, %1";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected cmov operator\", operands[4]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"move,move")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -1960,21 +1776,20 @@
 			 (match_operand:SI 2 "register_operand" "r,0")
 			 (match_operand:SI 3 "register_operand" "0,r")))]
   "TARGET_BOOLEANS"
-  "*
 {
   int isEq = (GET_CODE (operands[4]) == EQ);
   switch (which_alternative)
     {
     case 0:
-      if (isEq) return \"movf\\t%0, %2, %1\";
-      return \"movt\\t%0, %2, %1\";
+      if (isEq) return "movf\t%0, %2, %1";
+      return "movt\t%0, %2, %1";
     case 1:
-      if (isEq) return \"movt\\t%0, %3, %1\";
-      return \"movf\\t%0, %3, %1\";
+      if (isEq) return "movt\t%0, %3, %1";
+      return "movf\t%0, %3, %1";
     }
   abort ();
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"move,move")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3,3")])
@@ -1987,16 +1802,15 @@
 			 (match_operand:SF 2 "register_operand" "r,0,f,0")
 			 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
   ""
-  "*
 {
   if (which_alternative == 0)
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"moveqz\\t%0, %2, %1\";
-	case NE:	return \"movnez\\t%0, %2, %1\";
-	case LT:	return \"movltz\\t%0, %2, %1\";
-	case GE:	return \"movgez\\t%0, %2, %1\";
+	case EQ:	return "moveqz\t%0, %2, %1";
+	case NE:	return "movnez\t%0, %2, %1";
+	case LT:	return "movltz\t%0, %2, %1";
+	case GE:	return "movgez\t%0, %2, %1";
 	default:	break;
 	}
     }
@@ -2004,10 +1818,10 @@
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"movnez\\t%0, %3, %1\";
-	case NE:	return \"moveqz\\t%0, %3, %1\";
-	case LT:	return \"movgez\\t%0, %3, %1\";
-	case GE:	return \"movltz\\t%0, %3, %1\";
+	case EQ:	return "movnez\t%0, %3, %1";
+	case NE:	return "moveqz\t%0, %3, %1";
+	case LT:	return "movgez\t%0, %3, %1";
+	case GE:	return "movltz\t%0, %3, %1";
 	default:	break;
 	}
     }
@@ -2015,10 +1829,10 @@
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"moveqz.s %0, %2, %1\";
-	case NE:	return \"movnez.s %0, %2, %1\";
-	case LT:	return \"movltz.s %0, %2, %1\";
-	case GE:	return \"movgez.s %0, %2, %1\";
+	case EQ:	return "moveqz.s %0, %2, %1";
+	case NE:	return "movnez.s %0, %2, %1";
+	case LT:	return "movltz.s %0, %2, %1";
+	case GE:	return "movgez.s %0, %2, %1";
 	default:	break;
 	}
     }
@@ -2026,16 +1840,16 @@
     {
       switch (GET_CODE (operands[4]))
 	{
-	case EQ:	return \"movnez.s %0, %3, %1\";
-	case NE:	return \"moveqz.s %0, %3, %1\";
-	case LT:	return \"movgez.s %0, %3, %1\";
-	case GE:	return \"movltz.s %0, %3, %1\";
+	case EQ:	return "movnez.s %0, %3, %1";
+	case NE:	return "moveqz.s %0, %3, %1";
+	case LT:	return "movgez.s %0, %3, %1";
+	case GE:	return "movltz.s %0, %3, %1";
 	default:	break;
 	}
     }
-  fatal_insn (\"unexpected cmov operator\", operands[4]);
-  return \"\";
-}"
+  abort ();
+  return "";
+}
   [(set_attr "type"	"move,move,move,move")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3,3,3,3")])
@@ -2048,46 +1862,39 @@
 			 (match_operand:SF 2 "register_operand" "r,0,f,0")
 			 (match_operand:SF 3 "register_operand" "0,r,0,f")))]
   "TARGET_BOOLEANS"
-  "*
 {
   int isEq = (GET_CODE (operands[4]) == EQ);
   switch (which_alternative)
     {
     case 0:
-      if (isEq) return \"movf\\t%0, %2, %1\";
-      return \"movt\\t%0, %2, %1\";
+      if (isEq) return "movf\t%0, %2, %1";
+      return "movt\t%0, %2, %1";
     case 1:
-      if (isEq) return \"movt\\t%0, %3, %1\";
-      return \"movf\\t%0, %3, %1\";
+      if (isEq) return "movt\t%0, %3, %1";
+      return "movf\t%0, %3, %1";
     case 2:
-      if (isEq) return \"movf.s\\t%0, %2, %1\";
-      return \"movt.s\\t%0, %2, %1\";
+      if (isEq) return "movf.s\t%0, %2, %1";
+      return "movt.s\t%0, %2, %1";
     case 3:
-      if (isEq) return \"movt.s\\t%0, %3, %1\";
-      return \"movf.s\\t%0, %3, %1\";
+      if (isEq) return "movt.s\t%0, %3, %1";
+      return "movf.s\t%0, %3, %1";
     }
   abort ();
-  return \"\";
-}"
+  return "";
+}
   [(set_attr "type"	"move,move,move,move")
    (set_attr "mode"	"SF")
    (set_attr "length"	"3,3,3,3")])
 
-
-;;
-;;  ....................
-;;
-;;	FLOATING POINT COMPARISONS
-;;
-;;  ....................
-;;
+
+;; Floating-point comparisons.
 
 (define_insn "seq_sf"
   [(set (match_operand:CC 0 "register_operand" "=b")
 	(eq:CC (match_operand:SF 1 "register_operand" "f")
 	       (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "oeq.s\\t%0, %1, %2"
+  "oeq.s\t%0, %1, %2"
   [(set_attr "type"	"farith")
    (set_attr "mode"	"BL")
    (set_attr "length"	"3")])
@@ -2097,7 +1904,7 @@
 	(lt:CC (match_operand:SF 1 "register_operand" "f")
 	       (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "olt.s\\t%0, %1, %2"
+  "olt.s\t%0, %1, %2"
   [(set_attr "type"	"farith")
    (set_attr "mode"	"BL")
    (set_attr "length"	"3")])
@@ -2107,33 +1914,27 @@
 	(le:CC (match_operand:SF 1 "register_operand" "f")
 	       (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT"
-  "ole.s\\t%0, %1, %2"
+  "ole.s\t%0, %1, %2"
   [(set_attr "type"	"farith")
    (set_attr "mode"	"BL")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	UNCONDITIONAL BRANCHES
-;;
-;;  ....................
-;;
+
+;; Unconditional branches.
 
 (define_insn "jump"
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
   ""
-  "j\\t%l0"
+  "j\t%l0"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
 
 (define_expand "indirect_jump"
-  [(set (pc) (match_operand 0 "register_operand" ""))]
+  [(set (pc)
+	(match_operand 0 "register_operand" ""))]
   ""
-  "
 {
   rtx dest = operands[0];
   if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
@@ -2141,12 +1942,12 @@
 
   emit_jump_insn (gen_indirect_jump_internal (dest));
   DONE;
-}")
+})
 
 (define_insn "indirect_jump_internal"
   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
   ""
-  "jx\\t%0"
+  "jx\t%0"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -2156,12 +1957,11 @@
   [(use (match_operand:SI 0 "register_operand" ""))
    (use (label_ref (match_operand 1 "" "")))]
    ""
-   "
 {
   rtx target = operands[0];
   if (flag_pic)
     {
-      /* For PIC, the table entry is relative to the start of the table. */
+      /* For PIC, the table entry is relative to the start of the table.  */
       rtx label = gen_reg_rtx (SImode);
       target = gen_reg_rtx (SImode);
       emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
@@ -2169,26 +1969,20 @@
     }
   emit_jump_insn (gen_tablejump_internal (target, operands[1]));
   DONE;
-}")
+})
 
 (define_insn "tablejump_internal"
   [(set (pc)
 	(match_operand:SI 0 "register_operand" "r"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
-  "jx\\t%0"
+  "jx\t%0"
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
 
-
-;;
-;;  ....................
-;;
-;;	FUNCTION CALLS
-;;
-;;  ....................
-;;
+
+;; Function calls.
 
 (define_expand "sym_PLT"
   [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT))]
@@ -2199,22 +1993,21 @@
   [(call (match_operand 0 "memory_operand" "")
 	 (match_operand 1 "" ""))]
   ""
-  "
 {
   rtx addr = XEXP (operands[0], 0);
   if (flag_pic && GET_CODE (addr) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (addr))
     addr = gen_sym_PLT (addr);
   if (!call_insn_operand (addr, VOIDmode))
     XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
-}")
+})
 
 (define_insn "call_internal"
   [(call (mem (match_operand:SI 0 "call_insn_operand" "n,i,r"))
 	 (match_operand 1 "" "i,i,i"))]
   ""
-  "*
-    return xtensa_emit_call (0, operands);
-  "
+{
+  return xtensa_emit_call (0, operands);
+}
   [(set_attr "type"	"call")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -2224,19 +2017,18 @@
 	(call (match_operand 1 "memory_operand" "")
 	      (match_operand 2 "" "")))]
   ""
-  "
 {
   rtx addr = XEXP (operands[1], 0);
   if (flag_pic && GET_CODE (addr) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (addr))
     addr = gen_sym_PLT (addr);
   if (!call_insn_operand (addr, VOIDmode))
     XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
-}")
+})
 
-;; cannot combine constraints for operand 0 into "afvb"
+;; Cannot combine constraints for operand 0 into "afvb":
 ;; reload.c:find_reloads seems to assume that grouped constraints somehow
 ;; specify related register classes, and when they don't the constraints
-;; fail to match. By not grouping the constraints, we get the correct
+;; fail to match.  By not grouping the constraints, we get the correct
 ;; behavior.
 (define_insn "call_value_internal"
    [(set (match_operand 0 "register_operand" "=af,af,af,v,v,v,b,b,b")
@@ -2244,9 +2036,9 @@
 					"n,i,r,n,i,r,n,i,r"))
                (match_operand 2 "" "i,i,i,i,i,i,i,i,i")))]
   ""
-  "*
-    return xtensa_emit_call (1, operands);
-  "
+{
+  return xtensa_emit_call (1, operands);
+}
   [(set_attr "type"	"call")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -2257,14 +2049,13 @@
 			     (match_operand:SI 1 "const_int_operand" "i")]
 			    UNSPECV_ENTRY))]
   ""
-  "*
 {
   if (frame_pointer_needed)
-    output_asm_insn (\".frame\\ta7, %0\", operands);
+    output_asm_insn (".frame\ta7, %0", operands);
   else
-    output_asm_insn (\".frame\\tsp, %0\", operands);
-  return \"entry\\tsp, %1\";
-}"
+    output_asm_insn (".frame\tsp, %0", operands);
+  return "entry\tsp, %1";
+}
   [(set_attr "type"	"move")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -2273,48 +2064,38 @@
   [(return)
    (use (reg:SI A0_REG))]
   "reload_completed"
-  "*
 {
-  return (TARGET_DENSITY ? \"retw.n\" : \"retw\");
-}"
+  return (TARGET_DENSITY ? "retw.n" : "retw");
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"2")])
 
-
-;;
-;;  ....................
-;;
-;;	MISC.
-;;
-;;  ....................
-;;
+
+;; Miscellaneous instructions.
 
 (define_expand "prologue"
   [(const_int 0)]
   ""
-  "
 {
   xtensa_expand_prologue ();
   DONE;
-}")
+})
 
 (define_expand "epilogue"
   [(return)]
   ""
-  "
 {
   emit_jump_insn (gen_return ());
   DONE;
-}")
+})
 
 (define_insn "nop"
   [(const_int 0)]
   ""
-  "*
 {
-  return (TARGET_DENSITY ? \"nop.n\" : \"nop\");
-}"
+  return (TARGET_DENSITY ? "nop.n" : "nop");
+}
   [(set_attr "type"	"nop")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -2325,16 +2106,15 @@
    (match_operand:SI 2 "general_operand" "")
    (match_operand:SI 3 "" "")]
   ""
-  "
 {
   xtensa_expand_nonlocal_goto (operands);
   DONE;
-}")
+})
 
 ;; Setting up a frame pointer is tricky for Xtensa because GCC doesn't
 ;; know if a frame pointer is required until the reload pass, and
 ;; because there may be an incoming argument value in the hard frame
-;; pointer register (a7). If there is an incoming argument in that
+;; pointer register (a7).  If there is an incoming argument in that
 ;; register, the "set_frame_ptr" insn gets inserted immediately after
 ;; the insn that copies the incoming argument to a pseudo or to the
 ;; stack.  This serves several purposes here: (1) it keeps the
@@ -2342,19 +2122,18 @@
 ;; incoming argument away from the beginning of the function; (2) we
 ;; can use a post-reload splitter to expand away the insn if a frame
 ;; pointer is not required, so that the post-reload scheduler can do
-;; the right thing; and (3) it makes it easy for xtensa_reorg() to
-;; search for this insn to determine whether it should add a new insn
+;; the right thing; and (3) it makes it easy for the prologue expander
+;; to search for this insn to determine whether it should add a new insn
 ;; to set up the frame pointer.
 
 (define_insn "set_frame_ptr"
   [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
   ""
-  "*
 {
   if (frame_pointer_needed)
-    return \"mov\\ta7, sp\";
-  return \"\";
-}"
+    return "mov\ta7, sp";
+  return "";
+}
   [(set_attr "type"	"move")
    (set_attr "mode"	"SI")
    (set_attr "length"	"3")])
@@ -2379,7 +2158,6 @@
 
 ;; The fix_return_addr pattern sets the high 2 bits of an address in a
 ;; register to match the high bits of the current PC.
-
 (define_insn "fix_return_addr"
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "r")]
@@ -2387,22 +2165,14 @@
    (clobber (match_scratch:SI 2 "=r"))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
-  "mov\\t%2, a0\;call0\\t0f\;.align\\t4\;0:\;mov\\t%3, a0\;mov\\ta0, %2\;\
-srli\\t%3, %3, 30\;slli\\t%0, %1, 2\;ssai\\t2\;src\\t%0, %3, %0"
+  "mov\t%2, a0\;call0\t0f\;.align\t4\;0:\;mov\t%3, a0\;mov\ta0, %2\;\
+srli\t%3, %3, 30\;slli\t%0, %1, 2\;ssai\t2\;src\t%0, %3, %0"
   [(set_attr "type"	"multi")
    (set_attr "mode"	"SI")
    (set_attr "length"	"24")])
 
-
-;;
-;;  ....................
-;;
-;;	BOOLEANS
-;;
-;;  ....................
-;;
-
-;; branch patterns
+
+;; Instructions for the Xtensa "boolean" option.
 
 (define_insn "*booltrue"
   [(set (pc)
@@ -2412,13 +2182,12 @@ srli\\t%3, %3, 30\;slli\\t%0, %1, 2\;ssai\\t2\;src\\t%0, %3, %0"
 		      (label_ref (match_operand 1 "" ""))
 		      (pc)))]
   "TARGET_BOOLEANS"
-  "*
 {
   if (GET_CODE (operands[2]) == EQ)
-    return \"bf\\t%0, %1\";
+    return "bf\t%0, %1";
   else
-    return \"bt\\t%0, %1\";
-}"
+    return "bt\t%0, %1";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])
@@ -2431,13 +2200,12 @@ srli\\t%3, %3, 30\;slli\\t%0, %1, 2\;ssai\\t2\;src\\t%0, %3, %0"
 		      (pc)
 		      (label_ref (match_operand 1 "" ""))))]
   "TARGET_BOOLEANS"
-  "*
 {
   if (GET_CODE (operands[2]) == EQ)
-    return \"bt\\t%0, %1\";
+    return "bt\t%0, %1";
   else
-    return \"bf\\t%0, %1\";
-}"
+    return "bf\t%0, %1";
+}
   [(set_attr "type"	"jump")
    (set_attr "mode"	"none")
    (set_attr "length"	"3")])