diff options
| author | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-08-26 14:53:53 +0000 |
|---|---|---|
| committer | uweigand <uweigand@138bc75d-0d04-0410-961f-82ee72b054a4> | 2003-08-26 14:53:53 +0000 |
| commit | 614e283a6e2e6fce3efba230f5be8017a8929403 (patch) | |
| tree | f6ada7cf005c8c2fbab141008bf8eccd6df3f72a /gcc/config | |
| parent | 3a71fe48a2966f763ae74f90aa09b7646c34cbbb (diff) | |
* config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
"*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@70812 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/s390/s390.md | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index d9e65439af0..fa7203df47a 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -2440,6 +2440,77 @@ [(set_attr "op_type" "RXY")]) ; +; LLGT-type instructions (zero-extend from 31 bit to 64 bit). +; + +(define_insn "*llgt_sisi" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") + (const_int 2147483647)))] + "TARGET_64BIT" + "@ + llgtr\t%0,%1 + llgt\t%0,%1" + [(set_attr "op_type" "RRE,RXE")]) + +(define_insn_and_split "*llgt_sisi_split" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:SI (match_dup 1) + (const_int 2147483647)))] + "") + +(define_insn "*llgt_didi" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") + (const_int 2147483647)))] + "TARGET_64BIT" + "@ + llgtr\t%0,%1 + llgt\t%0,%N1" + [(set_attr "op_type" "RRE,RXE")]) + +(define_insn_and_split "*llgt_didi_split" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (match_dup 1) + (const_int 2147483647)))] + "") + +(define_insn "*llgt_sidi" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647)))] + "TARGET_64BIT" + "llgt\t%0,%1" + [(set_attr "op_type" "RXE")]) + +(define_insn_and_split "*llgt_sidi_split" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (subreg:DI (match_dup 1) 0) + (const_int 2147483647)))] + "") + +; ; zero_extendqidi2 instruction pattern(s) ; |