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| author | sudi <sudi@138bc75d-0d04-0410-961f-82ee72b054a4> | 2019-01-09 14:21:22 +0000 |
|---|---|---|
| committer | sudi <sudi@138bc75d-0d04-0410-961f-82ee72b054a4> | 2019-01-09 14:21:22 +0000 |
| commit | 15b179097a8d5405623953a29beced7636b05b3d (patch) | |
| tree | 42d0229f90e50a750e4e74a9c304b1bfb86af2c3 /gcc/testsuite/lib | |
| parent | db43f74e7270497f0f69cdd5c9fc2f944fcfba24 (diff) | |
[AArch64, 5/6] Enable BTI : Add new pass for BTI.
This patch is part of a series that enables ARMv8.5-A in GCC and
adds Branch Target Identification Mechanism.
This patch adds a new pass called "bti" which is triggered by the command
line argument -mbranch-protection whenever "bti" is turned on.
The pass iterates through the instructions and adds appropriated BTI
instructions based on the following:
* Add a new "BTI C" at the beginning of a function, unless its already
protected by a "PACIASP". We exempt the functions that are only called
directly.
* Add a new "BTI J" for every target of an indirect jump, jump table
targets, non-local goto targets or labels that might be referenced by
variables, constant pools, etc (NOTE_INSN_DELETED_LABEL).
Since we have already changed the use of indirect tail calls to only x16 and
x17, we do not have to use "BTI JC".
(check patch 3/6).
*** gcc/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config.gcc (aarch64*-*-*): Add aarch64-bti-insert.o.
* gcc/config/aarch64/aarch64.h: Update comment for TRAMPOLINE_SIZE.
* config/aarch64/aarch64.c (aarch64_asm_trampoline_template): Update
if bti is enabled.
* config/aarch64/aarch64-bti-insert.c: New file.
* config/aarch64/aarch64-passes.def (INSERT_PASS_BEFORE): Insert bti
pass.
* config/aarch64/aarch64-protos.h (make_pass_insert_bti): Declare the
new bti pass.
* config/aarch64/aarch64.md (unspecv): Add UNSPECV_BTI_NOARG,
UNSPECV_BTI_C, UNSPECV_BTI_J and UNSPECV_BTI_JC.
(bti_noarg, bti_j, bti_c, bti_jc): New define_insns.
* config/aarch64/t-aarch64: Add rule for aarch64-bti-insert.o.
*** gcc/testsuite/ChangeLog ***
2018-01-09 Sudakshina Das <sudi.das@arm.com>
* gcc.target/aarch64/bti-1.c: New test.
* gcc.target/aarch64/bti-2.c: New test.
* gcc.target/aarch64/bti-3.c: New test.
* lib/target-supports.exp
(check_effective_target_aarch64_bti_hw): Add new check for BTI hw.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@267769 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/testsuite/lib')
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index a9bb6b3bdc6..d694f495493 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -4313,6 +4313,22 @@ proc check_effective_target_arm_neonv2_hw { } { } [add_options_for_arm_neonv2 ""]] } +# ID_AA64PFR1_EL1.BT using bits[3:0] == 1 implies BTI implimented. +proc check_effective_target_aarch64_bti_hw { } { + if { ![istarget aarch64*-*-*] } { + return 0 + } + return [check_runtime aarch64_bti_hw_available { + int + main (void) + { + int a; + asm volatile ("mrs %0, id_aa64pfr1_el1" : "=r" (a)); + return !((a & 0xf) == 1); + } + } "-O2" ] +} + # Return 1 if the target supports the ARMv8.1 Adv.SIMD extension, 0 # otherwise. The test is valid for AArch64 and ARM. Record the command # line options needed. |