diff options
| author | claziss <claziss@138bc75d-0d04-0410-961f-82ee72b054a4> | 2018-01-26 11:34:00 +0000 |
|---|---|---|
| committer | claziss <claziss@138bc75d-0d04-0410-961f-82ee72b054a4> | 2018-01-26 11:34:00 +0000 |
| commit | eddd4dd0e94b8b4e29a1f6c48e44d2bce591849d (patch) | |
| tree | a293830dce49d551376add81e58f0ef3074906b1 /libgcc | |
| parent | c73f40d64a8b05996645181405abfa8e91a2ae6f (diff) | |
[ARC] Add support for reduced register file set
gcc/
2018-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc-arches.def: Option mrf16 valid for all
architectures.
* config/arc/arc-c.def (__ARC_RF16__): New predefined macro.
* config/arc/arc-cpus.def (em_mini): New cpu with rf16 on.
* config/arc/arc-options.def (FL_RF16): Add mrf16 option.
* config/arc/arc-tables.opt: Regenerate.
* config/arc/arc.c (arc_conditional_register_usage): Handle
reduced register file case.
(arc_file_start): Set must have build attributes.
* config/arc/arc.h (MAX_ARC_PARM_REGS): Conditional define using
mrf16 option value.
* config/arc/arc.opt (mrf16): Add new option.
* config/arc/elf.h (ATTRIBUTE_PCS): Define.
* config/arc/genmultilib.awk: Handle new mrf16 option.
* config/arc/linux.h (ATTRIBUTE_PCS): Define.
* config/arc/t-multilib: Regenerate.
* doc/invoke.texi (ARC Options): Document mrf16 option.
libgcc/
2018-01-26 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16
option.
(__divsi3): Use RF16 safe registers.
(__modsi3): Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@257083 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'libgcc')
| -rw-r--r-- | libgcc/ChangeLog | 7 | ||||
| -rw-r--r-- | libgcc/config/arc/lib1funcs.S | 22 |
2 files changed, 18 insertions, 11 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 778a455ca71..79c79e8c31c 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,10 @@ +2018-01-26 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/lib1funcs.S (__udivmodsi4): Use safe version for RF16 + option. + (__divsi3): Use RF16 safe registers. + (__modsi3): Likewise. + 2018-01-23 Max Filippov <jcmvbkbc@gmail.com> * config/xtensa/ieee754-df.S (__addsf3, __subsf3, __mulsf3) diff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S index f70cfd2f7f7..9a626022612 100644 --- a/libgcc/config/arc/lib1funcs.S +++ b/libgcc/config/arc/lib1funcs.S @@ -370,7 +370,7 @@ SYM(__udivmodsi4): mov_s r0,1 j_s.d [blink] mov.c r0,0 -#elif !defined (__OPTIMIZE_SIZE__) +#elif !defined (__OPTIMIZE_SIZE__) && !defined (__ARC_RF16__) #if defined (__ARC_NORM__) && defined (__ARC_BARREL_SHIFTER__) lsr_s r2,r0 brhs.d r1,r2,.Lret0_3 @@ -509,14 +509,14 @@ SYM(__udivsi3): #ifndef __ARC_EA__ SYM(__divsi3): /* A5 / ARC60? */ - mov r7,blink - xor r6,r0,r1 + mov r12,blink + xor r11,r0,r1 abs_s r0,r0 bl.d @SYM(__udivmodsi4) - abs_s r1,r1 - tst r6,r6 - j.d [r7] - neg.mi r0,r0 + abs_s r1,r1 + tst r11,r11 + j.d [r12] + neg.mi r0,r0 #else /* !ifndef __ARC_EA__ */ ;; We can use the abs, norm, divaw and mpy instructions for ARC700 #define MULDIV @@ -913,14 +913,14 @@ SYM(__modsi3): #ifndef __ARC_EA__ /* A5 / ARC60? */ mov_s r12,blink - mov_s r6,r0 + mov_s r11,r0 abs_s r0,r0 bl.d @SYM(__udivmodsi4) - abs_s r1,r1 - tst r6,r6 + abs_s r1,r1 + tst r11,r11 neg_s r0,r1 j_s.d [r12] - mov.pl r0,r1 + mov.pl r0,r1 #else /* __ARC_EA__ */ abs_s r2,r1 norm.f r4,r0 |