diff options
| -rw-r--r-- | libgcc/ChangeLog | 8 | ||||
| -rw-r--r-- | libgcc/config/arm/freebsd-atomic.c | 22 |
2 files changed, 18 insertions, 12 deletions
diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index 7e7c90b7388..7fcf2fb9d61 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,10 @@ +2018-04-27 Andreas Tobler <andreast@gcc.gnu.org> + Maryse Levavasseur <maryse.levavasseur@stormshield.eu> + + PR libgcc/84292 + * config/arm/freebsd-atomic.c (SYNC_OP_AND_FETCH_N): Fix the + op_and_fetch to return the right result. + 2018-04-27 Alan Modra <amodra@gmail.com> PR libgcc/85532 @@ -526,7 +533,6 @@ * config/i386/t-msabi: Modified to add avx and sse versions of stubs. 2017-09-01 Olivier Hainque <hainque@adacore.com> - * config.host (*-*-vxworks7): Widen scope to vxworks7*. 2017-08-31 Olivier Hainque <hainque@adacore.com> diff --git a/libgcc/config/arm/freebsd-atomic.c b/libgcc/config/arm/freebsd-atomic.c index 73a9ac6defc..77618da7cf6 100644 --- a/libgcc/config/arm/freebsd-atomic.c +++ b/libgcc/config/arm/freebsd-atomic.c @@ -171,32 +171,32 @@ __sync_fetch_and_##NAME##_##N (TYPE *mem, TYPE val) \ #define SYNC_OP_AND_FETCH_N(N, TYPE, LDR, STR, NAME, OP) \ TYPE HIDDEN \ -__sync_##NAME##_and_fetch_##N (TYPE *mem, TYPE val) \ +__sync_##NAME##_and_fetch_##N (TYPE *mem, TYPE val) \ { \ - unsigned int old, temp, ras_start; \ + unsigned int old, temp, ras_start, res; \ \ ras_start = ARM_RAS_START; \ __asm volatile ( \ /* Set up Restartable Atomic Sequence. */ \ "1:" \ "\tadr %2, 1b\n" \ - "\tstr %2, [%5]\n" \ + "\tstr %2, [%6]\n" \ "\tadr %2, 2f\n" \ - "\tstr %2, [%5, #4]\n" \ + "\tstr %2, [%6, #4]\n" \ \ - "\t"LDR" %0, %4\n" /* Load old value. */ \ - "\t"OP" %2, %0, %3\n" /* Calculate new value. */ \ - "\t"STR" %2, %1\n" /* Store new value. */ \ + "\t"LDR" %0, %5\n" /* Load old value. */ \ + "\t"OP" %3, %0, %4\n" /* Calculate new value. */ \ + "\t"STR" %3, %1\n" /* Store new value. */ \ \ /* Tear down Restartable Atomic Sequence. */ \ "2:" \ "\tmov %2, #0x00000000\n" \ - "\tstr %2, [%5]\n" \ + "\tstr %2, [%6]\n" \ "\tmov %2, #0xffffffff\n" \ - "\tstr %2, [%5, #4]\n" \ - : "=&r" (old), "=m" (*mem), "=&r" (temp) \ + "\tstr %2, [%6, #4]\n" \ + : "=&r" (old), "=m" (*mem), "=&r" (temp), "=&r" (res) \ : "r" (val), "m" (*mem), "r" (ras_start)); \ - return (old); \ + return (res); \ } #define EMIT_ALL_OPS_N(N, TYPE, LDR, STR, STREQ) \ |