diff options
Diffstat (limited to 'gcc/config/arm/arm.md')
| -rw-r--r-- | gcc/config/arm/arm.md | 660 |
1 files changed, 361 insertions, 299 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9a693a839d0..563c8ef387a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -145,7 +145,7 @@ ; Floating Point Unit. If we only have floating point emulation, then there ; is no point in scheduling the floating point insns. (Well, for best ; performance we should try and group them together). -(define_attr "fpu" "softfpa,fpa,fpe2,fpe3,maverick" +(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp" (const (symbol_ref "arm_fpu_attr"))) ; LENGTH of an instruction (in bytes) @@ -167,6 +167,14 @@ (set_attr "length" "4") (set_attr "pool_range" "250")]) +;; The instruction used to implement a particular pattern. This +;; information is used by pipeline descriptions to provide accurate +;; scheduling information. + +(define_attr "insn" + "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,other" + (const_string "other")) + ; TYPE attribute is used to detect floating point instructions which, if ; running on a co-processor can run in parallel with other, basic instructions ; If write-buffer scheduling is enabled then it can also be used in the @@ -191,19 +199,27 @@ ; r_mem_f the reverse of f_mem_r ; f_2_r fast transfer float to arm (no memory needed) ; r_2_f fast transfer arm to float +; branch a branch ; call a subroutine call -; load any load from memory -; store1 store 1 word to memory from arm registers +; load_byte load byte(s) from memory to arm registers +; load1 load 1 word from memory to arm registers +; load2 load 2 words from memory to arm registers +; load3 load 3 words from memory to arm registers +; load4 load 4 words from memory to arm registers +; store store 1 word to memory from arm registers ; store2 store 2 words ; store3 store 3 words -; store4 store 4 words +; store4 store 4 (or more) words ; Additions for Cirrus Maverick co-processor: ; mav_farith Floating point arithmetic (4 cycle) ; mav_dmult Double multiplies (7 cycle) ; (define_attr "type" - "normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4,mav_farith,mav_dmult" - (const_string "normal")) + "alu,alu_shift,alu_shift_reg,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,branch,call,load_byte,load1,load2,load3,load4,store1,store2,store3,store4,mav_farith,mav_dmult" + (if_then_else + (eq_attr "insn" "smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals") + (const_string "mult") + (const_string "alu"))) ; Load scheduling, set from the arm_ld_sched variable ; initialized by arm_override_options() @@ -251,7 +267,7 @@ ; to stall the processor. Used with model_wbuf above. (define_attr "write_conflict" "no,yes" (if_then_else (eq_attr "type" - "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load") + "block,float_em,f_load,f_store,f_mem_r,r_mem_f,call,load1") (const_string "yes") (const_string "no"))) @@ -259,7 +275,7 @@ ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "normal,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith") + "alu,alu_shift,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith") (const_string "single") (const_string "multi"))) @@ -267,115 +283,26 @@ ;; distant label. Only applicable to Thumb code. (define_attr "far_jump" "yes,no" (const_string "no")) -(define_automaton "arm") +;;--------------------------------------------------------------------------- +;; Pipeline descriptions -;; Write buffer -; -; Strictly, we should model a 4-deep write buffer for ARM7xx based chips -; -; The write buffer on some of the arm6 processors is hard to model exactly. -; There is room in the buffer for up to two addresses and up to eight words -; of memory, but the two needn't be split evenly. When writing the two -; addresses are fully pipelined. However, a read from memory that is not -; currently in the cache will block until the writes have completed. -; It is normally the case that FCLK and MCLK will be in the ratio 2:1, so -; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous -; (they aren't allowed to be at present) then there is a startup cost of 1MCLK -; cycle to add as well. -(define_cpu_unit "write_buf" "arm") - -;; Write blockage unit -; -; The write_blockage unit models (partially), the fact that reads will stall -; until the write buffer empties. -; The f_mem_r and r_mem_f could also block, but they are to the stack, -; so we don't model them here -(define_cpu_unit "write_blockage" "arm") +;; Processor type. This attribute must exactly match the table in +;; arm-cores.def. +(define_attr "tune" + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7m,arm7d,arm7dm,arm7di,arm7dmi,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7tdmi,arm710t,arm720t,arm740t,arm8,arm810,arm9,arm920,arm920t,arm940t,arm9tdmi,arm9e,ep9312,strongarm,strongarm110,strongarm1100,strongarm1110,arm10tdmi,arm1020t,arm926ejs,arm1026ejs,xscale,iwmmxt,arm1136js,arm1136jfs" + (const (symbol_ref "arm_tune"))) -;; Core -; -(define_cpu_unit "core" "arm") - -(define_insn_reservation "r_mem_f_wbuf" 5 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "r_mem_f")) - "core+write_buf*3") - -(define_insn_reservation "store1_wbuf" 5 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store1")) - "core+write_buf*3+write_blockage*5") - -(define_insn_reservation "store2_wbuf" 7 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store2")) - "core+write_buf*4+write_blockage*7") - -(define_insn_reservation "store3_wbuf" 9 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store3")) - "core+write_buf*5+write_blockage*9") - -(define_insn_reservation "store4_wbuf" 11 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store4")) - "core+write_buf*6+write_blockage*11") - -(define_insn_reservation "store2" 3 - (and (eq_attr "model_wbuf" "no") - (eq_attr "type" "store2")) - "core*3") - -(define_insn_reservation "store3" 4 - (and (eq_attr "model_wbuf" "no") - (eq_attr "type" "store3")) - "core*4") - -(define_insn_reservation "store4" 5 - (and (eq_attr "model_wbuf" "no") - (eq_attr "type" "store4")) - "core*5") - -(define_insn_reservation "store1_ldsched" 1 - (and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) - "core") - -(define_insn_reservation "load_ldsched_xscale" 3 - (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) - (eq_attr "is_xscale" "yes")) - "core") - -(define_insn_reservation "load_ldsched" 2 - (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) - (eq_attr "is_xscale" "no")) - "core") - -(define_insn_reservation "load_or_store" 2 - (and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) - "core*2") - -(define_insn_reservation "mult" 16 - (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) - "core*16") - -(define_insn_reservation "mult_ldsched_strongarm" 3 - (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes")) - (eq_attr "type" "mult")) - "core*2") - -(define_insn_reservation "mult_ldsched" 4 - (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no")) - (eq_attr "type" "mult")) - "core*4") - -(define_insn_reservation "multi_cycle" 32 - (and (eq_attr "core_cycles" "multi") - (eq_attr "type" "!mult,load,store1,store2,store3,store4")) - "core*32") - -(define_insn_reservation "single_cycle" 1 - (eq_attr "core_cycles" "single") - "core") +;; True if the generic scheduling description should be used. + +(define_attr "generic_sched" "yes,no" + (if_then_else + (eq_attr "tune" "arm1026ejs,arm1136js,arm1136jfs") + (const_string "no") + (const_string "yes"))) + +(include "arm-generic.md") +(include "arm1026ejs.md") +(include "arm1136jfs.md") ;;--------------------------------------------------------------------------- @@ -397,7 +324,7 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " - if (TARGET_CIRRUS) + if (TARGET_HARD_FLOAT && TARGET_MAVERICK) { if (!cirrus_fp_register (operands[0], DImode)) operands[0] = force_reg (DImode, operands[0]); @@ -433,7 +360,7 @@ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") (match_operand:DI 2 "s_register_operand" "r, 0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !TARGET_CIRRUS" + "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -461,7 +388,7 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !TARGET_CIRRUS" + "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -490,7 +417,7 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM && !TARGET_CIRRUS" + "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -801,7 +728,10 @@ (match_operand:SI 1 "s_register_operand" ""))))] "TARGET_ARM" "adc%?\\t%0, %1, %3%S2" - [(set_attr "conds" "use")] + [(set_attr "conds" "use") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*addsi3_carryin_alt1" @@ -851,9 +781,9 @@ [(set (match_operand:SF 0 "s_register_operand" "") (plus:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "fpa_add_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS + if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], SFmode)) operands[2] = force_reg (SFmode, operands[2]); ") @@ -862,9 +792,9 @@ [(set (match_operand:DF 0 "s_register_operand" "") (plus:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "fpa_add_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS + if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], DFmode)) operands[2] = force_reg (DFmode, operands[2]); ") @@ -877,7 +807,7 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " - if (TARGET_CIRRUS + if (TARGET_HARD_FLOAT && TARGET_MAVERICK && TARGET_ARM && cirrus_fp_register (operands[0], DImode) && cirrus_fp_register (operands[1], DImode)) @@ -1075,9 +1005,9 @@ [(set (match_operand:SF 0 "s_register_operand" "") (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "") (match_operand:SF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { if (!cirrus_fp_register (operands[1], SFmode)) operands[1] = force_reg (SFmode, operands[1]); @@ -1090,9 +1020,9 @@ [(set (match_operand:DF 0 "s_register_operand" "") (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "") (match_operand:DF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { if (!cirrus_fp_register (operands[1], DFmode)) operands[1] = force_reg (DFmode, operands[1]); @@ -1119,7 +1049,7 @@ (match_operand:SI 1 "s_register_operand" "%?r,0")))] "TARGET_ARM" "mul%?\\t%0, %2, %1" - [(set_attr "type" "mult") + [(set_attr "insn" "mul") (set_attr "predicable" "yes")] ) @@ -1140,7 +1070,7 @@ return \"mul\\t%0, %0, %2\"; " [(set_attr "length" "4,4,2") - (set_attr "type" "mult")] + (set_attr "insn" "mul")] ) (define_insn "*mulsi3_compare0" @@ -1154,7 +1084,7 @@ "TARGET_ARM && !arm_arch_xscale" "mul%?s\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "mult")] + (set_attr "insn" "muls")] ) (define_insn "*mulsi_compare0_scratch" @@ -1167,7 +1097,7 @@ "TARGET_ARM && !arm_arch_xscale" "mul%?s\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "mult")] + (set_attr "insn" "muls")] ) ;; Unnamed templates to match MLA instruction. @@ -1180,7 +1110,7 @@ (match_operand:SI 3 "s_register_operand" "?r,r,0,0")))] "TARGET_ARM" "mla%?\\t%0, %2, %1, %3" - [(set_attr "type" "mult") + [(set_attr "insn" "mla") (set_attr "predicable" "yes")] ) @@ -1198,7 +1128,7 @@ "TARGET_ARM && !arm_arch_xscale" "mla%?s\\t%0, %2, %1, %3" [(set_attr "conds" "set") - (set_attr "type" "mult")] + (set_attr "insn" "mlas")] ) (define_insn "*mulsi3addsi_compare0_scratch" @@ -1213,7 +1143,7 @@ "TARGET_ARM && !arm_arch_xscale" "mla%?s\\t%0, %2, %1, %3" [(set_attr "conds" "set") - (set_attr "type" "mult")] + (set_attr "insn" "mlas")] ) ;; Unnamed template to match long long multiply-accumlate (smlal) @@ -1227,7 +1157,7 @@ (match_operand:DI 1 "s_register_operand" "0")))] "TARGET_ARM && arm_fast_multiply" "smlal%?\\t%Q0, %R0, %3, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smlal") (set_attr "predicable" "yes")] ) @@ -1238,7 +1168,7 @@ (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] "TARGET_ARM && arm_fast_multiply" "smull%?\\t%Q0, %R0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smull") (set_attr "predicable" "yes")] ) @@ -1249,7 +1179,7 @@ (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r"))))] "TARGET_ARM && arm_fast_multiply" "umull%?\\t%Q0, %R0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "umull") (set_attr "predicable" "yes")] ) @@ -1264,7 +1194,7 @@ (match_operand:DI 1 "s_register_operand" "0")))] "TARGET_ARM && arm_fast_multiply" "umlal%?\\t%Q0, %R0, %3, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "umlal") (set_attr "predicable" "yes")] ) @@ -1279,7 +1209,7 @@ (clobber (match_scratch:SI 3 "=&r,&r"))] "TARGET_ARM && arm_fast_multiply" "smull%?\\t%3, %0, %2, %1" - [(set_attr "type" "mult") + [(set_attr "insn" "smull") (set_attr "predicable" "yes")] ) @@ -1294,7 +1224,7 @@ (clobber (match_scratch:SI 3 "=&r,&r"))] "TARGET_ARM && arm_fast_multiply" "umull%?\\t%3, %0, %2, %1" - [(set_attr "type" "mult") + [(set_attr "insn" "umull") (set_attr "predicable" "yes")] ) @@ -1306,7 +1236,7 @@ (match_operand:HI 2 "s_register_operand" "r"))))] "TARGET_ARM && arm_arch5e" "smulbb%?\\t%0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] ) @@ -1319,7 +1249,7 @@ (match_operand:HI 2 "s_register_operand" "r"))))] "TARGET_ARM && arm_arch5e" "smultb%?\\t%0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] ) @@ -1332,7 +1262,7 @@ (const_int 16))))] "TARGET_ARM && arm_arch5e" "smulbt%?\\t%0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] ) @@ -1346,7 +1276,7 @@ (const_int 16))))] "TARGET_ARM && arm_arch5e" "smultt%?\\t%0, %1, %2" - [(set_attr "type" "mult") + [(set_attr "insn" "smulxy") (set_attr "predicable" "yes")] ) @@ -1359,7 +1289,7 @@ (match_operand:HI 3 "s_register_operand" "r")))))] "TARGET_ARM && arm_arch5e" "smlabb%?\\t%0, %2, %3, %1" - [(set_attr "type" "mult") + [(set_attr "insn" "smlaxy") (set_attr "predicable" "yes")] ) @@ -1373,16 +1303,16 @@ (match_operand:HI 3 "s_register_operand" "r")))))] "TARGET_ARM && arm_arch5e" "smlalbb%?\\t%Q0, %R0, %2, %3" - [(set_attr "type" "mult") + [(set_attr "insn" "smlalxy") (set_attr "predicable" "yes")]) (define_expand "mulsf3" [(set (match_operand:SF 0 "s_register_operand" "") (mult:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS + if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], SFmode)) operands[2] = force_reg (SFmode, operands[2]); ") @@ -1391,9 +1321,9 @@ [(set (match_operand:DF 0 "s_register_operand" "") (mult:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS + if (TARGET_MAVERICK && !cirrus_fp_register (operands[2], DFmode)) operands[2] = force_reg (DFmode, operands[2]); ") @@ -1404,14 +1334,14 @@ [(set (match_operand:SF 0 "s_register_operand" "") (div:SF (match_operand:SF 1 "fpa_rhs_operand" "") (match_operand:SF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") (define_expand "divdf3" [(set (match_operand:DF 0 "s_register_operand" "") (div:DF (match_operand:DF 1 "fpa_rhs_operand" "") (match_operand:DF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") ;; Modulo insns @@ -1420,14 +1350,14 @@ [(set (match_operand:SF 0 "s_register_operand" "") (mod:SF (match_operand:SF 1 "s_register_operand" "") (match_operand:SF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") (define_expand "moddf3" [(set (match_operand:DF 0 "s_register_operand" "") (mod:DF (match_operand:DF 1 "s_register_operand" "") (match_operand:DF 2 "fpa_rhs_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") ;; Boolean and,ior,xor insns @@ -1999,7 +1929,9 @@ "bic%?\\t%0, %1, %2%S4" [(set_attr "predicable" "yes") (set_attr "shift" "2") - ] + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*andsi_notsi_si_compare0" @@ -2376,6 +2308,41 @@ ;; Shift and rotation insns +(define_expand "ashldi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (ashift:DI (match_operand:DI 1 "s_register_operand" "") + (match_operand:SI 2 "reg_or_int_operand" "")))] + "TARGET_ARM" + " + if (GET_CODE (operands[2]) == CONST_INT) + { + if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) + { + emit_insn (gen_arm_ashldi3_1bit (operands[0], operands[1])); + DONE; + } + /* Ideally we shouldn't fail here if we could know that operands[1] + ends up already living in an iwmmxt register. Otherwise it's + cheaper to have the alternate code being generated than moving + values to iwmmxt regs and back. */ + FAIL; + } + else if (!TARGET_REALLY_IWMMXT && !(TARGET_HARD_FLOAT && TARGET_MAVERICK)) + FAIL; + " +) + +(define_insn "arm_ashldi3_1bit" + [(set (match_operand:DI 0 "s_register_operand" "=&r,r") + (ashift:DI (match_operand:DI 1 "s_register_operand" "?r,0") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" + "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" + [(set_attr "conds" "clob") + (set_attr "length" "8")] +) + (define_expand "ashlsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashift:SI (match_operand:SI 1 "s_register_operand" "") @@ -2400,6 +2367,41 @@ [(set_attr "length" "2")] ) +(define_expand "ashrdi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "") + (match_operand:SI 2 "reg_or_int_operand" "")))] + "TARGET_ARM" + " + if (GET_CODE (operands[2]) == CONST_INT) + { + if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) + { + emit_insn (gen_arm_ashrdi3_1bit (operands[0], operands[1])); + DONE; + } + /* Ideally we shouldn't fail here if we could know that operands[1] + ends up already living in an iwmmxt register. Otherwise it's + cheaper to have the alternate code being generated than moving + values to iwmmxt regs and back. */ + FAIL; + } + else if (!TARGET_REALLY_IWMMXT) + FAIL; + " +) + +(define_insn "arm_ashrdi3_1bit" + [(set (match_operand:DI 0 "s_register_operand" "=&r,r") + (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" + "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" + [(set_attr "conds" "clob") + (set_attr "length" "8")] +) + (define_expand "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -2421,6 +2423,41 @@ [(set_attr "length" "2")] ) +(define_expand "lshrdi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "") + (match_operand:SI 2 "reg_or_int_operand" "")))] + "TARGET_ARM" + " + if (GET_CODE (operands[2]) == CONST_INT) + { + if ((HOST_WIDE_INT) INTVAL (operands[2]) == 1) + { + emit_insn (gen_arm_lshrdi3_1bit (operands[0], operands[1])); + DONE; + } + /* Ideally we shouldn't fail here if we could know that operands[1] + ends up already living in an iwmmxt register. Otherwise it's + cheaper to have the alternate code being generated than moving + values to iwmmxt regs and back. */ + FAIL; + } + else if (!TARGET_REALLY_IWMMXT) + FAIL; + " +) + +(define_insn "arm_lshrdi3_1bit" + [(set (match_operand:DI 0 "s_register_operand" "=&r,r") + (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "?r,0") + (const_int 1))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM" + "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" + [(set_attr "conds" "clob") + (set_attr "length" "8")] +) + (define_expand "lshrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -2491,19 +2528,6 @@ [(set_attr "length" "2")] ) -(define_expand "ashldi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (ashift:DI (match_operand:DI 1 "general_operand" "") - (match_operand:SI 2 "general_operand" "")))] - "TARGET_ARM && (TARGET_IWMMXT || TARGET_CIRRUS)" - " - if (! s_register_operand (operands[1], DImode)) - operands[1] = copy_to_mode_reg (DImode, operands[1]); - if (! s_register_operand (operands[2], SImode)) - operands[2] = copy_to_mode_reg (SImode, operands[2]); - " -) - (define_insn "*arm_shiftsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator:SI 3 "shift_operator" @@ -2513,7 +2537,9 @@ "mov%?\\t%0, %1%S3" [(set_attr "predicable" "yes") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*shiftsi3_compare0" @@ -2528,7 +2554,9 @@ "mov%?s\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*shiftsi3_compare0_scratch" @@ -2541,8 +2569,7 @@ "TARGET_ARM" "mov%?s\\t%0, %1%S3" [(set_attr "conds" "set") - (set_attr "shift" "1") - ] + (set_attr "shift" "1")] ) (define_insn "*notsi_shiftsi" @@ -2554,7 +2581,9 @@ "mvn%?\\t%0, %1%S3" [(set_attr "predicable" "yes") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*notsi_shiftsi_compare0" @@ -2569,7 +2598,9 @@ "mvn%?s\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*not_shiftsi_compare0_scratch" @@ -2583,7 +2614,9 @@ "mvn%?s\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) ;; We don't really have extzv, but defining this using shifts helps @@ -2680,14 +2713,14 @@ (define_expand "negsf2" [(set (match_operand:SF 0 "s_register_operand" "") (neg:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "" ) (define_expand "negdf2" [(set (match_operand:DF 0 "s_register_operand" "") (neg:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") ;; abssi2 doesn't really clobber the condition codes if a different register @@ -2734,25 +2767,25 @@ (define_expand "abssf2" [(set (match_operand:SF 0 "s_register_operand" "") (abs:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" "") (define_expand "absdf2" [(set (match_operand:DF 0 "s_register_operand" "") (abs:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" "") (define_expand "sqrtsf2" [(set (match_operand:SF 0 "s_register_operand" "") (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") (define_expand "sqrtdf2" [(set (match_operand:DF 0 "s_register_operand" "") (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "") (define_insn_and_split "one_cmpldi2" @@ -2823,9 +2856,9 @@ (define_expand "floatsisf2" [(set (match_operand:SF 0 "s_register_operand" "") (float:SF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); DONE; @@ -2835,9 +2868,9 @@ (define_expand "floatsidf2" [(set (match_operand:DF 0 "s_register_operand" "") (float:DF (match_operand:SI 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); DONE; @@ -2847,9 +2880,9 @@ (define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "s_register_operand" "") (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { if (!cirrus_fp_register (operands[0], SImode)) operands[0] = force_reg (SImode, operands[0]); @@ -2863,9 +2896,9 @@ (define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "s_register_operand" "") (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS) + if (TARGET_MAVERICK) { if (!cirrus_fp_register (operands[1], DFmode)) operands[1] = force_reg (DFmode, operands[0]); @@ -2880,7 +2913,7 @@ [(set (match_operand:SF 0 "s_register_operand" "") (float_truncate:SF (match_operand:DF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" "" ) @@ -2909,7 +2942,7 @@ ldr%?b\\t%Q0, %1\;mov%?\\t%R0, #0" [(set_attr "length" "8") (set_attr "predicable" "yes") - (set_attr "type" "*,load") + (set_attr "type" "*,load_byte") (set_attr "pool_range" "*,4092") (set_attr "neg_pool_range" "*,4084")] ) @@ -3038,7 +3071,7 @@ return \"ldrh\\t%0, %1\"; " [(set_attr "length" "4") - (set_attr "type" "load") + (set_attr "type" "load_byte") (set_attr "pool_range" "60")] ) @@ -3047,7 +3080,7 @@ (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4" "ldr%?h\\t%0, %1" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") (set_attr "neg_pool_range" "244")] @@ -3129,7 +3162,7 @@ "TARGET_THUMB" "ldrb\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "load") + (set_attr "type" "load_byte") (set_attr "pool_range" "32")] ) @@ -3138,7 +3171,7 @@ (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARM" "ldr%?b\\t%0, %1\\t%@ zero_extendqisi2" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "4096") (set_attr "neg_pool_range" "4084")] @@ -3271,7 +3304,7 @@ return \"\"; }" [(set_attr "length" "4") - (set_attr "type" "load") + (set_attr "type" "load_byte") (set_attr "pool_range" "1020")] ) @@ -3317,7 +3350,7 @@ (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4" "ldr%?sh\\t%0, %1" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "pool_range" "256") (set_attr "neg_pool_range" "244")] @@ -3389,7 +3422,7 @@ return \"#\"; return \"ldr%?sb\\t%0, %1\"; " - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "length" "8") (set_attr "pool_range" "256") @@ -3487,7 +3520,7 @@ return \"#\"; return \"ldr%?sb\\t%0, %1\"; " - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes") (set_attr "length" "8") (set_attr "pool_range" "256") @@ -3602,14 +3635,14 @@ return \"\"; }" [(set_attr "length" "2,6") - (set_attr "type" "load,load") + (set_attr "type" "load_byte,load_byte") (set_attr "pool_range" "32,32")] ) (define_expand "extendsfdf2" [(set (match_operand:DF 0 "s_register_operand" "") (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" "" ) @@ -3693,12 +3726,12 @@ (define_insn "*arm_movdi" [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>") (match_operand:DI 1 "di_operand" "rIK,mi,r"))] - "TARGET_ARM && !TARGET_CIRRUS && ! TARGET_IWMMXT" + "TARGET_ARM && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && ! TARGET_IWMMXT" "* return (output_move_double (operands)); " [(set_attr "length" "8") - (set_attr "type" "*,load,store2") + (set_attr "type" "*,load2,store2") (set_attr "pool_range" "*,1020,*") (set_attr "neg_pool_range" "*,1008,*")] ) @@ -3711,7 +3744,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] "TARGET_THUMB - && !TARGET_CIRRUS + && !(TARGET_HARD_FLOAT && TARGET_MAVERICK) && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* @@ -3746,7 +3779,7 @@ } }" [(set_attr "length" "4,4,6,2,2,6,4,4") - (set_attr "type" "*,*,*,load,store2,load,store2,*") + (set_attr "type" "*,*,*,load2,store2,load2,store2,*") (set_attr "pool_range" "*,*,*,*,*,1020,*,*")] ) @@ -3800,7 +3833,7 @@ mvn%?\\t%0, #%B1 ldr%?\\t%0, %1 str%?\\t%1, %0" - [(set_attr "type" "*,*,load,store1") + [(set_attr "type" "*,*,load1,store1") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,4096,*") (set_attr "neg_pool_range" "*,*,4084,*")] @@ -3837,7 +3870,7 @@ str\\t%1, %0 mov\\t%0, %1" [(set_attr "length" "2,2,4,4,2,2,2,2,2") - (set_attr "type" "*,*,*,*,load,store1,load,store1,*") + (set_attr "type" "*,*,*,*,load1,store1,load1,store1,*") (set_attr "pool_range" "*,*,*,*,*,*,1020,*,*")] ) @@ -3889,7 +3922,7 @@ (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))] "TARGET_ARM && flag_pic" "ldr%?\\t%0, %1" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set (attr "pool_range") (const_int 4096)) (set (attr "neg_pool_range") (const_int 4084))] ) @@ -3899,7 +3932,7 @@ (unspec:SI [(match_operand:SI 1 "" "mX")] UNSPEC_PIC_SYM))] "TARGET_THUMB && flag_pic" "ldr\\t%0, %1" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set (attr "pool_range") (const_int 1024))] ) @@ -3925,7 +3958,7 @@ output_asm_insn (\"ldr%?\\t%0, %a1\", operands); return \"\"; " - [(set_attr "type" "load") + [(set_attr "type" "load1") (set (attr "pool_range") (if_then_else (eq_attr "is_thumb" "yes") (const_int 1024) @@ -4350,7 +4383,7 @@ return \"ldrh %0, %1\"; }" [(set_attr "length" "2,4,2,2,2,2") - (set_attr "type" "*,load,store1,*,*,*") + (set_attr "type" "*,load1,store1,*,*,*") (set_attr "pool_range" "*,64,*,*,*,*")] ) @@ -4369,7 +4402,7 @@ output_asm_insn (\"ldr%?\\t%0, %1\\t%@ load-rotate\", ops); return \"\"; }" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes")] ) @@ -4437,7 +4470,7 @@ mvn%?\\t%0, #%B1\\t%@ movhi str%?h\\t%1, %0\\t%@ movhi ldr%?h\\t%0, %1\\t%@ movhi" - [(set_attr "type" "*,*,store1,load") + [(set_attr "type" "*,*,store1,load1") (set_attr "predicable" "yes") (set_attr "pool_range" "*,*,*,256") (set_attr "neg_pool_range" "*,*,*,244")] @@ -4457,7 +4490,7 @@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi ldr%?\\t%0, %1\\t%@ movhi" - [(set_attr "type" "*,*,load") + [(set_attr "type" "*,*,load1") (set_attr "predicable" "yes") (set_attr "pool_range" "4096") (set_attr "neg_pool_range" "4084")] @@ -4477,7 +4510,7 @@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi ldr%?\\t%0, %1\\t%@ movhi_bigend\;mov%?\\t%0, %0, asr #16" - [(set_attr "type" "*,*,load") + [(set_attr "type" "*,*,load1") (set_attr "predicable" "yes") (set_attr "length" "4,4,8") (set_attr "pool_range" "*,*,4092") @@ -4492,7 +4525,7 @@ && BYTES_BIG_ENDIAN && !TARGET_MMU_TRAPS" "ldr%?\\t%0, %1\\t%@ movhi_bigend" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes") (set_attr "pool_range" "4096") (set_attr "neg_pool_range" "4084")] @@ -4632,7 +4665,7 @@ mvn%?\\t%0, #%B1 ldr%?b\\t%0, %1 str%?b\\t%1, %0" - [(set_attr "type" "*,*,load,store1") + [(set_attr "type" "*,*,load1,store1") (set_attr "predicable" "yes")] ) @@ -4650,7 +4683,7 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "*,load,store1,*,*,*") + (set_attr "type" "*,load1,store1,*,*,*") (set_attr "pool_range" "*,32,*,*,*,*")] ) @@ -4679,7 +4712,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "") (match_operand:SF 1 "immediate_operand" ""))] "TARGET_ARM - && !TARGET_HARD_FLOAT + && !(TARGET_HARD_FLOAT && TARGET_FPA) && reload_completed && GET_CODE (operands[1]) == CONST_DOUBLE" [(set (match_dup 2) (match_dup 3))] @@ -4695,7 +4728,6 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") (match_operand:SF 1 "general_operand" "r,mE,r"))] "TARGET_ARM - && !TARGET_CIRRUS && TARGET_SOFT_FLOAT && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))" @@ -4705,7 +4737,7 @@ str%?\\t%1, %0\\t%@ float" [(set_attr "length" "4,4,4") (set_attr "predicable" "yes") - (set_attr "type" "*,load,store1") + (set_attr "type" "*,load1,store1") (set_attr "pool_range" "*,4096,*") (set_attr "neg_pool_range" "*,4084,*")] ) @@ -4726,7 +4758,7 @@ mov\\t%0, %1 mov\\t%0, %1" [(set_attr "length" "2") - (set_attr "type" "*,load,store1,load,store1,*,*") + (set_attr "type" "*,load1,store1,load1,store1,*,*") (set_attr "pool_range" "*,*,*,1020,*,*,*")] ) @@ -4798,11 +4830,10 @@ [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,m") (match_operand:DF 1 "soft_df_operand" "r,mF,r"))] "TARGET_ARM && TARGET_SOFT_FLOAT - && !TARGET_CIRRUS " "* return output_move_double (operands);" [(set_attr "length" "8,8,8") - (set_attr "type" "*,load,store2") + (set_attr "type" "*,load2,store2") (set_attr "pool_range" "1020") (set_attr "neg_pool_range" "1008")] ) @@ -4843,7 +4874,7 @@ } " [(set_attr "length" "4,2,2,6,4,4") - (set_attr "type" "*,load,store2,load,store2,*") + (set_attr "type" "*,load2,store2,load2,store2,*") (set_attr "pool_range" "*,*,*,1020,*,*")] ) @@ -4916,7 +4947,7 @@ (mem:SI (plus:SI (match_dup 2) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 5" "ldm%?ia\\t%1!, {%3, %4, %5, %6}" - [(set_attr "type" "load") + [(set_attr "type" "load4") (set_attr "predicable" "yes")] ) @@ -4933,7 +4964,7 @@ (mem:SI (plus:SI (match_dup 2) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%?ia\\t%1!, {%3, %4, %5}" - [(set_attr "type" "load") + [(set_attr "type" "load3") (set_attr "predicable" "yes")] ) @@ -4948,7 +4979,7 @@ (mem:SI (plus:SI (match_dup 2) (const_int 4))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%?ia\\t%1!, {%3, %4}" - [(set_attr "type" "load") + [(set_attr "type" "load2") (set_attr "predicable" "yes")] ) @@ -4966,7 +4997,7 @@ (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 4" "ldm%?ia\\t%1, {%2, %3, %4, %5}" - [(set_attr "type" "load") + [(set_attr "type" "load4") (set_attr "predicable" "yes")] ) @@ -4980,7 +5011,7 @@ (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 3" "ldm%?ia\\t%1, {%2, %3, %4}" - [(set_attr "type" "load") + [(set_attr "type" "load3") (set_attr "predicable" "yes")] ) @@ -4992,7 +5023,7 @@ (mem:SI (plus:SI (match_dup 1) (const_int 4))))])] "TARGET_ARM && XVECLEN (operands[0], 0) == 2" "ldm%?ia\\t%1, {%2, %3}" - [(set_attr "type" "load") + [(set_attr "type" "load2") (set_attr "predicable" "yes")] ) @@ -6243,9 +6274,9 @@ (define_expand "cmpsf" [(match_operand:SF 0 "s_register_operand" "") (match_operand:SF 1 "fpa_rhs_operand" "")] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], SFmode)) + if (TARGET_MAVERICK && !cirrus_fp_register (operands[1], SFmode)) operands[1] = force_reg (SFmode, operands[1]); arm_compare_op0 = operands[0]; @@ -6257,9 +6288,9 @@ (define_expand "cmpdf" [(match_operand:DF 0 "s_register_operand" "") (match_operand:DF 1 "fpa_rhs_operand" "")] - "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT" " - if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], DFmode)) + if (TARGET_MAVERICK && !cirrus_fp_register (operands[1], DFmode)) operands[1] = force_reg (DFmode, operands[1]); arm_compare_op0 = operands[0]; @@ -6289,7 +6320,9 @@ "cmp%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*cmpsi_shiftsi_swp" @@ -6302,7 +6335,9 @@ "cmp%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*cmpsi_neg_shiftsi" @@ -6315,7 +6350,9 @@ "cmn%?\\t%0, %1%S3" [(set_attr "conds" "set") (set_attr "shift" "1") - ] + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) ;; Cirrus SF compare instruction @@ -6323,7 +6360,7 @@ [(set (reg:CCFP CC_REGNUM) (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v") (match_operand:SF 1 "cirrus_fp_register" "v")))] - "TARGET_ARM && TARGET_CIRRUS" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" "cfcmps%?\\tr15, %V0, %V1" [(set_attr "type" "mav_farith") (set_attr "cirrus" "compare")] @@ -6334,7 +6371,7 @@ [(set (reg:CCFP CC_REGNUM) (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v") (match_operand:DF 1 "cirrus_fp_register" "v")))] - "TARGET_ARM && TARGET_CIRRUS" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" "cfcmpd%?\\tr15, %V0, %V1" [(set_attr "type" "mav_farith") (set_attr "cirrus" "compare")] @@ -6344,7 +6381,7 @@ (define_expand "cmpdi" [(match_operand:DI 0 "cirrus_fp_register" "") (match_operand:DI 1 "cirrus_fp_register" "")] - "TARGET_ARM && TARGET_CIRRUS" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" "{ arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; @@ -6355,7 +6392,7 @@ [(set (reg:CC CC_REGNUM) (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") (match_operand:DI 1 "cirrus_fp_register" "v")))] - "TARGET_ARM && TARGET_CIRRUS" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK" "cfcmp64%?\\tr15, %V0, %V1" [(set_attr "type" "mav_farith") (set_attr "cirrus" "compare")] @@ -6473,7 +6510,7 @@ (if_then_else (unordered (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -6483,7 +6520,7 @@ (if_then_else (ordered (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -6493,7 +6530,7 @@ (if_then_else (ungt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" ) @@ -6502,7 +6539,7 @@ (if_then_else (unlt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" ) @@ -6511,7 +6548,7 @@ (if_then_else (unge (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" ) @@ -6520,7 +6557,7 @@ (if_then_else (unle (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" ) @@ -6531,7 +6568,7 @@ (if_then_else (uneq (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNEQ, arm_compare_op0, arm_compare_op1);" ) @@ -6540,7 +6577,7 @@ (if_then_else (ltgt (match_dup 1) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (LTGT, arm_compare_op0, arm_compare_op1);" ) @@ -6554,7 +6591,7 @@ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "* if (arm_ccfsm_state != 0) abort (); @@ -6571,7 +6608,7 @@ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "* if (arm_ccfsm_state != 0) abort (); @@ -6597,7 +6634,8 @@ } return \"b%d1\\t%l0\"; " - [(set_attr "conds" "use")] + [(set_attr "conds" "use") + (set_attr "type" "branch")] ) ; Special pattern to match reversed UNEQ. @@ -6606,7 +6644,7 @@ (if_then_else (uneq (match_operand 1 "cc_register" "") (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "* if (arm_ccfsm_state != 0) abort (); @@ -6623,7 +6661,7 @@ (if_then_else (ltgt (match_operand 1 "cc_register" "") (const_int 0)) (pc) (label_ref (match_operand 0 "" ""))))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "* if (arm_ccfsm_state != 0) abort (); @@ -6649,7 +6687,8 @@ } return \"b%D1\\t%l0\"; " - [(set_attr "conds" "use")] + [(set_attr "conds" "use") + (set_attr "type" "branch")] ) @@ -6729,7 +6768,7 @@ (define_expand "sunordered" [(set (match_operand:SI 0 "s_register_operand" "") (unordered:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -6737,7 +6776,7 @@ (define_expand "sordered" [(set (match_operand:SI 0 "s_register_operand" "") (ordered:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, arm_compare_op1);" ) @@ -6745,7 +6784,7 @@ (define_expand "sungt" [(set (match_operand:SI 0 "s_register_operand" "") (ungt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, arm_compare_op1);" ) @@ -6753,7 +6792,7 @@ (define_expand "sunge" [(set (match_operand:SI 0 "s_register_operand" "") (unge:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, arm_compare_op1);" ) @@ -6761,7 +6800,7 @@ (define_expand "sunlt" [(set (match_operand:SI 0 "s_register_operand" "") (unlt:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, arm_compare_op1);" ) @@ -6769,7 +6808,7 @@ (define_expand "sunle" [(set (match_operand:SI 0 "s_register_operand" "") (unle:SI (match_dup 1) (const_int 0)))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, arm_compare_op1);" ) @@ -6780,14 +6819,14 @@ ; (define_expand "suneq" ; [(set (match_operand:SI 0 "s_register_operand" "") ; (uneq:SI (match_dup 1) (const_int 0)))] -; "TARGET_ARM && TARGET_HARD_FLOAT" +; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" ; "abort ();" ; ) ; ; (define_expand "sltgt" ; [(set (match_operand:SI 0 "s_register_operand" "") ; (ltgt:SI (match_dup 1) (const_int 0)))] -; "TARGET_ARM && TARGET_HARD_FLOAT" +; "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" ; "abort ();" ; ) @@ -6859,7 +6898,7 @@ /* When compiling for SOFT_FLOAT, ensure both arms are in registers. Otherwise, ensure it is a valid FP add operand */ - if ((!TARGET_HARD_FLOAT) + if ((!(TARGET_HARD_FLOAT && TARGET_FPA)) || (!fpa_add_operand (operands[3], SFmode))) operands[3] = force_reg (SFmode, operands[3]); @@ -6873,7 +6912,7 @@ (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") (match_operand:DF 2 "s_register_operand" "") (match_operand:DF 3 "fpa_add_operand" "")))] - "TARGET_ARM && TARGET_HARD_FLOAT" + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_FPA" " { enum rtx_code code = GET_CODE (operands[1]); @@ -7239,7 +7278,7 @@ } return output_return_instruction (const_true_rtx, TRUE, FALSE); }" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "length" "12") (set_attr "predicable" "yes")] ) @@ -7262,7 +7301,7 @@ }" [(set_attr "conds" "use") (set_attr "length" "12") - (set_attr "type" "load")] + (set_attr "type" "load1")] ) (define_insn "*cond_return_inverted" @@ -7282,7 +7321,7 @@ return output_return_instruction (operands[0], TRUE, TRUE); }" [(set_attr "conds" "use") - (set_attr "type" "load")] + (set_attr "type" "load1")] ) ;; Generate a sequence of instructions to determine if the processor is @@ -7426,7 +7465,7 @@ (match_operand:SI 0 "memory_operand" "m"))] "TARGET_ARM" "ldr%?\\t%|pc, %0\\t%@ indirect memory jump" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "pool_range" "4096") (set_attr "neg_pool_range" "4084") (set_attr "predicable" "yes")] @@ -7472,7 +7511,9 @@ "%i1%?\\t%0, %2, %4%S3" [(set_attr "predicable" "yes") (set_attr "shift" "4") - ] + (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*arith_shiftsi_compare0" @@ -7490,7 +7531,9 @@ "%i1%?s\\t%0, %2, %4%S3" [(set_attr "conds" "set") (set_attr "shift" "4") - ] + (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*arith_shiftsi_compare0_scratch" @@ -7506,7 +7549,9 @@ "%i1%?s\\t%0, %2, %4%S3" [(set_attr "conds" "set") (set_attr "shift" "4") - ] + (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*sub_shiftsi" @@ -7519,7 +7564,9 @@ "sub%?\\t%0, %1, %3%S2" [(set_attr "predicable" "yes") (set_attr "shift" "3") - ] + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*sub_shiftsi_compare0" @@ -7536,8 +7583,10 @@ "TARGET_ARM" "sub%?s\\t%0, %1, %3%S2" [(set_attr "conds" "set") - (set_attr "shift" "3") - ] + (set_attr "shift" "3") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*sub_shiftsi_compare0_scratch" @@ -7552,8 +7601,10 @@ "TARGET_ARM" "sub%?s\\t%0, %1, %3%S2" [(set_attr "conds" "set") - (set_attr "shift" "3") - ] + (set_attr "shift" "3") + (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) @@ -8388,7 +8439,10 @@ mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4" [(set_attr "conds" "use") (set_attr "shift" "2") - (set_attr "length" "4,8,8")] + (set_attr "length" "4,8,8") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*ifcompare_move_shift" @@ -8424,7 +8478,10 @@ mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4" [(set_attr "conds" "use") (set_attr "shift" "2") - (set_attr "length" "4,8,8")] + (set_attr "length" "4,8,8") + (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*ifcompare_shift_shift" @@ -8461,7 +8518,12 @@ "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7" [(set_attr "conds" "use") (set_attr "shift" "1") - (set_attr "length" "8")] + (set_attr "length" "8") + (set (attr "type") (if_then_else + (and (match_operand 2 "const_int_operand" "") + (match_operand 4 "const_int_operand" "")) + (const_string "alu_shift") + (const_string "alu_shift_reg")))] ) (define_insn "*ifcompare_not_arith" @@ -8662,7 +8724,7 @@ }" [(set_attr "length" "12") (set_attr "predicable" "yes") - (set_attr "type" "load")] + (set_attr "type" "load1")] ) ;; the arm can support extended pre-inc instructions @@ -8719,7 +8781,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?b\\t%3, [%0, %2]!" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8735,7 +8797,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?b\\t%3, [%0, -%2]!" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8752,7 +8814,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?b\\t%3, [%0, %2]!\\t%@ z_extendqisi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8769,7 +8831,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?b\\t%3, [%0, -%2]!\\t%@ z_extendqisi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8817,7 +8879,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?\\t%3, [%0, %2]!" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes")] ) @@ -8833,7 +8895,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?\\t%3, [%0, -%2]!" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes")] ) @@ -8852,7 +8914,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?\\t%3, [%0, %2]!\\t%@ loadhi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8871,7 +8933,7 @@ && (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != FRAME_POINTER_REGNUM)" "ldr%?\\t%3, [%0, -%2]!\\t%@ loadhi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8925,7 +8987,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?b\\t%5, [%0, %3%S2]!" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8943,7 +9005,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?b\\t%5, [%0, -%3%S2]!" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -8997,7 +9059,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?\\t%5, [%0, %3%S2]!" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes")] ) @@ -9015,7 +9077,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?\\t%5, [%0, -%3%S2]!" - [(set_attr "type" "load") + [(set_attr "type" "load1") (set_attr "predicable" "yes")]) (define_insn "*loadhi_shiftpreinc" @@ -9035,7 +9097,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?\\t%5, [%0, %3%S2]!\\t%@ loadhi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -9056,7 +9118,7 @@ && REGNO (operands[1]) != FRAME_POINTER_REGNUM && REGNO (operands[3]) != FRAME_POINTER_REGNUM" "ldr%?\\t%5, [%0, -%3%S2]!\\t%@ loadhi" - [(set_attr "type" "load") + [(set_attr "type" "load_byte") (set_attr "predicable" "yes")] ) @@ -9168,7 +9230,7 @@ (set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))] "TARGET_ARM - && (!TARGET_CIRRUS + && (!(TARGET_HARD_FLOAT && TARGET_MAVERICK) || (!cirrus_fp_register (operands[0], SImode) && !cirrus_fp_register (operands[1], SImode))) " |