diff options
Diffstat (limited to 'gcc/config/pa')
| -rw-r--r-- | gcc/config/pa/milli64.S | 2 | ||||
| -rw-r--r-- | gcc/config/pa/pa-hpux.h | 9 | ||||
| -rw-r--r-- | gcc/config/pa/pa-hpux10.h | 8 | ||||
| -rw-r--r-- | gcc/config/pa/pa-hpux11.h | 33 | ||||
| -rw-r--r-- | gcc/config/pa/pa-protos.h | 10 | ||||
| -rw-r--r-- | gcc/config/pa/pa.c | 685 | ||||
| -rw-r--r-- | gcc/config/pa/pa.h | 55 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 1385 | ||||
| -rw-r--r-- | gcc/config/pa/pa32-regs.h | 2 | ||||
| -rw-r--r-- | gcc/config/pa/pa64-hpux.h | 213 | ||||
| -rw-r--r-- | gcc/config/pa/pa64-regs.h | 4 | ||||
| -rw-r--r-- | gcc/config/pa/rtems.h | 5 | ||||
| -rw-r--r-- | gcc/config/pa/som.h | 53 | ||||
| -rw-r--r-- | gcc/config/pa/t-hpux-shlib | 6 |
14 files changed, 1864 insertions, 606 deletions
diff --git a/gcc/config/pa/milli64.S b/gcc/config/pa/milli64.S index 2190a36e2c9..99d2d2e12a3 100644 --- a/gcc/config/pa/milli64.S +++ b/gcc/config/pa/milli64.S @@ -1776,7 +1776,7 @@ DISCUSSION: .align 16 .proc .callinfo millicode - .export $$mulI, millicode + .export $$mulI,millicode GSYM($$mulI) combt,<<= a1,a0,LREF(l4) /* swap args if unsigned a1>a0 */ copy 0,r /* zero out the result */ diff --git a/gcc/config/pa/pa-hpux.h b/gcc/config/pa/pa-hpux.h index b9d563e09be..d6e15164013 100644 --- a/gcc/config/pa/pa-hpux.h +++ b/gcc/config/pa/pa-hpux.h @@ -96,3 +96,12 @@ Boston, MA 02111-1307, USA. */ /* hpux8 and later have C++ compatible include files, so do not pretend they are `extern "C"'. */ #define NO_IMPLICIT_EXTERN_C + +/* hpux11 and earlier don't have fputc_unlocked, so we must inhibit the + transformation of fputs_unlocked and fprintf_unlocked to fputc_unlocked. */ +#define DONT_HAVE_FPUTC_UNLOCKED + +/* We want the entry value of SP saved in the frame marker for + compatibility with the HP-UX unwind library. */ +#undef TARGET_HPUX_UNWIND_LIBRARY +#define TARGET_HPUX_UNWIND_LIBRARY 1 diff --git a/gcc/config/pa/pa-hpux10.h b/gcc/config/pa/pa-hpux10.h index 0354543e3d0..9cd7c1b9de7 100644 --- a/gcc/config/pa/pa-hpux10.h +++ b/gcc/config/pa/pa-hpux10.h @@ -82,10 +82,12 @@ Boston, MA 02111-1307, USA. */ #define LIB_SPEC \ "%{!shared:\ %{!p:%{!pg:\ - %{!threads:-lc}\ + %{!threads:-lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\ %{threads:-lcma -lc_r}}}\ - %{p: -L/lib/libp/ -lc}\ - %{pg: -L/lib/libp/ -lc}}" + %{p: -L/lib/libp/ -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\ + %{pg: -L/lib/libp/ -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}" #undef THREAD_MODEL_SPEC #define THREAD_MODEL_SPEC "%{!threads:single}%{threads:dce}" diff --git a/gcc/config/pa/pa-hpux11.h b/gcc/config/pa/pa-hpux11.h index 0bc7f1010a5..23ec45ba822 100644 --- a/gcc/config/pa/pa-hpux11.h +++ b/gcc/config/pa/pa-hpux11.h @@ -72,10 +72,13 @@ Boston, MA 02111-1307, USA. */ #undef LINK_SPEC #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & 1) #define LINK_SPEC \ - "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}" + "%{!mpa-risc-1-0:%{!shared:-L/lib/pa1.1 -L/usr/lib/pa1.1 }} -z\ + %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\ + %{static:-a archive} %{shared:-b}" #else #define LINK_SPEC \ - "-z %{mlinker-opt:-O} %{!shared:-u main} %{static:-a archive} %{shared:-b}" + "-z %{mlinker-opt:-O} %{!shared:-u main -u __gcc_plt_call}\ + %{static:-a archive} %{shared:-b}" #endif /* Like the default, except no -lg. */ @@ -83,10 +86,12 @@ Boston, MA 02111-1307, USA. */ #define LIB_SPEC \ "%{!shared:\ %{!p:%{!pg:\ - %{!threads:-lc}\ + %{!threads:-lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\ %{threads:-lcma -lc_r}}}\ - %{p: -L/lib/libp/ -lc}\ - %{pg: -L/lib/libp/ -lc}}" + %{p: -L/lib/libp/ -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\ + %{pg: -L/lib/libp/ -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}" /* Under hpux11, the normal location of the `ld' and `as' programs is the /usr/ccs/bin directory. */ @@ -117,3 +122,21 @@ Boston, MA 02111-1307, USA. */ #define SIZE_TYPE "long unsigned int" #define PTRDIFF_TYPE "long int" + +/* HP-UX 11.0 and above provides initialization and finalization function + support from linker command line. We don't need to invoke __main to run + constructors. We also don't need chatr to determine the dependencies of + dynamically linked executables and shared libraries. */ +#undef LDD_SUFFIX +#undef PARSE_LDD_OUTPUT +#undef HAS_INIT_SECTION +#define HAS_INIT_SECTION 1 +#undef LD_INIT_SWITCH +#define LD_INIT_SWITCH "+init" +#undef LD_FINI_SWITCH +#define LD_FINI_SWITCH "+fini" + +/* The HP-UX 11.X SOM linker (ld32) can successfully link shared libraries + with secondary definition (weak) symbols. */ +#undef TARGET_SOM_SDEF +#define TARGET_SOM_SDEF 1 diff --git a/gcc/config/pa/pa-protos.h b/gcc/config/pa/pa-protos.h index 8ea36f3a44e..626ac1a7682 100644 --- a/gcc/config/pa/pa-protos.h +++ b/gcc/config/pa/pa-protos.h @@ -1,5 +1,5 @@ /* Prototypes for pa.c functions used in the md file & elsewhere. - Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 2000, 2001, 2002, 2003 Free Software Foundation, Inc. This file is part of GNU CC. @@ -44,6 +44,7 @@ extern const char *output_move_double PARAMS ((rtx *)); extern const char *output_fp_move_double PARAMS ((rtx *)); extern const char *output_block_move PARAMS ((rtx *, int)); extern const char *output_cbranch PARAMS ((rtx *, int, int, int, rtx)); +extern const char *output_lbranch PARAMS ((rtx, rtx)); extern const char *output_bb PARAMS ((rtx *, int, int, int, rtx, int)); extern const char *output_bvb PARAMS ((rtx *, int, int, int, rtx, int)); extern const char *output_dbra PARAMS ((rtx *, rtx, int)); @@ -51,6 +52,7 @@ extern const char *output_movb PARAMS ((rtx *, rtx, int, int)); extern const char *output_parallel_movb PARAMS ((rtx *, int)); extern const char *output_parallel_addb PARAMS ((rtx *, int)); extern const char *output_call PARAMS ((rtx, rtx, int)); +extern const char *output_indirect_call PARAMS ((rtx, rtx)); extern const char *output_millicode_call PARAMS ((rtx, rtx)); extern const char *output_mul_insn PARAMS ((int, rtx)); extern const char *output_div_insn PARAMS ((rtx *, int, rtx)); @@ -105,8 +107,10 @@ extern int jump_in_call_delay PARAMS ((rtx)); extern enum reg_class secondary_reload_class PARAMS ((enum reg_class, enum machine_mode, rtx)); extern int hppa_fpstore_bypass_p PARAMS ((rtx, rtx)); -extern int attr_length_millicode_call PARAMS ((rtx, int)); +extern int attr_length_millicode_call PARAMS ((rtx)); extern int attr_length_call PARAMS ((rtx, int)); +extern int attr_length_indirect_call PARAMS ((rtx)); +extern int attr_length_save_restore_dltp PARAMS ((rtx)); /* Declare functions defined in pa.c and used in templates. */ @@ -157,7 +161,7 @@ extern int cmpib_comparison_operator PARAMS ((rtx, enum machine_mode)); extern int reloc_needed PARAMS ((tree)); #ifdef RTX_CODE extern rtx function_arg PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, - tree, int, int)); + tree, int)); extern rtx function_value PARAMS ((tree, tree)); #endif extern int function_arg_partial_nregs PARAMS ((CUMULATIVE_ARGS *, diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 0d5f111a41a..a81d06e31c6 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -1,6 +1,6 @@ /* Subroutines for insn-output.c for HPPA. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, - 2002 Free Software Foundation, Inc. + 2002, 2003 Free Software Foundation, Inc. Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c This file is part of GNU CC. @@ -121,6 +121,11 @@ static void pa_globalize_label PARAMS ((FILE *, const char *)) ATTRIBUTE_UNUSED; static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree)); +#if !defined(USE_COLLECT2) +static void pa_asm_out_constructor PARAMS ((rtx, int)); +static void pa_asm_out_destructor PARAMS ((rtx, int)); +#endif +static void pa_init_builtins PARAMS ((void)); static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED; static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED; static struct deferred_plabel *get_plabel PARAMS ((const char *)) @@ -203,6 +208,16 @@ static size_t n_deferred_plabels = 0; #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall +#if !defined(USE_COLLECT2) +#undef TARGET_ASM_CONSTRUCTOR +#define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor +#undef TARGET_ASM_DESTRUCTOR +#define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor +#endif + +#undef TARGET_INIT_BUILTINS +#define TARGET_INIT_BUILTINS pa_init_builtins + struct gcc_target targetm = TARGET_INITIALIZER; void @@ -314,6 +329,14 @@ override_options () } } +static void +pa_init_builtins () +{ +#ifdef DONT_HAVE_FPUTC_UNLOCKED + built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE; +#endif +} + /* Return nonzero only if OP is a register of mode MODE, or CONST0_RTX. */ int @@ -3132,12 +3155,13 @@ compute_frame_size (size, fregs_live) fsize += current_function_outgoing_args_size; /* Allocate space for the fixed frame marker. This space must be - allocated for any function that makes calls or otherwise allocates + allocated for any function that makes calls or allocates stack space. */ if (!current_function_is_leaf || fsize) - fsize += TARGET_64BIT ? 16 : 32; + fsize += TARGET_64BIT ? 48 : 32; - return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1); + return ((fsize + PREFERRED_STACK_BOUNDARY / 8 - 1) + & ~(PREFERRED_STACK_BOUNDARY / 8 - 1)); } /* Generate the assembly code for function entry. FILE is a stdio @@ -3177,6 +3201,15 @@ pa_output_function_prologue (file, size) else fputs (",NO_CALLS", file); + /* The SAVE_SP flag is used to indicate that register %r3 is stored + at the beginning of the frame and that it is used as the frame + pointer for the frame. We do this because our current frame + layout doesn't conform to that specified in the the HP runtime + documentation and we need a way to indicate to programs such as + GDB where %r3 is saved. The SAVE_SP flag was chosen because it + isn't used by HP compilers but is supported by the assembler. + However, SAVE_SP is supposed to indicate that the previous stack + pointer has been saved in the frame marker. */ if (frame_pointer_needed) fputs (",SAVE_SP", file); @@ -3196,26 +3229,6 @@ pa_output_function_prologue (file, size) fputs ("\n\t.ENTRY\n", file); - /* If we're using GAS and SOM, and not using the portable runtime model, - or function sections, then we don't need to accumulate the total number - of code bytes. */ - if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME) - || flag_function_sections) - total_code_bytes = 0; - else if (INSN_ADDRESSES_SET_P ()) - { - unsigned long old_total = total_code_bytes; - - total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ())); - total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT; - - /* Be prepared to handle overflows. */ - if (old_total > total_code_bytes) - total_code_bytes = -1; - } - else - total_code_bytes = -1; - remove_useless_addtr_insns (get_insns (), 0); } @@ -3297,11 +3310,32 @@ hppa_expand_prologue () adjust2, 1); } - /* Prevent register spills from being scheduled before the - stack pointer is raised. Necessary as we will be storing - registers using the frame pointer as a base register, and - we happen to set fp before raising sp. */ - emit_insn (gen_blockage ()); + /* We set SAVE_SP in frames that need a frame pointer. Thus, + we need to store the previous stack pointer (frame pointer) + into the frame marker on targets that use the HP unwind + library. This allows the HP unwind library to be used to + unwind GCC frames. However, we are not fully compatible + with the HP library because our frame layout differs from + that specified in the HP runtime specification. + + We don't want a frame note on this instruction as the frame + marker moves during dynamic stack allocation. + + This instruction also serves as a blockage to prevent + register spills from being scheduled before the stack + pointer is raised. This is necessary as we store + registers using the frame pointer as a base register, + and the frame pointer is set before sp is raised. */ + if (TARGET_HPUX_UNWIND_LIBRARY) + { + rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (TARGET_64BIT ? -8 : -4)); + + emit_move_insn (gen_rtx_MEM (word_mode, addr), + frame_pointer_rtx); + } + else + emit_insn (gen_blockage ()); } /* no frame pointer needed. */ else @@ -3537,6 +3571,7 @@ pa_output_function_epilogue (file, size) FILE *file; HOST_WIDE_INT size ATTRIBUTE_UNUSED; { + int last_address = 0; rtx insn = get_last_insn (); /* hppa_expand_epilogue does the dirty work now. We just need @@ -3559,9 +3594,36 @@ pa_output_function_epilogue (file, size) /* If insn is a CALL_INSN, then it must be a call to a volatile function (otherwise there would be epilogue insns). */ if (insn && GET_CODE (insn) == CALL_INSN) - fputs ("\tnop\n", file); + { + fputs ("\tnop\n", file); + last_address += 4; + } fputs ("\t.EXIT\n\t.PROCEND\n", file); + + /* Finally, update the total number of code bytes output so far. */ + if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM) + && !flag_function_sections) + { + if (INSN_ADDRESSES_SET_P ()) + { + unsigned long old_total = total_code_bytes; + + insn = get_last_nonnote_insn (); + last_address += INSN_ADDRESSES (INSN_UID (insn)); + if (INSN_P (insn)) + last_address += insn_default_length (insn); + + total_code_bytes += last_address; + total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT; + + /* Be prepared to handle overflows. */ + if (old_total > total_code_bytes) + total_code_bytes = -1; + } + else + total_code_bytes = -1; + } } void @@ -4784,7 +4846,9 @@ output_deferred_plabels (file) /* Now output the deferred plabels. */ for (i = 0; i < n_deferred_plabels; i++) { - ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label)); + rtx label = deferred_plabels[i].internal_label; + + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (label)); assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name), TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1); } @@ -5370,14 +5434,19 @@ output_cbranch (operands, nullify, length, negated, insn) { static char buf[100]; int useskip = 0; + rtx xoperands[5]; - /* A conditional branch to the following instruction (eg the delay slot) is - asking for a disaster. This can happen when not optimizing. - - In such cases it is safe to emit nothing. */ + /* A conditional branch to the following instruction (eg the delay slot) + is asking for a disaster. This can happen when not optimizing and + when jump optimization fails. - if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) - return ""; + While it is usually safe to emit nothing, this can fail if the + preceding instruction is a nullified branch with an empty delay + slot and the same branch target as this branch. We could check + for this but jump optimization should eliminate nop jumps. It + is always safe to emit a nop. */ + if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) + return "nop"; /* If this is a long branch with its delay slot unfilled, set `nullify' as it can nullify the delay slot and save a nop. */ @@ -5475,98 +5544,182 @@ output_cbranch (operands, nullify, length, negated, insn) break; case 20: - /* Very long branch. Right now we only handle these when not - optimizing. See "jump" pattern in pa.md for details. */ - if (optimize) - abort (); + case 28: + xoperands[0] = operands[0]; + xoperands[1] = operands[1]; + xoperands[2] = operands[2]; + xoperands[3] = operands[3]; + + /* The reversed conditional branch must branch over one additional + instruction if the delay slot is filled. If the delay slot + is empty, the instruction after the reversed condition branch + must be nullified. */ + nullify = dbr_sequence_length () == 0; + xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4); /* Create a reversed conditional branch which branches around the following insns. */ - if (negated) - strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}"); + if (GET_MODE (operands[1]) != DImode) + { + if (nullify) + { + if (negated) + strcpy (buf, + "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}"); + else + strcpy (buf, + "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}"); + } + else + { + if (negated) + strcpy (buf, + "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}"); + else + strcpy (buf, + "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}"); + } + } else - strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}"); - if (GET_MODE (operands[1]) == DImode) { - if (negated) - strcpy (buf, - "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}"); + if (nullify) + { + if (negated) + strcpy (buf, + "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}"); + else + strcpy (buf, + "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}"); + } else - strcpy (buf, - "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}"); + { + if (negated) + strcpy (buf, + "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}"); + else + strcpy (buf, + "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}"); + } } - output_asm_insn (buf, operands); - /* Output an insn to save %r1. */ - output_asm_insn ("stw %%r1,-16(%%r30)", operands); + output_asm_insn (buf, xoperands); + return output_lbranch (operands[0], insn); - /* Now output a very long branch to the original target. */ - output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands); + default: + abort (); + } + return buf; +} - /* Now restore the value of %r1 in the delay slot. We're not - optimizing so we know nothing else can be in the delay slot. */ - return "ldw -16(%%r30),%%r1"; +/* This routine handles long unconditional branches that exceed the + maximum range of a simple branch instruction. */ - case 28: - /* Very long branch when generating PIC code. Right now we only - handle these when not optimizing. See "jump" pattern in pa.md - for details. */ - if (optimize) - abort (); +const char * +output_lbranch (dest, insn) + rtx dest, insn; +{ + rtx xoperands[2]; + + xoperands[0] = dest; - /* Create a reversed conditional branch which branches around - the following insns. */ - if (negated) - strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}"); - else - strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}"); - if (GET_MODE (operands[1]) == DImode) - { - if (negated) - strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}"); - else - strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}"); - } - output_asm_insn (buf, operands); + /* First, free up the delay slot. */ + if (dbr_sequence_length () != 0) + { + /* We can't handle a jump in the delay slot. */ + if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN) + abort (); - /* Output an insn to save %r1. */ - output_asm_insn ("stw %%r1,-16(%%r30)", operands); + final_scan_insn (NEXT_INSN (insn), asm_out_file, + optimize, 0, 0); + + /* Now delete the delay insn. */ + PUT_CODE (NEXT_INSN (insn), NOTE); + NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED; + NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0; + } + + /* Output an insn to save %r1. The runtime documentation doesn't + specify whether the "Clean Up" slot in the callers frame can + be clobbered by the callee. It isn't copied by HP's builtin + alloca, so this suggests that it can be clobbered if necessary. + The "Static Link" location is copied by HP builtin alloca, so + we avoid using it. Using the cleanup slot might be a problem + if we have to interoperate with languages that pass cleanup + information. However, it should be possible to handle these + situations with GCC's asm feature. + + The "Current RP" slot is reserved for the called procedure, so + we try to use it when we don't have a frame of our own. It's + rather unlikely that we won't have a frame when we need to emit + a very long branch. + + Really the way to go long term is a register scavenger; goto + the target of the jump and find a register which we can use + as a scratch to hold the value in %r1. Then, we wouldn't have + to free up the delay slot or clobber a slot that may be needed + for other purposes. */ + if (TARGET_64BIT) + { + if (actual_fsize == 0 && !regs_ever_live[2]) + /* Use the return pointer slot in the frame marker. */ + output_asm_insn ("std %%r1,-16(%%r30)", xoperands); + else + /* Use the slot at -40 in the frame marker since HP builtin + alloca doesn't copy it. */ + output_asm_insn ("std %%r1,-40(%%r30)", xoperands); + } + else + { + if (actual_fsize == 0 && !regs_ever_live[2]) + /* Use the return pointer slot in the frame marker. */ + output_asm_insn ("stw %%r1,-20(%%r30)", xoperands); + else + /* Use the "Clean Up" slot in the frame marker. In GCC, + the only other use of this location is for copying a + floating point double argument from a floating-point + register to two general registers. The copy is done + as an "atomic" operation when outputing a call, so it + won't interfere with our using the location here. */ + output_asm_insn ("stw %%r1,-12(%%r30)", xoperands); + } - /* Now output a very long PIC branch to the original target. */ + if (flag_pic) + { + output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); + if (TARGET_SOM || !TARGET_GAS) { - rtx xoperands[5]; - - xoperands[0] = operands[0]; - xoperands[1] = operands[1]; - xoperands[2] = operands[2]; - xoperands[3] = operands[3]; - - output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); - if (TARGET_SOM || !TARGET_GAS) - { - xoperands[4] = gen_label_rtx (); - output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", - CODE_LABEL_NUMBER (xoperands[4])); - output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands); - } - else - { - output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); - output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", - xoperands); - } - output_asm_insn ("bv %%r0(%%r1)", xoperands); + xoperands[1] = gen_label_rtx (); + output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", + CODE_LABEL_NUMBER (xoperands[1])); + output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands); } + else + { + output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands); + output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands); + } + output_asm_insn ("bv %%r0(%%r1)", xoperands); + } + else + /* Now output a very long branch to the original target. */ + output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands); - /* Now restore the value of %r1 in the delay slot. We're not - optimizing so we know nothing else can be in the delay slot. */ - return "ldw -16(%%r30),%%r1"; - - default: - abort (); + /* Now restore the value of %r1 in the delay slot. */ + if (TARGET_64BIT) + { + if (actual_fsize == 0 && !regs_ever_live[2]) + return "ldd -16(%%r30),%%r1"; + else + return "ldd -40(%%r30),%%r1"; + } + else + { + if (actual_fsize == 0 && !regs_ever_live[2]) + return "ldw -20(%%r30),%%r1"; + else + return "ldw -12(%%r30),%%r1"; } - return buf; } /* This routine handles all the branch-on-bit conditional branch sequences we @@ -5589,8 +5742,8 @@ output_bb (operands, nullify, length, negated, insn, which) is only used when optimizing; jump optimization should eliminate the jump. But be prepared just in case. */ - if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) - return ""; + if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) + return "nop"; /* If this is a long branch with its delay slot unfilled, set `nullify' as it can nullify the delay slot and save a nop. */ @@ -5737,8 +5890,8 @@ output_bvb (operands, nullify, length, negated, insn, which) is only used when optimizing; jump optimization should eliminate the jump. But be prepared just in case. */ - if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) - return ""; + if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) + return "nop"; /* If this is a long branch with its delay slot unfilled, set `nullify' as it can nullify the delay slot and save a nop. */ @@ -5878,7 +6031,7 @@ output_dbra (operands, insn, which_alternative) /* A conditional branch to the following instruction (eg the delay slot) is asking for a disaster. Be prepared! */ - if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) + if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) { if (which_alternative == 0) return "ldo %1(%0),%0"; @@ -5985,7 +6138,7 @@ output_movb (operands, insn, which_alternative, reverse_comparison) /* A conditional branch to the following instruction (eg the delay slot) is asking for a disaster. Be prepared! */ - if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn)) + if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn)) { if (which_alternative == 0) return "copy %1,%0"; @@ -6161,37 +6314,42 @@ length_fp_args (insn) return length; } -/* We include the delay slot in the returned length as it is better to +/* Return the attribute length for the millicode call instruction INSN. + The length must match the code generated by output_millicode_call. + We include the delay slot in the returned length as it is better to over estimate the length than to under estimate it. */ int -attr_length_millicode_call (insn, length) +attr_length_millicode_call (insn) rtx insn; - int length; { - unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn)); + unsigned long distance = -1; - if (distance < total_code_bytes) - distance = -1; + if (INSN_ADDRESSES_SET_P ()) + { + distance = (total_code_bytes + insn_current_reference_address (insn)); + if (distance < total_code_bytes) + distance = -1; + } if (TARGET_64BIT) { if (!TARGET_LONG_CALLS && distance < 7600000) - return length + 8; + return 8; - return length + 20; + return 20; } else if (TARGET_PORTABLE_RUNTIME) - return length + 24; + return 24; else { if (!TARGET_LONG_CALLS && distance < 240000) - return length + 8; + return 8; if (TARGET_LONG_ABS_CALL && !flag_pic) - return length + 12; + return 12; - return length + 24; + return 24; } } @@ -6321,16 +6479,22 @@ output_millicode_call (insn, call_dest) /* See if the return address can be adjusted. Use the containing sequence insn's address. */ - seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); - distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) - - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); - - if (VAL_14_BITS_P (distance)) + if (INSN_ADDRESSES_SET_P ()) { - xoperands[1] = gen_label_rtx (); - output_asm_insn ("ldo %0-%1(%2),%2", xoperands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", - CODE_LABEL_NUMBER (xoperands[3])); + seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0))); + distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn)))) + - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8); + + if (VAL_14_BITS_P (distance)) + { + xoperands[1] = gen_label_rtx (); + output_asm_insn ("ldo %0-%1(%2),%2", xoperands); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", + CODE_LABEL_NUMBER (xoperands[1])); + } + else + /* ??? This branch may not reach its target. */ + output_asm_insn ("nop\n\tb,n %0", xoperands); } else /* ??? This branch may not reach its target. */ @@ -6344,18 +6508,25 @@ output_millicode_call (insn, call_dest) return ""; } -/* We include the delay slot in the returned length as it is better to - over estimate the length than to under estimate it. */ +/* Return the attribute length of the call instruction INSN. The SIBCALL + flag indicates whether INSN is a regular call or a sibling call. The + length must match the code generated by output_call. We include the delay + slot in the returned length as it is better to over estimate the length + than to under estimate it. */ int attr_length_call (insn, sibcall) rtx insn; int sibcall; { - unsigned long distance = total_code_bytes + INSN_ADDRESSES (INSN_UID (insn)); + unsigned long distance = -1; - if (distance < total_code_bytes) - distance = -1; + if (INSN_ADDRESSES_SET_P ()) + { + distance = (total_code_bytes + insn_current_reference_address (insn)); + if (distance < total_code_bytes) + distance = -1; + } if (TARGET_64BIT) { @@ -6396,10 +6567,13 @@ attr_length_call (insn, sibcall) if (TARGET_PA_20) return (length + 32); + if (!TARGET_NO_SPACE_REGS) + length += 8; + if (!sibcall) length += 8; - return (length + 40); + return (length + 32); } } } @@ -6417,7 +6591,6 @@ output_call (insn, call_dest, sibcall) { int delay_insn_deleted = 0; int delay_slot_filled = 0; - int attr_length = get_attr_length (insn); int seq_length = dbr_sequence_length (); rtx xoperands[2]; @@ -6425,9 +6598,7 @@ output_call (insn, call_dest, sibcall) /* Handle the common case where we're sure that the branch will reach the beginning of the $CODE$ subspace. */ - if (!TARGET_LONG_CALLS - && ((seq_length == 0 && attr_length == 12) - || (seq_length != 0 && attr_length == 8))) + if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8) { xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2); output_asm_insn ("{bl|b,l} %0,%1", xoperands); @@ -6597,7 +6768,10 @@ output_call (insn, call_dest, sibcall) if (!sibcall && !TARGET_PA_20) { output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands); - output_asm_insn ("addi 16,%%r2,%%r2", xoperands); + if (TARGET_NO_SPACE_REGS) + output_asm_insn ("addi 8,%%r2,%%r2", xoperands); + else + output_asm_insn ("addi 16,%%r2,%%r2", xoperands); } } @@ -6619,14 +6793,23 @@ output_call (insn, call_dest, sibcall) } else { - output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", - xoperands); + if (!TARGET_NO_SPACE_REGS) + output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0", + xoperands); if (sibcall) - output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); + { + if (TARGET_NO_SPACE_REGS) + output_asm_insn ("be 0(%%sr4,%%r1)", xoperands); + else + output_asm_insn ("be 0(%%sr0,%%r1)", xoperands); + } else { - output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); + if (TARGET_NO_SPACE_REGS) + output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands); + else + output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands); if (indirect_call) output_asm_insn ("stw %%r31,-24(%%sp)", xoperands); @@ -6655,7 +6838,7 @@ output_call (insn, call_dest, sibcall) /* This call has an unconditional jump in its delay slot. */ xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1); - if (!delay_slot_filled) + if (!delay_slot_filled && INSN_ADDRESSES_SET_P ()) { /* See if the return address can be adjusted. Use the containing sequence insn's address. */ @@ -6668,7 +6851,7 @@ output_call (insn, call_dest, sibcall) xoperands[1] = gen_label_rtx (); output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands); ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", - CODE_LABEL_NUMBER (xoperands[3])); + CODE_LABEL_NUMBER (xoperands[1])); } else /* ??? This branch may not reach its target. */ @@ -6686,6 +6869,114 @@ output_call (insn, call_dest, sibcall) return ""; } +/* Return the attribute length of the indirect call instruction INSN. + The length must match the code generated by output_indirect call. + The returned length includes the delay slot. Currently, the delay + slot of an indirect call sequence is not exposed and it is used by + the sequence itself. */ + +int +attr_length_indirect_call (insn) + rtx insn; +{ + unsigned long distance = -1; + + if (INSN_ADDRESSES_SET_P ()) + { + distance = (total_code_bytes + insn_current_reference_address (insn)); + if (distance < total_code_bytes) + distance = -1; + } + + if (TARGET_64BIT) + return 12; + + if (TARGET_FAST_INDIRECT_CALLS + || (!TARGET_PORTABLE_RUNTIME + && ((TARGET_PA_20 && distance < 7600000) || distance < 240000))) + return 8; + + if (flag_pic) + return 24; + + if (TARGET_PORTABLE_RUNTIME) + return 20; + + /* Out of reach, can use ble. */ + return 12; +} + +const char * +output_indirect_call (insn, call_dest) + rtx insn; + rtx call_dest; +{ + rtx xoperands[1]; + + if (TARGET_64BIT) + { + xoperands[0] = call_dest; + output_asm_insn ("ldd 16(%0),%%r2", xoperands); + output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands); + return ""; + } + + /* First the special case for kernels, level 0 systems, etc. */ + if (TARGET_FAST_INDIRECT_CALLS) + return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2"; + + /* Now the normal case -- we can reach $$dyncall directly or + we're sure that we can get there via a long-branch stub. + + No need to check target flags as the length uniquely identifies + the remaining cases. */ + if (attr_length_indirect_call (insn) == 8) + return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2"; + + /* Long millicode call, but we are not generating PIC or portable runtime + code. */ + if (attr_length_indirect_call (insn) == 12) + return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2"; + + /* Long millicode call for portable runtime. */ + if (attr_length_indirect_call (insn) == 20) + return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop"; + + /* We need a long PIC call to $$dyncall. */ + xoperands[0] = NULL_RTX; + output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands); + if (TARGET_SOM || !TARGET_GAS) + { + xoperands[0] = gen_label_rtx (); + output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L", + CODE_LABEL_NUMBER (xoperands[0])); + output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands); + } + else + { + output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands); + output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1", + xoperands); + } + output_asm_insn ("blr %%r0,%%r2", xoperands); + output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands); + return ""; +} + +/* Return the total length of the save and restore instructions needed for + the data linkage table pointer (i.e., the PIC register) across the call instruction INSN. No-return calls do not require a save and restore. In addition, we may be able to avoid the save and restore for calls within the same translation unit. */ + +int +attr_length_save_restore_dltp (insn) + rtx insn; +{ + if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) + return 0; + + return 8; +} + /* In HPUX 8.0's shared library scheme, special relocations are needed for function labels if they might be passed to a function in a shared library (because shared libraries don't live in code @@ -6782,7 +7073,7 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) pa_output_function_prologue (file, 0); if (VAL_14_BITS_P (delta)) { - if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic) + if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic) { fprintf (file, "\taddil LT'%s,%%r19\n", lab); fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab); @@ -6791,8 +7082,14 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) fprintf (file, "\tdepi 0,31,2,%%r22\n"); fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); - fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n"); - fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo "); + if (TARGET_NO_SPACE_REGS) + fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo "); + else + { + fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n"); + fprintf (file, "\tmtsp %%r1,%%sr0\n"); + fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo "); + } fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); fprintf (file, "(%%r26),%%r26\n"); } @@ -6805,7 +7102,7 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) } else { - if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic) + if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic) { fprintf (file, "\taddil L'"); fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta); @@ -6819,8 +7116,14 @@ pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) fprintf (file, "\tdepi 0,31,2,%%r22\n"); fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n"); fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n"); - fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n"); - fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n"); + if (TARGET_NO_SPACE_REGS) + fprintf (file, "\tbe 0(%%sr4,%%r22)"); + else + { + fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n"); + fprintf (file, "\tmtsp %%r1,%%sr0\n"); + fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n"); + } } else { @@ -6903,6 +7206,46 @@ fmpyaddoperands (operands) return 1; } +#if !defined(USE_COLLECT2) +static void +pa_asm_out_constructor (symbol, priority) + rtx symbol; + int priority; +{ + if (!function_label_operand (symbol, VOIDmode)) + hppa_encode_label (symbol); + +#ifdef CTORS_SECTION_ASM_OP + default_ctor_section_asm_out_constructor (symbol, priority); +#else +# ifdef TARGET_ASM_NAMED_SECTION + default_named_section_asm_out_constructor (symbol, priority); +# else + default_stabs_asm_out_constructor (symbol, priority); +# endif +#endif +} + +static void +pa_asm_out_destructor (symbol, priority) + rtx symbol; + int priority; +{ + if (!function_label_operand (symbol, VOIDmode)) + hppa_encode_label (symbol); + +#ifdef DTORS_SECTION_ASM_OP + default_dtor_section_asm_out_destructor (symbol, priority); +#else +# ifdef TARGET_ASM_NAMED_SECTION + default_named_section_asm_out_destructor (symbol, priority); +# else + default_stabs_asm_out_destructor (symbol, priority); +# endif +#endif +} +#endif + /* Returns 1 if the 6 operands specified in OPERANDS are suitable for use in fmpysub instructions. */ int @@ -7080,9 +7423,9 @@ jump_in_call_delay (insn) if (PREV_INSN (insn) && PREV_INSN (PREV_INSN (insn)) - && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) + && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN) { - rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn))); + rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn))); return (GET_CODE (PATTERN (test_insn)) == SEQUENCE && XVECEXP (PATTERN (test_insn), 0, 1) == insn); @@ -7737,12 +8080,11 @@ function_value (valtype, func) ??? We might want to restructure this so that it looks more like other ports. */ rtx -function_arg (cum, mode, type, named, incoming) +function_arg (cum, mode, type, named) CUMULATIVE_ARGS *cum; enum machine_mode mode; tree type; int named ATTRIBUTE_UNUSED; - int incoming; { int max_arg_words = (TARGET_64BIT ? 8 : 4); int alignment = 0; @@ -7884,7 +8226,7 @@ function_arg (cum, mode, type, named, incoming) if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32) /* If we are doing soft-float with portable runtime, then there is no need to worry about FP regs. */ - && ! TARGET_SOFT_FLOAT + && !TARGET_SOFT_FLOAT /* The parameter must be some kind of float, else we can just pass it in integer registers. */ && FLOAT_MODE_P (mode) @@ -7893,14 +8235,15 @@ function_arg (cum, mode, type, named, incoming) /* libcalls do not need to pass items in both FP and general registers. */ && type != NULL_TREE - /* All this hair applies to outgoing args only. */ - && ! incoming) + /* All this hair applies to "outgoing" args only. This includes + sibcall arguments setup with FUNCTION_INCOMING_ARG. */ + && !cum->incoming) /* Also pass outgoing floating arguments in both registers in indirect calls with the 32 bit ABI and the HP assembler since there is no way to the specify argument locations in static functions. */ - || (! TARGET_64BIT - && ! TARGET_GAS - && ! incoming + || (!TARGET_64BIT + && !TARGET_GAS + && !cum->incoming && cum->indirect && FLOAT_MODE_P (mode))) { diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 860b7590d98..02791ce466d 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -206,6 +206,20 @@ extern int target_flags; not for external calls. */ #define TARGET_LONG_PIC_PCREL_CALL 0 +/* Define to a C expression evaluating to true to use SOM secondary + definition symbols for weak support. Linker support for secondary + definition symbols is buggy prior to HP-UX 11.X. */ +#define TARGET_SOM_SDEF 0 + +/* Define to a C expression evaluating to true to save the entry value + of SP in the current frame marker. This is normally unnecessary. + However, the HP-UX unwind library looks at the SAVE_SP callinfo flag. + HP compilers don't use this flag but it is supported by the assembler. + We set this flag to indicate that register %r3 has been saved at the + start of the frame. Thus, when the HP unwind library is used, we + need to generate additional code to save SP into the frame marker. */ +#define TARGET_HPUX_UNWIND_LIBRARY 0 + /* Macro to define tables used to set the flags. This is a list in braces of target switches with each switch being { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set, @@ -456,11 +470,12 @@ do { \ /* Boundary (in *bits*) on which stack pointer is always aligned; certain optimizations in combine depend on this. - GCC for the PA always rounds its stacks to a 8 * STACK_BOUNDARY - boundary, but that happens late in the compilation process. */ + The HP-UX runtime documents mandate 64-byte and 16-byte alignment for + the stack on the 32 and 64-bit ports, respectively. However, we + are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT + in main. Thus, we treat the former as the preferred alignment. */ #define STACK_BOUNDARY BIGGEST_ALIGNMENT - -#define PREFERRED_STACK_BOUNDARY (8 * STACK_BOUNDARY) +#define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512) /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY BITS_PER_WORD @@ -706,9 +721,13 @@ extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void)); /* The weird HPPA calling conventions require a minimum of 48 bytes on the stack: 16 bytes for register saves, and 32 bytes for magic. This is the difference between the logical top of stack and the - actual sp. */ + actual sp. + + On the 64-bit port, the HP C compiler allocates a 48-byte frame + marker, although the runtime documentation only describes a 16 + byte marker. For compatibility, we allocate 48 bytes. */ #define STACK_POINTER_OFFSET \ - (TARGET_64BIT ? -(current_function_outgoing_args_size + 16): -32) + (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32) #define STACK_DYNAMIC_OFFSET(FNDECL) \ (TARGET_64BIT \ @@ -751,12 +770,21 @@ extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void)); and about the args processed so far, enough to enable macros such as FUNCTION_ARG to determine where the next arg should go. - On the HP-PA, this is a single integer, which is a number of words + On the HP-PA, the WORDS field holds the number of words of arguments scanned so far (including the invisible argument, - if any, which holds the structure-value-address). - Thus 4 or more means all following args should go on the stack. */ + if any, which holds the structure-value-address). Thus, 4 or + more means all following args should go on the stack. + + The INCOMING field tracks whether this is an "incoming" or + "outgoing" argument. + + The INDIRECT field indicates whether this is is an indirect + call or not. + + The NARGS_PROTOTYPE field indicates that an argument does not + have a prototype when it less than or equal to 0. */ -struct hppa_args {int words, nargs_prototype, indirect; }; +struct hppa_args {int words, nargs_prototype, incoming, indirect; }; #define CUMULATIVE_ARGS struct hppa_args @@ -766,6 +794,7 @@ struct hppa_args {int words, nargs_prototype, indirect; }; #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ (CUM).words = 0, \ + (CUM).incoming = 0, \ (CUM).indirect = INDIRECT, \ (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \ ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \ @@ -780,6 +809,7 @@ struct hppa_args {int words, nargs_prototype, indirect; }; #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \ (CUM).words = 0, \ + (CUM).incoming = 1, \ (CUM).indirect = 0, \ (CUM).nargs_prototype = 1000 @@ -855,7 +885,7 @@ struct hppa_args {int words, nargs_prototype, indirect; }; tempted to try and simply it, but I worry about breaking something. */ #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - function_arg (&CUM, MODE, TYPE, NAMED, 0) + function_arg (&CUM, MODE, TYPE, NAMED) /* Nonzero if we do not know how to pass TYPE solely in registers. */ #define MUST_PASS_IN_STACK(MODE,TYPE) \ @@ -863,9 +893,6 @@ struct hppa_args {int words, nargs_prototype, indirect; }; && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ || TREE_ADDRESSABLE (TYPE))) -#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ - function_arg (&CUM, MODE, TYPE, NAMED, 1) - /* For an arg passed partly in registers and partly in memory, this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 640196b067d..d69e329dc6a 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -1,6 +1,6 @@ ;;- Machine description for HP PA-RISC architecture for GNU C compiler ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -;; 2002 Free Software Foundation, Inc. +;; 2002, 2003 Free Software Foundation, Inc. ;; Contributed by the Center for Software Science at the University ;; of Utah. @@ -625,23 +625,37 @@ [(set_attr "length" "4") (set_attr "type" "fpcc")]) -;; The following two patterns are optimization placeholders. In almost +;; Provide a means to emit the movccfp0 and movccfp1 optimization +;; placeholders. This is necessary in rare situations when a +;; placeholder is re-emitted (see PR 8705). + +(define_expand "movccfp" + [(set (reg:CCFP 0) + (match_operand 0 "const_int_operand" ""))] + "! TARGET_SOFT_FLOAT" + " +{ + if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1) + FAIL; +}") + +;; The following patterns are optimization placeholders. In almost ;; all cases, the user of the condition code will be simplified and the ;; original condition code setting insn should be eliminated. -(define_insn "*setccfp0" +(define_insn "*movccfp0" [(set (reg:CCFP 0) (const_int 0))] "! TARGET_SOFT_FLOAT" - "fcmp,dbl,!= %%fr0,%%fr0" + "fcmp,dbl,= %%fr0,%%fr0" [(set_attr "length" "4") (set_attr "type" "fpcc")]) -(define_insn "*setccfp1" +(define_insn "*movccfp1" [(set (reg:CCFP 0) (const_int 1))] "! TARGET_SOFT_FLOAT" - "fcmp,dbl,= %%fr0,%%fr0" + "fcmp,dbl,!= %%fr0,%%fr0" [(set_attr "length" "4") (set_attr "type" "fpcc")]) @@ -4086,7 +4100,7 @@ "!TARGET_64BIT" "* return output_mul_insn (0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_insn "" [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25))) @@ -4097,7 +4111,7 @@ "TARGET_64BIT" "* return output_mul_insn (0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_expand "muldi3" [(set (match_operand:DI 0 "register_operand" "") @@ -4135,7 +4149,7 @@ emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r)); /* Emit a multiply for the low sub-word. */ - emit_insn (gen_umulsidi3 (low_product, op2r, op1r)); + emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r))); /* Sum the cross products and shift them into proper position. */ emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2)); @@ -4188,7 +4202,7 @@ "* return output_div_insn (operands, 0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_insn "" [(set (reg:SI 29) @@ -4202,7 +4216,7 @@ "* return output_div_insn (operands, 0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_expand "udivsi3" [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) @@ -4245,7 +4259,7 @@ "* return output_div_insn (operands, 1, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_insn "" [(set (reg:SI 29) @@ -4259,7 +4273,7 @@ "* return output_div_insn (operands, 1, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_expand "modsi3" [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) @@ -4298,7 +4312,7 @@ "* return output_mod_insn (0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_insn "" [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25))) @@ -4311,7 +4325,7 @@ "* return output_mod_insn (0, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_expand "umodsi3" [(set (reg:SI 26) (match_operand:SI 1 "move_operand" "")) @@ -4350,7 +4364,7 @@ "* return output_mod_insn (1, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) (define_insn "" [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25))) @@ -4363,7 +4377,7 @@ "* return output_mod_insn (1, insn);" [(set_attr "type" "milli") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 0)"))]) + (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))]) ;;- and instructions ;; We define DImode `and` so with DImode `not` we can get @@ -5614,23 +5628,7 @@ [(return) (use (reg:SI 2)) (const_int 1)] - "! flag_pic" - "* -{ - if (TARGET_PA_20) - return \"bve%* (%%r2)\"; - return \"bv%* %%r0(%%r2)\"; -}" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - -;; Use the PIC register to ensure it's restored after a -;; call in PIC mode. -(define_insn "return_internal_pic" - [(return) - (use (match_operand 0 "register_operand" "r")) - (use (reg:SI 2))] - "flag_pic && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM" + "" "* { if (TARGET_PA_20) @@ -5640,17 +5638,14 @@ [(set_attr "type" "branch") (set_attr "length" "4")]) -;; Use the PIC register to ensure it's restored after a -;; call in PIC mode. This is used for eh returns which -;; bypass the return stub. +;; This is used for eh returns which bypass the return stub. (define_insn "return_external_pic" [(return) - (use (match_operand 0 "register_operand" "r")) - (use (reg:SI 2)) - (clobber (reg:SI 1))] - "flag_pic - && current_function_calls_eh_return - && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM" + (clobber (reg:SI 1)) + (use (reg:SI 2))] + "!TARGET_NO_SPACE_REGS + && !TARGET_PA_20 + && flag_pic && current_function_calls_eh_return" "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)" [(set_attr "type" "branch") (set_attr "length" "12")]) @@ -5683,20 +5678,18 @@ rtx x; hppa_expand_epilogue (); - if (flag_pic) - { - rtx pic = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM); - /* EH returns bypass the normal return stub. Thus, we must do an - interspace branch to return from functions that call eh_return. - This is only a problem for returns from shared code. */ - if (current_function_calls_eh_return) - x = gen_return_external_pic (pic); - else - x = gen_return_internal_pic (pic); - } + /* EH returns bypass the normal return stub. Thus, we must do an + interspace branch to return from functions that call eh_return. + This is only a problem for returns from shared code on ports + using space registers. */ + if (!TARGET_NO_SPACE_REGS + && !TARGET_PA_20 + && flag_pic && current_function_calls_eh_return) + x = gen_return_external_pic (); else x = gen_return_internal (); + emit_jump_insn (x); } DONE; @@ -5742,8 +5735,6 @@ "" "* { - extern int optimize; - if (GET_MODE (insn) == SImode) return \"b %l0%#\"; @@ -5752,61 +5743,7 @@ && get_attr_length (insn) != 16) return \"b%* %l0\"; - /* An unconditional branch which can not reach its target. - - We need to be able to use %r1 as a scratch register; however, - we can never be sure whether or not it's got a live value in - it. Therefore, we must restore its original value after the - jump. - - To make matters worse, we don't have a stack slot which we - can always clobber. sp-12/sp-16 shouldn't ever have a live - value during a non-optimizing compilation, so we use those - slots for now. We don't support very long branches when - optimizing -- they should be quite rare when optimizing. - - Really the way to go long term is a register scavenger; goto - the target of the jump and find a register which we can use - as a scratch to hold the value in %r1. */ - - /* We don't know how to register scavenge yet. */ - if (optimize) - abort (); - - /* First store %r1 into the stack. */ - output_asm_insn (\"stw %%r1,-16(%%r30)\", operands); - - /* Now load the target address into %r1 and do an indirect jump - to the value specified in %r1. Be careful to generate PIC - code as needed. */ - if (flag_pic) - { - rtx xoperands[2]; - xoperands[0] = operands[0]; - if (TARGET_SOM || ! TARGET_GAS) - { - xoperands[1] = gen_label_rtx (); - - output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\", - xoperands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xoperands[1])); - output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\", xoperands); - } - else - { - output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands); - output_asm_insn (\"addil L'%l0-$PIC_pcrel$0+4,%%r1\", xoperands); - output_asm_insn (\"ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1\", xoperands); - } - output_asm_insn (\"bv %%r0(%%r1)\", xoperands); - } - else - output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);; - - /* And restore the value of %r1 in the delay slot. We're not optimizing, - so we know nothing else can be in the delay slot. */ - return \"ldw -16(%%r30),%%r1\"; + return output_lbranch (operands[0], insn); }" [(set_attr "type" "uncond_branch") (set_attr "pa_combine_type" "uncond_branch") @@ -5901,8 +5838,8 @@ "" " { - rtx op; - rtx call_insn; + rtx op, call_insn; + rtx nb = operands[1]; if (TARGET_PORTABLE_RUNTIME) op = force_reg (SImode, XEXP (operands[0], 0)); @@ -5910,51 +5847,127 @@ op = XEXP (operands[0], 0); if (TARGET_64BIT) - emit_move_insn (arg_pointer_rtx, - gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, - GEN_INT (64))); + { + if (!virtuals_instantiated) + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, + GEN_INT (64))); + else + { + /* The loop pass can generate new libcalls after the virtual + registers are instantiated when fpregs are disabled because + the only method that we have for doing DImode multiplication + is with a libcall. This could be trouble if we haven't + allocated enough space for the outgoing arguments. */ + if (INTVAL (nb) > current_function_outgoing_args_size) + abort (); + + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + 64))); + } + } /* Use two different patterns for calls to explicitly named functions and calls through function pointers. This is necessary as these two types of calls use different calling conventions, and CSE might try to change the named call into an indirect call in some cases (using - two patterns keeps CSE from performing this optimization). */ - if (GET_CODE (op) == SYMBOL_REF) - call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1])); - else if (TARGET_64BIT) + two patterns keeps CSE from performing this optimization). + + We now use even more call patterns as there was a subtle bug in + attempting to restore the pic register after a call using a simple + move insn. During reload, a instruction involving a pseudo register + with no explicit dependence on the PIC register can be converted + to an equivalent load from memory using the PIC register. If we + emit a simple move to restore the PIC register in the initial rtl + generation, then it can potentially be repositioned during scheduling. + and an instruction that eventually uses the PIC register may end up + between the call and the PIC register restore. + + This only worked because there is a post call group of instructions + that are scheduled with the call. These instructions are included + in the same basic block as the call. However, calls can throw in + C++ code and a basic block has to terminate at the call if the call + can throw. This results in the PIC register restore being scheduled + independently from the call. So, we now hide the save and restore + of the PIC register in the call pattern until after reload. Then, + we split the moves out. A small side benefit is that we now don't + need to have a use of the PIC register in the return pattern and + the final save/restore operation is not needed. + + I elected to just clobber %r4 in the PIC patterns and use it instead + of trying to force hppa_pic_save_rtx () to a callee saved register. + This might have required a new register class and constraint. It + was also simpler to just handle the restore from a register than a + generic pseudo. */ + if (TARGET_64BIT) { - rtx tmpreg = force_reg (word_mode, op); - call_insn = emit_call_insn (gen_call_internal_reg_64bit (tmpreg, - operands[1])); + if (GET_CODE (op) == SYMBOL_REF) + call_insn = emit_call_insn (gen_call_symref_64bit (op, nb)); + else + { + op = force_reg (word_mode, op); + call_insn = emit_call_insn (gen_call_reg_64bit (op, nb)); + } } else { - rtx tmpreg = gen_rtx_REG (word_mode, 22); - emit_move_insn (tmpreg, force_reg (word_mode, op)); - call_insn = emit_call_insn (gen_call_internal_reg (operands[1])); - } - - if (TARGET_64BIT) - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); - - if (flag_pic) - { - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); + if (GET_CODE (op) == SYMBOL_REF) + { + if (flag_pic) + call_insn = emit_call_insn (gen_call_symref_pic (op, nb)); + else + call_insn = emit_call_insn (gen_call_symref (op, nb)); + } + else + { + rtx tmpreg = gen_rtx_REG (word_mode, 22); - /* After each call we must restore the PIC register, even if it - doesn't appear to be used. */ - emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); + emit_move_insn (tmpreg, force_reg (word_mode, op)); + if (flag_pic) + call_insn = emit_call_insn (gen_call_reg_pic (nb)); + else + call_insn = emit_call_insn (gen_call_reg (nb)); + } } + DONE; }") -(define_insn "call_internal_symref" +;; We use function calls to set the attribute length of calls and millicode +;; calls. This is necessary because of the large variety of call sequences. +;; Implementing the calculation in rtl is difficult as well as ugly. As +;; we need the same calculation in several places, maintenance becomes a +;; nightmare. +;; +;; However, this has a subtle impact on branch shortening. When the +;; expression used to set the length attribute of an instruction depends +;; on a relative address (e.g., pc or a branch address), genattrtab +;; notes that the insn's length is variable, and attempts to determine a +;; worst-case default length and code to compute an insn's current length. + +;; The use of a function call hides the variable dependence of our calls +;; and millicode calls. The result is genattrtab doesn't treat the operation +;; as variable and it only generates code for the default case using our +;; function call. Because of this, calls and millicode calls have a fixed +;; length in the branch shortening pass, and some branches will use a longer +;; code sequence than necessary. However, the length of any given call +;; will still reflect its final code location and it may be shorter than +;; the initial length estimate. + +;; It's possible to trick genattrtab by adding an expression involving `pc' +;; in the set. However, when genattrtab hits a function call in its attempt +;; to compute the default length, it marks the result as unknown and sets +;; the default result to MAX_INT ;-( One possible fix that would allow +;; calls to participate in branch shortening would be to make the call to ;; insn_default_length a target option. Then, we could massage unknown ;; results. Another fix might be to change genattrtab so that it just does ;; the call in the variable case as it already does for the fixed case. + +(define_insn "call_symref" [(call (mem:SI (match_operand 0 "call_operand_address" "")) (match_operand 1 "" "i")) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (use (const_int 0))] - "! TARGET_PORTABLE_RUNTIME" + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" "* { output_arg_descriptor (insn); @@ -5963,102 +5976,356 @@ [(set_attr "type" "call") (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) -(define_insn "call_internal_reg_64bit" - [(call (mem:SI (match_operand:DI 0 "register_operand" "r")) +(define_insn "call_symref_pic" + [(call (mem:SI (match_operand 0 "call_operand_address" "")) (match_operand 1 "" "i")) + (clobber (reg:SI 1)) (clobber (reg:SI 2)) - (use (const_int 1))] + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[0], 0); +}" + [(set_attr "type" "call") + (set (attr "length") + (plus (symbol_ref "attr_length_call (insn, 0)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))])] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:SI 4) (reg:SI 19)) + (parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))]) + (set (reg:SI 19) (reg:SI 4))] + "") + +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))])] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed" + [(parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))])] + "") + +(define_insn "*call_symref_pic_post_reload" + [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "i")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[0], 0); +}" + [(set_attr "type" "call") + (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) + +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_symref_64bit" + [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "i")) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))] "TARGET_64BIT" "* { - /* ??? Needs more work. Length computation, split into multiple insns, - expose delay slot. */ - return \"ldd 16(%0),%%r2\;bve,l (%%r2),%%r2\;ldd 24(%0),%%r27\"; + output_arg_descriptor (insn); + return output_call (insn, operands[0], 0); }" - [(set_attr "type" "dyncall") - (set (attr "length") (const_int 12))]) + [(set_attr "type" "call") + (set (attr "length") + (plus (symbol_ref "attr_length_call (insn, 0)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "")) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:DI 4) (reg:DI 27)) + (parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))]) + (set (reg:DI 27) (reg:DI 4))] + "") -(define_insn "call_internal_reg" +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "")) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "TARGET_64BIT && reload_completed" + [(parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "") + +(define_insn "*call_symref_64bit_post_reload" + [(call (mem:SI (match_operand 0 "call_operand_address" "")) + (match_operand 1 "" "i")) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))] + "TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[0], 0); +}" + [(set_attr "type" "call") + (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) + +(define_insn "call_reg" [(call (mem:SI (reg:SI 22)) (match_operand 0 "" "i")) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (use (const_int 1))] - "" + "!TARGET_64BIT" "* { - rtx xoperands[2]; + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) - /* First the special case for kernels, level 0 systems, etc. */ - if (TARGET_FAST_INDIRECT_CALLS) - return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\"; +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_reg_pic" + [(call (mem:SI (reg:SI 22)) + (match_operand 0 "" "i")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))] + "!TARGET_64BIT" + "* +{ + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") + (plus (symbol_ref "attr_length_indirect_call (insn)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(call (mem:SI (reg:SI 22)) + (match_operand 0 "" "")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))])] + "!TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:SI 4) (reg:SI 19)) + (parallel [(call (mem:SI (reg:SI 22)) + (match_dup 0)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))]) + (set (reg:SI 19) (reg:SI 4))] + "") - /* Now the normal case -- we can reach $$dyncall directly or - we're sure that we can get there via a long-branch stub. +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(call (mem:SI (reg:SI 22)) + (match_operand 0 "" "")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))])] + "!TARGET_64BIT && reload_completed" + [(parallel [(call (mem:SI (reg:SI 22)) + (match_dup 0)) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))])] + "") - No need to check target flags as the length uniquely identifies - the remaining cases. */ - if (get_attr_length (insn) == 8) - return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\"; +(define_insn "*call_reg_pic_post_reload" + [(call (mem:SI (reg:SI 22)) + (match_operand 0 "" "i")) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))] + "!TARGET_64BIT" + "* +{ + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) - /* Long millicode call, but we are not generating PIC or portable runtime - code. */ - if (get_attr_length (insn) == 12) - return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\"; +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_reg_64bit" + [(call (mem:SI (match_operand:DI 0 "register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))] + "TARGET_64BIT" + "* +{ + return output_indirect_call (insn, operands[0]); +}" + [(set_attr "type" "dyncall") + (set (attr "length") + (plus (symbol_ref "attr_length_indirect_call (insn)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(call (mem:SI (match_operand 0 "register_operand" "")) + (match_operand 1 "" "")) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:DI 4) (reg:DI 27)) + (parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))]) + (set (reg:DI 27) (reg:DI 4))] + "") - /* Long millicode call for portable runtime. */ - if (get_attr_length (insn) == 20) - return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\"; +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(call (mem:SI (match_operand 0 "register_operand" "")) + (match_operand 1 "" "")) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "TARGET_64BIT && reload_completed" + [(parallel [(call (mem:SI (match_dup 0)) + (match_dup 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "") - /* If we're generating PIC code. */ - xoperands[0] = operands[0]; - if (TARGET_SOM || ! TARGET_GAS) - xoperands[1] = gen_label_rtx (); - output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands); - if (TARGET_SOM || ! TARGET_GAS) - { - output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xoperands[1])); - output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands); - } - else - { - output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands); - output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\", - xoperands); - } - output_asm_insn (\"blr %%r0,%%r2\", xoperands); - output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands); - return \"\"; +(define_insn "*call_reg_64bit_post_reload" + [(call (mem:SI (match_operand:DI 0 "register_operand" "r")) + (match_operand 1 "" "i")) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))] + "TARGET_64BIT" + "* +{ + return output_indirect_call (insn, operands[0]); }" [(set_attr "type" "dyncall") - (set (attr "length") - (cond [ -;; First FAST_INDIRECT_CALLS - (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS") - (const_int 0)) - (const_int 8) - -;; Target (or stub) within reach - (and (lt (plus (symbol_ref "total_code_bytes") (pc)) - (const_int 240000)) - (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") - (const_int 0))) - (const_int 8) - -;; Out of reach PIC - (ne (symbol_ref "flag_pic") - (const_int 0)) - (const_int 24) - -;; Out of reach PORTABLE_RUNTIME - (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") - (const_int 0)) - (const_int 20)] - -;; Out of reach, can use ble - (const_int 12)))]) + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) (define_expand "call_value" [(parallel [(set (match_operand 0 "" "") @@ -6068,67 +6335,111 @@ "" " { - rtx op; - rtx call_insn; + rtx op, call_insn; + rtx dst = operands[0]; + rtx nb = operands[2]; if (TARGET_PORTABLE_RUNTIME) - op = force_reg (word_mode, XEXP (operands[1], 0)); + op = force_reg (SImode, XEXP (operands[1], 0)); else op = XEXP (operands[1], 0); if (TARGET_64BIT) - emit_move_insn (arg_pointer_rtx, - gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, - GEN_INT (64))); + { + if (!virtuals_instantiated) + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, + GEN_INT (64))); + else + { + /* The loop pass can generate new libcalls after the virtual + registers are instantiated when fpregs are disabled because + the only method that we have for doing DImode multiplication + is with a libcall. This could be trouble if we haven't + allocated enough space for the outgoing arguments. */ + if (INTVAL (nb) > current_function_outgoing_args_size) + abort (); + + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + 64))); + } + } /* Use two different patterns for calls to explicitly named functions and calls through function pointers. This is necessary as these two types of calls use different calling conventions, and CSE might try to change the named call into an indirect call in some cases (using - two patterns keeps CSE from performing this optimization). */ - if (GET_CODE (op) == SYMBOL_REF) - call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0], - op, - operands[2])); - else if (TARGET_64BIT) + two patterns keeps CSE from performing this optimization). + + We now use even more call patterns as there was a subtle bug in + attempting to restore the pic register after a call using a simple + move insn. During reload, a instruction involving a pseudo register + with no explicit dependence on the PIC register can be converted + to an equivalent load from memory using the PIC register. If we + emit a simple move to restore the PIC register in the initial rtl + generation, then it can potentially be repositioned during scheduling. + and an instruction that eventually uses the PIC register may end up + between the call and the PIC register restore. + + This only worked because there is a post call group of instructions + that are scheduled with the call. These instructions are included + in the same basic block as the call. However, calls can throw in + C++ code and a basic block has to terminate at the call if the call + can throw. This results in the PIC register restore being scheduled + independently from the call. So, we now hide the save and restore + of the PIC register in the call pattern until after reload. Then, + we split the moves out. A small side benefit is that we now don't + need to have a use of the PIC register in the return pattern and + the final save/restore operation is not needed. + + I elected to just clobber %r4 in the PIC patterns and use it instead + of trying to force hppa_pic_save_rtx () to a callee saved register. + This might have required a new register class and constraint. It + was also simpler to just handle the restore from a register than a + generic pseudo. */ + if (TARGET_64BIT) { - rtx tmpreg = force_reg (word_mode, op); - call_insn - = emit_call_insn (gen_call_value_internal_reg_64bit (operands[0], - tmpreg, - operands[2])); + if (GET_CODE (op) == SYMBOL_REF) + call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb)); + else + { + op = force_reg (word_mode, op); + call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb)); + } } else { - rtx tmpreg = gen_rtx_REG (word_mode, 22); - emit_move_insn (tmpreg, force_reg (word_mode, op)); - call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0], - operands[2])); - } - - if (TARGET_64BIT) - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); - - if (flag_pic) - { - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); + if (GET_CODE (op) == SYMBOL_REF) + { + if (flag_pic) + call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb)); + else + call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb)); + } + else + { + rtx tmpreg = gen_rtx_REG (word_mode, 22); - /* After each call we must restore the PIC register, even if it - doesn't appear to be used. */ - emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); + emit_move_insn (tmpreg, force_reg (word_mode, op)); + if (flag_pic) + call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb)); + else + call_insn = emit_call_insn (gen_call_val_reg (dst, nb)); + } } + DONE; }") -(define_insn "call_value_internal_symref" +(define_insn "call_val_symref" [(set (match_operand 0 "" "") (call (mem:SI (match_operand 1 "call_operand_address" "")) (match_operand 2 "" "i"))) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (use (const_int 0))] - ;;- Don't use operand 1 for most machines. - "! TARGET_PORTABLE_RUNTIME" + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" "* { output_arg_descriptor (insn); @@ -6137,104 +6448,380 @@ [(set_attr "type" "call") (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) -(define_insn "call_value_internal_reg_64bit" +(define_insn "call_val_symref_pic" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:DI 1 "register_operand" "r")) - (match_operand 2 "" "i"))) + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" "i"))) + (clobber (reg:SI 1)) (clobber (reg:SI 2)) - (use (const_int 1))] + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[1], 0); +}" + [(set_attr "type" "call") + (set (attr "length") + (plus (symbol_ref "attr_length_call (insn, 0)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" ""))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))])] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:SI 4) (reg:SI 19)) + (parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))]) + (set (reg:SI 19) (reg:SI 4))] + "") + +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" ""))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 0))])] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed" + [(parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))])] + "") + +(define_insn "*call_val_symref_pic_post_reload" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" "i"))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 0))] + "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[1], 0); +}" + [(set_attr "type" "call") + (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) + +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_val_symref_64bit" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" "i"))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))] "TARGET_64BIT" "* { - /* ??? Needs more work. Length computation, split into multiple insns, - expose delay slot. */ - return \"ldd 16(%1),%%r2\;bve,l (%%r2),%%r2\;ldd 24(%1),%%r27\"; + output_arg_descriptor (insn); + return output_call (insn, operands[1], 0); }" - [(set_attr "type" "dyncall") - (set (attr "length") (const_int 12))]) + [(set_attr "type" "call") + (set (attr "length") + (plus (symbol_ref "attr_length_call (insn, 0)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" ""))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:DI 4) (reg:DI 27)) + (parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))]) + (set (reg:DI 27) (reg:DI 4))] + "") + +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" ""))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "TARGET_64BIT && reload_completed" + [(parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))])] + "") -(define_insn "call_value_internal_reg" +(define_insn "*call_val_symref_64bit_post_reload" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand 1 "call_operand_address" "")) + (match_operand 2 "" "i"))) + (clobber (reg:DI 1)) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 0))] + "TARGET_64BIT" + "* +{ + output_arg_descriptor (insn); + return output_call (insn, operands[1], 0); +}" + [(set_attr "type" "call") + (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))]) + +(define_insn "call_val_reg" [(set (match_operand 0 "" "") (call (mem:SI (reg:SI 22)) (match_operand 1 "" "i"))) (clobber (reg:SI 1)) (clobber (reg:SI 2)) (use (const_int 1))] - "" + "!TARGET_64BIT" "* { - rtx xoperands[2]; + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) - /* First the special case for kernels, level 0 systems, etc. */ - if (TARGET_FAST_INDIRECT_CALLS) - return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\"; +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_val_reg_pic" + [(set (match_operand 0 "" "") + (call (mem:SI (reg:SI 22)) + (match_operand 1 "" "i"))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))] + "!TARGET_64BIT" + "* +{ + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") + (plus (symbol_ref "attr_length_indirect_call (insn)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (reg:SI 22)) + (match_operand 1 "" ""))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))])] + "!TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:SI 4) (reg:SI 19)) + (parallel [(set (match_dup 0) + (call (mem:SI (reg:SI 22)) + (match_dup 1))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))]) + (set (reg:SI 19) (reg:SI 4))] + "") - /* Now the normal case -- we can reach $$dyncall directly or - we're sure that we can get there via a long-branch stub. +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (reg:SI 22)) + (match_operand 1 "" ""))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (clobber (reg:SI 4)) + (use (reg:SI 19)) + (use (const_int 1))])] + "!TARGET_64BIT && reload_completed" + [(parallel [(set (match_dup 0) + (call (mem:SI (reg:SI 22)) + (match_dup 1))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))])] + "") - No need to check target flags as the length uniquely identifies - the remaining cases. */ - if (get_attr_length (insn) == 8) - return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\"; +(define_insn "*call_val_reg_pic_post_reload" + [(set (match_operand 0 "" "") + (call (mem:SI (reg:SI 22)) + (match_operand 1 "" "i"))) + (clobber (reg:SI 1)) + (clobber (reg:SI 2)) + (use (reg:SI 19)) + (use (const_int 1))] + "!TARGET_64BIT" + "* +{ + return output_indirect_call (insn, gen_rtx_REG (word_mode, 22)); +}" + [(set_attr "type" "dyncall") + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) - /* Long millicode call, but we are not generating PIC or portable runtime - code. */ - if (get_attr_length (insn) == 12) - return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\"; +;; This pattern is split if it is necessary to save and restore the +;; PIC register. +(define_insn "call_val_reg_64bit" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))] + "TARGET_64BIT" + "* +{ + return output_indirect_call (insn, operands[1]); +}" + [(set_attr "type" "dyncall") + (set (attr "length") + (plus (symbol_ref "attr_length_indirect_call (insn)") + (symbol_ref "attr_length_save_restore_dltp (insn)")))]) + +;; Split out the PIC register save and restore after reload. This is +;; done only if the function returns. As the split is done after reload, +;; there are some situations in which we unnecessarily save and restore +;; %r4. This happens when there is a single call and the PIC register +;; is "dead" after the call. This isn't easy to fix as the usage of +;; the PIC register isn't completely determined until the reload pass. +(define_split + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "register_operand" "")) + (match_operand 2 "" ""))) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "TARGET_64BIT + && reload_completed + && !find_reg_note (insn, REG_NORETURN, NULL_RTX)" + [(set (reg:DI 4) (reg:DI 27)) + (parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))]) + (set (reg:DI 27) (reg:DI 4))] + "") - /* Long millicode call for portable runtime. */ - if (get_attr_length (insn) == 20) - return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\"; +;; Remove the clobber of register 4 when optimizing. This has to be +;; done with a peephole optimization rather than a split because the +;; split sequence for a call must be longer than one instruction. +(define_peephole2 + [(parallel [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "register_operand" "")) + (match_operand 2 "" ""))) + (clobber (reg:DI 2)) + (clobber (reg:DI 4)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "TARGET_64BIT && reload_completed" + [(parallel [(set (match_dup 0) + (call (mem:SI (match_dup 1)) + (match_dup 2))) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))])] + "") - /* If we're generating PIC code. */ - xoperands[0] = operands[1]; - if (TARGET_SOM || ! TARGET_GAS) - xoperands[1] = gen_label_rtx (); - output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands); - if (TARGET_SOM || ! TARGET_GAS) - { - output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands); - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", - CODE_LABEL_NUMBER (xoperands[1])); - output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands); - } - else - { - output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands); - output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\", - xoperands); - } - output_asm_insn (\"blr %%r0,%%r2\", xoperands); - output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands); - return \"\"; +(define_insn "*call_val_reg_64bit_post_reload" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "register_operand" "r")) + (match_operand 2 "" "i"))) + (clobber (reg:DI 2)) + (use (reg:DI 27)) + (use (reg:DI 29)) + (use (const_int 1))] + "TARGET_64BIT" + "* +{ + return output_indirect_call (insn, operands[1]); }" [(set_attr "type" "dyncall") - (set (attr "length") - (cond [ -;; First FAST_INDIRECT_CALLS - (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS") - (const_int 0)) - (const_int 8) - -;; Target (or stub) within reach - (and (lt (plus (symbol_ref "total_code_bytes") (pc)) - (const_int 240000)) - (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") - (const_int 0))) - (const_int 8) - -;; Out of reach PIC - (ne (symbol_ref "flag_pic") - (const_int 0)) - (const_int 24) - -;; Out of reach PORTABLE_RUNTIME - (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") - (const_int 0)) - (const_int 20)] - -;; Out of reach, can use ble - (const_int 12)))]) + (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))]) ;; Call subroutine returning any type. @@ -6271,15 +6858,32 @@ "!TARGET_PORTABLE_RUNTIME" " { - rtx op; - rtx call_insn; + rtx op, call_insn; + rtx nb = operands[1]; op = XEXP (operands[0], 0); if (TARGET_64BIT) - emit_move_insn (arg_pointer_rtx, - gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, - GEN_INT (64))); + { + if (!virtuals_instantiated) + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, + GEN_INT (64))); + else + { + /* The loop pass can generate new libcalls after the virtual + registers are instantiated when fpregs are disabled because + the only method that we have for doing DImode multiplication + is with a libcall. This could be trouble if we haven't + allocated enough space for the outgoing arguments. */ + if (INTVAL (nb) > current_function_outgoing_args_size) + abort (); + + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + 64))); + } + } /* Indirect sibling calls are not allowed. */ if (TARGET_64BIT) @@ -6292,14 +6896,10 @@ if (TARGET_64BIT) use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); + /* We don't have to restore the PIC register. */ if (flag_pic) - { - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); + use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); - /* After each call we must restore the PIC register, even if it - doesn't appear to be used. */ - emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); - } DONE; }") @@ -6321,9 +6921,8 @@ (define_insn "sibcall_internal_symref_64bit" [(call (mem:SI (match_operand 0 "call_operand_address" "")) (match_operand 1 "" "i")) - (clobber (reg:SI 1)) - (clobber (reg:SI 27)) - (use (reg:SI 2)) + (clobber (reg:DI 1)) + (use (reg:DI 2)) (use (const_int 0))] "TARGET_64BIT" "* @@ -6341,15 +6940,32 @@ "!TARGET_PORTABLE_RUNTIME" " { - rtx op; - rtx call_insn; + rtx op, call_insn; + rtx nb = operands[1]; op = XEXP (operands[1], 0); if (TARGET_64BIT) - emit_move_insn (arg_pointer_rtx, - gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, - GEN_INT (64))); + { + if (!virtuals_instantiated) + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx, + GEN_INT (64))); + else + { + /* The loop pass can generate new libcalls after the virtual + registers are instantiated when fpregs are disabled because + the only method that we have for doing DImode multiplication + is with a libcall. This could be trouble if we haven't + allocated enough space for the outgoing arguments. */ + if (INTVAL (nb) > current_function_outgoing_args_size) + abort (); + + emit_move_insn (arg_pointer_rtx, + gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (STACK_POINTER_OFFSET + 64))); + } + } /* Indirect sibling calls are not allowed. */ if (TARGET_64BIT) @@ -6364,14 +6980,10 @@ if (TARGET_64BIT) use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx); + /* We don't have to restore the PIC register. */ if (flag_pic) - { - use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); + use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx); - /* After each call we must restore the PIC register, even if it - doesn't appear to be used. */ - emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); - } DONE; }") @@ -6395,9 +7007,8 @@ [(set (match_operand 0 "" "") (call (mem:SI (match_operand 1 "call_operand_address" "")) (match_operand 2 "" "i"))) - (clobber (reg:SI 1)) - (clobber (reg:SI 27)) - (use (reg:SI 2)) + (clobber (reg:DI 1)) + (use (reg:DI 2)) (use (const_int 0))] "TARGET_64BIT" "* @@ -6447,7 +7058,8 @@ ;;; EH does longjmp's from and within the data section. Thus, ;;; an interspace branch is required for the longjmp implementation. -;;; Registers r1 and r2 are used as scratch registers for the jump. +;;; Registers r1 and r2 are used as scratch registers for the jump +;;; when necessary. (define_expand "interspace_jump" [(parallel [(set (pc) (match_operand 0 "pmode_register_operand" "a")) @@ -6461,6 +7073,22 @@ (define_insn "" [(set (pc) (match_operand 0 "pmode_register_operand" "a")) (clobber (reg:SI 2))] + "TARGET_PA_20 && !TARGET_64BIT" + "bve%* (%0)" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "" + [(set (pc) (match_operand 0 "pmode_register_operand" "a")) + (clobber (reg:SI 2))] + "TARGET_NO_SPACE_REGS && !TARGET_64BIT" + "be%* 0(%%sr4,%0)" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "" + [(set (pc) (match_operand 0 "pmode_register_operand" "a")) + (clobber (reg:SI 2))] "!TARGET_64BIT" "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)" [(set_attr "type" "branch") @@ -6470,9 +7098,9 @@ [(set (pc) (match_operand 0 "pmode_register_operand" "a")) (clobber (reg:DI 2))] "TARGET_64BIT" - "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)" + "bve%* (%0)" [(set_attr "type" "branch") - (set_attr "length" "12")]) + (set_attr "length" "4")]) (define_expand "builtin_longjmp" [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] @@ -6523,6 +7151,10 @@ "" " { + /* PA extraction insns don't support zero length bitfields. */ + if (INTVAL (operands[2]) == 0) + FAIL; + if (TARGET_64BIT) emit_insn (gen_extzv_64 (operands[0], operands[1], operands[2], operands[3])); @@ -6585,6 +7217,10 @@ "" " { + /* PA extraction insns don't support zero length bitfields. */ + if (INTVAL (operands[2]) == 0) + FAIL; + if (TARGET_64BIT) emit_insn (gen_extv_64 (operands[0], operands[1], operands[2], operands[3])); @@ -7340,7 +7976,9 @@ \"$$sh_func_adrs\")); }" [(set_attr "type" "multi") - (set (attr "length") (symbol_ref "attr_length_millicode_call (insn, 20)"))]) + (set (attr "length") + (plus (symbol_ref "attr_length_millicode_call (insn)") + (const_int 20)))]) ;; On the PA, the PIC register is call clobbered, so it must ;; be saved & restored around calls by the caller. If the call @@ -7361,6 +7999,7 @@ /* Restore the PIC register using hppa_pic_save_rtx (). The PIC register is not saved in the frame in 64-bit ABI. */ emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); + emit_insn (gen_blockage ()); DONE; }") @@ -7375,5 +8014,41 @@ a stack slot. The only registers that are valid after a builtin_longjmp are the stack and frame pointers. */ emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ()); + emit_insn (gen_blockage ()); + DONE; +}") + +;; Allocate new stack space and update the saved stack pointer in the +;; frame marker. The HP C compilers also copy additional words in the +;; frame marker. The 64-bit compiler copies words at -48, -32 and -24. +;; The 32-bit compiler copies the word at -16 (Static Link). We +;; currently don't copy these values. +;; +;; Since the copy of the frame marker can't be done atomically, I +;; suspect that using it for unwind purposes may be somewhat unreliable. +;; The HP compilers appear to raise the stack and copy the frame +;; marker in a strict instruction sequence. This suggests that the +;; unwind library may check for an alloca sequence when ALLOCA_FRAME +;; is set in the callinfo data. We currently don't set ALLOCA_FRAME +;; as GAS doesn't support it, or try to keep the instructions emitted +;; here in strict sequence. +(define_expand "allocate_stack" + [(match_operand 0 "" "") + (match_operand 1 "" "")] + "" + " +{ + /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx + in operand 0 before adjusting the stack. */ + emit_move_insn (operands[0], virtual_stack_dynamic_rtx); + anti_adjust_stack (operands[1]); + if (TARGET_HPUX_UNWIND_LIBRARY) + { + rtx dst = gen_rtx_MEM (word_mode, + gen_rtx_PLUS (word_mode, stack_pointer_rtx, + GEN_INT (TARGET_64BIT ? -8 : -4))); + + emit_move_insn (dst, frame_pointer_rtx); + } DONE; }") diff --git a/gcc/config/pa/pa32-regs.h b/gcc/config/pa/pa32-regs.h index f5c6aaa615c..ac23a69173a 100644 --- a/gcc/config/pa/pa32-regs.h +++ b/gcc/config/pa/pa32-regs.h @@ -259,7 +259,6 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, : (REGNO) < 32 ? GENERAL_REGS \ : (REGNO) < 56 ? FP_REGS \ : (REGNO) < 88 ? FPUPPER_REGS \ - : (REGNO) < 88 ? FPUPPER_REGS \ : SHIFT_REGS) /* Get reg_class from a letter such as appears in the machine description. */ @@ -267,7 +266,6 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'f' ? FP_REGS : \ (C) == 'y' ? FPUPPER_REGS : \ - (C) == 'y' ? FPUPPER_REGS : \ (C) == 'x' ? FP_REGS : \ (C) == 'q' ? SHIFT_REGS : \ (C) == 'a' ? R1_REGS : \ diff --git a/gcc/config/pa/pa64-hpux.h b/gcc/config/pa/pa64-hpux.h index aa7dac75382..78fb4cf5112 100644 --- a/gcc/config/pa/pa64-hpux.h +++ b/gcc/config/pa/pa64-hpux.h @@ -47,10 +47,12 @@ Boston, MA 02111-1307, USA. */ #undef LIB_SPEC #define LIB_SPEC \ "%{!shared:\ - %{!p:\ - %{!pg: %{!threads:-lc} %{threads:-lcma -lc_r}}\ - %{pg: -L/usr/lib/pa20_64/libp/ -lgprof -lc}}\ - %{p: -L/usr/lib/pa20_64/libp/ -lprof -lc}} /usr/lib/pa20_64/milli.a" + %{!p:%{!pg: -lc %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ + %{pg: -L/usr/lib/pa20_64/libp/ -lgprof -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}\ + %{p: -L/usr/lib/pa20_64/libp/ -lprof -lc\ + %{static:%{!nolibdld:-a shared -ldld -a archive -lc}}}}\ + /usr/lib/pa20_64/milli.a" /* Under hpux11, the normal location of the `ld' and `as' programs is the /usr/ccs/bin directory. */ @@ -112,6 +114,13 @@ do { \ #define DATA_SECTION_ASM_OP "\t.data" #define BSS_SECTION_ASM_OP "\t.section\t.bss" +#define JCR_SECTION_NAME ".jcr" + +#define HP_INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init" +#define GNU_INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array" +#define HP_FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini" +#define GNU_FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array" + #undef ASM_OUTPUT_ALIGNED_COMMON #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ do { \ @@ -224,55 +233,175 @@ do { \ } while (0) #undef TEXT_SECTION_ASM_OP -#define TEXT_SECTION_ASM_OP "\t.SUBSPA $CODE$\n" +#define TEXT_SECTION_ASM_OP "\t.SUBSPA $CODE$\n" #undef READONLY_DATA_SECTION_ASM_OP -#define READONLY_DATA_SECTION_ASM_OP "\t.SUBSPA $LIT$\n" +#define READONLY_DATA_SECTION_ASM_OP "\t.SUBSPA $LIT$\n" #undef DATA_SECTION_ASM_OP -#define DATA_SECTION_ASM_OP "\t.SUBSPA $DATA$\n" +#define DATA_SECTION_ASM_OP "\t.SUBSPA $DATA$\n" #undef BSS_SECTION_ASM_OP -#define BSS_SECTION_ASM_OP "\t.SUBSPA $BSS$\n" +#define BSS_SECTION_ASM_OP "\t.SUBSPA $BSS$\n" + +/* We provide explicit defines for CTORS_SECTION_ASM_OP and + DTORS_SECTION_ASM_OP since we don't yet have support for + named sections with the HP assembler. */ +#undef CTORS_SECTION_ASM_OP +#define CTORS_SECTION_ASM_OP "\t.SUBSPA \\.ctors,QUAD=1,ALIGN=8,ACCESS=31" +#undef DTORS_SECTION_ASM_OP +#define DTORS_SECTION_ASM_OP "\t.SUBSPA \\.dtors,QUAD=1,ALIGN=8,ACCESS=31" + +#define HP_INIT_ARRAY_SECTION_ASM_OP \ + "\t.SUBSPA \\.init,QUAD=1,ALIGN=8,ACCESS=31" +#define GNU_INIT_ARRAY_SECTION_ASM_OP \ + "\t.SUBSPA \\.init_array,QUAD=1,ALIGN=8,ACCESS=31" +#define HP_FINI_ARRAY_SECTION_ASM_OP \ + "\t.SUBSPA \\.fini,QUAD=1,ALIGN=8,ACCESS=31" +#define GNU_FINI_ARRAY_SECTION_ASM_OP \ + "\t.SUBSPA \\.fini_array,QUAD=1,ALIGN=8,ACCESS=31" #endif /* USING_ELFOS_H */ -/* For the time being, we aren't using init sections. `P' relocations - are currently used for function references. However, P relocations are - treated as data references and data references are bound by dld.sl - immediately at program startup. This causes an abort due to undefined - weak symbols in crtbegin.o (e.g., __register_frame_info). Possibly - Q relocations might avoid this problem but the GNU assembler doesn't - support them. */ +/* The following defines, used to run constructors and destructors with + the SOM linker under HP-UX 11, are not needed. */ +#undef HAS_INIT_SECTION +#undef LD_INIT_SWITCH +#undef LD_FINI_SWITCH + +/* The following STARTFILE_SPEC and ENDFILE_SPEC defines provide the + magic needed to run initializers and finalizers. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shared: %{!symbolic: crt0.o%s}} %{static:crtbeginT.o%s} \ + %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "%{!shared:crtend.o%s} %{shared:crtendS.o%s}" + +/* Since HP uses the .init and .fini sections for array initializers + and finalizers, we need different defines for INIT_SECTION_ASM_OP + and FINI_SECTION_ASM_OP. With the implementation adopted below, + the sections are not actually used. However, we still must provide + defines to select the proper code path. */ #undef INIT_SECTION_ASM_OP +#define INIT_SECTION_ASM_OP #undef FINI_SECTION_ASM_OP +#define FINI_SECTION_ASM_OP + +/* We are using array initializers and don't want calls in the INIT + and FINI sections. */ +#undef CRT_CALL_STATIC_FUNCTION +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) + +/* The init_priority attribute is not supported with HP ld. This could be + supported if collect2 was used with LD_INIT_SWITCH. Unfortunately, this + approach doesn't work with GNU ld since HP-UX doesn't support DT_INIT, + and therefore the -init and -fini GNU ld switches. */ +#undef SUPPORTS_INIT_PRIORITY +#define SUPPORTS_INIT_PRIORITY (TARGET_GNU_LD ? 1 : 0) + +/* We use DTOR_LIST_BEGIN to carry a bunch of hacks to allow us to use + the init and fini array sections with both the HP and GNU linkers. + The linkers setup the required dynamic entries in the dynamic segment + and the dynamic linker does the calls. This approach avoids using + collect2. + + The first hack is to implement __do_global_ctors_aux in crtbegin as + it needs to be the first entry in the init array so that it is called + last. HP got the order of the init array backwards. The DT_INIT_ARRAY + is supposed to be executed in the same order as the addresses appear in + the array. DT_FINI_ARRAY is supposed to be executed in the opposite + order. + + The second hack is stubs for __cxa_finalize and _Jv_RegisterClasses. + The HP implementation of undefined weak symbols is broken. The linker + and dynamic loader both search for undefined weak symbols contrary the + generic System V ABI. An undefined weak symbol should resolve to a + value of 0 rather than causing an error. The prototypes for + __cxa_finalize and _Jv_RegisterClasses in crtstuff.c are weak when + weak is supported (GNU as), so in theory a strong define should override + the stub functions provided here. + + The final hack is a set of plabels to implement the effect of + CRT_CALL_STATIC_FUNCTION. HP-UX 11 only supports DI_INIT_ARRAY and + DT_FINI_ARRAY and they put the arrays in .init and .fini, rather than + in .init_array and .fini_array. The standard defines for .init and + .fini have the execute flag set. So, the assembler has to be hacked + to munge the standard flags for these sections to make them agree + with what the HP linker expects. With the GNU linker, we need to + used the .init_array and .fini_array sections. So, we set up for + both just in case. Once we have built the table, the linker does + the rest of the work. + + The order is significant. Placing __do_global_ctors_aux first in + the list, results in it being called last. User specified initializers, + either using the linker +init command or a plabel, run before the + initializers specified here. */ + +/* We need a __cxa_finalize stub if CRTSTUFFS_O is defined. */ +#ifdef CRTSTUFFS_O +#define PA_CXA_FINALIZE_STUB \ +extern void __cxa_finalize (void *) TARGET_ATTRIBUTE_WEAK; \ +void \ +__cxa_finalize (void *p __attribute__((unused))) {} +#else +#define PA_CXA_FINALIZE_STUB +#endif -#define EH_FRAME_IN_DATA_SECTION 1 +/* We need a _Jv_RegisterClasses stub if JCR_SECTION_NAME is defined. */ +#ifdef JCR_SECTION_NAME +#define PA_JV_REGISTERCLASSES_STUB \ +void \ +_Jv_RegisterClasses (void *p __attribute__((unused))) {} +#else +#define PA_JV_REGISTERCLASSES_STUB +#endif -#undef ENDFILE_SPEC -#define ENDFILE_SPEC "" +/* We need to add frame_dummy to the initializer list if EH_FRAME_SECTION_NAME + or JCR_SECTION_NAME is defined. */ +#if defined(EH_FRAME_SECTION_NAME) || defined(JCR_SECTION_NAME) +#define PA_INIT_FRAME_DUMMY_ASM_OP ".dword P%frame_dummy" +#else +#define PA_INIT_FRAME_DUMMY_ASM_OP "" +#endif -#undef STARTFILE_SPEC -#define STARTFILE_SPEC "%{!shared: %{!symbolic: crt0.o%s}}" - -/* Since we are not yet using .init and .fini sections, we need to - explicitly arrange to run the global constructors and destructors. - We could use ldd for this but it depends on LD_LIBRARY_PATH being - correctly set. So, we use the ld init and fini switches. However, - we need to support different switches for the GNU and HP linkers. - We can't check TARGET_GNU_LD in collect2, so we need a different - test. The +Accept switch is always the first switch when we are - using the HP linker (see define for LINK_SPEC). Checking for it - is a somewhat fragile as it depends on internal details of the - collect2 program but it is better than testing ld_file_name. - - FIXME: The GNU linker is broken. The -init/-fini switches don't - work and ldd can't determine the dynamic dependences of executables - linked with GNU ld. The init and fini routines are not executed - although DT_INIT and DT_FINI appear ok. As a result, defining - LD_INIT_SWITCH and LD_FINI_SWITCH causes more harm than good when - using GNU ld. However, the definitions appear to work fine with - the HP linker. */ -#if 0 -#define LD_INIT_SWITCH (strcmp ("+Accept", ld2_argv[1]) ? "-init" : "+init") -#define LD_FINI_SWITCH (strcmp ("+Accept", ld2_argv[1]) ? "-fini" : "+fini") +#define PA_INIT_FINI_HACK \ +static void __attribute__((used)) \ +__do_global_ctors_aux (void) \ +{ \ + func_ptr *p = __CTOR_LIST__; \ + while (*(p + 1)) \ + p++; \ + for (; *p != (func_ptr) -1; p--) \ + (*p) (); \ +} \ + \ +PA_CXA_FINALIZE_STUB \ +PA_JV_REGISTERCLASSES_STUB \ + \ +asm (HP_INIT_ARRAY_SECTION_ASM_OP); \ +asm (".dword P%__do_global_ctors_aux"); \ +asm (PA_INIT_FRAME_DUMMY_ASM_OP); \ +asm (GNU_INIT_ARRAY_SECTION_ASM_OP); \ +asm (".dword P%__do_global_ctors_aux"); \ +asm (PA_INIT_FRAME_DUMMY_ASM_OP); \ +asm (HP_FINI_ARRAY_SECTION_ASM_OP); \ +asm (".dword P%__do_global_dtors_aux"); \ +asm (GNU_FINI_ARRAY_SECTION_ASM_OP); \ +asm (".dword P%__do_global_dtors_aux") + +/* The following two variants of DTOR_LIST_BEGIN are identical to those + in crtstuff.c except for the addition of the above init-fini hack. */ +#ifdef DTORS_SECTION_ASM_OP +#define DTOR_LIST_BEGIN \ +asm (DTORS_SECTION_ASM_OP); \ +STATIC func_ptr __DTOR_LIST__[1] \ + __attribute__ ((aligned(sizeof(func_ptr)))) \ + = { (func_ptr) (-1) }; \ +PA_INIT_FINI_HACK +#else +#define DTOR_LIST_BEGIN \ +STATIC func_ptr __DTOR_LIST__[1] \ + __attribute__ ((section(".dtors"), aligned(sizeof(func_ptr)))) \ + = { (func_ptr) (-1) }; \ +PA_INIT_FINI_HACK #endif /* If using HP ld do not call pxdb. Use size as a program that does nothing diff --git a/gcc/config/pa/pa64-regs.h b/gcc/config/pa/pa64-regs.h index 2d0ebe3d172..ced7df737e7 100644 --- a/gcc/config/pa/pa64-regs.h +++ b/gcc/config/pa/pa64-regs.h @@ -240,9 +240,9 @@ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS, we inhibit changes from SImode unless they are to a mode that is identical in size. */ -#define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ - ? FP_REGS : NO_REGS) + ? reg_classes_intersect_p (CLASS, FP_REGS) : 0) /* Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression diff --git a/gcc/config/pa/rtems.h b/gcc/config/pa/rtems.h index b03b5c802c3..c71ac6e8441 100644 --- a/gcc/config/pa/rtems.h +++ b/gcc/config/pa/rtems.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for PRO. - Copyright (C) 1997, 2000, 2002 Free Software Foundation, Inc. + Copyright (C) 1997, 2000, 2002, 2003 Free Software Foundation, Inc. Contributed by Joel Sherrill (joel@OARcorp.com). This file is part of GNU CC. @@ -35,3 +35,6 @@ Boston, MA 02111-1307, USA. */ builtin_assert ("system=rtems"); \ } \ while (0) + +#undef LIB_SPEC +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p: -lc}%{pg: -lc} -N" diff --git a/gcc/config/pa/som.h b/gcc/config/pa/som.h index 98c66fbfe37..7609fdbe176 100644 --- a/gcc/config/pa/som.h +++ b/gcc/config/pa/som.h @@ -362,10 +362,6 @@ do { \ /* The .align directive in the HP assembler allows up to a 32 alignment. */ #define MAX_OFILE_ALIGNMENT 32768 -/* SOM does not support the init_priority C++ attribute. */ -#undef SUPPORTS_INIT_PRIORITY -#define SUPPORTS_INIT_PRIORITY 0 - /* The SOM linker hardcodes paths into binaries. As a result, dotdots must be removed from library prefixes to prevent binaries from depending on the location of the GCC tool directory. The downside is GCC @@ -375,3 +371,52 @@ do { \ /* Aggregates with a single float or double field should be passed and returned in the general registers. */ #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) (MODE==SFmode || MODE==DFmode) + +/* If GAS supports weak, we can support weak when we have working linker + support for secondary definitions and are generating code for GAS. */ +#ifdef HAVE_GAS_WEAK +#define SUPPORTS_WEAK (TARGET_SOM_SDEF && TARGET_GAS) +#else +#define SUPPORTS_WEAK 0 +#endif + +/* We can support one only if we support weak. */ +#define SUPPORTS_ONE_ONLY SUPPORTS_WEAK + +/* Use weak (secondary definitions) to make one only declarations. */ +#define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1) + +/* This is how we tell the assembler that a symbol is weak. The SOM + weak implementation uses the secondary definition (sdef) flag. + + The behavior of sdef symbols is similar to ELF weak symbols in that + multiple definitions can occur without incurring a link error. + However, they differ in the following ways: + 1) Undefined sdef symbols are not allowed. + 2) The linker searches for undefined sdef symbols and will load an + archive library member to resolve an undefined sdef symbol. + 3) The exported symbol from a shared library is a primary symbol + rather than a sdef symbol. Thus, more care is needed in the + ordering of libraries. + + It appears that the linker discards extra copies of "weak" functions + when linking shared libraries, independent of whether or not they + are in their own section. In linking final executables, -Wl,-O can + be used to remove dead procedures. Thus, support for named sections + is not needed and in previous testing caused problems with various + HP tools. */ +#define ASM_WEAKEN_LABEL(FILE,NAME) \ + do { fputs ("\t.weak\t", FILE); \ + assemble_name (FILE, NAME); \ + fputc ('\n', FILE); \ + if (! FUNCTION_NAME_P (NAME)) \ + { \ + fputs ("\t.EXPORT ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (",DATA\n", FILE); \ + } \ + } while (0) + +/* We can't handle weak aliases, and therefore can't support pragma weak. + Suppress the use of pragma weak in gthr-dce.h and gthr-posix.h. */ +#define GTHREAD_USE_WEAK 0 diff --git a/gcc/config/pa/t-hpux-shlib b/gcc/config/pa/t-hpux-shlib index 52c3fd90c4f..1c924497c0b 100644 --- a/gcc/config/pa/t-hpux-shlib +++ b/gcc/config/pa/t-hpux-shlib @@ -13,7 +13,7 @@ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \ # $(slibdir) double quoted to protect it from expansion while building # libgcc.mk. We want this delayed until actual install time. SHLIB_INSTALL = $(INSTALL_DATA) -m 555 $(SHLIB_NAME) \ - $$(slibdir)/$(SHLIB_SONAME); \ - rm -f $$(slibdir)/$(SHLIB_NAME); \ - $(LN_S) $(SHLIB_SONAME) $$(slibdir)/$(SHLIB_NAME) + $$(DESTDIR)$$(slibdir)/$(SHLIB_SONAME); \ + rm -f $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME); \ + $(LN_S) $(SHLIB_SONAME) $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME) |