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-rw-r--r--gcc/config/rs6000/altivec.h16
-rw-r--r--gcc/config/rs6000/altivec.md63
-rw-r--r--gcc/config/rs6000/darwin.h4
-rw-r--r--gcc/config/rs6000/linux.h46
-rw-r--r--gcc/config/rs6000/ppc64-fp.c146
-rw-r--r--gcc/config/rs6000/rs6000.c107
-rw-r--r--gcc/config/rs6000/rs6000.h53
-rw-r--r--gcc/config/rs6000/rs6000.md37
-rw-r--r--gcc/config/rs6000/rtems.h5
-rw-r--r--gcc/config/rs6000/spe.h353
-rw-r--r--gcc/config/rs6000/sysv4.h20
-rw-r--r--gcc/config/rs6000/t-aix432
-rw-r--r--gcc/config/rs6000/t-aix522
-rw-r--r--gcc/config/rs6000/t-linux643
-rw-r--r--gcc/config/rs6000/t-rtems86
15 files changed, 632 insertions, 311 deletions
diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index f1387c0c898..1e2d8c8d408 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -1102,43 +1102,43 @@ vec_cmple (vector float a1, vector float a2)
inline vector signed char
vec_cmplt (vector unsigned char a1, vector unsigned char a2)
{
- return (vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) a1, (vector signed char) a2);
+ return (vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) a2, (vector signed char) a1);
}
inline vector signed char
vec_cmplt (vector signed char a1, vector signed char a2)
{
- return (vector signed char) __builtin_altivec_vcmpgtsb ((vector signed char) a1, (vector signed char) a2);
+ return (vector signed char) __builtin_altivec_vcmpgtsb ((vector signed char) a2, (vector signed char) a1);
}
inline vector signed short
vec_cmplt (vector unsigned short a1, vector unsigned short a2)
{
- return (vector signed short) __builtin_altivec_vcmpgtuh ((vector signed short) a1, (vector signed short) a2);
+ return (vector signed short) __builtin_altivec_vcmpgtuh ((vector signed short) a2, (vector signed short) a1);
}
inline vector signed short
vec_cmplt (vector signed short a1, vector signed short a2)
{
- return (vector signed short) __builtin_altivec_vcmpgtsh ((vector signed short) a1, (vector signed short) a2);
+ return (vector signed short) __builtin_altivec_vcmpgtsh ((vector signed short) a2, (vector signed short) a1);
}
inline vector signed int
vec_cmplt (vector unsigned int a1, vector unsigned int a2)
{
- return (vector signed int) __builtin_altivec_vcmpgtuw ((vector signed int) a1, (vector signed int) a2);
+ return (vector signed int) __builtin_altivec_vcmpgtuw ((vector signed int) a2, (vector signed int) a1);
}
inline vector signed int
vec_cmplt (vector signed int a1, vector signed int a2)
{
- return (vector signed int) __builtin_altivec_vcmpgtsw ((vector signed int) a1, (vector signed int) a2);
+ return (vector signed int) __builtin_altivec_vcmpgtsw ((vector signed int) a2, (vector signed int) a1);
}
inline vector signed int
vec_cmplt (vector float a1, vector float a2)
{
- return (vector signed int) __builtin_altivec_vcmpgtfp ((vector float) a1, (vector float) a2);
+ return (vector signed int) __builtin_altivec_vcmpgtfp ((vector float) a2, (vector float) a1);
}
/* vec_ctf */
@@ -6523,7 +6523,7 @@ __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \
#define vec_cmple(a1, a2) __builtin_altivec_vcmpgefp ((a1), (a2))
-#define vec_cmplt(a1, a2) \
+#define vec_cmplt(a2, a1) \
__ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \
((vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) (a1), (vector signed char) (a2))), \
__ch (__bin_args_eq (vector signed char, (a1), vector signed char, (a2)), \
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 3d20ff48e23..25e4b084433 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -490,18 +490,27 @@
"vmaddfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
-;; The unspec here is a vec splat of 0. We do multiply as a fused
-;; multiply-add with an add of a 0 vector.
+;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "mulv4sf3"
- [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142))
- (set (match_operand:V4SF 0 "register_operand" "=v")
- (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
- (match_operand:V4SF 2 "register_operand" "v"))
- (match_dup 3)))]
+ [(use (match_operand:V4SF 0 "register_operand" ""))
+ (use (match_operand:V4SF 1 "register_operand" ""))
+ (use (match_operand:V4SF 2 "register_operand" ""))]
"TARGET_ALTIVEC && TARGET_FUSED_MADD"
"
-{ operands[3] = gen_reg_rtx (V4SFmode); }")
+{
+ rtx neg0;
+
+ /* Generate [-0.0, -0.0, -0.0, -0.0]. */
+ neg0 = gen_reg_rtx (V4SFmode);
+ emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
+ emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
+
+ /* Use the multiply-add. */
+ emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
+ neg0));
+ DONE;
+}")
;; Fused multiply subtract
(define_insn "altivec_vnmsubfp"
@@ -1043,6 +1052,14 @@
"vslw %0,%1,%2"
[(set_attr "type" "vecsimple")])
+(define_insn "altivec_vslw_v4sf"
+ [(set (match_operand:V4SF 0 "register_operand" "=v")
+ (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
+ (match_operand:V4SF 2 "register_operand" "v")] 109))]
+ "TARGET_ALTIVEC"
+ "vslw %0,%1,%2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "altivec_vsl"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
@@ -1316,7 +1333,7 @@
"vspltisw %0, %1"
[(set_attr "type" "vecsimple")])
-(define_insn ""
+(define_insn "altivec_vspltisw_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
"TARGET_ALTIVEC"
@@ -1830,8 +1847,8 @@
(define_insn "absv16qi2"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
- (clobber (match_scratch:V16QI 2 "=v"))
- (clobber (match_scratch:V16QI 3 "=v"))]
+ (clobber (match_scratch:V16QI 2 "=&v"))
+ (clobber (match_scratch:V16QI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1840,8 +1857,8 @@
(define_insn "absv8hi2"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
- (clobber (match_scratch:V8HI 2 "=v"))
- (clobber (match_scratch:V8HI 3 "=v"))]
+ (clobber (match_scratch:V8HI 2 "=&v"))
+ (clobber (match_scratch:V8HI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1850,8 +1867,8 @@
(define_insn "absv4si2"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
- (clobber (match_scratch:V4SI 2 "=v"))
- (clobber (match_scratch:V4SI 3 "=v"))]
+ (clobber (match_scratch:V4SI 2 "=&v"))
+ (clobber (match_scratch:V4SI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1860,8 +1877,8 @@
(define_insn "absv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(abs:V4SF (match_operand:V4SF 1 "register_operand" "v")))
- (clobber (match_scratch:V4SF 2 "=v"))
- (clobber (match_scratch:V4SF 3 "=v"))]
+ (clobber (match_scratch:V4SF 2 "=&v"))
+ (clobber (match_scratch:V4SF 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1870,8 +1887,8 @@
(define_insn "altivec_abss_v16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
- (clobber (match_scratch:V16QI 2 "=v"))
- (clobber (match_scratch:V16QI 3 "=v"))]
+ (clobber (match_scratch:V16QI 2 "=&v"))
+ (clobber (match_scratch:V16QI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1880,8 +1897,8 @@
(define_insn "altivec_abss_v8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
- (clobber (match_scratch:V8HI 2 "=v"))
- (clobber (match_scratch:V8HI 3 "=v"))]
+ (clobber (match_scratch:V8HI 2 "=&v"))
+ (clobber (match_scratch:V8HI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
[(set_attr "type" "altivec")
@@ -1890,8 +1907,8 @@
(define_insn "altivec_abss_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
- (clobber (match_scratch:V4SI 2 "=v"))
- (clobber (match_scratch:V4SI 3 "=v"))]
+ (clobber (match_scratch:V4SI 2 "=&v"))
+ (clobber (match_scratch:V4SI 3 "=&v"))]
"TARGET_ALTIVEC"
"vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
[(set_attr "type" "altivec")
diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h
index 73041a28775..b3468f2b66b 100644
--- a/gcc/config/rs6000/darwin.h
+++ b/gcc/config/rs6000/darwin.h
@@ -58,7 +58,9 @@ Boston, MA 02111-1307, USA. */
/* We want -fPIC by default, unless we're using -static to compile for
the kernel or some such. */
-#define CC1_SPEC "%{!static:-fPIC}"
+#define CC1_SPEC "\
+%{static: %{Zdynamic: %e conflicting code gen style switches are used}}\
+%{!static:-fPIC}"
/* Make both r2 and r3 available for allocation. */
#define FIXED_R2 0
diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
index 1711354da76..bb195d00829 100644
--- a/gcc/config/rs6000/linux.h
+++ b/gcc/config/rs6000/linux.h
@@ -1,7 +1,7 @@
/* Definitions of target machine for GNU compiler,
for PowerPC machines running Linux.
- Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation,
- Inc.
+ Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
+ Free Software Foundation, Inc.
Contributed by Michael Meissner (meissner@cygnus.com).
This file is part of GNU CC.
@@ -96,12 +96,34 @@ enum { SIGNAL_FRAMESIZE = 64 };
long new_cfa_; \
int i_; \
\
- /* li r0, 0x7777; sc (rt_sigreturn) */ \
- /* li r0, 0x6666; sc (sigreturn) */ \
- if (((*(unsigned int *) (pc_+0) == 0x38007777) \
- || (*(unsigned int *) (pc_+0) == 0x38006666)) \
- && (*(unsigned int *) (pc_+4) == 0x44000002)) \
- sc_ = (CONTEXT)->cfa + SIGNAL_FRAMESIZE; \
+ /* li r0, 0x7777; sc (sigreturn old) */ \
+ /* li r0, 0x0077; sc (sigreturn new) */ \
+ /* li r0, 0x6666; sc (rt_sigreturn old) */ \
+ /* li r0, 0x00AC; sc (rt_sigreturn new) */ \
+ if (*(unsigned int *) (pc_+4) != 0x44000002) \
+ break; \
+ if (*(unsigned int *) (pc_+0) == 0x38007777 \
+ || *(unsigned int *) (pc_+0) == 0x38000077) \
+ { \
+ struct sigframe { \
+ char gap[SIGNAL_FRAMESIZE]; \
+ struct sigcontext sigctx; \
+ } *rt_ = (CONTEXT)->cfa; \
+ sc_ = &rt_->sigctx; \
+ } \
+ else if (*(unsigned int *) (pc_+0) == 0x38006666 \
+ || *(unsigned int *) (pc_+0) == 0x380000AC) \
+ { \
+ struct rt_sigframe { \
+ char gap[SIGNAL_FRAMESIZE]; \
+ unsigned long _unused[2]; \
+ struct siginfo *pinfo; \
+ void *puc; \
+ struct siginfo info; \
+ struct ucontext uc; \
+ } *rt_ = (CONTEXT)->cfa; \
+ sc_ = &rt_->uc.uc_mcontext; \
+ } \
else \
break; \
\
@@ -124,11 +146,13 @@ enum { SIGNAL_FRAMESIZE = 64 };
\
/* The unwinder expects the IP to point to the following insn, \
whereas the kernel returns the address of the actual \
- faulting insn. */ \
- sc_->regs->nip += 4; \
+ faulting insn. We store NIP+4 in an unused register slot to \
+ get the same result for multiple evaluation of the same signal \
+ frame. */ \
+ sc_->regs->gpr[47] = sc_->regs->nip + 4; \
(FS)->regs.reg[CR0_REGNO].how = REG_SAVED_OFFSET; \
(FS)->regs.reg[CR0_REGNO].loc.offset \
- = (long)&(sc_->regs->nip) - new_cfa_; \
+ = (long)&(sc_->regs->gpr[47]) - new_cfa_; \
(FS)->retaddr_column = CR0_REGNO; \
goto SUCCESS; \
} while (0)
diff --git a/gcc/config/rs6000/ppc64-fp.c b/gcc/config/rs6000/ppc64-fp.c
new file mode 100644
index 00000000000..3f6d7cd1bb0
--- /dev/null
+++ b/gcc/config/rs6000/ppc64-fp.c
@@ -0,0 +1,146 @@
+/* Functions needed for soft-float on powerpc64-linux, copied from
+ libgcc2.c with macros expanded to force the use of specific types.
+
+ Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 2, or (at your option) any later
+version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public License restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING. If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA. */
+
+#if defined(__powerpc64__)
+#include "fp-bit.h"
+
+extern DItype __fixdfdi (DFtype);
+extern DItype __fixsfdi (SFtype);
+extern USItype __fixunsdfsi (DFtype);
+extern USItype __fixunssfsi (SFtype);
+extern DFtype __floatdidf (DItype);
+extern SFtype __floatdisf (DItype);
+
+static DItype local_fixunssfdi (SFtype);
+static DItype local_fixunsdfdi (DFtype);
+
+DItype
+__fixdfdi (DFtype a)
+{
+ if (a < 0)
+ return - local_fixunsdfdi (-a);
+ return local_fixunsdfdi (a);
+}
+
+DItype
+__fixsfdi (SFtype a)
+{
+ if (a < 0)
+ return - local_fixunssfdi (-a);
+ return local_fixunssfdi (a);
+}
+
+USItype
+__fixunsdfsi (DFtype a)
+{
+ if (a >= - (DFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1))
+ return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1))
+ - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1);
+ return (SItype) a;
+}
+
+USItype
+__fixunssfsi (SFtype a)
+{
+ if (a >= - (SFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1))
+ return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1))
+ - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1);
+ return (SItype) a;
+}
+
+DFtype
+__floatdidf (DItype u)
+{
+ DFtype d;
+
+ d = (SItype) (u >> (sizeof (SItype) * 8));
+ d *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2));
+ d *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2));
+ d += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1));
+
+ return d;
+}
+
+SFtype
+__floatdisf (DItype u)
+{
+ DFtype f;
+
+ if (53 < (sizeof (DItype) * 8)
+ && 53 > ((sizeof (DItype) * 8) - 53 + 24))
+ {
+ if (! (- ((DItype) 1 << 53) < u
+ && u < ((DItype) 1 << 53)))
+ {
+ if ((UDItype) u & (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1))
+ {
+ u &= ~ (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1);
+ u |= ((UDItype) 1 << ((sizeof (DItype) * 8) - 53));
+ }
+ }
+ }
+ f = (SItype) (u >> (sizeof (SItype) * 8));
+ f *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2));
+ f *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2));
+ f += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1));
+
+ return (SFtype) f;
+}
+
+/* This version is needed to prevent recursion; fixunsdfdi in libgcc
+ calls fixdfdi, which in turn calls calls fixunsdfdi. */
+
+static DItype
+local_fixunsdfdi (DFtype a)
+{
+ USItype hi, lo;
+
+ hi = a / (((UDItype) 1) << (sizeof (SItype) * 8));
+ lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8)));
+ return ((UDItype) hi << (sizeof (SItype) * 8)) | lo;
+}
+
+/* This version is needed to prevent recursion; fixunssfdi in libgcc
+ calls fixsfdi, which in turn calls calls fixunssfdi. */
+
+static DItype
+local_fixunssfdi (SFtype original_a)
+{
+ DFtype a = original_a;
+ USItype hi, lo;
+
+ hi = a / (((UDItype) 1) << (sizeof (SItype) * 8));
+ lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8)));
+ return ((UDItype) hi << (sizeof (SItype) * 8)) | lo;
+}
+
+#endif /* __powerpc64__ */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 5c0ef2f6f30..84bb343918e 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1,6 +1,6 @@
/* Subroutines used for code generation on IBM RS/6000.
Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GNU CC.
@@ -284,7 +284,9 @@ char rs6000_reg_names[][8] =
"8", "9", "10", "11", "12", "13", "14", "15",
"16", "17", "18", "19", "20", "21", "22", "23",
"24", "25", "26", "27", "28", "29", "30", "31",
- "vrsave"
+ "vrsave", "vscr",
+ /* SPE registers. */
+ "spe_acc", "spefscr"
};
#ifdef TARGET_REGNAMES
@@ -301,12 +303,14 @@ static const char alt_reg_names[][8] =
"mq", "lr", "ctr", "ap",
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
"xer",
- /* AltiVec registers. */
+ /* AltiVec registers. */
"%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
- "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
- "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
- "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
- "vrsave"
+ "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
+ "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
+ "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
+ "vrsave", "vscr",
+ /* SPE registers. */
+ "spe_acc", "spefscr"
};
#endif
@@ -2841,6 +2845,16 @@ rs6000_emit_move (dest, source, mode)
operands[1]
= replace_equiv_address (operands[1],
copy_addr_to_reg (XEXP (operands[1], 0)));
+ if (TARGET_POWER)
+ {
+ emit_insn (gen_rtx_PARALLEL (VOIDmode,
+ gen_rtvec (2,
+ gen_rtx_SET (VOIDmode,
+ operands[0], operands[1]),
+ gen_rtx_CLOBBER (VOIDmode,
+ gen_rtx_SCRATCH (SImode)))));
+ return;
+ }
break;
default:
@@ -3275,7 +3289,10 @@ function_arg_partial_nregs (cum, mode, type, named)
the argument itself. The pointer is passed in whatever way is
appropriate for passing a pointer to that type.
- Under V.4, structures and unions are passed by reference. */
+ Under V.4, structures and unions are passed by reference.
+
+ As an extension to all ABIs, variable sized types are passed by
+ reference. */
int
function_arg_pass_by_reference (cum, mode, type, named)
@@ -3293,8 +3310,7 @@ function_arg_pass_by_reference (cum, mode, type, named)
return 1;
}
-
- return 0;
+ return type && int_size_in_bytes (type) <= 0;
}
/* Perform any needed actions needed for a function that is receiving a
@@ -3533,7 +3549,28 @@ rs6000_va_arg (valist, type)
rtx lab_false, lab_over, addr_rtx, r;
if (DEFAULT_ABI != ABI_V4)
- return std_expand_builtin_va_arg (valist, type);
+ {
+ /* Variable sized types are passed by reference. */
+ if (int_size_in_bytes (type) <= 0)
+ {
+ u = build_pointer_type (type);
+
+ /* Args grow upward. */
+ t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
+ build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
+ TREE_SIDE_EFFECTS (t) = 1;
+
+ t = build1 (NOP_EXPR, build_pointer_type (u), t);
+ TREE_SIDE_EFFECTS (t) = 1;
+
+ t = build1 (INDIRECT_REF, u, t);
+ TREE_SIDE_EFFECTS (t) = 1;
+
+ return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
+ }
+ else
+ return std_expand_builtin_va_arg (valist, type);
+ }
f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
f_fpr = TREE_CHAIN (f_gpr);
@@ -8837,7 +8874,7 @@ first_reg_to_save ()
if (regs_ever_live[first_reg]
&& (! call_used_regs[first_reg]
|| (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
- && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
+ && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic)))))
break;
@@ -9609,7 +9646,7 @@ void
rs6000_emit_load_toc_table (fromprolog)
int fromprolog;
{
- rtx dest;
+ rtx dest, insn;
dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
@@ -9617,8 +9654,12 @@ rs6000_emit_load_toc_table (fromprolog)
rtx temp = (fromprolog
? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
: gen_reg_rtx (Pmode));
- rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp)));
- rs6000_maybe_dead (emit_move_insn (dest, temp));
+ insn = emit_insn (gen_load_toc_v4_pic_si (temp));
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
+ insn = emit_move_insn (dest, temp);
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
}
else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
{
@@ -9665,14 +9706,13 @@ rs6000_emit_load_toc_table (fromprolog)
ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
- rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR,
- symF,
- tocsym)));
- rs6000_maybe_dead (emit_move_insn (dest, tempLR));
- rs6000_maybe_dead (emit_move_insn (temp0,
- gen_rtx_MEM (Pmode, dest)));
+ emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
+ emit_move_insn (dest, tempLR);
+ emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
}
- rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest)));
+ insn = emit_insn (gen_addsi3 (dest, temp0, dest));
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
}
else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
{
@@ -9682,15 +9722,21 @@ rs6000_emit_load_toc_table (fromprolog)
ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
- rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym)));
- rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym)));
+ insn = emit_insn (gen_elf_high (dest, realsym));
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
+ insn = emit_insn (gen_elf_low (dest, dest, realsym));
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
}
else if (DEFAULT_ABI == ABI_AIX)
{
if (TARGET_32BIT)
- rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest)));
+ insn = emit_insn (gen_load_toc_aix_si (dest));
else
- rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest)));
+ insn = emit_insn (gen_load_toc_aix_di (dest));
+ if (fromprolog)
+ rs6000_maybe_dead (insn);
}
else
abort ();
@@ -10423,7 +10469,7 @@ rs6000_emit_prologue ()
if ((regs_ever_live[info->first_gp_reg_save+i]
&& ! call_used_regs[info->first_gp_reg_save+i])
|| (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
- && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
+ && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
{
rtx addr, reg, mem;
@@ -10839,7 +10885,7 @@ rs6000_emit_epilogue (sibcall)
if ((regs_ever_live[info->first_gp_reg_save+i]
&& ! call_used_regs[info->first_gp_reg_save+i])
|| (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
- && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1)
+ && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
|| (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
{
rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
@@ -12617,11 +12663,15 @@ rs6000_elf_encode_section_info (decl, first)
&& DEFAULT_ABI == ABI_V4
&& TREE_CODE (decl) == VAR_DECL)
{
+ rtx sym_ref = XEXP (DECL_RTL (decl), 0);
int size = int_size_in_bytes (TREE_TYPE (decl));
tree section_name = DECL_SECTION_NAME (decl);
const char *name = (char *)0;
int len = 0;
+ if ((*targetm.binds_local_p) (decl))
+ SYMBOL_REF_FLAG (sym_ref) = 1;
+
if (section_name)
{
if (TREE_CODE (section_name) == STRING_CST)
@@ -12648,7 +12698,6 @@ rs6000_elf_encode_section_info (decl, first)
|| (len == sizeof (".PPC.EMB.sbss0") - 1
&& strcmp (name, ".PPC.EMB.sbss0") == 0))))
{
- rtx sym_ref = XEXP (DECL_RTL (decl), 0);
size_t len = strlen (XSTR (sym_ref, 0));
char *str = alloca (len + 2);
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index e5e9e27cce9..e1454bbae53 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1,6 +1,6 @@
/* Definitions of target machine for GNU compiler, for IBM RS/6000.
Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
- 2000, 2001, 2002 Free Software Foundation, Inc.
+ 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
This file is part of GNU CC.
@@ -611,6 +611,9 @@ extern int rs6000_default_long_calls;
#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
#endif
+/* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
+#define WIDEST_HARDWARE_FP_SIZE 64
+
/* Width in bits of a pointer.
See also the macro `Pmode' defined below. */
#define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
@@ -997,6 +1000,10 @@ extern int rs6000_default_long_calls;
= call_really_used_regs[i] = 1; \
if (DEFAULT_ABI == ABI_V4 \
&& PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
+ && flag_pic == 2) \
+ fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
+ if (DEFAULT_ABI == ABI_V4 \
+ && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
&& flag_pic == 1) \
fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
= call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
@@ -1337,10 +1344,12 @@ enum reg_class
/* Return a class of registers that cannot change FROM mode to TO mode. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \
- (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FLOAT_REGS \
- : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 ? GENERAL_REGS \
- : NO_REGS)
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
+ ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
+ : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \
+ ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
+ : 0)
/* Stack layout; function entry, exit and calling. */
@@ -1612,20 +1621,20 @@ typedef struct rs6000_stack {
as seen by the caller.
On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
-#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
- || ((N) == FP_ARG_RETURN) \
- || (TARGET_ALTIVEC && \
- (N) == ALTIVEC_ARG_RETURN))
+#define FUNCTION_VALUE_REGNO_P(N) \
+ ((N) == GP_ARG_RETURN \
+ || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \
+ || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC))
/* 1 if N is a possible register number for function argument passing.
On RS/6000, these are r3-r10 and fp1-fp13.
On AltiVec, v2 - v13 are used for passing vectors. */
#define FUNCTION_ARG_REGNO_P(N) \
- (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
- || (TARGET_ALTIVEC && \
- (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
- || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
-
+ ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
+ || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
+ && TARGET_ALTIVEC) \
+ || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
+ && TARGET_HARD_FLOAT))
/* A C structure for machine-specific, per-function data.
This is added to the cfun structure. */
@@ -2382,12 +2391,16 @@ do { \
return COSTS_N_INSNS (4); \
case PROCESSOR_PPC620: \
case PROCESSOR_PPC630: \
- case PROCESSOR_POWER4: \
return (GET_CODE (XEXP (X, 1)) != CONST_INT \
? GET_MODE (XEXP (X, 1)) != DImode \
? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
: INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
+ case PROCESSOR_POWER4: \
+ return (GET_CODE (XEXP (X, 1)) != CONST_INT \
+ ? GET_MODE (XEXP (X, 1)) != DImode \
+ ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) \
+ : COSTS_N_INSNS (2)); \
} \
case DIV: \
case MOD: \
@@ -2723,8 +2736,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
#define DEBUG_REGISTER_NAMES \
{ \
- "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
- "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
@@ -2733,13 +2746,13 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
"mq", "lr", "ctr", "ap", \
"cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
- "xer", \
+ "xer", \
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
- "vrsave", "vscr" \
- , "spe_acc", "spefscr" \
+ "vrsave", "vscr", \
+ "spe_acc", "spefscr" \
}
/* Table of additional register names to use in user input. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index a031a295e9b..6ce597ece61 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1,6 +1,6 @@
;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
;; This file is part of GNU CC.
@@ -772,17 +772,17 @@
2 1)
(define_function_unit "iu2" 2 0
- (and (eq_attr "type" "imul,lmul")
+ (and (eq_attr "type" "lmul")
(eq_attr "cpu" "power4"))
7 6)
(define_function_unit "iu2" 2 0
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "imul")
(eq_attr "cpu" "power4"))
5 4)
(define_function_unit "iu2" 2 0
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "imul2,imul3")
(eq_attr "cpu" "power4"))
4 3)
@@ -9133,6 +9133,32 @@
operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
}")
+(define_split
+ [(set (match_operand:TI 0 "gpc_reg_operand" "")
+ (match_operand:TI 1 "const_double_operand" ""))]
+ "TARGET_POWERPC64"
+ [(set (match_dup 2) (match_dup 4))
+ (set (match_dup 3) (match_dup 5))]
+ "
+{
+ operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
+ TImode);
+ operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
+ TImode);
+ if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ {
+ operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
+ operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
+ }
+ else if (GET_CODE (operands[1]) == CONST_INT)
+ {
+ operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
+ operands[5] = operands[1];
+ }
+ else
+ FAIL;
+}")
+
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
(match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
@@ -9313,8 +9339,7 @@
(define_insn "*movti_string"
[(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
- (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
- (clobber (match_scratch:SI 2 "X,X,X,X,X"))]
+ (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
"*
diff --git a/gcc/config/rs6000/rtems.h b/gcc/config/rs6000/rtems.h
index 072d86c4ca2..7e7584604e9 100644
--- a/gcc/config/rs6000/rtems.h
+++ b/gcc/config/rs6000/rtems.h
@@ -1,5 +1,5 @@
/* Definitions for rtems targeting a PowerPC using elf.
- Copyright (C) 1996, 1997, 2000, 2001, 2002 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
Contributed by Joel Sherrill (joel@OARcorp.com).
This file is part of GNU CC.
@@ -32,3 +32,6 @@ Boston, MA 02111-1307, USA. */
builtin_assert ("machine=powerpc"); \
} \
while (0)
+
+#undef CPP_OS_DEFAULT_SPEC
+#define CPP_OS_DEFAULT_SPEC "%(cpp_os_rtems)"
diff --git a/gcc/config/rs6000/spe.h b/gcc/config/rs6000/spe.h
index 48d5b28b6b9..b15dac5a38b 100644
--- a/gcc/config/rs6000/spe.h
+++ b/gcc/config/rs6000/spe.h
@@ -1,5 +1,5 @@
/* PowerPC E500 user include file.
- Copyright (C) 2002 Free Software Foundation, Inc.
+ Copyright (C) 2002, 2003 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GNU CC.
@@ -42,10 +42,9 @@ typedef short __vector __ev64_s16__;
typedef unsigned short __vector __ev64_u16__;
typedef int __vector __ev64_s32__;
typedef unsigned __vector __ev64_u32__;
-typedef long long __ev64_s64__;
-typedef unsigned long long __ev64_u64__;
+typedef long long __vector __ev64_s64__;
+typedef unsigned long long __vector __ev64_u64__;
typedef float __vector __ev64_fs__;
-
typedef int __vector __ev64_opaque__;
#define __v2si __ev64_opaque__
@@ -54,7 +53,11 @@ typedef int __vector __ev64_opaque__;
#define __ev_addw(a,b) __builtin_spe_evaddw((__v2si) (a), (__v2si) (b))
#define __ev_addiw(a,b) __builtin_spe_evaddiw ((__v2si) (a), (b))
#define __ev_subfw(a,b) __builtin_spe_evsubfw ((__v2si) (a), (__v2si) (b))
-#define __ev_subifw(a,b) __builtin_spe_evsubifw ((__v2si) (a), (b))
+#define __ev_subw(a,b) __builtin_spe_evsubfw ((__v2si) (b), (__v2si) (a))
+/* ??? The spe_evsubifw pattern accepts operands reversed, so we need to also
+ reverse them here between the intrinsic and the builtin function. */
+#define __ev_subifw(a,b) __builtin_spe_evsubifw ((__v2si) (b), (a))
+#define __ev_subiw(a,b) __builtin_spe_evsubifw ((__v2si) (a), (b))
#define __ev_abs(a) __builtin_spe_evabs ((__v2si) (a))
#define __ev_neg(a) __builtin_spe_evneg ((__v2si) (a))
#define __ev_extsb(a) __builtin_spe_evextsb ((__v2si) (a))
@@ -124,9 +127,9 @@ typedef int __vector __ev64_opaque__;
#define __ev_stwwox(a,b,c) __builtin_spe_evstwwox ((__v2si)(a), (b), (c))
#define __ev_stwhex(a,b,c) __builtin_spe_evstwhex ((__v2si)(a), (b), (c))
#define __ev_stwhox(a,b,c) __builtin_spe_evstwhox ((__v2si)(a), (b), (c))
-#define __ev_stdd(a,b,c) __builtin_spe_evstdd ((__v2si)(a), (b), (c))
-#define __ev_stdw(a,b,c) __builtin_spe_evstdw ((__v2si)(a), (b), (c))
-#define __ev_stdh(a,b,c) __builtin_spe_evstdh ((__v2si)(a), (b), (c))
+#define __ev_stdd(a,b,c) __builtin_spe_evstdd ((__v2si)(a), (void *)(b), (c))
+#define __ev_stdw(a,b,c) __builtin_spe_evstdw ((__v2si)(a), (void *)(b), (c))
+#define __ev_stdh(a,b,c) __builtin_spe_evstdh ((__v2si)(a), (void *)(b), (c))
#define __ev_stwwe(a,b,c) __builtin_spe_evstwwe ((__v2si)(a), (b), (c))
#define __ev_stwwo(a,b,c) __builtin_spe_evstwwo ((__v2si)(a), (b), (c))
#define __ev_stwhe(a,b,c) __builtin_spe_evstwhe ((__v2si)(a), (b), (c))
@@ -224,24 +227,16 @@ typedef int __vector __ev64_opaque__;
#define __ev_mwhumf __ev_mwhumi
#define __ev_mwhumfa __ev_mwhumia
-#define __ev_mwlssf(a, b) __builtin_spe_evmwlssf ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlsmf(a, b) __builtin_spe_evmwlsmf ((__v2si) (a), (__v2si) (b))
#define __ev_mwlumi(a, b) __builtin_spe_evmwlumi ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlssfa(a, b) __builtin_spe_evmwlssfa ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlsmfa(a, b) __builtin_spe_evmwlsmfa ((__v2si) (a), (__v2si) (b))
#define __ev_mwlumia(a, b) __builtin_spe_evmwlumia ((__v2si) (a), (__v2si) (b))
#define __ev_mwlumiaaw(a, b) __builtin_spe_evmwlumiaaw ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlssfaaw(a, b) __builtin_spe_evmwlssfaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlssiaaw(a, b) __builtin_spe_evmwlssiaaw ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlsmfaaw(a, b) __builtin_spe_evmwlsmfaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlsmiaaw(a, b) __builtin_spe_evmwlsmiaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlusiaaw(a, b) __builtin_spe_evmwlusiaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlusiaaw(a, b) __builtin_spe_evmwlusiaaw ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlssfanw(a, b) __builtin_spe_evmwlssfanw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlssianw(a, b) __builtin_spe_evmwlssianw ((__v2si) (a), (__v2si) (b))
-#define __ev_mwlsmfanw(a, b) __builtin_spe_evmwlsmfanw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlsmianw(a, b) __builtin_spe_evmwlsmianw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlusianw(a, b) __builtin_spe_evmwlusianw ((__v2si) (a), (__v2si) (b))
#define __ev_mwlumianw(a, b) __builtin_spe_evmwlumianw ((__v2si) (a), (__v2si) (b))
@@ -294,26 +289,26 @@ typedef int __vector __ev64_opaque__;
/* Floating Point SIMD Instructions */
-/* These all return V2SF, but we need to cast them to V2SI because the SPE
- expect all functions to be __ev64_opaque__. */
-
-#define __ev_fsabs(a) ((__v2si) __builtin_spe_evfsabs ((__v2sf) a))
-#define __ev_fsnabs(a) ((__v2si) __builtin_spe_evfsnabs ((__v2sf) a))
-#define __ev_fsneg(a) ((__v2si) __builtin_spe_evfsneg ((__v2sf) a))
-#define __ev_fsadd(a, b) ((__v2si) __builtin_spe_evfsadd ((__v2sf) a, (__v2sf) b))
-#define __ev_fssub(a, b) ((__v2si) __builtin_spe_evfssub ((__v2sf) a, (__v2sf) b))
-#define __ev_fsmul(a, b) ((__v2si) __builtin_spe_evfsmul ((__v2sf) a, (__v2sf) b))
-#define __ev_fsdiv(a, b) ((__v2si) __builtin_spe_evfsdiv ((__v2sf) a, (__v2sf) b))
-#define __ev_fscfui(a) ((__v2si) __builtin_spe_evfscfui ((__v2si) a))
-#define __ev_fscfsi(a) ((__v2si) __builtin_spe_evfscfsi ((__v2sf) a))
-#define __ev_fscfuf(a) ((__v2si) __builtin_spe_evfscfuf ((__v2sf) a))
-#define __ev_fscfsf(a) ((__v2si) __builtin_spe_evfscfsf ((__v2sf) a))
-#define __ev_fsctui(a) ((__v2si) __builtin_spe_evfsctui ((__v2sf) a))
-#define __ev_fsctsi(a) ((__v2si) __builtin_spe_evfsctsi ((__v2sf) a))
-#define __ev_fsctuf(a) ((__v2si) __builtin_spe_evfsctuf ((__v2sf) a))
-#define __ev_fsctsf(a) ((__v2si) __builtin_spe_evfsctsf ((__v2sf) a))
-#define __ev_fsctuiz(a) ((__v2si) __builtin_spe_evfsctuiz ((__v2sf) a))
-#define __ev_fsctsiz(a) ((__v2si) __builtin_spe_evfsctsiz ((__v2sf) a))
+/* These all return V2SF, but we need to cast them to V2SI
+ because the SPE expect all functions to be __ev64_opaque__. */
+
+#define __ev_fsabs(a) ((__v2si) __builtin_spe_evfsabs ((__v2sf) (a)))
+#define __ev_fsnabs(a) ((__v2si) __builtin_spe_evfsnabs ((__v2sf) (a)))
+#define __ev_fsneg(a) ((__v2si) __builtin_spe_evfsneg ((__v2sf) (a)))
+#define __ev_fsadd(a, b) ((__v2si) __builtin_spe_evfsadd ((__v2sf) (a), (__v2sf) (b)))
+#define __ev_fssub(a, b) ((__v2si) __builtin_spe_evfssub ((__v2sf) (a), (__v2sf) (b)))
+#define __ev_fsmul(a, b) ((__v2si) __builtin_spe_evfsmul ((__v2sf) (a), (__v2sf) b))
+#define __ev_fsdiv(a, b) ((__v2si) __builtin_spe_evfsdiv ((__v2sf) (a), (__v2sf) b))
+#define __ev_fscfui(a) ((__v2si) __builtin_spe_evfscfui ((__v2si) (a)))
+#define __ev_fscfsi(a) ((__v2si) __builtin_spe_evfscfsi ((__v2sf) (a)))
+#define __ev_fscfuf(a) ((__v2si) __builtin_spe_evfscfuf ((__v2sf) (a)))
+#define __ev_fscfsf(a) ((__v2si) __builtin_spe_evfscfsf ((__v2sf) (a)))
+#define __ev_fsctui(a) ((__v2si) __builtin_spe_evfsctui ((__v2sf) (a)))
+#define __ev_fsctsi(a) ((__v2si) __builtin_spe_evfsctsi ((__v2sf) (a)))
+#define __ev_fsctuf(a) ((__v2si) __builtin_spe_evfsctuf ((__v2sf) (a)))
+#define __ev_fsctsf(a) ((__v2si) __builtin_spe_evfsctsf ((__v2sf) (a)))
+#define __ev_fsctuiz(a) ((__v2si) __builtin_spe_evfsctuiz ((__v2sf) (a)))
+#define __ev_fsctsiz(a) ((__v2si) __builtin_spe_evfsctsiz ((__v2sf) (a)))
/* NOT SUPPORTED IN FIRST e500, support via two instructions: */
@@ -332,7 +327,6 @@ typedef int __vector __ev64_opaque__;
#define __ev_mwhgsmfan(a, b) __internal_ev_mwhgsmfan ((__v2si) (a), (__v2si) (b))
#define __ev_mwhgsmian(a, b) __internal_ev_mwhgsmian ((__v2si) (a), (__v2si) (b))
#define __ev_mwhgumian(a, b) __internal_ev_mwhgumian ((__v2si) (a), (__v2si) (b))
-
#define __ev_mwhssiaaw(a, b) __internal_ev_mwhssiaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwhssfaaw(a, b) __internal_ev_mwhssfaaw ((__v2si) (a), (__v2si) (b))
#define __ev_mwhsmfaaw(a, b) __internal_ev_mwhsmfaaw ((__v2si) (a), (__v2si) (b))
@@ -352,7 +346,7 @@ __internal_ev_mwhssfaaw (__ev64_opaque__ a, __ev64_opaque__ b)
__ev64_opaque__ t;
t = __ev_mwhssf (a, b);
- return __ev_addssiaaw(t);
+ return __ev_addssiaaw (t);
}
static inline __ev64_opaque__
@@ -360,7 +354,7 @@ __internal_ev_mwhssiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmi (a,b);
+ t = __ev_mwhsmi (a, b);
return __ev_addssiaaw (t);
}
@@ -369,7 +363,7 @@ __internal_ev_mwhsmfaaw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmf (a,b);
+ t = __ev_mwhsmf (a, b);
return __ev_addsmiaaw (t);
}
@@ -378,7 +372,7 @@ __internal_ev_mwhsmiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmi (a,b);
+ t = __ev_mwhsmi (a, b);
return __ev_addsmiaaw (t);
}
@@ -387,7 +381,7 @@ __internal_ev_mwhusiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhumi (a,b);
+ t = __ev_mwhumi (a, b);
return __ev_addusiaaw (t);
}
@@ -396,7 +390,7 @@ __internal_ev_mwhumiaaw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhumi (a,b);
+ t = __ev_mwhumi (a, b);
return __ev_addumiaaw (t);
}
@@ -405,7 +399,7 @@ __internal_ev_mwhssfanw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhssf (a,b);
+ t = __ev_mwhssf (a, b);
return __ev_subfssiaaw (t);
}
@@ -414,7 +408,7 @@ __internal_ev_mwhssianw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmi (a,b);
+ t = __ev_mwhsmi (a, b);
return __ev_subfssiaaw (t);
}
@@ -423,7 +417,7 @@ __internal_ev_mwhsmfanw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmf (a,b);
+ t = __ev_mwhsmf (a, b);
return __ev_subfsmiaaw (t);
}
@@ -432,7 +426,7 @@ __internal_ev_mwhsmianw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhsmi (a,b);
+ t = __ev_mwhsmi (a, b);
return __ev_subfsmiaaw (t);
}
@@ -441,7 +435,7 @@ __internal_ev_mwhusianw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhumi (a,b);
+ t = __ev_mwhumi (a, b);
return __ev_subfusiaaw (t);
}
@@ -450,7 +444,7 @@ __internal_ev_mwhumianw (__ev64_opaque__ a, __ev64_opaque__ b)
{
__ev64_opaque__ t;
- t = __ev_mwhumi (a,b);
+ t = __ev_mwhumi (a, b);
return __ev_subfumiaaw (t);
}
@@ -619,7 +613,7 @@ __ev_create_sfix32_fs (float a, float b)
__ev64_opaque__ ev;
ev = (__ev64_opaque__) __ev_create_fs (a, b);
- return (__ev64_opaque__) __builtin_spe_evfsctsf (ev);
+ return (__ev64_opaque__) __builtin_spe_evfsctsf ((__v2sf) ev);
}
static inline __ev64_opaque__
@@ -628,7 +622,7 @@ __ev_create_ufix32_fs (float a, float b)
__ev64_opaque__ ev;
ev = (__ev64_opaque__) __ev_create_fs (a, b);
- return (__ev64_opaque__) __builtin_spe_evfsctuf (ev);
+ return (__ev64_opaque__) __builtin_spe_evfsctuf ((__v2sf) ev);
}
static inline __ev64_opaque__
@@ -657,17 +651,26 @@ __ev_create_u64 (uint64_t a)
return u.v;
}
-#define __ev_convert_u64(a) ((uint64_t) (a))
-#define __ev_convert_s64(a) ((int64_t) (a))
+static inline uint64_t
+__ev_convert_u64 (__ev64_opaque__ a)
+{
+ return (uint64_t) a;
+}
+
+static inline int64_t
+__ev_convert_s64 (__ev64_opaque__ a)
+{
+ return (int64_t) a;
+}
/* __ev_get_* functions. */
-#define __ev_get_upper_u32(a) __ev_get_u32_internal ((__ev64_opaque__) a, 0)
-#define __ev_get_lower_u32(a) __ev_get_u32_internal ((__ev64_opaque__) a, 1)
-#define __ev_get_upper_s32(a) __ev_get_s32_internal ((__ev64_opaque__) a, 0)
-#define __ev_get_lower_s32(a) __ev_get_s32_internal ((__ev64_opaque__) a, 1)
-#define __ev_get_upper_fs(a) __ev_get_fs_internal ((__ev64_opaque__) a, 0)
-#define __ev_get_lower_fs(a) __ev_get_fs_internal ((__ev64_opaque__) a, 1)
+#define __ev_get_upper_u32(a) __ev_get_u32_internal ((__ev64_opaque__) (a), 0)
+#define __ev_get_lower_u32(a) __ev_get_u32_internal ((__ev64_opaque__) (a), 1)
+#define __ev_get_upper_s32(a) __ev_get_s32_internal ((__ev64_opaque__) (a), 0)
+#define __ev_get_lower_s32(a) __ev_get_s32_internal ((__ev64_opaque__) (a), 1)
+#define __ev_get_upper_fs(a) __ev_get_fs_internal ((__ev64_opaque__) (a), 0)
+#define __ev_get_lower_fs(a) __ev_get_fs_internal ((__ev64_opaque__) (a), 1)
#define __ev_get_upper_ufix32_u32(a) __ev_get_upper_u32(a)
#define __ev_get_lower_ufix32_u32(a) __ev_get_lower_u32(a)
#define __ev_get_upper_sfix32_s32(a) __ev_get_upper_s32(a)
@@ -677,11 +680,11 @@ __ev_create_u64 (uint64_t a)
#define __ev_get_upper_ufix32_fs(a) __ev_get_ufix32_fs (a, 0)
#define __ev_get_lower_ufix32_fs(a) __ev_get_ufix32_fs (a, 1)
-#define __ev_get_u32(a, b) __ev_get_u32_internal ((__ev64_opaque__) a, b)
-#define __ev_get_s32(a, b) __ev_get_s32_internal ((__ev64_opaque__) a, b)
-#define __ev_get_fs(a, b) __ev_get_fs_internal ((__ev64_opaque__) a, b)
-#define __ev_get_u16(a, b) __ev_get_u16_internal ((__ev64_opaque__) a, b)
-#define __ev_get_s16(a, b) __ev_get_s16_internal ((__ev64_opaque__) a, b)
+#define __ev_get_u32(a, b) __ev_get_u32_internal ((__ev64_opaque__) (a), b)
+#define __ev_get_s32(a, b) __ev_get_s32_internal ((__ev64_opaque__) (a), b)
+#define __ev_get_fs(a, b) __ev_get_fs_internal ((__ev64_opaque__) (a), b)
+#define __ev_get_u16(a, b) __ev_get_u16_internal ((__ev64_opaque__) (a), b)
+#define __ev_get_s16(a, b) __ev_get_s16_internal ((__ev64_opaque__) (a), b)
#define __ev_get_ufix32_u32(a, b) __ev_get_u32 (a, b)
#define __ev_get_sfix32_s32(a, b) __ev_get_s32 (a, b)
@@ -732,8 +735,8 @@ __ev_get_sfix32_fs_internal (__ev64_opaque__ a, uint32_t pos)
{
__ev64_fs__ v;
- v = __builtin_spe_evfscfsf (a);
- return __ev_get_fs_internal (v, pos);
+ v = __builtin_spe_evfscfsf ((__v2sf) a);
+ return __ev_get_fs_internal ((__ev64_opaque__) v, pos);
}
static inline float
@@ -741,8 +744,8 @@ __ev_get_ufix32_fs_internal (__ev64_opaque__ a, uint32_t pos)
{
__ev64_fs__ v;
- v = __builtin_spe_evfscfuf (a);
- return __ev_get_fs_internal (v, pos);
+ v = __builtin_spe_evfscfuf ((__v2sf) a);
+ return __ev_get_fs_internal ((__ev64_opaque__) v, pos);
}
static inline uint16_t
@@ -785,7 +788,7 @@ __ev_get_s16_internal (__ev64_opaque__ a, uint32_t pos)
#define __ev_set_sfix32_fs(a, b, c) __ev_set_sfix32_fs_internal ((__ev64_opaque__) (a), b, c)
#define __ev_set_ufix32_fs(a, b, c) __ev_set_ufix32_fs_internal ((__ev64_opaque__) (a), b, c)
-#define __ev_set_upper_u32(a, b) __ev_set_u32(a, b, 0)
+#define __ev_set_upper_u32(a, b) __ev_set_u32 (a, b, 0)
#define __ev_set_lower_u32(a, b) __ev_set_u32 (a, b, 1)
#define __ev_set_upper_s32(a, b) __ev_set_s32 (a, b, 0)
#define __ev_set_lower_s32(a, b) __ev_set_s32 (a, b, 1)
@@ -821,7 +824,7 @@ __ev_set_acc_s64 (int64_t a)
}
static inline __ev64_opaque__
-__ev_set_u32_internal (__ev64_opaque__ a, uint32_t b, uint32_t pos )
+__ev_set_u32_internal (__ev64_opaque__ a, uint32_t b, uint32_t pos)
{
union
{
@@ -835,7 +838,7 @@ __ev_set_u32_internal (__ev64_opaque__ a, uint32_t b, uint32_t pos )
}
static inline __ev64_opaque__
-__ev_set_s32_internal (__ev64_opaque__ a, int32_t b, uint32_t pos )
+__ev_set_s32_internal (__ev64_opaque__ a, int32_t b, uint32_t pos)
{
union
{
@@ -849,7 +852,7 @@ __ev_set_s32_internal (__ev64_opaque__ a, int32_t b, uint32_t pos )
}
static inline __ev64_opaque__
-__ev_set_fs_internal (__ev64_opaque__ a, float b, uint32_t pos )
+__ev_set_fs_internal (__ev64_opaque__ a, float b, uint32_t pos)
{
union
{
@@ -895,7 +898,7 @@ __ev_set_ufix32_fs_internal (__ev64_opaque__ a, float b, uint32_t pos)
}
static inline __ev64_opaque__
-__ev_set_u16_internal (__ev64_opaque__ a, uint16_t b, uint32_t pos )
+__ev_set_u16_internal (__ev64_opaque__ a, uint16_t b, uint32_t pos)
{
union
{
@@ -909,7 +912,7 @@ __ev_set_u16_internal (__ev64_opaque__ a, uint16_t b, uint32_t pos )
}
static inline __ev64_opaque__
-__ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos )
+__ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos)
{
union
{
@@ -929,136 +932,70 @@ __ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos )
#define __pred_upper 2
#define __pred_lower 3
-#define __ev_any_gts(a, b) \
- __builtin_spe_evcmpgts (__pred_any, (__v2si)(a), (__v2si)(b))
-#define __ev_all_gts(a, b) \
- __builtin_spe_evcmpgts (__pred_all, (__v2si)(a), (__v2si)(b))
-#define __ev_upper_gts(a, b) \
- __builtin_spe_evcmpgts (__pred_upper, (__v2si)(a), (__v2si)(b))
-#define __ev_lower_gts(a, b) \
- __builtin_spe_evcmpgts (__pred_lower, (__v2si)(a), (__v2si)(b))
-#define __ev_select_gts(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_gts ((__v2si)(a), (__v2si)(b), \
- (__v2si)(c), (__v2si)(d)))
-
-#define __ev_any_gtu(a, b) \
- __builtin_spe_evcmpgtu (__pred_any, (__v2si)(a), (__v2si)(b))
-#define __ev_all_gtu(a, b) \
- __builtin_spe_evcmpgtu (__pred_all, (__v2si)(a), (__v2si)(b))
-#define __ev_upper_gtu(a, b) \
- __builtin_spe_evcmpgtu (__pred_upper, (__v2si)(a), (__v2si)(b))
-#define __ev_lower_gtu(a, b) \
- __builtin_spe_evcmpgtu (__pred_lower, (__v2si)(a), (__v2si)(b))
-#define __ev_select_gtu(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_gtu ((__v2si)(a), (__v2si)(b), \
- (__v2si)(c), (__v2si)(d)))
-
-#define __ev_any_lts(a, b) \
- __builtin_spe_evcmplts (__pred_any, (__v2si)(a), (__v2si)(b))
-#define __ev_all_lts(a, b) \
- __builtin_spe_evcmplts (__pred_all, (__v2si)(a), (__v2si)(b))
-#define __ev_upper_lts(a, b) \
- __builtin_spe_evcmplts (__pred_upper, (__v2si)(a), (__v2si)(b))
-#define __ev_lower_lts(a, b) \
- __builtin_spe_evcmplts (__pred_lower, (__v2si)(a), (__v2si)(b))
-#define __ev_select_lts(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_lts ((__v2si)(a), (__v2si)(b), \
- (__v2si)(c), (__v2si)(d)))
-
-#define __ev_any_ltu(a, b) \
- __builtin_spe_evcmpltu (__pred_any, (__v2si)(a), (__v2si)(b))
-#define __ev_all_ltu(a, b) \
- __builtin_spe_evcmpltu (__pred_all, (__v2si)(a), (__v2si)(b))
-#define __ev_upper_ltu(a, b) \
- __builtin_spe_evcmpltu (__pred_upper, (__v2si)(a), (__v2si)(b))
-#define __ev_lower_ltu(a, b) \
- __builtin_spe_evcmpltu (__pred_lower, (__v2si)(a), (__v2si)(b))
-#define __ev_select_ltu(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_ltu ((__v2si)(a), (__v2si)(b), \
- (__v2si)(c), (__v2si)(d)))
-#define __ev_any_eq(a, b) \
- __builtin_spe_evcmpeq (__pred_any, (__v2si)(a), (__v2si)(b))
-#define __ev_all_eq(a, b) \
- __builtin_spe_evcmpeq (__pred_all, (__v2si)(a), (__v2si)(b))
-#define __ev_upper_eq(a, b) \
- __builtin_spe_evcmpeq (__pred_upper, (__v2si)(a), (__v2si)(b))
-#define __ev_lower_eq(a, b) \
- __builtin_spe_evcmpeq (__pred_lower, (__v2si)(a), (__v2si)(b))
-#define __ev_select_eq(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_eq ((__v2si)(a), (__v2si)(b), \
- (__v2si)(c), (__v2si)(d)))
-
-#define __ev_any_fs_gt(a, b) \
- __builtin_spe_evfscmpgt (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_gt(a, b) \
- __builtin_spe_evfscmpgt (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_gt(a, b) \
- __builtin_spe_evfscmpgt (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_gt(a, b) \
- __builtin_spe_evfscmpgt (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_gt(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fsgt ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
-
-#define __ev_any_fs_lt(a, b) \
- __builtin_spe_evfscmplt (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_lt(a, b) \
- __builtin_spe_evfscmplt (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_lt(a, b) \
- __builtin_spe_evfscmplt (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_lt(a, b) \
- __builtin_spe_evfscmplt (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_lt(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fslt ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
-
-#define __ev_any_fs_eq(a, b) \
- __builtin_spe_evfscmpeq (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_eq(a, b) \
- __builtin_spe_evfscmpeq (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_eq(a, b) \
- __builtin_spe_evfscmpeq (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_eq(a, b) \
- __builtin_spe_evfscmpeq (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_eq(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fseq ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
-
-#define __ev_any_fs_tst_gt(a, b) \
- __builtin_spe_evfststgt (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_tst_gt(a, b) \
- __builtin_spe_evfststgt (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_tst_gt(a, b) \
- __builtin_spe_evfststgt (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_tst_gt(a, b) \
- __builtin_spe_evfststgt (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_tst_gt(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fststgt ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
-
-#define __ev_any_fs_tst_lt(a, b) \
- __builtin_spe_evfststlt (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_tst_lt(a, b) \
- __builtin_spe_evfststlt (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_tst_lt(a, b) \
- __builtin_spe_evfststlt (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_tst_lt(a, b) \
- __builtin_spe_evfststlt (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_tst_lt(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fststlt ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
-
-#define __ev_any_fs_tst_eq(a, b) \
- __builtin_spe_evfststeq (__pred_any, (__v2sf)(a), (__v2sf)(b))
-#define __ev_all_fs_tst_eq(a, b) \
- __builtin_spe_evfststeq (__pred_all, (__v2sf)(a), (__v2sf)(b))
-#define __ev_upper_fs_tst_eq(a, b) \
- __builtin_spe_evfststeq (__pred_upper, (__v2sf)(a), (__v2sf)(b))
-#define __ev_lower_fs_tst_eq(a, b) \
- __builtin_spe_evfststeq (__pred_lower, (__v2sf)(a), (__v2sf)(b))
-#define __ev_select_fs_tst_eq(a, b, c, d) \
- ((__v2si) __builtin_spe_evsel_fststeq ((__v2sf)(a), (__v2sf)(b), \
- (__v2sf)(c), (__v2sf)(d)))
+#define __ev_any_gts(a, b) __builtin_spe_evcmpgts (__pred_any, (__v2si) (a), (__v2si) (b))
+#define __ev_all_gts(a, b) __builtin_spe_evcmpgts (__pred_all, (__v2si) (a), (__v2si) (b))
+#define __ev_upper_gts(a, b) __builtin_spe_evcmpgts (__pred_upper, (__v2si) (a), (__v2si) (b))
+#define __ev_lower_gts(a, b) __builtin_spe_evcmpgts (__pred_lower, (__v2si) (a), (__v2si) (b))
+#define __ev_select_gts(a, b, c, d) ((__v2si) __builtin_spe_evsel_gts ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d)))
+
+#define __ev_any_gtu(a, b) __builtin_spe_evcmpgtu (__pred_any, (__v2si) (a), (__v2si) (b))
+#define __ev_all_gtu(a, b) __builtin_spe_evcmpgtu (__pred_all, (__v2si) (a), (__v2si) (b))
+#define __ev_upper_gtu(a, b) __builtin_spe_evcmpgtu (__pred_upper, (__v2si) (a), (__v2si) (b))
+#define __ev_lower_gtu(a, b) __builtin_spe_evcmpgtu (__pred_lower, (__v2si) (a), (__v2si) (b))
+#define __ev_select_gtu(a, b, c, d) ((__v2si) __builtin_spe_evsel_gtu ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d)))
+
+#define __ev_any_lts(a, b) __builtin_spe_evcmplts (__pred_any, (__v2si) (a), (__v2si) (b))
+#define __ev_all_lts(a, b) __builtin_spe_evcmplts (__pred_all, (__v2si) (a), (__v2si) (b))
+#define __ev_upper_lts(a, b) __builtin_spe_evcmplts (__pred_upper, (__v2si) (a), (__v2si) (b))
+#define __ev_lower_lts(a, b) __builtin_spe_evcmplts (__pred_lower, (__v2si) (a), (__v2si) (b))
+#define __ev_select_lts(a, b, c, d) ((__v2si) __builtin_spe_evsel_lts ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d)))
+
+#define __ev_any_ltu(a, b) __builtin_spe_evcmpltu (__pred_any, (__v2si) (a), (__v2si) (b))
+#define __ev_all_ltu(a, b) __builtin_spe_evcmpltu (__pred_all, (__v2si) (a), (__v2si) (b))
+#define __ev_upper_ltu(a, b) __builtin_spe_evcmpltu (__pred_upper, (__v2si) (a), (__v2si) (b))
+#define __ev_lower_ltu(a, b) __builtin_spe_evcmpltu (__pred_lower, (__v2si) (a), (__v2si) (b))
+#define __ev_select_ltu(a, b, c, d) ((__v2si) __builtin_spe_evsel_ltu ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d)))
+#define __ev_any_eq(a, b) __builtin_spe_evcmpeq (__pred_any, (__v2si) (a), (__v2si) (b))
+#define __ev_all_eq(a, b) __builtin_spe_evcmpeq (__pred_all, (__v2si) (a), (__v2si) (b))
+#define __ev_upper_eq(a, b) __builtin_spe_evcmpeq (__pred_upper, (__v2si) (a), (__v2si) (b))
+#define __ev_lower_eq(a, b) __builtin_spe_evcmpeq (__pred_lower, (__v2si) (a), (__v2si) (b))
+#define __ev_select_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_eq ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d)))
+
+#define __ev_any_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_gt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fsgt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
+
+#define __ev_any_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_lt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fslt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
+
+#define __ev_any_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_fseq ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
+
+#define __ev_any_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_tst_gt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststgt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
+
+#define __ev_any_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_tst_lt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststlt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
+
+#define __ev_any_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_any, (__v2sf) (a), (__v2sf) (b))
+#define __ev_all_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_all, (__v2sf) (a), (__v2sf) (b))
+#define __ev_upper_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_upper, (__v2sf) (a), (__v2sf) (b))
+#define __ev_lower_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_lower, (__v2sf) (a), (__v2sf) (b))
+#define __ev_select_fs_tst_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststeq ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d)))
/* SPEFSCR accesor functions. */
@@ -1070,7 +1007,7 @@ __ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos )
#define __SPEFSCR_FDBZH 0x04000000
#define __SPEFSCR_FUNFH 0x02000000
#define __SPEFSCR_FOVFH 0x01000000
-/* 2 unused bits */
+/* 2 unused bits. */
#define __SPEFSCR_FINXS 0x00200000
#define __SPEFSCR_FINVS 0x00100000
#define __SPEFSCR_FDBZS 0x00080000
@@ -1085,7 +1022,7 @@ __ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos )
#define __SPEFSCR_FDBZ 0x00000400
#define __SPEFSCR_FUNF 0x00000200
#define __SPEFSCR_FOVF 0x00000100
-/* 1 unused bit */
+/* 1 unused bit. */
#define __SPEFSCR_FINXE 0x00000040
#define __SPEFSCR_FINVE 0x00000020
#define __SPEFSCR_FDBZE 0x00000010
@@ -1144,8 +1081,8 @@ __ev_clr_spefscr_field (int mask)
rnd = 0 (nearest)
rnd = 1 (zero)
rnd = 2 (+inf)
- rnd = 3 (-inf)
-*/
+ rnd = 3 (-inf). */
+
static inline void
__ev_set_spefscr_frmc (int rnd)
{
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 68fa73f7997..861ca538362 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -1,5 +1,5 @@
/* Target definitions for GNU compiler for PowerPC running System V.4
- Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
+ Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Contributed by Cygnus Support.
@@ -683,12 +683,12 @@ do { \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \
} \
+ ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
} while (0)
/* Describe how to emit uninitialized external linkage items. */
#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
do { \
- (*targetm.asm_out.globalize_label) (FILE, NAME); \
ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
} while (0)
@@ -1205,6 +1205,21 @@ ncrtn.o%s"
#define CPP_OS_NETBSD_SPEC "\
-D__powerpc__ -D__NetBSD__ -D__ELF__ -D__KPRINTF_ATTRIBUTE__"
+/* RTEMS support. */
+
+#define CPP_OS_RTEMS_SPEC "\
+%{!mcpu*: %{!Dppc*: %{!Dmpc*: -Dmpc750} } }\
+%{mcpu=403: %{!Dppc*: %{!Dmpc*: -Dppc403} } } \
+%{mcpu=505: %{!Dppc*: %{!Dmpc*: -Dmpc505} } } \
+%{mcpu=601: %{!Dppc*: %{!Dmpc*: -Dppc601} } } \
+%{mcpu=602: %{!Dppc*: %{!Dmpc*: -Dppc602} } } \
+%{mcpu=603: %{!Dppc*: %{!Dmpc*: -Dppc603} } } \
+%{mcpu=603e: %{!Dppc*: %{!Dmpc*: -Dppc603e} } } \
+%{mcpu=604: %{!Dppc*: %{!Dmpc*: -Dmpc604} } } \
+%{mcpu=750: %{!Dppc*: %{!Dmpc*: -Dmpc750} } } \
+%{mcpu=821: %{!Dppc*: %{!Dmpc*: -Dmpc821} } } \
+%{mcpu=860: %{!Dppc*: %{!Dmpc*: -Dmpc860} } }"
+
/* VxWorks support. */
/* VxWorks does all the library stuff itself. */
#define LIB_VXWORKS_SPEC ""
@@ -1343,6 +1358,7 @@ ncrtn.o%s"
{ "cpp_os_gnu", CPP_OS_GNU_SPEC }, \
{ "cpp_os_linux", CPP_OS_LINUX_SPEC }, \
{ "cpp_os_netbsd", CPP_OS_NETBSD_SPEC }, \
+ { "cpp_os_rtems", CPP_OS_RTEMS_SPEC }, \
{ "cpp_os_vxworks", CPP_OS_VXWORKS_SPEC }, \
{ "cpp_os_windiss", CPP_OS_WINDISS_SPEC }, \
{ "cpp_os_default", CPP_OS_DEFAULT_SPEC },
diff --git a/gcc/config/rs6000/t-aix43 b/gcc/config/rs6000/t-aix43
index 1acccf64d10..a716209e9bc 100644
--- a/gcc/config/rs6000/t-aix43
+++ b/gcc/config/rs6000/t-aix43
@@ -55,7 +55,7 @@ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
rm -f @multilib_dir@/shr.o
# $(slibdir) double quoted to protect it from expansion while building
# libgcc.mk. We want this delayed until actual install time.
-SHLIB_INSTALL = $(INSTALL_DATA) @shlib_base_name@.a $$(slibdir)/
+SHLIB_INSTALL = $(INSTALL_DATA) @shlib_base_name@.a $$(DESTDIR)$$(slibdir)/
SHLIB_LIBS = -lc `case @shlib_base_name@ in *pthread*) echo -lpthread ;; esac`
SHLIB_MKMAP = $(srcdir)/mkmap-flat.awk
SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver
diff --git a/gcc/config/rs6000/t-aix52 b/gcc/config/rs6000/t-aix52
index 97e1e079508..bddcdb11490 100644
--- a/gcc/config/rs6000/t-aix52
+++ b/gcc/config/rs6000/t-aix52
@@ -36,7 +36,7 @@ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \
rm -f @multilib_dir@/shr.o
# $(slibdir) double quoted to protect it from expansion while building
# libgcc.mk. We want this delayed until actual install time.
-SHLIB_INSTALL = $(INSTALL_DATA) @shlib_base_name@.a $$(slibdir)/
+SHLIB_INSTALL = $(INSTALL_DATA) @shlib_base_name@.a $$(DESTDIR)$$(slibdir)/
SHLIB_LIBS = -lc `case @shlib_base_name@ in *pthread*) echo -lpthread ;; esac`
SHLIB_MKMAP = $(srcdir)/mkmap-flat.awk
SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver
diff --git a/gcc/config/rs6000/t-linux64 b/gcc/config/rs6000/t-linux64
index 48b61505bf1..af7b44bd70b 100644
--- a/gcc/config/rs6000/t-linux64
+++ b/gcc/config/rs6000/t-linux64
@@ -5,6 +5,9 @@ TARGET_LIBGCC2_CFLAGS =
EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o \
crtsavres.o
+# These functions are needed for soft-float on powerpc64-linux.
+LIB2FUNCS_EXTRA = $(srcdir)/config/rs6000/ppc64-fp.c
+
# ld provides these functions as needed.
crtsavres.S:
echo >crtsavres.S
diff --git a/gcc/config/rs6000/t-rtems b/gcc/config/rs6000/t-rtems
new file mode 100644
index 00000000000..364a22d2278
--- /dev/null
+++ b/gcc/config/rs6000/t-rtems
@@ -0,0 +1,86 @@
+# Multilibs for powerpc RTEMS targets.
+
+MULTILIB_OPTIONS = \
+mcpu=403/mcpu=505/mcpu=601/mcpu=602/mcpu=603/mcpu=603e/mcpu=604/mcpu=750/mcpu=821/mcpu=860 \
+Dmpc509/Dmpc8260 \
+D_OLD_EXCEPTIONS \
+msoft-float
+
+MULTILIB_DIRNAMES = \
+m403 m505 m601 m602 m603 m603e m604 m750 m821 m860 \
+mpc509 \
+mpc8260 \
+roe \
+nof
+
+MULTILIB_EXTRA_OPTS = mrelocatable-lib mno-eabi mstrict-align
+
+# MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT}
+MULTILIB_MATCHES = ${MULTILIB_MATCHES_ENDIAN} \
+ ${MULTILIB_MATCHES_SYSV} \
+ mcpu?505/Dmpc505=mcpu?505/Dmpc509
+
+#
+# RTEMS old/new-exceptions handling
+#
+# old-exception processing is depredicated, therefore
+#
+# * Cpu-variants supporting new exception processing are build
+# with new exception processing only
+# * Cpu-variants not having been ported to new exception processing are
+# build with old and new exception processing
+#
+
+# Cpu-variants supporting new exception processing only
+MULTILIB_NEW_EXCEPTIONS_ONLY = \
+*mcpu=604*/*D_OLD_EXCEPTIONS* \
+*mcpu=750*/*D_OLD_EXCEPTIONS* \
+*mcpu=821*/*D_OLD_EXCEPTIONS* \
+*Dmpc8260*/*D_OLD_EXCEPTIONS* \
+*mcpu=860*/*D_OLD_EXCEPTIONS*
+
+# Soft-float only, default implies msoft-float
+# NOTE: Must match with MULTILIB_MATCHES_FLOAT and MULTILIB_MATCHES
+MULTILIB_SOFTFLOAT_ONLY = \
+mcpu=403/*msoft-float* \
+mcpu=821/*msoft-float* \
+mcpu=860/*msoft-float*
+
+# Hard-float only, take out msoft-float
+MULTILIB_HARDFLOAT_ONLY = \
+mcpu=505/*msoft-float*
+
+MULTILIB_EXCEPTIONS =
+
+# Disallow -D_OLD_EXCEPTIONS without other options
+MULTILIB_EXCEPTIONS += D_OLD_EXCEPTIONS*
+
+# Disallow -Dppc and -Dmpc without other options
+MULTILIB_EXCEPTIONS += Dppc* Dmpc*
+
+MULTILIB_EXCEPTIONS += \
+${MULTILIB_NEW_EXCEPTIONS_ONLY} \
+${MULTILIB_SOFTFLOAT_ONLY} \
+${MULTILIB_HARDFLOAT_ONLY}
+
+# Special rules
+# Take out all variants we don't want
+MULTILIB_EXCEPTIONS += mcpu=403/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=403/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=505/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=505/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=601/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=601/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=602/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=602/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=603/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=603/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=603e/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=604/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=604/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=750/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=750/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=821/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=821/Dmpc8260*
+MULTILIB_EXCEPTIONS += mcpu=860/Dmpc509*
+MULTILIB_EXCEPTIONS += mcpu=860/Dmpc8260*
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-25 03:54:27 +0000