diff options
Diffstat (limited to 'gcc/config/s390/s390.h')
| -rw-r--r-- | gcc/config/s390/s390.h | 1265 |
1 files changed, 498 insertions, 767 deletions
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h index c5ba4270d37..6d8943e760d 100644 --- a/gcc/config/s390/s390.h +++ b/gcc/config/s390/s390.h @@ -22,13 +22,29 @@ Boston, MA 02111-1307, USA. */ #ifndef _S390_H #define _S390_H -extern int flag_pic; +/* Override the __fixdfdi etc. routines when building libgcc2. + ??? This should be done in a cleaner way ... */ +#ifdef IN_LIBGCC2 +#include <s390/fixdfdi.h> +#endif -/* Run-time compilation parameters selecting different hardware subsets. */ -extern int target_flags; +/* Run-time target specification. */ + +/* Target CPU builtins. */ +#define TARGET_CPU_CPP_BUILTINS() \ + do \ + { \ + builtin_assert ("cpu=s390"); \ + builtin_assert ("machine=s390"); \ + builtin_define ("__s390__"); \ + if (TARGET_64BIT) \ + builtin_define ("__s390x__"); \ + } \ + while (0) -/* Target macros checked at runtime of compiler. */ +/* Optional target features. */ +extern int target_flags; #define TARGET_HARD_FLOAT (target_flags & 1) #define TARGET_SOFT_FLOAT (!(target_flags & 1)) @@ -38,20 +54,16 @@ extern int target_flags; #define TARGET_64BIT (target_flags & 16) #define TARGET_MVCLE (target_flags & 32) +/* ??? Once this actually works, it could be made a runtime option. */ +#define TARGET_IBM_FLOAT 0 +#define TARGET_IEEE_FLOAT 1 + #ifdef DEFAULT_TARGET_64BIT #define TARGET_DEFAULT 0x13 -#define TARGET_VERSION fprintf (stderr, " (zSeries)"); #else #define TARGET_DEFAULT 0x3 -#define TARGET_VERSION fprintf (stderr, " (S/390)"); #endif - -/* Macro to define tables used to set the flags. This is a list in braces - of pairs in braces, each pair being { "NAME", VALUE } - where VALUE is the bits to set or minus the bits to clear. - An empty string NAME is used to identify the default VALUE. */ - #define TARGET_SWITCHES \ { { "hard-float", 1, N_("Use hardware fp")}, \ { "soft-float", -1, N_("Don't use hardware fp")}, \ @@ -67,97 +79,37 @@ extern int target_flags; { "no-mvcle", -32, N_("mvc&ex")}, \ { "", TARGET_DEFAULT, 0 } } -/* Define this to change the optimizations performed by default. */ -#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) +/* Target version string. Overridden by the OS header. */ +#ifdef DEFAULT_TARGET_64BIT +#define TARGET_VERSION fprintf (stderr, " (zSeries)"); +#else +#define TARGET_VERSION fprintf (stderr, " (S/390)"); +#endif -/* Sometimes certain combinations of command options do not make sense - on a particular target machine. You can define a macro - `OVERRIDE_OPTIONS' to take account of this. This macro, if - defined, is executed once just after all the command options have - been parsed. */ +/* Hooks to override options. */ +#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) #define OVERRIDE_OPTIONS override_options () -/* Target CPU builtins. */ -#define TARGET_CPU_CPP_BUILTINS() \ - do \ - { \ - builtin_assert ("cpu=s390"); \ - builtin_assert ("machine=s390"); \ - builtin_define ("__s390__"); \ - if (TARGET_64BIT) \ - builtin_define ("__s390x__"); \ - } \ - while (0) - -/* Defines for real.c. */ -#define IEEE_FLOAT 1 -#define TARGET_IBM_FLOAT 0 -#define TARGET_IEEE_FLOAT 1 - -/* The current function count for create unique internal labels. */ - -extern int s390_function_count; - -/* The amount of space used for outgoing arguments. */ +/* Frame pointer is not used for debugging. */ +#define CAN_DEBUG_WITHOUT_FP -extern int current_function_outgoing_args_size; /* Target machine storage layout. */ -/* Define this if most significant bit is lowest numbered in instructions - that operate on numbered bit-fields. */ - +/* Everything is big-endian. */ #define BITS_BIG_ENDIAN 1 - -/* Define this if most significant byte of a word is the lowest numbered. */ - #define BYTES_BIG_ENDIAN 1 - -/* Define this if MS word of a multiword is the lowest numbered. */ - #define WORDS_BIG_ENDIAN 1 -#define MAX_BITS_PER_WORD 64 - /* Width of a word, in units (bytes). */ - #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) #define MIN_UNITS_PER_WORD 4 +#define MAX_BITS_PER_WORD 64 -/* A C expression for the size in bits of the type `short' on the - target machine. If you don't define this, the default is half a - word. (If this would be less than one storage unit, it is - rounded up to one unit.) */ -#define SHORT_TYPE_SIZE 16 - -/* A C expression for the size in bits of the type `int' on the - target machine. If you don't define this, the default is one - word. */ -#define INT_TYPE_SIZE 32 - -/* A C expression for the size in bits of the type `long' on the - target machine. If you don't define this, the default is one - word. */ -#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) -#define MAX_LONG_TYPE_SIZE 64 - -/* A C expression for the size in bits of the type `long long' on the - target machine. If you don't define this, the default is two - words. */ -#define LONG_LONG_TYPE_SIZE 64 - -/* Right now we only support two floating point formats, the - 32 and 64 bit ieee formats. */ - -#define FLOAT_TYPE_SIZE 32 -#define DOUBLE_TYPE_SIZE 64 -#define LONG_DOUBLE_TYPE_SIZE 64 - -/* Define this macro if it is advisable to hold scalars in registers - in a wider mode than that declared by the program. In such cases, - the value is constrained to be within the bounds of the declared - type, but kept valid in the wider mode. The signedness of the - extension may differ from that of the type. */ +/* Function arguments and return values are promoted to word size. */ +#define PROMOTE_FUNCTION_ARGS +#define PROMOTE_FUNCTION_RETURN +#define PROMOTE_FOR_CALL_ONLY #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ if (INTEGRAL_MODE_P (MODE) && \ @@ -165,105 +117,107 @@ if (INTEGRAL_MODE_P (MODE) && \ (MODE) = Pmode; \ } -/* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign - extensions applied to char/short functions arguments. Defining - PROMOTE_FUNCTION_RETURN does the same for function returns. */ - -#define PROMOTE_FUNCTION_ARGS -#define PROMOTE_FUNCTION_RETURN -#define PROMOTE_FOR_CALL_ONLY - -/* Allocation boundary (in *bits*) for storing pointers in memory. */ - -#define POINTER_BOUNDARY 32 - /* Allocation boundary (in *bits*) for storing arguments in argument list. */ - #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) /* Boundary (in *bits*) on which stack pointer should be aligned. */ - #define STACK_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ - #define FUNCTION_BOUNDARY 32 /* There is no point aligning anything to a rounder boundary than this. */ - #define BIGGEST_ALIGNMENT 64 /* Alignment of field after `int : 0' in a structure. */ - #define EMPTY_FIELD_BOUNDARY 32 /* Alignment on even addresses for LARL instruction. */ - #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) - #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) -/* Define this if move instructions will actually fail to work when given - unaligned data. */ - +/* Alignment is not required by the hardware. */ #define STRICT_ALIGNMENT 0 +/* Mode of stack savearea. + FUNCTION is VOIDmode because calling convention maintains SP. + BLOCK needs Pmode for SP. + NONLOCAL needs twice Pmode to maintain both backchain and SP. */ +#define STACK_SAVEAREA_MODE(LEVEL) \ + (LEVEL == SAVE_FUNCTION ? VOIDmode \ + : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) + /* Define target floating point format. */ +#define TARGET_FLOAT_FORMAT \ + (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT) -#undef TARGET_FLOAT_FORMAT -#ifdef IEEE_FLOAT -#define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT -#else -#define TARGET_FLOAT_FORMAT IBM_FLOAT_FORMAT -#endif -/* Define if special allocation order desired. */ +/* Type layout. */ -#define REG_ALLOC_ORDER \ -{ 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \ - 16, 17, 18, 19, 20, 21, 22, 23, \ - 24, 25, 26, 27, 28, 29, 30, 31, \ - 15, 32, 33, 34 } +/* Sizes in bits of the source language data types. */ +#define SHORT_TYPE_SIZE 16 +#define INT_TYPE_SIZE 32 +#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) +#define MAX_LONG_TYPE_SIZE 64 +#define LONG_LONG_TYPE_SIZE 64 +#define FLOAT_TYPE_SIZE 32 +#define DOUBLE_TYPE_SIZE 64 +#define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */ -/* Standard register usage. */ +/* We use "unsigned char" as default. */ +#define DEFAULT_SIGNED_CHAR 0 + + +/* Register usage. */ + +/* We have 16 general purpose registers (registers 0-15), + and 16 floating point registers (registers 16-31). + (On non-IEEE machines, we have only 4 fp registers.) -#define INT_REGNO_P(N) ( (int)(N) >= 0 && (N) < 16 ) -#ifdef IEEE_FLOAT -#define FLOAT_REGNO_P(N) ( (N) >= 16 && (N) < 32 ) -#else -#define FLOAT_REGNO_P(N) ( (N) >= 16 && (N) < 20 ) -#endif -#define CC_REGNO_P(N) ( (N) == 33 ) - -/* Number of actual hardware registers. The hardware registers are - assigned numbers for the compiler from 0 to just below - FIRST_PSEUDO_REGISTER. - All registers that the compiler knows about must be given numbers, - even those that are not normally considered general registers. - For the 390, we give the data registers numbers 0-15, - and the floating point registers numbers 16-19. - G5 and following have 16 IEEE floating point register, - which get numbers 16-31. */ + Amongst the general purpose registers, some are used + for specific purposes: + GPR 11: Hard frame pointer (if needed) + GPR 12: Global offset table pointer (if needed) + GPR 13: Literal pool base register + GPR 14: Return address register + GPR 15: Stack pointer + + Registers 32-34 are 'fake' hard registers that do not + correspond to actual hardware: + Reg 32: Argument pointer + Reg 33: Condition code + Reg 34: Frame pointer */ #define FIRST_PSEUDO_REGISTER 35 -/* Number of hardware registers that go into the DWARF-2 unwind info. - If not defined, equals FIRST_PSEUDO_REGISTER. */ - -#define DWARF_FRAME_REGISTERS 34 +/* Standard register usage. */ +#define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) +#define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) +#define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20)) +#define CC_REGNO_P(N) ((N) == 33) -/* The following register have a fix usage - GPR 12: GOT register points to the GOT, setup in prologue, - GOT contains pointer to variables in shared libraries - GPR 13: Base register setup in prologue to point to the - literal table of each function - GPR 14: Return registers holds the return address - GPR 15: Stack pointer */ +#define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) +#define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) +#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) +#define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) -#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) #define BASE_REGISTER 13 #define RETURN_REGNUM 14 -#define STACK_POINTER_REGNUM 15 +#define CC_REGNUM 33 + +/* Set up fixed registers and calling convention: + + GPRs 0-5 are always call-clobbered, + GPRs 6-15 are always call-saved. + GPR 12 is fixed if used as GOT pointer. + GPR 13 is always fixed (as literal pool pointer). + GPR 14 is always fixed (as return address). + GPR 15 is always fixed (as stack pointer). + The 'fake' hard registers are call-clobbered and fixed. + + On 31-bit, FPRs 18-19 are call-clobbered; + on 64-bit, FPRs 24-31 are call-clobbered. + The remaining FPRs are call-saved. */ #define FIXED_REGISTERS \ { 0, 0, 0, 0, \ @@ -276,12 +230,6 @@ if (INTEGRAL_MODE_P (MODE) && \ 0, 0, 0, 0, \ 1, 1, 1 } -/* 1 for registers not available across function calls. These must include - the FIXED_REGISTERS and also any registers that can be used without being - saved. - The latter must include the registers where values are returned - and the register where structure-value addresses are passed. */ - #define CALL_USED_REGISTERS \ { 1, 1, 1, 1, \ 1, 1, 0, 0, \ @@ -293,10 +241,6 @@ if (INTEGRAL_MODE_P (MODE) && \ 1, 1, 1, 1, \ 1, 1, 1 } -/* Like `CALL_USED_REGISTERS' except this macro doesn't require that - the entire set of `FIXED_REGISTERS' be included. - (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). */ - #define CALL_REALLY_USED_REGISTERS \ { 1, 1, 1, 1, \ 1, 1, 0, 0, \ @@ -308,8 +252,6 @@ if (INTEGRAL_MODE_P (MODE) && \ 1, 1, 1, 1, \ 1, 1, 1 } -/* Macro to conditionally modify fixed_regs/call_used_regs. */ - #define CONDITIONAL_REGISTER_USAGE \ do \ { \ @@ -332,134 +274,82 @@ do \ } \ } while (0) -/* The following register have a special usage - GPR 11: Frame pointer if needed to point to automatic variables. - GPR 32: In functions with more the 5 args this register - points to that arguments, it is always eliminated - with stack- or frame-pointer. - GPR 33: Condition code 'register' */ - -#define HARD_FRAME_POINTER_REGNUM 11 -#define FRAME_POINTER_REGNUM 34 - -#define ARG_POINTER_REGNUM 32 - -#define CC_REGNUM 33 - -/* We use the register %r0 to pass the static chain to a nested function. - - Note: It is assumed that this register is call-clobbered! - We can't use any of the function-argument registers either, - and register 1 is needed by the trampoline code, so we have - no other choice but using this one ... */ +/* Preferred register allocation order. */ +#define REG_ALLOC_ORDER \ +{ 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \ + 16, 17, 18, 19, 20, 21, 22, 23, \ + 24, 25, 26, 27, 28, 29, 30, 31, \ + 15, 32, 33, 34 } -#define STATIC_CHAIN_REGNUM 0 -/* Return number of consecutive hard regs needed starting at reg REGNO - to hold something of mode MODE. - This is ordinarily the length in words of a value of mode MODE - but can be less for certain modes in special long registers. */ +/* Fitting values into registers. */ + +/* Integer modes <= word size fit into any GPR. + Integer modes > word size fit into successive GPRs, starting with + an even-numbered register. + SImode and DImode fit into FPRs as well. + + Floating point modes <= word size fit into any FPR or GPR. + Floating point modes > word size (i.e. DFmode on 32-bit) fit + into any FPR, or an even-odd GPR pair. + + Complex floating point modes fit either into two FPRs, or into + successive GPRs (again starting with an even number). + + Condition code modes fit only into the CC register. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ - (FLOAT_REGNO_P(REGNO)? \ + (FP_REGNO_P(REGNO)? \ (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ - INT_REGNO_P(REGNO)? \ + GENERAL_REGNO_P(REGNO)? \ ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \ 1) -/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. - The gprs can hold QI, HI, SI, SF, DF, SC and DC. - Even gprs can hold DI. - The floating point registers can hold DF, SF, DC and SC. */ - #define HARD_REGNO_MODE_OK(REGNO, MODE) \ - (FLOAT_REGNO_P(REGNO)? \ - (GET_MODE_CLASS(MODE) == MODE_FLOAT || \ - GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT || \ - (MODE) == SImode || (MODE) == DImode) : \ - INT_REGNO_P(REGNO)? \ + (FP_REGNO_P(REGNO)? \ + ((MODE) == SImode || (MODE) == DImode || \ + GET_MODE_CLASS(MODE) == MODE_FLOAT || \ + GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \ + GENERAL_REGNO_P(REGNO)? \ (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \ CC_REGNO_P(REGNO)? \ GET_MODE_CLASS (MODE) == MODE_CC : \ 0) -/* Value is 1 if it is a good idea to tie two pseudo registers when one has - mode MODE1 and one has mode MODE2. - If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ - #define MODES_TIEABLE_P(MODE1, MODE2) \ (((MODE1) == SFmode || (MODE1) == DFmode) \ == ((MODE2) == SFmode || (MODE2) == DFmode)) -/* If defined, gives a class of registers that cannot be used as the - operand of a SUBREG that changes the mode of the object illegally. */ - -#define CLASS_CANNOT_CHANGE_MODE FP_REGS - -/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ - -#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) - -/* This is an array of structures. Each structure initializes one pair - of eliminable registers. The "from" register number is given first, - followed by "to". Eliminations of the same "from" register are listed - in order of preference. */ - -#define ELIMINABLE_REGS \ -{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ - { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} - -#define CAN_ELIMINATE(FROM, TO) (1) - -#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ -{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - { (OFFSET) = 0; } \ - else if ((FROM) == FRAME_POINTER_REGNUM \ - && (TO) == HARD_FRAME_POINTER_REGNUM) \ - { (OFFSET) = 0; } \ - else if ((FROM) == ARG_POINTER_REGNUM \ - && (TO) == HARD_FRAME_POINTER_REGNUM) \ - { (OFFSET) = s390_arg_frame_offset (); } \ - else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ - { (OFFSET) = s390_arg_frame_offset (); } \ - else \ - abort(); \ -} - -#define CAN_DEBUG_WITHOUT_FP - -/* Value should be nonzero if functions must have frame pointers. - Zero means the frame pointer need not be set up (and parms may be - accessed via the stack pointer) in functions that seem suitable. - This is computed in `reload', in reload1.c. */ +/* Maximum number of registers to represent a value of mode MODE + in a register of class CLASS. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + ((CLASS) == FP_REGS ? \ + (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ + (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -#define FRAME_POINTER_REQUIRED 0 +/* If a 4-byte value is loaded into a FPR, it is placed into the + *upper* half of the register, not the lower. Therefore, we + cannot use SUBREGs to switch between modes in FP registers. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FP_REGS : NO_REGS) -/* Define the classes of registers for register constraints in the - machine description. Also define ranges of constants. - - One of the classes must always be named ALL_REGS and include all hard regs. - If there is more than one class, another class must be named NO_REGS - and contain no registers. +/* Register classes. */ + +/* We use the following register classes: + GENERAL_REGS All general purpose registers + ADDR_REGS All general purpose registers except %r0 + (These registers can be used in address generation) + FP_REGS All floating point registers + + GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS + ADDR_FP_REGS Union of ADDR_REGS and FP_REGS - The name GENERAL_REGS must be the name of a class (or an alias for - another name such as ALL_REGS). This is the class of registers - that is allowed by "g" or "r" in a register constraint. - Also, registers outside this class are allocated only when - instructions express preferences for them. - - The classes must be numbered in nondecreasing order; that is, - a larger-numbered class must never be contained completely - in a smaller-numbered class. - - For any two classes, it is very desirable that there be another - class that represents their union. */ - -/*#define SMALL_REGISTER_CLASSES 1*/ + NO_REGS No registers + ALL_REGS All registers + + Note that the 'fake' frame pointer and argument pointer registers + are included amongst the address registers here. The condition + code register is only included in ALL_REGS. */ enum reg_class { @@ -467,19 +357,13 @@ enum reg_class FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, ALL_REGS, LIM_REG_CLASSES }; - #define N_REG_CLASSES (int) LIM_REG_CLASSES -/* Give names of register classes as strings for dump file. */ - #define REG_CLASS_NAMES \ { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \ "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } -/* Define which registers fit in which classes. This is an initializer for - a vector of HARD_REG_SET of length N_REG_CLASSES. - G5 and latter have 16 register and support IEEE floating point operations. */ - +/* Class -> register mapping. */ #define REG_CLASS_CONTENTS \ { \ { 0x00000000, 0x00000000 }, /* NO_REGS */ \ @@ -491,107 +375,97 @@ enum reg_class { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \ } +/* Register -> class mapping. */ +extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; +#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) -/* The same information, inverted: - Return the class number of the smallest class containing - reg number REGNO. This could be a conditional expression - or could index an array. */ +/* ADDR_REGS can be used as base or index register. */ +#define INDEX_REG_CLASS ADDR_REGS +#define BASE_REG_CLASS ADDR_REGS -#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) +/* Check whether REGNO is a hard register of the suitable class + or a pseudo register currently allocated to one such. */ +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + (((REGNO) < FIRST_PSEUDO_REGISTER \ + && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ + || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) +#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) -extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ -/* The class value for index registers, and the one for base regs. */ +/* Given an rtx X being reloaded into a reg required to be in class CLASS, + return the class of reg to actually use. */ +#define PREFERRED_RELOAD_CLASS(X, CLASS) \ + s390_preferred_reload_class ((X), (CLASS)) + +/* We need a secondary reload when loading a PLUS which is + not a valid operand for LOAD ADDRESS. */ +#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ + s390_secondary_input_reload_class ((CLASS), (MODE), (IN)) + +/* We need secondary memory to move data between GPRs and FPRs. */ +#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ + ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) + +/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit + because the movsi and movsf patterns don't handle r/f moves. */ +#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ + (GET_MODE_BITSIZE (MODE) < 32 \ + ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ + : MODE) -#define INDEX_REG_CLASS ADDR_REGS -#define BASE_REG_CLASS ADDR_REGS -/* Get reg_class from a letter such as appears in the machine description. */ +/* Define various machine-dependent constraint letters. */ #define REG_CLASS_FROM_LETTER(C) \ ((C) == 'a' ? ADDR_REGS : \ (C) == 'd' ? GENERAL_REGS : \ (C) == 'f' ? FP_REGS : NO_REGS) -/* The letters I, J, K, L and M in a register constraint string can be used - to stand for particular ranges of immediate operands. - This macro defines what the ranges are. - C is the letter, and VALUE is a constant value. - Return 1 if VALUE is in the range specified by C. */ - #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \ (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \ (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \ (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0) -/* Similar, but for floating constants, and defining letters G and H. - Here VALUE is the CONST_DOUBLE rtx itself. */ - #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 -/* 'Q' means a memory-reference for a S-type operand. */ - #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? q_constraint (OP) : \ (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0) #define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'Q') -/* Given an rtx X being reloaded into a reg required to be in class CLASS, - return the class of reg to actually use. In general this is just CLASS; - but on some machines in some cases it is preferable to use a more - restrictive class. */ - -#define PREFERRED_RELOAD_CLASS(X, CLASS) \ - s390_preferred_reload_class ((X), (CLASS)) - -/* Return the maximum number of consecutive registers needed to represent - mode MODE in a register of class CLASS. */ - -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((CLASS) == FP_REGS ? \ - (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ - (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) - -/* We need a secondary reload when loading a PLUS which is - not a valid operand for LOAD ADDRESS. */ - -#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ - s390_secondary_input_reload_class ((CLASS), (MODE), (IN)) - -/* If we are copying between FP registers and anything else, we need a memory - location. */ - -#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) -/* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit - because the movsi and movsf patterns don't handle r/f moves. */ +/* Stack layout and calling conventions. */ + +/* Our stack grows from higher to lower addresses. However, local variables + are accessed by positive offsets, and function arguments are stored at + increasing addresses. */ +#define STACK_GROWS_DOWNWARD +/* #undef FRAME_GROWS_DOWNWARD */ +/* #undef ARGS_GROW_DOWNWARD */ -#define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ - (GET_MODE_BITSIZE (MODE) < 32 \ - ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ - : MODE) +/* The basic stack layout looks like this: the stack pointer points + to the register save area for called functions. Above that area + is the location to place outgoing arguments. Above those follow + dynamic allocations (alloca), and finally the local variables. */ +/* Offset from stack-pointer to first location of outgoing args. */ +#define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) -/* A C expression whose value is nonzero if pseudos that have been - assigned to registers of class CLASS would likely be spilled - because registers of CLASS are needed for spill registers. +/* Offset within stack frame to start allocating local variables at. */ +extern int current_function_outgoing_args_size; +#define STARTING_FRAME_OFFSET \ + (STACK_POINTER_OFFSET + current_function_outgoing_args_size) - The default value of this macro returns 1 if CLASS has exactly one - register and zero otherwise. On most machines, this default - should be used. Only define this macro to some other expression - if pseudo allocated by `local-alloc.c' end up in memory because - their hard registers were needed for spill registers. If this - macro returns nonzero for those classes, those pseudos will only - be allocated by `global.c', which knows how to reallocate the - pseudo to another register. If there would not be another - register available for reallocation, you should not change the - definition of this macro since the only effect of such a - definition would be to slow down register allocation. */ +/* Offset from the stack pointer register to an item dynamically + allocated on the stack, e.g., by `alloca'. */ +#define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET) -/* Stack layout; function entry, exit and calling. */ +/* Offset of first parameter from the argument pointer register value. + We have a fake argument pointer register that points directly to + the argument area. */ +#define FIRST_PARM_OFFSET(FNDECL) 0 /* The return address of the current frame is retrieved from the initial value of register RETURN_REGNUM. @@ -603,29 +477,17 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled clas plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) #define RETURN_ADDR_RTX(COUNT, FRAME) \ - ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, RETURN_REGNUM) : \ - gen_rtx_MEM (Pmode, \ - memory_address (Pmode, \ - plus_constant (DYNAMIC_CHAIN_ADDRESS ((FRAME)), \ - RETURN_REGNUM * UNITS_PER_WORD)))) - -/* The following macros will turn on dwarf2 exception hndling - Other code location for this exception handling are - in s390.md (eh_return insn) and in linux.c in the prologue. */ - -#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) - -/* We have 31 bit mode. */ + s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) +/* In 31-bit mode, we need to mask off the high bit of return addresses. */ #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff)) -/* The offset from the incoming value of %sp to the top of the stack frame - for the current function. */ +/* Exception handling. */ + +/* Describe calling conventions for DWARF-2 exception handling. */ +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET - -/* Location, from where return address to load. */ - #define DWARF_FRAME_RETURN_COLUMN 14 /* Describe how we implement __builtin_eh_return. */ @@ -635,76 +497,72 @@ extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled clas gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \ TARGET_64BIT? -48 : -40)) -/* Define this if pushing a word on the stack makes the stack pointer a - smaller address. */ - -#define STACK_GROWS_DOWNWARD - -/* Define this if the nominal address of the stack frame is at the - high-address end of the local variables; that is, each additional local - variable allocated goes at a more negative offset in the frame. */ - -/* #define FRAME_GROWS_DOWNWARD */ - -/* Offset from stack-pointer to first location of outgoing args. */ +/* Select a format to encode pointers in exception handling data. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ + (flag_pic \ + ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ + : DW_EH_PE_absptr) -#define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) -/* Offset within stack frame to start allocating local variables at. - If FRAME_GROWS_DOWNWARD, this is the offset to the END of the - first local allocated. Otherwise, it is the offset to the BEGINNING - of the first local allocated. */ +/* Frame registers. */ -#define STARTING_FRAME_OFFSET \ - (STACK_POINTER_OFFSET + current_function_outgoing_args_size) +#define STACK_POINTER_REGNUM 15 +#define FRAME_POINTER_REGNUM 34 +#define HARD_FRAME_POINTER_REGNUM 11 +#define ARG_POINTER_REGNUM 32 -#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 +/* The static chain must be call-clobbered, but not used for + function argument passing. As register 1 is clobbered by + the trampoline code, we only have one option. */ +#define STATIC_CHAIN_REGNUM 0 -/* If we generate an insn to push BYTES bytes, this says how many the stack - pointer really advances by. On S/390, we have no push instruction. */ +/* Number of hardware registers that go into the DWARF-2 unwind info. + To avoid ABI incompatibility, this number must not change even as + 'fake' hard registers are added or removed. */ +#define DWARF_FRAME_REGISTERS 34 -/* #define PUSH_ROUNDING(BYTES) */ -/* Accumulate the outgoing argument count so we can request the right - DSA size and determine stack offset. */ +/* Frame pointer and argument pointer elimination. */ -#define ACCUMULATE_OUTGOING_ARGS 1 +#define FRAME_POINTER_REQUIRED 0 -/* Offset from the stack pointer register to an item dynamically - allocated on the stack, e.g., by `alloca'. +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 - The default value for this macro is `STACK_POINTER_OFFSET' plus the - length of the outgoing arguments. The default is correct for most - machines. See `function.c' for details. */ -#define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET) +#define ELIMINABLE_REGS \ +{{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} -/* Offset of first parameter from the argument pointer register value. - On the S/390, we define the argument pointer to the start of the fixed - area. */ -#define FIRST_PARM_OFFSET(FNDECL) 0 +#define CAN_ELIMINATE(FROM, TO) (1) -/* Define this if stack space is still allocated for a parameter passed - in a register. The value is the number of bytes allocated to this - area. */ -/* #define REG_PARM_STACK_SPACE(FNDECL) 32 */ +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ +{ if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ + { (OFFSET) = 0; } \ + else if ((FROM) == FRAME_POINTER_REGNUM \ + && (TO) == HARD_FRAME_POINTER_REGNUM) \ + { (OFFSET) = 0; } \ + else if ((FROM) == ARG_POINTER_REGNUM \ + && (TO) == HARD_FRAME_POINTER_REGNUM) \ + { (OFFSET) = s390_arg_frame_offset (); } \ + else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ + { (OFFSET) = s390_arg_frame_offset (); } \ + else \ + abort(); \ +} -/* Define this if the above stack space is to be considered part of the - space allocated by the caller. */ -/* #define OUTGOING_REG_PARM_STACK_SPACE */ -/* 1 if N is a possible register number for function argument passing. - On S390, general registers 2 - 6 and floating point register 0 and 2 - are used in this way. */ +/* Stack arguments. */ + +/* We need current_function_outgoing_args to be valid. */ +#define ACCUMULATE_OUTGOING_ARGS 1 -#define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ - (N) == 16 || (N) == 17) +/* Return doesn't modify the stack. */ +#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 -/* Define a data type for recording info about an argument list during - the scan of that argument list. This data type should hold all - necessary information about the function itself and about the args - processed so far, enough to enable macros such as FUNCTION_ARG to - determine where the next arg should go. */ +/* Register arguments. */ + typedef struct s390_arg_structure { int gprs; /* gpr so far */ @@ -712,84 +570,30 @@ typedef struct s390_arg_structure } CUMULATIVE_ARGS; - -/* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to - a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. */ - #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \ ((CUM).gprs=0, (CUM).fprs=0) -/* Update the data in CUM to advance over an argument of mode MODE and - data type TYPE. (TYPE is null for libcalls where that information - may not be available.) */ - #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) -/* Define where to put the arguments to a function. Value is zero to push - the argument on the stack, or a hard register in which to store the - argument. */ - #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ s390_function_arg (&CUM, MODE, TYPE, NAMED) -/* Define where to expect the arguments of a function. Value is zero, if - the argument is on the stack, or a hard register in which the argument - is stored. It is the same like FUNCTION_ARG, except for unnamed args - That means, that all in case of varargs used, the arguments are expected - from the stack. - S/390 has already space on the stack for args coming in registers, - they are pushed in prologue, if needed. */ - - -/* Define the `__builtin_va_list' type. */ - -#define BUILD_VA_LIST_TYPE(VALIST) \ - (VALIST) = s390_build_va_list () - -/* Implement `va_start' for varargs and stdarg. */ - -#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ - s390_va_start (valist, nextarg) - -/* Implement `va_arg'. */ - -#define EXPAND_BUILTIN_VA_ARG(valist, type) \ - s390_va_arg (valist, type) - -/* For an arg passed partly in registers and partly in memory, this is the - number of registers used. For args passed entirely in registers or - entirely in memory, zero. */ - -#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 - - -/* Define if returning from a function call automatically pops the - arguments described by the number-of-args field in the call. */ - -#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 - - -/* Define how to find the value returned by a function. VALTYPE is the - data type of the value (as a tree). - If the precise function being called is known, FUNC is its FUNCTION_DECL; - otherwise, FUNC is 15. */ - -#define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \ - || TARGET_SOFT_FLOAT ) ? 2 : 16) - - -/* for structs the address is passed, and the Callee makes a - copy, only if needed */ - #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ s390_function_arg_pass_by_reference (MODE, TYPE) +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 + +/* Arguments can be placed in general registers 2 to 6, + or in floating point registers 0 and 2. */ +#define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ + (N) == 16 || (N) == 17) -/* Register 2 (and 3) for integral values - or floating point register 0 (and 2) for fp values are used. */ +/* Scalar return values. */ + +/* We return scalars in general purpose register 2 for integral values, + and floating point register 0 for fp values. */ #define FUNCTION_VALUE(VALTYPE, FUNC) \ gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ @@ -799,133 +603,77 @@ CUMULATIVE_ARGS; /* Define how to find the value returned by a library function assuming the value has mode MODE. */ - +#define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \ + || TARGET_SOFT_FLOAT ) ? 2 : 16) #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE)) -/* 1 if N is a possible register number for a function value. */ - +/* Only gpr 2 and fpr 0 are ever used as return registers. */ #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) + +/* Aggregate return values. */ + /* The definition of this macro implies that there are cases where a scalar value cannot be returned in registers. */ - #define RETURN_IN_MEMORY(type) \ (TYPE_MODE (type) == BLKmode || \ GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \ GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT) -/* Mode of stack savearea. - FUNCTION is VOIDmode because calling convention maintains SP. - BLOCK needs Pmode for SP. - NONLOCAL needs twice Pmode to maintain both backchain and SP. */ - -#define STACK_SAVEAREA_MODE(LEVEL) \ - (LEVEL == SAVE_FUNCTION ? VOIDmode \ - : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) - /* Structure value address is passed as invisible first argument (gpr 2). */ - #define STRUCT_VALUE 0 -/* This macro definition sets up a default value for `main' to return. */ - -#define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) - -/* Length in units of the trampoline for entering a nested function. */ - -#define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20) - -/* Initialize the dynamic part of trampoline. */ -#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ - s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) - -/* Template for constant part of trampoline. */ +/* Function entry and exit. */ + +/* When returning from a function, the stack pointer does not matter. */ +#define EXIT_IGNORE_STACK 1 -#define TRAMPOLINE_TEMPLATE(FILE) \ - s390_trampoline_template (FILE) -/* Output assembler code to FILE to increment profiler label # LABELNO - for profiling a function entry. */ +/* Profiling. */ #define FUNCTION_PROFILER(FILE, LABELNO) \ - s390_function_profiler ((FILE), ((LABELNO))) + s390_function_profiler ((FILE), ((LABELNO))) #define PROFILE_BEFORE_PROLOGUE 1 -/* Define EXIT_IGNORE_STACK if, when returning from a function, the stack - pointer does not matter (provided there is a frame pointer). */ - -#define EXIT_IGNORE_STACK 1 - -/* Addressing modes, and classification of registers for them. */ - -/* #define HAVE_POST_INCREMENT */ -/* #define HAVE_POST_DECREMENT */ -/* #define HAVE_PRE_DECREMENT */ -/* #define HAVE_PRE_INCREMENT */ +/* Implementing the varargs macros. */ -/* These assume that REGNO is a hard or pseudo reg number. They give - nonzero only if REGNO is a hard reg of the suitable class or a pseudo - reg currently allocated to a suitable hard reg. - These definitions are NOT overridden anywhere. */ - -#define REGNO_OK_FOR_INDEX_P(REGNO) \ - (((REGNO) < FIRST_PSEUDO_REGISTER \ - && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ - || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) - -#define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) +#define BUILD_VA_LIST_TYPE(VALIST) \ + (VALIST) = s390_build_va_list () -#define REGNO_OK_FOR_DATA_P(REGNO) \ - ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) +#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ + s390_va_start (valist, nextarg) -#define REGNO_OK_FOR_FP_P(REGNO) \ - FLOAT_REGNO_P (REGNO) +#define EXPAND_BUILTIN_VA_ARG(valist, type) \ + s390_va_arg (valist, type) -/* Now macros that check whether X is a register and also, - strictly, whether it is in a specified class. */ -/* 1 if X is a data register. */ +/* Trampolines for nested functions. */ -#define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) +#define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20) -/* 1 if X is an fp register. */ +#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ + s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) -#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) +#define TRAMPOLINE_TEMPLATE(FILE) \ + s390_trampoline_template (FILE) -/* 1 if X is an address register. */ -#define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) +/* Library calls. */ + +/* We should use memcpy, not bcopy. */ +#define TARGET_MEM_FUNCTIONS -/* Maximum number of registers that can appear in a valid memory address. */ -#define MAX_REGS_PER_ADDRESS 2 +/* Addressing modes, and classification of registers for them. */ /* Recognize any constant value that is a valid address. */ - #define CONSTANT_ADDRESS_P(X) 0 -#define SYMBOLIC_CONST(X) \ -(GET_CODE (X) == SYMBOL_REF \ - || GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) - -/* General operand is everything except SYMBOL_REF, CONST and CONST_DOUBLE - they have to be forced to constant pool - CONST_INT have to be forced into constant pool, if greater than - 64k. Depending on the insn they have to be force into constant pool - for smaller value; in this case we have to work with nonimmediate operand. */ - -#define LEGITIMATE_PIC_OPERAND_P(X) \ - legitimate_pic_operand_p (X) - -/* Nonzero if the constant value X is a legitimate general operand. - It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ - -#define LEGITIMATE_CONSTANT_P(X) \ - legitimate_constant_p (X) +/* Maximum number of registers that can appear in a valid memory address. */ +#define MAX_REGS_PER_ADDRESS 2 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. We have two alternate definitions @@ -938,32 +686,19 @@ CUMULATIVE_ARGS; Some source files that are used after register allocation need to be strict. */ -/* - * Nonzero if X is a hard reg that can be used as an index or if it is - * a pseudo reg. - */ - #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ ((GET_MODE (X) == Pmode) && \ ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \ || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS)) -/* Nonzero if X is a hard reg that can be used as a base reg or if it is - a pseudo reg. */ - #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) -/* Nonzero if X is a hard reg that can be used as an index. */ - #define REG_OK_FOR_INDEX_STRICT_P(X) \ ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X)))) -/* Nonzero if X is a hard reg that can be used as a base reg. */ - #define REG_OK_FOR_BASE_STRICT_P(X) \ ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X)))) - #ifndef REG_OK_STRICT #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) @@ -972,15 +707,13 @@ CUMULATIVE_ARGS; #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) #endif +/* S/390 has no mode dependent addresses. */ +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, - except for CONSTANT_ADDRESS_P which is actually machine-independent. */ - + that wants to use this address. */ #ifdef REG_OK_STRICT #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ { \ @@ -995,15 +728,9 @@ CUMULATIVE_ARGS; } #endif - -/* S/390 has no mode dependent addresses. */ - -#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) - /* Try machine-dependent ways of modifying an illegitimate address to be legitimate. If we find one, return the new, valid address. This macro is used in only one place: `memory_address' in explow.c. */ - #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ { \ (X) = legitimize_address (X, OLDX, MODE); \ @@ -1011,73 +738,31 @@ CUMULATIVE_ARGS; goto WIN; \ } -/* Specify the machine mode that this machine uses for the index in the - tablejump instruction. */ - -#define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) - -/* Define this if the tablejump instruction expects the table to contain - offsets from the address of the table. - Do not define this if the table should contain absolute addresses. */ - -/* #define CASE_VECTOR_PC_RELATIVE */ - -/* Load from integral MODE < SI from memory into register makes sign_extend - or zero_extend - In our case sign_extension happens for Halfwords, other no extension. */ - -#define LOAD_EXTEND_OP(MODE) \ -(TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ - (MODE) == HImode ? SIGN_EXTEND : NIL) \ - : ((MODE) == HImode ? SIGN_EXTEND : NIL)) - -/* Define this if fixuns_trunc is the same as fix_trunc. */ - -/* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ - -/* We use "unsigned char" as default. */ - -#define DEFAULT_SIGNED_CHAR 0 - -/* Max number of bytes we can move from memory to memory in one reasonably - fast instruction. */ - -#define MOVE_MAX 256 - -/* Nonzero if access to memory by bytes is slow and undesirable. */ - -#define SLOW_BYTE_ACCESS 1 - -/* Define if shifts truncate the shift count which implies one can omit - a sign-extension or zero-extension of a shift count. */ - -/* #define SHIFT_COUNT_TRUNCATED */ - -/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits - is done just by pretending it is already truncated. */ - -#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 - -/* We assume that the store-condition-codes instructions store 0 for false - and some other value for true. This is the value stored for true. */ - -/* #define STORE_FLAG_VALUE -1 */ - -/* Don't perform CSE on function addresses. */ +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ +#define LEGITIMATE_CONSTANT_P(X) \ + legitimate_constant_p (X) -#define NO_FUNCTION_CSE +/* Helper macro for s390.c and s390.md to check for symbolic constants. */ +#define SYMBOLIC_CONST(X) \ +(GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == LABEL_REF \ + || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) -/* Specify the machine mode that pointers have. - After generation of rtl, the compiler makes no further distinction - between pointers and any other objects of this machine mode. */ -#define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) +/* Condition codes. */ -/* A function address in a call instruction is a byte address (for - indexing purposes) so give the MEM rtx a byte's mode. */ +/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. */ +#define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) + +/* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ +extern struct rtx_def *s390_compare_op0, *s390_compare_op1; -#define FUNCTION_MODE QImode +/* Relative costs of operations. */ /* A part of a C `switch' statement that describes the relative costs of constant RTL expressions. It must contain `case' labels for @@ -1098,7 +783,6 @@ CUMULATIVE_ARGS; than a short. Because of that we give an addition of greater constants a cost of 3 (reload1.c 10096). */ - #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ case CONST: \ if ((GET_CODE (XEXP (RTX, 0)) == MINUS) && \ @@ -1120,10 +804,7 @@ CUMULATIVE_ARGS; instruction is. In writing this macro, you can use the construct `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions. OUTER_CODE is the code of the expression in which X - is contained. - - This macro is optional; do not define it if the default cost - assumptions are adequate for the target machine. */ + is contained. */ #define RTX_COSTS(X, CODE, OUTER_CODE) \ case ASHIFT: \ @@ -1136,146 +817,72 @@ CUMULATIVE_ARGS; case MINUS: \ case NEG: \ case NOT: \ - return 1; \ + return COSTS_N_INSNS (1); \ case MULT: \ if (GET_MODE (XEXP (X, 0)) == DImode) \ - return 40; \ - else \ - return 7; \ + return COSTS_N_INSNS (40); \ + else \ + return COSTS_N_INSNS (7); \ case DIV: \ case UDIV: \ case MOD: \ case UMOD: \ - return 33; + return COSTS_N_INSNS (33); /* An expression giving the cost of an addressing mode that contains ADDRESS. If not defined, the cost is computed from the ADDRESS - expression and the `CONST_COSTS' values. - - For most CISC machines, the default cost is a good approximation - of the true cost of the addressing mode. However, on RISC - machines, all instructions normally have the same length and - execution time. Hence all addresses will have equal costs. - - In cases where more than one form of an address is known, the form - with the lowest cost will be used. If multiple forms have the - same, lowest, cost, the one that is the most complex will be used. - - For example, suppose an address that is equal to the sum of a - register and a constant is used twice in the same basic block. - When this macro is not defined, the address will be computed in a - register and memory references will be indirect through that - register. On machines where the cost of the addressing mode - containing the sum is no higher than that of a simple indirect - reference, this will produce an additional instruction and - possibly require an additional register. Proper specification of - this macro eliminates this overhead for such machines. - - Similar use of this macro is made in strength reduction of loops. - - ADDRESS need not be valid as an address. In such a case, the cost - is not relevant and can be any value; invalid addresses need not be - assigned a different cost. - - On machines where an address involving more than one register is as - cheap as an address computation involving only one register, - defining `ADDRESS_COST' to reflect this can cause two registers to - be live over a region of code where only one would have been if - `ADDRESS_COST' were not defined in that manner. This effect should - be considered in the definition of this macro. Equivalent costs - should probably only be given to addresses with different numbers - of registers on machines with lots of registers. - - This macro will normally either not be defined or be defined as a - constant. - - On s390 symbols are expensive if compiled with fpic - lifetimes. */ - -#define ADDRESS_COST(RTX) \ - ((flag_pic && GET_CODE (RTX) == SYMBOL_REF) ? 2 : 1) + expression and the `CONST_COSTS' values. */ +#define ADDRESS_COST(RTX) s390_address_cost ((RTX)) /* On s390, copy between fprs and gprs is expensive. */ - #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) - /* A C expression for the cost of moving data of mode M between a register and memory. A value of 2 is the default; this cost is - relative to those in `REGISTER_MOVE_COST'. - - If moving between registers and memory is more expensive than - between two registers, you should define this macro to express the - relative cost. */ - + relative to those in `REGISTER_MOVE_COST'. */ #define MEMORY_MOVE_COST(M, C, I) 1 /* A C expression for the cost of a branch instruction. A value of 1 is the default; other values are interpreted relative to that. */ - #define BRANCH_COST 1 -/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, - return the mode to be used for the comparison. */ - -#define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) - - -/* Define the information needed to generate branch and scc insns. This is - stored from the compare operation. Note that we can't use "rtx" here - since it hasn't been defined! */ - -extern struct rtx_def *s390_compare_op0, *s390_compare_op1; - - -/* How to refer to registers in assembler output. This sequence is - indexed by compiler's hard-register-number (see above). */ - -#define REGISTER_NAMES \ -{ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ - "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ - "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ - "%ap", "%cc", "%fp" \ -} +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 1 -/* implicit call of memcpy, not bcopy */ +/* The maximum number of bytes that a single instruction can move quickly + between memory and registers or between two memory locations. */ +#define MOVE_MAX (TARGET_64BIT ? 16 : 8) +#define MAX_MOVE_MAX 16 -#define TARGET_MEM_FUNCTIONS +/* Determine whether to use move_by_pieces or block move insn. */ +#define MOVE_BY_PIECES_P(SIZE, ALIGN) \ + ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ + || (TARGET_64BIT && (SIZE) == 8) ) -/* Either simplify a location expression, or return the original. */ +/* Determine whether to use clear_by_pieces or block clear insn. */ +#define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ + ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ + || (TARGET_64BIT && (SIZE) == 8) ) -#define ASM_SIMPLIFY_DWARF_ADDR(X) \ - s390_simplify_dwarf_addr (X) - -/* Print operand X (an rtx) in assembler syntax to file FILE. - CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. - For `%' followed by punctuation, CODE is the punctuation and X is null. */ - -#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) +/* Don't perform CSE on function addresses. */ +#define NO_FUNCTION_CSE -#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) +/* Sections. */ -/* Define the codes that are matched by predicates in aux-output.c. */ +/* Output before read-only data. */ +#define TEXT_SECTION_ASM_OP ".text" -#define PREDICATE_CODES \ - {"s_operand", { SUBREG, MEM }}, \ - {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \ - {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \ - {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \ - {"load_multiple_operation", {PARALLEL}}, \ - {"store_multiple_operation", {PARALLEL}}, \ - {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \ - {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \ - CONST_INT, CONST_DOUBLE }}, \ - {"s390_plus_operand", { PLUS }}, +/* Output before writable (initialized) data. */ +#define DATA_SECTION_ASM_OP ".data" +/* Output before writable (uninitialized) data. */ +#define BSS_SECTION_ASM_OP ".bss" /* S/390 constant pool breaks the devices in crtstuff.c to control section in where code resides. We have to write it as asm code. */ @@ -1289,12 +896,86 @@ extern struct rtx_def *s390_compare_op0, *s390_compare_op1; .previous"); #endif + +/* Position independent code. */ + +extern int flag_pic; + +#define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) + +#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) + + +/* Assembler file format. */ + +/* Character to start a comment. */ +#define ASM_COMMENT_START "#" + +/* Declare an uninitialized external linkage data object. */ +#define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ + asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) + +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP ".globl " + +/* Advance the location counter to a multiple of 2**LOG bytes. */ +#define ASM_OUTPUT_ALIGN(FILE, LOG) \ + if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) + +/* Advance the location counter by SIZE bytes. */ +#define ASM_OUTPUT_SKIP(FILE, SIZE) \ + fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE)) + +/* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ +#define LOCAL_LABEL_PREFIX "." + +/* Either simplify a location expression, or return the original. */ +#define ASM_SIMPLIFY_DWARF_ADDR(X) \ + s390_simplify_dwarf_addr (X) + +/* How to refer to registers in assembler output. This sequence is + indexed by compiler's hard-register-number (see above). */ +#define REGISTER_NAMES \ +{ "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ + "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ + "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ + "%ap", "%cc", "%fp" \ +} + +/* Print operand X (an rtx) in assembler syntax to file FILE. */ +#define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) + +/* Output an element of a case-vector that is absolute. */ +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ +do { \ + char buf[32]; \ + fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ + ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ + assemble_name ((FILE), buf); \ + fputc ('\n', (FILE)); \ +} while (0) + +/* Output an element of a case-vector that is relative. */ +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ +do { \ + char buf[32]; \ + fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ + ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ + assemble_name ((FILE), buf); \ + fputc ('-', (FILE)); \ + ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ + assemble_name ((FILE), buf); \ + fputc ('\n', (FILE)); \ +} while (0) + + /* Constant Pool for all symbols operands which are changed with force_const_mem during insn generation (expand_insn). */ extern int s390_pool_count; extern int s390_nr_constants; -extern int s390_pool_overflow; #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \ { \ @@ -1349,4 +1030,54 @@ extern int s390_pool_overflow; goto WIN; \ } + +/* Miscellaneous parameters. */ + +/* Define the codes that are matched by predicates in aux-output.c. */ +#define PREDICATE_CODES \ + {"s_operand", { SUBREG, MEM }}, \ + {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \ + {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \ + {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \ + {"load_multiple_operation", {PARALLEL}}, \ + {"store_multiple_operation", {PARALLEL}}, \ + {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \ + {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \ + CONST_INT, CONST_DOUBLE }}, \ + {"s390_plus_operand", { PLUS }}, + +/* Specify the machine mode that this machine uses for the index in the + tablejump instruction. */ +#define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) + +/* Load from integral MODE < SI from memory into register makes sign_extend + or zero_extend + In our case sign_extension happens for Halfwords, other no extension. */ +#define LOAD_EXTEND_OP(MODE) \ +(TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ + (MODE) == HImode ? SIGN_EXTEND : NIL) \ + : ((MODE) == HImode ? SIGN_EXTEND : NIL)) + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) + +/* A function address in a call instruction is a byte address (for + indexing purposes) so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* This macro definition sets up a default value for `main' to return. */ +#define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) + +/* In rare cases, correct code generation requires extra machine dependent + processing between the second jump optimization pass and delayed branch + scheduling. On those machines, define this macro as a C statement to act on + the code starting at INSN. */ +#define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN) + #endif |