diff options
Diffstat (limited to 'gcc/config/s390/s390.md')
| -rw-r--r-- | gcc/config/s390/s390.md | 2957 |
1 files changed, 1538 insertions, 1419 deletions
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 703f0d7a484..b2eff87c640 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -50,7 +50,24 @@ ;; (define_constants - [; TLS relocation specifiers + [; Miscellaneous + (UNSPEC_ROUND 1) + (UNSPEC_SETHIGH 10) + + ; GOT/PLT and lt-relative accesses + (UNSPEC_LTREL_OFFSET 100) + (UNSPEC_LTREL_BASE 101) + (UNSPEC_GOTENT 110) + (UNSPEC_GOT 111) + (UNSPEC_GOTOFF 112) + (UNSPEC_PLT 113) + (UNSPEC_PLTOFF 114) + + ; Literal pool + (UNSPEC_RELOAD_BASE 210) + (UNSPEC_MAIN_BASE 211) + + ; TLS relocation specifiers (UNSPEC_TLSGD 500) (UNSPEC_TLSLDM 501) (UNSPEC_NTPOFF 502) @@ -69,7 +86,17 @@ ;; (define_constants - [; TLS support + [; Blockage + (UNSPECV_BLOCKAGE 0) + + ; Literal pool + (UNSPECV_POOL 200) + (UNSPECV_POOL_START 201) + (UNSPECV_POOL_END 202) + (UNSPECV_POOL_ENTRY 203) + (UNSPECV_MAIN_POOL 300) + + ; TLS support (UNSPECV_SET_TP 500) ]) @@ -90,7 +117,7 @@ fmuld,fmuls,fdivd,fdivs, ftoi,itof,fsqrtd,fsqrts, other,o2,o3" - (const_string "integer")) + (const_string "integer")) ;; Operand type. Used to default length attribute values @@ -122,7 +149,7 @@ (eq_attr "op_type" "SIY") (const_string "agen")] (const_string "reg"))) -;; Generic pipeline function unit. +;; Generic pipeline function unit. (define_function_unit "integer" 1 0 (eq_attr "type" "none") 0 0) @@ -261,11 +288,11 @@ ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) - + ; CCZ -> CCL / CCZ1 ; CCZ1 -> CCA/CCU/CCS/CCT ; CCS -> CCA - + ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT @@ -279,48 +306,44 @@ (compare:CC (match_operand:DI 0 "register_operand" "") (match_operand:DI 1 "general_operand" "")))] "TARGET_64BIT" - " { s390_compare_op0 = operands[0]; s390_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpsi" [(set (reg:CC 33) (compare:CC (match_operand:SI 0 "register_operand" "") (match_operand:SI 1 "general_operand" "")))] "" - " { s390_compare_op0 = operands[0]; s390_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpdf" [(set (reg:CC 33) (compare:CC (match_operand:DF 0 "register_operand" "") (match_operand:DF 1 "general_operand" "")))] "TARGET_HARD_FLOAT" - " { s390_compare_op0 = operands[0]; s390_compare_op1 = operands[1]; DONE; -}") +}) (define_expand "cmpsf" [(set (reg:CC 33) (compare:CC (match_operand:SF 0 "register_operand" "") (match_operand:SF 1 "general_operand" "")))] "TARGET_HARD_FLOAT" - " { s390_compare_op0 = operands[0]; s390_compare_op1 = operands[1]; DONE; -}") +}) ; Test-under-Mask (zero_extract) instructions @@ -332,11 +355,10 @@ (match_operand:DI 2 "const_int_operand" "n")) (const_int 0)))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT - && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 + && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 == INTVAL (operands[2]) >> 4" - "* { int part = INTVAL (operands[2]) >> 4; int block = (1 << INTVAL (operands[1])) - 1; @@ -346,13 +368,13 @@ switch (part) { - case 0: return \"tmhh\\t%0,%x2\"; - case 1: return \"tmhl\\t%0,%x2\"; - case 2: return \"tmlh\\t%0,%x2\"; - case 3: return \"tmll\\t%0,%x2\"; + case 0: return "tmhh\t%0,%x2"; + case 1: return "tmhl\t%0,%x2"; + case 2: return "tmlh\t%0,%x2"; + case 3: return "tmll\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*tmsi_ext" @@ -362,11 +384,10 @@ (match_operand:SI 2 "const_int_operand" "n")) (const_int 0)))] "s390_match_ccmode(insn, CCTmode) - && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 + && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 == INTVAL (operands[2]) >> 4" - "* { int part = INTVAL (operands[2]) >> 4; int block = (1 << INTVAL (operands[1])) - 1; @@ -376,11 +397,11 @@ switch (part) { - case 0: return \"tmh\\t%0,%x2\"; - case 1: return \"tml\\t%0,%x2\"; + case 0: return "tmh\t%0,%x2"; + case 1: return "tml\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*tmqi_ext" @@ -390,16 +411,15 @@ (match_operand:SI 2 "const_int_operand" "n,n")) (const_int 0)))] "s390_match_ccmode(insn, CCTmode) - && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 + && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" - "* { int block = (1 << INTVAL (operands[1])) - 1; int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); operands[2] = GEN_INT (block << shift); - return which_alternative == 0 ? \"tm\\t%0,%b2\" : \"tmy\\t%0,%b2\"; -}" + return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; +} [(set_attr "op_type" "SI,SIY")]) ; Test-under-Mask instructions @@ -409,18 +429,16 @@ (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") (match_operand:DI 1 "immediate_operand" "n,n")) (match_operand:DI 2 "immediate_operand" "n,n")))] - "TARGET_64BIT - && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) + "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) && s390_single_qi (operands[1], DImode, 0) >= 0" - "* { int part = s390_single_qi (operands[1], DImode, 0); operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); - operands[0] = gen_rtx_MEM (QImode, + operands[0] = gen_rtx_MEM (QImode, plus_constant (XEXP (operands[0], 0), part)); - return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; -}" + return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; +} [(set_attr "op_type" "SI,SIY")]) (define_insn "*tmsi_mem" @@ -430,15 +448,14 @@ (match_operand:SI 2 "immediate_operand" "n,n")))] "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) && s390_single_qi (operands[1], SImode, 0) >= 0" - "* { int part = s390_single_qi (operands[1], SImode, 0); operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); - operands[0] = gen_rtx_MEM (QImode, + operands[0] = gen_rtx_MEM (QImode, plus_constant (XEXP (operands[0], 0), part)); - return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; -}" + return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; +} [(set_attr "op_type" "SI")]) (define_insn "*tmhi_mem" @@ -448,15 +465,14 @@ (match_operand:SI 2 "immediate_operand" "n,n")))] "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) && s390_single_qi (operands[1], HImode, 0) >= 0" - "* { int part = s390_single_qi (operands[1], HImode, 0); operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); - operands[0] = gen_rtx_MEM (QImode, + operands[0] = gen_rtx_MEM (QImode, plus_constant (XEXP (operands[0], 0), part)); - return which_alternative == 0 ? \"tm\\t%0,%b1\" : \"tmy\\t%0,%b1\"; -}" + return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; +} [(set_attr "op_type" "SI")]) (define_insn "*tmqi_mem" @@ -466,8 +482,8 @@ (match_operand:SI 2 "immediate_operand" "n,n")))] "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" "@ - tm\\t%0,%b1 - tmy\\t%0,%b1" + tm\t%0,%b1 + tmy\t%0,%b1" [(set_attr "op_type" "SI,SIY")]) (define_insn "*tmdi_reg" @@ -478,20 +494,19 @@ "TARGET_64BIT && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) && s390_single_hi (operands[1], DImode, 0) >= 0" - "* { int part = s390_single_hi (operands[1], DImode, 0); operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); switch (part) { - case 0: return \"tmhh\\t%0,%x1\"; - case 1: return \"tmhl\\t%0,%x1\"; - case 2: return \"tmlh\\t%0,%x1\"; - case 3: return \"tmll\\t%0,%x1\"; + case 0: return "tmhh\t%0,%x1"; + case 1: return "tmhl\t%0,%x1"; + case 2: return "tmlh\t%0,%x1"; + case 3: return "tmll\t%0,%x1"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*tmsi_reg" @@ -501,18 +516,17 @@ (match_operand:SI 2 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) && s390_single_hi (operands[1], SImode, 0) >= 0" - "* { int part = s390_single_hi (operands[1], SImode, 0); operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); switch (part) { - case 0: return \"tmh\\t%0,%x1\"; - case 1: return \"tml\\t%0,%x1\"; + case 0: return "tmh\t%0,%x1"; + case 1: return "tml\t%0,%x1"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*tmhi_full" @@ -520,7 +534,7 @@ (compare (match_operand:HI 0 "register_operand" "d") (match_operand:HI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" - "tml\\t%0,65535" + "tml\t%0,65535" [(set_attr "op_type" "RX")]) (define_insn "*tmqi_full" @@ -528,7 +542,7 @@ (compare (match_operand:QI 0 "register_operand" "d") (match_operand:QI 1 "immediate_operand" "n")))] "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" - "tml\\t%0,255" + "tml\t%0,255" [(set_attr "op_type" "RI")]) @@ -542,7 +556,7 @@ (set (match_operand:DI 2 "register_operand" "=d") (sign_extend:DI (match_dup 0)))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "ltgfr\\t%2,%0" + "ltgfr\t%2,%0" [(set_attr "op_type" "RRE")]) (define_insn "*tstdi" @@ -552,7 +566,7 @@ (set (match_operand:DI 2 "register_operand" "=d") (match_dup 0))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "ltgr\\t%2,%0" + "ltgr\t%2,%0" [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly" @@ -560,7 +574,7 @@ (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" - "ltgr\\t%0,%0" + "ltgr\t%0,%0" [(set_attr "op_type" "RRE")]) (define_insn "*tstdi_cconly_31" @@ -568,7 +582,7 @@ (compare (match_operand:DI 0 "register_operand" "d") (match_operand:DI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" - "srda\\t%0,0" + "srda\t%0,0" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -581,9 +595,9 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "@ - ltr\\t%2,%0 - icm\\t%2,15,%0 - icmy\\t%2,15,%0" + ltr\t%2,%0 + icm\t%2,15,%0 + icmy\t%2,15,%0" [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly" @@ -593,9 +607,9 @@ (clobber (match_scratch:SI 2 "=X,d,d"))] "s390_match_ccmode(insn, CCSmode)" "@ - ltr\\t%0,%0 - icm\\t%2,15,%0 - icmy\\t%2,15,%0" + ltr\t%0,%0 + icm\t%2,15,%0 + icmy\t%2,15,%0" [(set_attr "op_type" "RR,RS,RSY")]) (define_insn "*tstsi_cconly2" @@ -603,7 +617,7 @@ (compare (match_operand:SI 0 "register_operand" "d") (match_operand:SI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" - "ltr\\t%0,%0" + "ltr\t%0,%0" [(set_attr "op_type" "RR")]) (define_insn "*tsthiCCT" @@ -614,9 +628,9 @@ (match_dup 0))] "s390_match_ccmode(insn, CCTmode)" "@ - icm\\t%2,3,%0 - icmy\\t%2,3,%0 - tml\\t%0,65535" + icm\t%2,3,%0 + icmy\t%2,3,%0 + tml\t%0,65535" [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tsthiCCT_cconly" @@ -626,9 +640,9 @@ (clobber (match_scratch:HI 2 "=d,d,X"))] "s390_match_ccmode(insn, CCTmode)" "@ - icm\\t%2,3,%0 - icmy\\t%2,3,%0 - tml\\t%0,65535" + icm\t%2,3,%0 + icmy\t%2,3,%0 + tml\t%0,65535" [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tsthi" @@ -639,8 +653,8 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\\t%2,3,%0 - icmy\\t%2,3,%0" + icm\t%2,3,%0 + icmy\t%2,3,%0" [(set_attr "op_type" "RS,RSY")]) (define_insn "*tsthi_cconly" @@ -650,8 +664,8 @@ (clobber (match_scratch:HI 2 "=d,d"))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\\t%2,3,%0 - icmy\\t%2,3,%0" + icm\t%2,3,%0 + icmy\t%2,3,%0" [(set_attr "op_type" "RS,RSY")]) (define_insn "*tstqiCCT" @@ -662,9 +676,9 @@ (match_dup 0))] "s390_match_ccmode(insn, CCTmode)" "@ - icm\\t%2,1,%0 - icmy\\t%2,1,%0 - tml\\t%0,255" + icm\t%2,1,%0 + icmy\t%2,1,%0 + tml\t%0,255" [(set_attr "op_type" "RS,RSY,RI")]) (define_insn "*tstqiCCT_cconly" @@ -673,9 +687,9 @@ (match_operand:QI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCTmode)" "@ - cli\\t%0,0 - cliy\\t%0,0 - tml\\t%0,255" + cli\t%0,0 + cliy\t%0,0 + tml\t%0,255" [(set_attr "op_type" "SI,SIY,RI")]) (define_insn "*tstqi" @@ -686,8 +700,8 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\\t%2,1,%0 - icmy\\t%2,1,%0" + icm\t%2,1,%0 + icmy\t%2,1,%0" [(set_attr "op_type" "RS,RSY")]) (define_insn "*tstqi_cconly" @@ -697,8 +711,8 @@ (clobber (match_scratch:QI 2 "=d,d"))] "s390_match_ccmode(insn, CCSmode)" "@ - icm\\t%2,1,%0 - icmy\\t%2,1,%0" + icm\t%2,1,%0 + icmy\t%2,1,%0" [(set_attr "op_type" "RS,RSY")]) @@ -710,8 +724,8 @@ (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" "@ - cgfr\\t%0,%1 - cgf\\t%0,%1" + cgfr\t%0,%1 + cgf\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccs" @@ -720,19 +734,19 @@ (match_operand:DI 1 "general_operand" "d,K,m")))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "@ - cgr\\t%0,%1 - cghi\\t%0,%c1 - cg\\t%0,%1" + cgr\t%0,%1 + cghi\t%0,%c1 + cg\t%0,%1" [(set_attr "op_type" "RRE,RI,RXY")]) - + (define_insn "*cmpsi_ccs_sign" [(set (reg 33) (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) (match_operand:SI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCSRmode)" "@ - ch\\t%0,%1 - chy\\t%0,%1" + ch\t%0,%1 + chy\t%0,%1" [(set_attr "op_type" "RX,RXY")]) (define_insn "*cmpsi_ccs" @@ -741,12 +755,12 @@ (match_operand:SI 1 "general_operand" "d,K,R,T")))] "s390_match_ccmode(insn, CCSmode)" "@ - cr\\t%0,%1 - chi\\t%0,%c1 - c\\t%0,%1 - cy\\t%0,%1" + cr\t%0,%1 + chi\t%0,%c1 + c\t%0,%1 + cy\t%0,%1" [(set_attr "op_type" "RR,RI,RX,RXY")]) - + ; Compare (unsigned) instructions @@ -756,8 +770,8 @@ (match_operand:DI 0 "register_operand" "d,d")))] "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" "@ - clgfr\\t%0,%1 - clgf\\t%0,%1" + clgfr\t%0,%1 + clgf\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpdi_ccu" @@ -766,8 +780,8 @@ (match_operand:DI 1 "general_operand" "d,m")))] "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" "@ - clgr\\t%0,%1 - clg\\t%0,%1" + clgr\t%0,%1 + clg\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*cmpsi_ccu" @@ -776,9 +790,9 @@ (match_operand:SI 1 "general_operand" "d,R,T")))] "s390_match_ccmode(insn, CCUmode)" "@ - clr\\t%0,%1 - cl\\t%0,%1 - cly\\t%0,%1" + clr\t%0,%1 + cl\t%0,%1 + cly\t%0,%1" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*cmphi_ccu" @@ -787,8 +801,8 @@ (match_operand:HI 1 "s_imm_operand" "Q,S")))] "s390_match_ccmode(insn, CCUmode)" "@ - clm\\t%0,3,%1 - clmy\\t%0,3,%1" + clm\t%0,3,%1 + clmy\t%0,3,%1" [(set_attr "op_type" "RS,RSY")]) (define_insn "*cmpqi_ccu" @@ -797,8 +811,8 @@ (match_operand:QI 1 "s_imm_operand" "Q,S")))] "s390_match_ccmode(insn, CCUmode)" "@ - clm\\t%0,1,%1 - clmy\\t%0,1,%1" + clm\t%0,1,%1 + clmy\t%0,1,%1" [(set_attr "op_type" "RS,RSY")]) (define_insn "*cli" @@ -807,8 +821,8 @@ (match_operand:QI 1 "immediate_operand" "n,n")))] "s390_match_ccmode (insn, CCUmode)" "@ - cli\\t%0,%b1 - cliy\\t%0,%b1" + cli\t%0,%b1 + cliy\t%0,%b1" [(set_attr "op_type" "SI,SIY")]) (define_insn "*cmpdi_ccu_mem" @@ -816,7 +830,7 @@ (compare (match_operand:DI 0 "s_operand" "Q") (match_operand:DI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" - "clc\\t%O0(8,%R0),%1" + "clc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*cmpsi_ccu_mem" @@ -824,7 +838,7 @@ (compare (match_operand:SI 0 "s_operand" "Q") (match_operand:SI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" - "clc\\t%O0(4,%R0),%1" + "clc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*cmphi_ccu_mem" @@ -832,7 +846,7 @@ (compare (match_operand:HI 0 "s_operand" "Q") (match_operand:HI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" - "clc\\t%O0(2,%R0),%1" + "clc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*cmpqi_ccu_mem" @@ -840,7 +854,7 @@ (compare (match_operand:QI 0 "s_operand" "Q") (match_operand:QI 1 "s_imm_operand" "Q")))] "s390_match_ccmode(insn, CCUmode)" - "clc\\t%O0(1,%R0),%1" + "clc\t%O0(1,%R0),%1" [(set_attr "op_type" "SS")]) @@ -851,7 +865,7 @@ (compare (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ltdbr\\t%0,%0" + "ltdbr\t%0,%0" [(set_attr "op_type" "RRE") (set_attr "type" "fsimpd")]) @@ -860,7 +874,7 @@ (compare (match_operand:DF 0 "register_operand" "f") (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "ltdr\\t%0,%0" + "ltdr\t%0,%0" [(set_attr "op_type" "RR") (set_attr "type" "fsimpd")]) @@ -870,8 +884,8 @@ (match_operand:DF 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - cdbr\\t%0,%1 - cdb\\t%0,%1" + cdbr\t%0,%1 + cdb\t%0,%1" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimpd")]) @@ -881,8 +895,8 @@ (match_operand:DF 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - cdr\\t%0,%1 - cd\\t%0,%1" + cdr\t%0,%1 + cd\t%0,%1" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimpd")]) @@ -894,7 +908,7 @@ (compare (match_operand:SF 0 "register_operand" "f") (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ltebr\\t%0,%0" + "ltebr\t%0,%0" [(set_attr "op_type" "RRE") (set_attr "type" "fsimps")]) @@ -903,7 +917,7 @@ (compare (match_operand:SF 0 "register_operand" "f") (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lter\\t%0,%0" + "lter\t%0,%0" [(set_attr "op_type" "RR") (set_attr "type" "fsimps")]) @@ -913,8 +927,8 @@ (match_operand:SF 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - cebr\\t%0,%1 - ceb\\t%0,%1" + cebr\t%0,%1 + ceb\t%0,%1" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimps")]) @@ -924,8 +938,8 @@ (match_operand:SF 1 "general_operand" "f,R")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - cer\\t%0,%1 - ce\\t%0,%1" + cer\t%0,%1 + ce\t%0,%1" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimps")]) @@ -943,11 +957,11 @@ (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] "TARGET_64BIT" "@ - lmg\\t%0,%N0,%1 - stmg\\t%1,%N1,%0 + lmg\t%0,%N0,%1 + stmg\t%1,%N1,%0 # # - mvc\\t%O0(16,%R0),%1" + mvc\t%O0(16,%R0),%1" [(set_attr "op_type" "RSY,RSY,NN,NN,SS") (set_attr "type" "lm,stm,*,*,cs")]) @@ -1011,7 +1025,6 @@ [(set (match_operand:DI 0 "general_operand" "") (match_operand:DI 1 "general_operand" ""))] "" - " { /* Handle symbolic constants. */ if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) @@ -1020,11 +1033,11 @@ /* During and after reload, we need to force constants to the literal pool ourselves, if necessary. */ if ((reload_in_progress || reload_completed) - && CONSTANT_P (operands[1]) + && CONSTANT_P (operands[1]) && (!legitimate_reload_constant_p (operands[1]) || FP_REG_P (operands[0]))) operands[1] = force_const_mem (DImode, operands[1]); -}") +}) (define_insn "*movdi_lhi" [(set (match_operand:DI 0 "register_operand" "=d") @@ -1033,7 +1046,7 @@ && GET_CODE (operands[1]) == CONST_INT && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') && !FP_REG_P (operands[0])" - "lghi\\t%0,%h1" + "lghi\t%0,%h1" [(set_attr "op_type" "RI")]) (define_insn "*movdi_lli" @@ -1041,30 +1054,29 @@ (match_operand:DI 1 "immediate_operand" "n"))] "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 && !FP_REG_P (operands[0])" - "* { int part = s390_single_hi (operands[1], DImode, 0); operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); switch (part) { - case 0: return \"llihh\\t%0,%x1\"; - case 1: return \"llihl\\t%0,%x1\"; - case 2: return \"llilh\\t%0,%x1\"; - case 3: return \"llill\\t%0,%x1\"; + case 0: return "llihh\t%0,%x1"; + case 1: return "llihl\t%0,%x1"; + case 2: return "llilh\t%0,%x1"; + case 3: return "llill\t%0,%x1"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*movdi_lay" [(set (match_operand:DI 0 "register_operand" "=d") (match_operand:DI 1 "address_operand" "p"))] - "TARGET_64BIT + "TARGET_64BIT && TARGET_LONG_DISPLACEMENT && GET_CODE (operands[1]) == CONST_INT && !FP_REG_P (operands[0])" - "lay\\t%0,%a1" + "lay\t%0,%a1" [(set_attr "op_type" "RXY") (set_attr "type" "la")]) @@ -1073,7 +1085,7 @@ (match_operand:DI 1 "larl_operand" "X"))] "TARGET_64BIT && !FP_REG_P (operands[0])" - "larl\\t%0,%1" + "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl")]) @@ -1082,15 +1094,15 @@ (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))] "TARGET_64BIT" "@ - lgr\\t%0,%1 - lg\\t%0,%1 - stg\\t%1,%0 - ldr\\t%0,%1 - ld\\t%0,%1 - ldy\\t%0,%1 - std\\t%1,%0 - stdy\\t%1,%0 - mvc\\t%O0(8,%R0),%1" + lgr\t%0,%1 + lg\t%0,%1 + stg\t%1,%0 + ldr\t%0,%1 + ld\t%0,%1 + ldy\t%0,%1 + std\t%1,%0 + stdy\t%1,%0 + mvc\t%O0(8,%R0),%1" [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")]) @@ -1099,16 +1111,16 @@ (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] "!TARGET_64BIT" "@ - lm\\t%0,%N0,%1 - stm\\t%1,%N1,%0 + lm\t%0,%N0,%1 + stm\t%1,%N1,%0 # # - ldr\\t%0,%1 - ld\\t%0,%1 - ldy\\t%0,%1 - std\\t%1,%0 - stdy\\t%1,%0 - mvc\\t%O0(8,%R0),%1" + ldr\t%0,%1 + ld\t%0,%1 + ldy\t%0,%1 + std\t%1,%0 + stdy\t%1,%0 + mvc\t%O0(8,%R0),%1" [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) @@ -1185,14 +1197,13 @@ [(set (match_operand:SI 0 "general_operand" "") (match_operand:SI 1 "general_operand" ""))] "" - " { /* Handle symbolic constants. */ if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) emit_symbolic_move (operands); - /* expr.c tries to load an effective address using - force_reg. This fails because we don't have a + /* expr.c tries to load an effective address using + force_reg. This fails because we don't have a generic load_address pattern. Convert the move to a proper arithmetic operation instead, unless it is guaranteed to be OK. */ @@ -1207,11 +1218,11 @@ /* During and after reload, we need to force constants to the literal pool ourselves, if necessary. */ if ((reload_in_progress || reload_completed) - && CONSTANT_P (operands[1]) + && CONSTANT_P (operands[1]) && (!legitimate_reload_constant_p (operands[1]) || FP_REG_P (operands[0]))) operands[1] = force_const_mem (SImode, operands[1]); -}") +}) (define_insn "*movsi_lhi" [(set (match_operand:SI 0 "register_operand" "=d") @@ -1219,26 +1230,25 @@ "GET_CODE (operands[1]) == CONST_INT && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') && !FP_REG_P (operands[0])" - "lhi\\t%0,%h1" + "lhi\t%0,%h1" [(set_attr "op_type" "RI")]) (define_insn "*movsi_lli" [(set (match_operand:SI 0 "register_operand" "=d") (match_operand:SI 1 "immediate_operand" "n"))] - "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 + "TARGET_ZARCH && s390_single_hi (operands[1], SImode, 0) >= 0 && !FP_REG_P (operands[0])" - "* { int part = s390_single_hi (operands[1], SImode, 0); operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); switch (part) { - case 0: return \"llilh\\t%0,%x1\"; - case 1: return \"llill\\t%0,%x1\"; + case 0: return "llilh\t%0,%x1"; + case 1: return "llill\t%0,%x1"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "*movsi_lay" @@ -1247,26 +1257,35 @@ "TARGET_LONG_DISPLACEMENT && GET_CODE (operands[1]) == CONST_INT && !FP_REG_P (operands[0])" - "lay\\t%0,%a1" + "lay\t%0,%a1" [(set_attr "op_type" "RXY") (set_attr "type" "la")]) +(define_insn "*movsi_larl" + [(set (match_operand:SI 0 "register_operand" "=d") + (match_operand:SI 1 "larl_operand" "X"))] + "!TARGET_64BIT && TARGET_CPU_ZARCH + && !FP_REG_P (operands[0])" + "larl\t%0,%1" + [(set_attr "op_type" "RIL") + (set_attr "type" "larl")]) + (define_insn "*movsi" [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))] "" "@ - lr\\t%0,%1 - l\\t%0,%1 - ly\\t%0,%1 - st\\t%1,%0 - sty\\t%1,%0 - ler\\t%0,%1 - le\\t%0,%1 - ley\\t%0,%1 - ste\\t%1,%0 - stey\\t%1,%0 - mvc\\t%O0(4,%R0),%1" + lr\t%0,%1 + l\t%0,%1 + ly\t%0,%1 + st\t%1,%0 + sty\t%1,%0 + ler\t%0,%1 + le\t%0,%1 + ley\t%0,%1 + ste\t%1,%0 + stey\t%1,%0 + mvc\t%O0(4,%R0),%1" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) @@ -1285,18 +1304,36 @@ ; movhi instruction pattern(s). ; -(define_insn "movhi" +(define_expand "movhi" + [(set (match_operand:HI 0 "nonimmediate_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" +{ + /* Make it explicit that loading a register from memory + always sign-extends (at least) to SImode. */ + if (optimize && !no_new_pseudos + && register_operand (operands[0], VOIDmode) + && memory_operand (operands[1], VOIDmode)) + { + rtx tmp = gen_reg_rtx (SImode); + rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); + emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); + operands[1] = gen_lowpart (HImode, tmp); + } +}) + +(define_insn "*movhi" [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] "" "@ - lr\\t%0,%1 - lhi\\t%0,%h1 - lh\\t%0,%1 - lhy\\t%0,%1 - sth\\t%1,%0 - sthy\\t%1,%0 - mvc\\t%O0(2,%R0),%1" + lr\t%0,%1 + lhi\t%0,%h1 + lh\t%0,%1 + lhy\t%0,%1 + sth\t%1,%0 + sthy\t%1,%0 + mvc\t%O0(2,%R0),%1" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") (set_attr "type" "lr,*,*,*,store,store,cs")]) @@ -1314,36 +1351,38 @@ ; movqi instruction pattern(s). ; -(define_insn "movqi_64" - [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q") - (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))] - "TARGET_64BIT" - "@ - lr\\t%0,%1 - lhi\\t%0,%b1 - llgc\\t%0,%1 - stc\\t%1,%0 - stcy\\t%1,%0 - mvi\\t%0,%b1 - mviy\\t%0,%b1 - mvc\\t%O0(1,%R0),%1" - [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS") - (set_attr "type" "lr,*,*,store,store,store,store,cs")]) - -(define_insn "movqi" +(define_expand "movqi" + [(set (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" +{ + /* On 64-bit, zero-extending from memory to register + is just as fast as a QImode load. */ + if (TARGET_64BIT && optimize && !no_new_pseudos + && register_operand (operands[0], VOIDmode) + && memory_operand (operands[1], VOIDmode)) + { + rtx tmp = gen_reg_rtx (DImode); + rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); + emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); + operands[1] = gen_lowpart (QImode, tmp); + } +}) + +(define_insn "*movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] "" "@ - lr\\t%0,%1 - lhi\\t%0,%b1 - ic\\t%0,%1 - icy\\t%0,%1 - stc\\t%1,%0 - stcy\\t%1,%0 - mvi\\t%0,%b1 - mviy\\t%0,%b1 - mvc\\t%O0(1,%R0),%1" + lr\t%0,%1 + lhi\t%0,%b1 + ic\t%0,%1 + icy\t%0,%1 + stc\t%1,%0 + stcy\t%1,%0 + mvi\t%0,%b1 + mviy\t%0,%b1 + mvc\t%O0(1,%R0),%1" [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) @@ -1366,8 +1405,8 @@ (match_operand:QI 1 "memory_operand" "R,T"))] "" "@ - ic\\t%0,%1 - icy\\t%0,%1" + ic\t%0,%1 + icy\t%0,%1" [(set_attr "op_type" "RX,RXY")]) ; @@ -1380,8 +1419,8 @@ (clobber (reg:CC 33))] "" "@ - icm\\t%0,3,%1 - icmy\\t%0,3,%1" + icm\t%0,3,%1 + icmy\t%0,3,%1" [(set_attr "op_type" "RS,RSY")]) ; @@ -1393,9 +1432,9 @@ (match_operand:SI 1 "general_operand" "d,R,T"))] "TARGET_64BIT" "@ - lr\\t%0,%1 - l\\t%0,%1 - ly\\t%0,%1" + lr\t%0,%1 + l\t%0,%1 + ly\t%0,%1" [(set_attr "op_type" "RR,RX,RXY") (set_attr "type" "lr,load,load")]) @@ -1407,29 +1446,28 @@ [(set (match_operand:DF 0 "nonimmediate_operand" "") (match_operand:DF 1 "general_operand" ""))] "" - " { /* During and after reload, we need to force constants to the literal pool ourselves, if necessary. */ if ((reload_in_progress || reload_completed) && CONSTANT_P (operands[1])) operands[1] = force_const_mem (DFmode, operands[1]); -}") +}) (define_insn "*movdf_64" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] "TARGET_64BIT" "@ - ldr\\t%0,%1 - ld\\t%0,%1 - ldy\\t%0,%1 - std\\t%1,%0 - stdy\\t%1,%0 - lgr\\t%0,%1 - lg\\t%0,%1 - stg\\t%1,%0 - mvc\\t%O0(8,%R0),%1" + ldr\t%0,%1 + ld\t%0,%1 + ldy\t%0,%1 + std\t%1,%0 + stdy\t%1,%0 + lgr\t%0,%1 + lg\t%0,%1 + stg\t%1,%0 + mvc\t%O0(8,%R0),%1" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) @@ -1438,16 +1476,16 @@ (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] "!TARGET_64BIT" "@ - ldr\\t%0,%1 - ld\\t%0,%1 - ldy\\t%0,%1 - std\\t%1,%0 - stdy\\t%1,%0 - lm\\t%0,%N0,%1 - stm\\t%1,%N1,%0 + ldr\t%0,%1 + ld\t%0,%1 + ldy\t%0,%1 + std\t%1,%0 + stdy\t%1,%0 + lm\t%0,%N0,%1 + stm\t%1,%N1,%0 # # - mvc\\t%O0(8,%R0),%1" + mvc\t%O0(8,%R0),%1" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) @@ -1512,31 +1550,30 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "") (match_operand:SF 1 "general_operand" ""))] "" - " { /* During and after reload, we need to force constants to the literal pool ourselves, if necessary. */ if ((reload_in_progress || reload_completed) && CONSTANT_P (operands[1])) operands[1] = force_const_mem (SFmode, operands[1]); -}") +}) (define_insn "*movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] "" "@ - ler\\t%0,%1 - le\\t%0,%1 - ley\\t%0,%1 - ste\\t%1,%0 - stey\\t%1,%0 - lr\\t%0,%1 - l\\t%0,%1 - ly\\t%0,%1 - st\\t%1,%0 - sty\\t%1,%0 - mvc\\t%O0(4,%R0),%1" + ler\t%0,%1 + le\t%0,%1 + ley\t%0,%1 + ste\t%1,%0 + stey\t%1,%0 + lr\t%0,%1 + l\t%0,%1 + ly\t%0,%1 + st\t%1,%0 + sty\t%1,%0 + mvc\t%O0(4,%R0),%1" [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) @@ -1549,7 +1586,6 @@ (match_operand 1 "" "")) (use (match_operand 2 "" ""))])] "" - " { int regno; int count; @@ -1602,19 +1638,18 @@ change_address (operands[1], Pmode, plus_constant (from, off + i * UNITS_PER_WORD))); -}") +}) (define_insn "*load_multiple_di" [(match_parallel 0 "load_multiple_operation" [(set (match_operand:DI 1 "register_operand" "=r") (match_operand:DI 2 "s_operand" "QS"))])] "" - "* { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); - return \"lmg\\t%1,%0,%2\"; -}" + return "lmg\t%1,%0,%2"; +} [(set_attr "op_type" "RSY") (set_attr "type" "lm")]) @@ -1623,17 +1658,16 @@ [(set (match_operand:SI 1 "register_operand" "=r,r") (match_operand:SI 2 "s_operand" "Q,S"))])] "" - "* { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); - return which_alternative == 0 ? \"lm\\t%1,%0,%2\" : \"lmy\\t%1,%0,%2\"; -}" + return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; +} [(set_attr "op_type" "RS,RSY") (set_attr "type" "lm")]) ; -; store multiple pattern(s). +; store multiple pattern(s). ; (define_expand "store_multiple" @@ -1641,7 +1675,6 @@ (match_operand 1 "" "")) (use (match_operand 2 "" ""))])] "" - " { int regno; int count; @@ -1683,7 +1716,7 @@ if (to == frame_pointer_rtx || to == arg_pointer_rtx) FAIL; } - else + else { to = force_reg (Pmode, XEXP (operands[0], 0)); off = 0; @@ -1696,19 +1729,18 @@ plus_constant (to, off + i * UNITS_PER_WORD)), gen_rtx_REG (Pmode, regno + i)); -}") +}) (define_insn "*store_multiple_di" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:DI 1 "s_operand" "=QS") (match_operand:DI 2 "register_operand" "r"))])] "" - "* { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); - return \"stmg\\t%2,%0,%1\"; -}" + return "stmg\t%2,%0,%1"; +} [(set_attr "op_type" "RSY") (set_attr "type" "stm")]) @@ -1718,12 +1750,11 @@ [(set (match_operand:SI 1 "s_operand" "=Q,S") (match_operand:SI 2 "register_operand" "r,r"))])] "" - "* { int words = XVECLEN (operands[0], 0); operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); - return which_alternative == 0 ? \"stm\\t%2,%0,%1\" : \"stmy\\t%2,%0,%1\"; -}" + return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; +} [(set_attr "op_type" "RS,RSY") (set_attr "type" "stm")]) @@ -1760,22 +1791,21 @@ (use (match_operand:DI 2 "nonmemory_operand" "n,a")) (clobber (match_scratch:DI 3 "=X,&a"))] "TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"mvc\\t%O0(%b2+1,%R0),%1\"; + return "mvc\t%O0(%b2+1,%R0),%1"; case 1: - output_asm_insn (\"bras\\t%3,.+10\", operands); - output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); - return \"ex\\t%2,0(%3)\"; + output_asm_insn ("bras\t%3,.+10", operands); + output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); + return "ex\t%2,0(%3)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") @@ -1787,22 +1817,21 @@ (use (match_operand:SI 2 "nonmemory_operand" "n,a")) (clobber (match_scratch:SI 3 "=X,&a"))] "!TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"mvc\\t%O0(%b2+1,%R0),%1\"; + return "mvc\t%O0(%b2+1,%R0),%1"; case 1: - output_asm_insn (\"bras\\t%3,.+10\", operands); - output_asm_insn (\"mvc\\t%O0(1,%R0),%1\", operands); - return \"ex\\t%2,0(%3)\"; + output_asm_insn ("bras\t%3,.+10", operands); + output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); + return "ex\t%2,0(%3)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") @@ -1823,7 +1852,7 @@ (mem:BLK (subreg:DI (match_dup 3) 0))) (clobber (reg:CC 33))] "TARGET_64BIT" - "mvcle\\t%0,%1,0\;jo\\t.-4" + "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") (set_attr "length" "8")]) @@ -1841,7 +1870,7 @@ (mem:BLK (subreg:SI (match_dup 3) 0))) (clobber (reg:CC 33))] "!TARGET_64BIT" - "mvcle\\t%0,%1,0\;jo\\t.-4" + "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") (set_attr "length" "8")]) @@ -1876,22 +1905,21 @@ (clobber (match_scratch:DI 2 "=X,&a")) (clobber (reg:CC 33))] "TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"xc\\t%O0(%b1+1,%R0),%0\"; + return "xc\t%O0(%b1+1,%R0),%0"; case 1: - output_asm_insn (\"bras\\t%2,.+10\", operands); - output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); - return \"ex\\t%1,0(%2)\"; + output_asm_insn ("bras\t%2,.+10", operands); + output_asm_insn ("xc\t%O0(1,%R0),%0", operands); + return "ex\t%1,0(%2)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") @@ -1904,22 +1932,21 @@ (clobber (match_scratch:SI 2 "=X,&a")) (clobber (reg:CC 33))] "!TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"xc\\t%O0(%b1+1,%R0),%0\"; + return "xc\t%O0(%b1+1,%R0),%0"; case 1: - output_asm_insn (\"bras\\t%2,.+10\", operands); - output_asm_insn (\"xc\\t%O0(1,%R0),%0\", operands); - return \"ex\\t%1,0(%2)\"; + output_asm_insn ("bras\t%2,.+10", operands); + output_asm_insn ("xc\t%O0(1,%R0),%0", operands); + return "ex\t%1,0(%2)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") @@ -1937,7 +1964,7 @@ (use (match_operand:TI 1 "register_operand" "d")) (clobber (reg:CC 33))] "TARGET_64BIT" - "mvcle\\t%0,%1,0\;jo\\t.-4" + "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") (set_attr "length" "8")]) @@ -1952,89 +1979,87 @@ (use (match_operand:DI 1 "register_operand" "d")) (clobber (reg:CC 33))] "!TARGET_64BIT" - "mvcle\\t%0,%1,0\;jo\\t.-4" + "mvcle\t%0,%1,0\;jo\t.-4" [(set_attr "op_type" "NN") (set_attr "type" "vs") (set_attr "length" "8")]) ; -; cmpstrM instruction pattern(s). +; cmpmemM instruction pattern(s). ; -(define_expand "cmpstrdi" +(define_expand "cmpmemdi" [(set (match_operand:DI 0 "register_operand" "") (compare:DI (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "") ) ) (use (match_operand:DI 3 "general_operand" "")) (use (match_operand:DI 4 "" ""))] "TARGET_64BIT" - "s390_expand_cmpstr (operands[0], operands[1], + "s390_expand_cmpmem (operands[0], operands[1], operands[2], operands[3]); DONE;") -(define_expand "cmpstrsi" +(define_expand "cmpmemsi" [(set (match_operand:SI 0 "register_operand" "") (compare:SI (match_operand:BLK 1 "memory_operand" "") (match_operand:BLK 2 "memory_operand" "") ) ) (use (match_operand:SI 3 "general_operand" "")) (use (match_operand:SI 4 "" ""))] "" - "s390_expand_cmpstr (operands[0], operands[1], + "s390_expand_cmpmem (operands[0], operands[1], operands[2], operands[3]); DONE;") ; Compare a block that is up to 256 bytes in length. ; The block length is taken as (operands[2] % 256) + 1. -(define_insn "cmpstr_short_64" +(define_insn "cmpmem_short_64" [(set (reg:CCS 33) (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") (match_operand:BLK 1 "memory_operand" "Q,Q"))) (use (match_operand:DI 2 "nonmemory_operand" "n,a")) (clobber (match_scratch:DI 3 "=X,&a"))] "TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"clc\\t%O0(%b2+1,%R0),%1\"; + return "clc\t%O0(%b2+1,%R0),%1"; case 1: - output_asm_insn (\"bras\\t%3,.+10\", operands); - output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); - return \"ex\\t%2,0(%3)\"; + output_asm_insn ("bras\t%3,.+10", operands); + output_asm_insn ("clc\t%O0(1,%R0),%1", operands); + return "ex\t%2,0(%3)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") (set_attr "length" "*,14")]) -(define_insn "cmpstr_short_31" +(define_insn "cmpmem_short_31" [(set (reg:CCS 33) (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") (match_operand:BLK 1 "memory_operand" "Q,Q"))) (use (match_operand:SI 2 "nonmemory_operand" "n,a")) (clobber (match_scratch:SI 3 "=X,&a"))] "!TARGET_64BIT" - "* { switch (which_alternative) { case 0: - return \"clc\\t%O0(%b2+1,%R0),%1\"; + return "clc\t%O0(%b2+1,%R0),%1"; case 1: - output_asm_insn (\"bras\\t%3,.+10\", operands); - output_asm_insn (\"clc\\t%O0(1,%R0),%1\", operands); - return \"ex\\t%2,0(%3)\"; + output_asm_insn ("bras\t%3,.+10", operands); + output_asm_insn ("clc\t%O0(1,%R0),%1", operands); + return "ex\t%2,0(%3)"; default: abort (); } -}" +} [(set_attr "op_type" "SS,NN") (set_attr "type" "cs,cs") (set_attr "atype" "*,agen") @@ -2042,7 +2067,7 @@ ; Compare a block of arbitrary length. -(define_insn "cmpstr_long_64" +(define_insn "cmpmem_long_64" [(clobber (match_operand:TI 0 "register_operand" "=d")) (clobber (match_operand:TI 1 "register_operand" "=d")) (set (reg:CCS 33) @@ -2051,11 +2076,11 @@ (use (match_dup 2)) (use (match_dup 3))] "TARGET_64BIT" - "clcl\\t%0,%1" + "clcl\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "vs")]) -(define_insn "cmpstr_long_31" +(define_insn "cmpmem_long_31" [(clobber (match_operand:DI 0 "register_operand" "=d")) (clobber (match_operand:DI 1 "register_operand" "=d")) (set (reg:CCS 33) @@ -2064,7 +2089,7 @@ (use (match_dup 2)) (use (match_dup 3))] "!TARGET_64BIT" - "clcl\\t%0,%1" + "clcl\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "vs")]) @@ -2074,14 +2099,13 @@ [(set (match_operand:SI 0 "register_operand" "=d") (compare:SI (reg:CCS 33) (const_int 0)))] "" - "* { - output_asm_insn (\"lhi\\t%0,1\", operands); - output_asm_insn (\"jh\\t.+12\", operands); - output_asm_insn (\"jl\\t.+6\", operands); - output_asm_insn (\"sr\\t%0,%0\", operands); - return \"lcr\\t%0,%0\"; -}" + output_asm_insn ("lhi\t%0,1", operands); + output_asm_insn ("jh\t.+12", operands); + output_asm_insn ("jl\t.+6", operands); + output_asm_insn ("sr\t%0,%0", operands); + return "lcr\t%0,%0"; +} [(set_attr "op_type" "NN") (set_attr "length" "16") (set_attr "type" "other")]) @@ -2090,14 +2114,13 @@ [(set (match_operand:DI 0 "register_operand" "=d") (compare:DI (reg:CCS 33) (const_int 0)))] "TARGET_64BIT" - "* { - output_asm_insn (\"lghi\\t%0,1\", operands); - output_asm_insn (\"jh\\t.+12\", operands); - output_asm_insn (\"jl\\t.+6\", operands); - output_asm_insn (\"sgr\\t%0,%0\", operands); - return \"lcgr\\t%0,%0\"; -}" + output_asm_insn ("lghi\t%0,1", operands); + output_asm_insn ("jh\t.+12", operands); + output_asm_insn ("jl\t.+6", operands); + output_asm_insn ("sgr\t%0,%0", operands); + return "lcgr\t%0,%0"; +} [(set_attr "op_type" "NN") (set_attr "length" "22") (set_attr "type" "other")]) @@ -2109,40 +2132,40 @@ (define_insn "*sethighqisi" [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] 10)) + (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) (clobber (reg:CC 33))] "" "@ - icm\\t%0,8,%1 - icmy\\t%0,8,%1" + icm\t%0,8,%1 + icmy\t%0,8,%1" [(set_attr "op_type" "RS,RSY")]) (define_insn "*sethighhisi" [(set (match_operand:SI 0 "register_operand" "=d,d") - (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] 10)) + (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) (clobber (reg:CC 33))] "" "@ - icm\\t%0,12,%1 - icmy\\t%0,12,%1" + icm\t%0,12,%1 + icmy\t%0,12,%1" [(set_attr "op_type" "RS,RSY")]) (define_insn "*sethighqidi_64" [(set (match_operand:DI 0 "register_operand" "=d") - (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] 10)) + (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) (clobber (reg:CC 33))] "TARGET_64BIT" - "icmh\\t%0,8,%1" + "icmh\t%0,8,%1" [(set_attr "op_type" "RSY")]) (define_insn "*sethighqidi_31" [(set (match_operand:DI 0 "register_operand" "=d,d") - (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] 10)) + (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) (clobber (reg:CC 33))] "!TARGET_64BIT" "@ - icm\\t%0,8,%1 - icmy\\t%0,8,%1" + icm\t%0,8,%1 + icmy\t%0,8,%1" [(set_attr "op_type" "RS,RSY")]) (define_insn_and_split "*extractqi" @@ -2156,14 +2179,13 @@ "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) (clobber (reg:CC 33))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] - " { operands[2] = GEN_INT (32 - INTVAL (operands[2])); operands[1] = change_address (operands[1], QImode, 0); -}" +} [(set_attr "atype" "agen")]) (define_insn_and_split "*extracthi" @@ -2177,14 +2199,13 @@ "#" "&& reload_completed" [(parallel - [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) (clobber (reg:CC 33))]) (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] - " { operands[2] = GEN_INT (32 - INTVAL (operands[2])); operands[1] = change_address (operands[1], HImode, 0); -}" +} [(set_attr "atype" "agen")]) ; @@ -2213,8 +2234,8 @@ (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] "TARGET_64BIT" "@ - lgfr\\t%0,%1 - lgf\\t%0,%1" + lgfr\t%0,%1 + lgf\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) ; @@ -2238,7 +2259,7 @@ { operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); - emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); + emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); DONE; } } @@ -2248,7 +2269,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" - "lgh\\t%0,%1" + "lgh\t%0,%1" [(set_attr "op_type" "RXY")]) ; @@ -2272,7 +2293,7 @@ { operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); - emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); + emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); DONE; } } @@ -2282,7 +2303,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" - "lgb\\t%0,%1" + "lgb\t%0,%1" [(set_attr "op_type" "RXY")]) (define_split @@ -2290,7 +2311,7 @@ (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed" [(parallel - [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10)) + [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) (clobber (reg:CC 33))]) (parallel [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) @@ -2309,7 +2330,7 @@ { operands[1] = gen_lowpart (SImode, operands[1]); emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); - emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); + emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); DONE; } ") @@ -2319,8 +2340,8 @@ (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] "" "@ - lh\\t%0,%1 - lhy\\t%0,%1" + lh\t%0,%1 + lhy\t%0,%1" [(set_attr "op_type" "RX,RXY")]) ; @@ -2335,7 +2356,7 @@ { operands[1] = gen_lowpart (SImode, operands[1]); emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); - emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); + emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); DONE; } ") @@ -2343,16 +2364,16 @@ (define_insn "*extendqisi2" [(set (match_operand:SI 0 "register_operand" "=d") (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" - "lb\\t%0,%1" + "TARGET_LONG_DISPLACEMENT" + "lb\t%0,%1" [(set_attr "op_type" "RXY")]) (define_split [(set (match_operand:SI 0 "register_operand" "") (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] - "(!TARGET_64BIT || !TARGET_LONG_DISPLACEMENT) && !reload_completed" + "!TARGET_LONG_DISPLACEMENT && !reload_completed" [(parallel - [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) + [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) (clobber (reg:CC 33))]) (parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) @@ -2389,8 +2410,8 @@ (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] "TARGET_64BIT" "@ - llgfr\\t%0,%1 - llgf\\t%0,%1" + llgfr\t%0,%1 + llgf\t%0,%1" [(set_attr "op_type" "RRE,RXY")]) ; @@ -2414,7 +2435,7 @@ { operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); - emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); + emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); DONE; } } @@ -2424,10 +2445,81 @@ [(set (match_operand:DI 0 "register_operand" "=d") (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" - "llgh\\t%0,%1" + "llgh\t%0,%1" [(set_attr "op_type" "RXY")]) ; +; LLGT-type instructions (zero-extend from 31 bit to 64 bit). +; + +(define_insn "*llgt_sisi" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") + (const_int 2147483647)))] + "TARGET_64BIT" + "@ + llgtr\t%0,%1 + llgt\t%0,%1" + [(set_attr "op_type" "RRE,RXE")]) + +(define_insn_and_split "*llgt_sisi_split" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:SI (match_dup 1) + (const_int 2147483647)))] + "") + +(define_insn "*llgt_didi" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") + (const_int 2147483647)))] + "TARGET_64BIT" + "@ + llgtr\t%0,%1 + llgt\t%0,%N1" + [(set_attr "op_type" "RRE,RXE")]) + +(define_insn_and_split "*llgt_didi_split" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (match_dup 1) + (const_int 2147483647)))] + "") + +(define_insn "*llgt_sidi" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647)))] + "TARGET_64BIT" + "llgt\t%0,%1" + [(set_attr "op_type" "RXE")]) + +(define_insn_and_split "*llgt_sidi_split" + [(set (match_operand:DI 0 "register_operand" "=d") + (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) + (const_int 2147483647))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(set (match_dup 0) + (and:DI (subreg:DI (match_dup 1) 0) + (const_int 2147483647)))] + "") + +; ; zero_extendqidi2 instruction pattern(s) ; @@ -2448,7 +2540,7 @@ { operands[1] = gen_lowpart (DImode, operands[1]); emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); - emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); + emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); DONE; } } @@ -2458,7 +2550,7 @@ [(set (match_operand:DI 0 "register_operand" "=d") (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_64BIT" - "llgc\\t%0,%1" + "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) ; @@ -2481,12 +2573,12 @@ [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] "TARGET_64BIT" - "llgh\\t%0,%1" + "llgh\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendhisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") - (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS"))) + (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) (clobber (reg:CC 33))] "!TARGET_64BIT" "#" @@ -2497,7 +2589,7 @@ (clobber (reg:CC 33))])] "operands[2] = gen_lowpart (HImode, operands[0]);" [(set_attr "atype" "agen")]) - + ; ; zero_extendqisi2 instruction pattern(s). ; @@ -2517,21 +2609,21 @@ (define_insn "*zero_extendqisi2_64" [(set (match_operand:SI 0 "register_operand" "=d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT" - "llgc\\t%0,%1" + "TARGET_ZARCH" + "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqisi2_31" [(set (match_operand:SI 0 "register_operand" "=&d") (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) (set (strict_low_part (match_dup 2)) (match_dup 1))] "operands[2] = gen_lowpart (QImode, operands[0]);" [(set_attr "atype" "agen")]) - + ; ; zero_extendqihi2 instruction pattern(s). ; @@ -2539,7 +2631,7 @@ (define_expand "zero_extendqihi2" [(set (match_operand:HI 0 "register_operand" "") (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] - "TARGET_64BIT" + "TARGET_ZARCH" " { operands[1] = gen_lowpart (HImode, operands[1]); @@ -2551,14 +2643,14 @@ (define_insn "*zero_extendqihi2_64" [(set (match_operand:HI 0 "register_operand" "=d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] - "TARGET_64BIT" - "llgc\\t%0,%1" + "TARGET_ZARCH" + "llgc\t%0,%1" [(set_attr "op_type" "RXY")]) (define_insn_and_split "*zero_extendqihi2_31" [(set (match_operand:HI 0 "register_operand" "=&d") (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] - "!TARGET_64BIT" + "!TARGET_ZARCH" "#" "&& reload_completed" [(set (match_dup 0) (const_int 0)) @@ -2575,20 +2667,19 @@ [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (DFmode); operands[1] = force_reg (DFmode, operands[1]); - emit_insn (gen_cmpdf (operands[1], + emit_insn (gen_cmpdf (operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode))); + REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); emit_jump_insn (gen_blt (label1)); emit_insn (gen_subdf3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode))); + REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); emit_jump (label2); @@ -2596,26 +2687,25 @@ emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); emit_label (label2); DONE; -}") +}) (define_expand "fix_truncdfdi2" [(set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { operands[1] = force_reg (DFmode, operands[1]); emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); DONE; -}") +}) (define_insn "fix_truncdfdi2_ieee" [(set (match_operand:DI 0 "register_operand" "=d") (fix:DI (match_operand:DF 1 "register_operand" "f"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) + (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC 33))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cgdbr\\t%0,%h2,%1" + "cgdbr\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) @@ -2627,20 +2717,19 @@ [(set (match_operand:SI 0 "register_operand" "") (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (DFmode); operands[1] = force_reg (DFmode,operands[1]); - emit_insn (gen_cmpdf (operands[1], + emit_insn (gen_cmpdf (operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode))); + REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); emit_jump_insn (gen_blt (label1)); emit_insn (gen_subdf3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode))); + REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); emit_jump (label2); @@ -2648,15 +2737,14 @@ emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); emit_label (label2); DONE; -}") +}) (define_expand "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] "TARGET_HARD_FLOAT" - " { - if (TARGET_IBM_FLOAT) + if (TARGET_IBM_FLOAT) { /* This is the algorithm from POP chapter A.5.7.2. */ @@ -2665,25 +2753,25 @@ rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); operands[1] = force_reg (DFmode, operands[1]); - emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], + emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], two31r, two32, temp)); - } - else + } + else { operands[1] = force_reg (DFmode, operands[1]); emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); } DONE; -}") +}) (define_insn "fix_truncdfsi2_ieee" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (match_operand:DF 1 "register_operand" "f"))) - (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) + (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cfdbr\\t%0,%h2,%1" + "cfdbr\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "other" )]) @@ -2695,14 +2783,13 @@ (use (match_operand:BLK 4 "memory_operand" "m")) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "* { - output_asm_insn (\"sd\\t%1,%2\", operands); - output_asm_insn (\"aw\\t%1,%3\", operands); - output_asm_insn (\"std\\t%1,%4\", operands); - output_asm_insn (\"xi\\t%N4,128\", operands); - return \"l\\t%0,%N4\"; -}" + output_asm_insn ("sd\t%1,%2", operands); + output_asm_insn ("aw\t%1,%3", operands); + output_asm_insn ("std\t%1,%4", operands); + output_asm_insn ("xi\t%N4,128", operands); + return "l\t%0,%N4"; +} [(set_attr "op_type" "NN") (set_attr "type" "ftoi") (set_attr "atype" "agen") @@ -2716,21 +2803,20 @@ [(set (match_operand:DI 0 "register_operand" "") (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx temp = gen_reg_rtx (SFmode); operands[1] = force_reg (SFmode, operands[1]); - emit_insn (gen_cmpsf (operands[1], + emit_insn (gen_cmpsf (operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode))); + REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); emit_jump_insn (gen_blt (label1)); emit_insn (gen_subsf3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode))); + REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); emit_jump (label2); @@ -2738,26 +2824,25 @@ emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); emit_label (label2); DONE; -}") +}) (define_expand "fix_truncsfdi2" [(set (match_operand:DI 0 "register_operand" "") (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { operands[1] = force_reg (SFmode, operands[1]); emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); DONE; -}") +}) (define_insn "fix_truncsfdi2_ieee" [(set (match_operand:DI 0 "register_operand" "=d") (fix:DI (match_operand:SF 1 "register_operand" "f"))) - (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) + (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC 33))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cgebr\\t%0,%h2,%1" + "cgebr\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) @@ -2769,7 +2854,6 @@ [(set (match_operand:SI 0 "register_operand" "") (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - " { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); @@ -2778,11 +2862,11 @@ operands[1] = force_reg (SFmode, operands[1]); emit_insn (gen_cmpsf (operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode))); + REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); emit_jump_insn (gen_blt (label1)); emit_insn (gen_subsf3 (temp, operands[1], CONST_DOUBLE_FROM_REAL_VALUE ( - REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode))); + REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); emit_jump (label2); @@ -2790,13 +2874,12 @@ emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); emit_label (label2); DONE; -}") +}) (define_expand "fix_truncsfsi2" [(set (match_operand:SI 0 "register_operand" "") (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] "TARGET_HARD_FLOAT" - " { if (TARGET_IBM_FLOAT) { @@ -2812,15 +2895,15 @@ } DONE; -}") +}) (define_insn "fix_truncsfsi2_ieee" [(set (match_operand:SI 0 "register_operand" "=d") (fix:SI (match_operand:SF 1 "register_operand" "f"))) - (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) + (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cfebr\\t%0,%h2,%1" + "cfebr\t%0,%h2,%1" [(set_attr "op_type" "RRE") (set_attr "type" "ftoi")]) @@ -2833,7 +2916,7 @@ (float:DF (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cdgbr\\t%0,%1" + "cdgbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -2846,7 +2929,7 @@ (float:SF (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cegbr\\t%0,%1" + "cegbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -2860,26 +2943,25 @@ (float:DF (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 33))])] "TARGET_HARD_FLOAT" - " { - if (TARGET_IBM_FLOAT) + if (TARGET_IBM_FLOAT) { /* This is the algorithm from POP chapter A.5.7.1. */ rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); - rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); + rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); DONE; } -}") +}) (define_insn "floatsidf2_ieee" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cdfbr\\t%0,%1" + "cdfbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -2890,14 +2972,13 @@ (use (match_operand:BLK 3 "memory_operand" "m")) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "* { - output_asm_insn (\"st\\t%1,%N3\", operands); - output_asm_insn (\"xi\\t%N3,128\", operands); - output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands); - output_asm_insn (\"ld\\t%0,%3\", operands); - return \"sd\\t%0,%2\"; -}" + output_asm_insn ("st\t%1,%N3", operands); + output_asm_insn ("xi\t%N3,128", operands); + output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); + output_asm_insn ("ld\t%0,%3", operands); + return "sd\t%0,%2"; +} [(set_attr "op_type" "NN") (set_attr "type" "other" ) (set_attr "atype" "agen") @@ -2913,7 +2994,6 @@ (float:SF (match_operand:SI 1 "register_operand" ""))) (clobber (reg:CC 33))])] "TARGET_HARD_FLOAT" - " { if (TARGET_IBM_FLOAT) { @@ -2923,14 +3003,14 @@ emit_insn (gen_truncdfsf2 (operands[0], temp)); DONE; } -}") +}) (define_insn "floatsisf2_ieee" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "cefbr\\t%0,%1" + "cefbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "itof" )]) @@ -2948,7 +3028,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "ledbr\\t%0,%1" + "ledbr\t%0,%1" [(set_attr "op_type" "RRE")]) (define_insn "truncdfsf2_ibm" @@ -2956,8 +3036,8 @@ (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - lrer\\t%0,%1 - le\\t%0,%1" + lrer\t%0,%1 + le\t%0,%1" [(set_attr "op_type" "RR,RX") (set_attr "type" "floads,floads")]) @@ -2969,22 +3049,21 @@ [(set (match_operand:DF 0 "register_operand" "") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] "TARGET_HARD_FLOAT" - " { if (TARGET_IBM_FLOAT) { emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); DONE; } -}") +}) (define_insn "extendsfdf2_ieee" [(set (match_operand:DF 0 "register_operand" "=f,f") (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - ldebr\\t%0,%1 - ldeb\\t%0,%1" + ldebr\t%0,%1 + ldeb\t%0,%1" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "floads,floads")]) @@ -2994,12 +3073,12 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - sdr\\t%0,%0\;ler\\t%0,%1 - sdr\\t%0,%0\;le\\t%0,%1" + sdr\t%0,%0\;ler\t%0,%1 + sdr\t%0,%0\;le\t%0,%1" [(set_attr "op_type" "NN,NN") (set_attr "atype" "reg,agen") (set_attr "length" "4,6") - (set_attr "type" "o2,o2")]) + (set_attr "type" "o2,o2")]) ;; @@ -3024,12 +3103,12 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - agfr\\t%0,%2 - agf\\t%0,%2" + agfr\t%0,%2 + agf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) @@ -3037,20 +3116,20 @@ (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - algfr\\t%0,%2 - algf\\t%0,%2" + algfr\t%0,%2 + algf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero_cconly" - [(set (reg 33) + [(set (reg 33) (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) (match_operand:DI 1 "register_operand" "0,0")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - algfr\\t%0,%2 - algf\\t%0,%2" + algfr\t%0,%2 + algf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_zero" @@ -3060,25 +3139,25 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - algfr\\t%0,%2 - algf\\t%0,%2" + algfr\t%0,%2 + algf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_imm_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") (match_operand:DI 2 "const_int_operand" "K")) (const_int 0))) (set (match_operand:DI 0 "register_operand" "=d") (plus:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT - && s390_match_ccmode (insn, CCAmode) + "TARGET_64BIT + && s390_match_ccmode (insn, CCAmode) && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" - "aghi\\t%0,%h2" + "aghi\t%0,%h2" [(set_attr "op_type" "RI")]) (define_insn "*adddi3_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) @@ -3086,31 +3165,31 @@ (plus:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - algr\\t%0,%2 - alg\\t%0,%2" + algr\t%0,%2 + alg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly" - [(set (reg 33) + [(set (reg 33) (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") (match_operand:DI 2 "general_operand" "d,m")) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - algr\\t%0,%2 - alg\\t%0,%2" + algr\t%0,%2 + alg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_cconly2" - [(set (reg 33) + [(set (reg 33) (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" "@ - algr\\t%0,%2 - alg\\t%0,%2" + algr\t%0,%2 + alg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*adddi3_64" @@ -3120,9 +3199,9 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - agr\\t%0,%2 - aghi\\t%0,%h2 - ag\\t%0,%2" + agr\t%0,%2 + aghi\t%0,%h2 + ag\t%0,%2" [(set_attr "op_type" "RRE,RI,RXY")]) (define_insn_and_split "*adddi3_31" @@ -3172,8 +3251,8 @@ (match_operand:QI 1 "address_operand" "U,W"))] "TARGET_64BIT" "@ - la\\t%0,%a1 - lay\\t%0,%a1" + la\t%0,%a1 + lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la")]) @@ -3208,19 +3287,18 @@ (match_operand:DI 1 "s390_plus_operand" "") (match_operand:DI 2 "register_operand" "=&a")])] "TARGET_64BIT" - " { s390_expand_plus_operand (operands[0], operands[1], operands[2]); DONE; -}") +}) + - ; ; addsi3 instruction pattern(s). ; (define_insn "*addsi3_imm_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "const_int_operand" "K")) (const_int 0))) @@ -3228,100 +3306,100 @@ (plus:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCAmode) && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" - "ahi\\t%0,%h2" + "ahi\t%0,%h2" [(set_attr "op_type" "RI")]) (define_insn "*addsi3_carry1_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) (set (match_operand:SI 0 "register_operand" "=d,d,d") (plus:SI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode (insn, CCL1mode)" + "s390_match_ccmode (insn, CCL1mode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry1_cconly" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 1))) (clobber (match_scratch:SI 0 "=d,d,d"))] - "s390_match_ccmode (insn, CCL1mode)" + "s390_match_ccmode (insn, CCL1mode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) (set (match_operand:SI 0 "register_operand" "=d,d,d") (plus:SI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode (insn, CCL1mode)" + "s390_match_ccmode (insn, CCL1mode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_carry2_cconly" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (match_dup 2))) (clobber (match_scratch:SI 0 "=d,d,d"))] - "s390_match_ccmode (insn, CCL1mode)" + "s390_match_ccmode (insn, CCL1mode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cc" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=d,d,d") (plus:SI (match_dup 1) (match_dup 2)))] - "s390_match_ccmode (insn, CCLmode)" + "s390_match_ccmode (insn, CCLmode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly" - [(set (reg 33) + [(set (reg 33) (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (match_operand:SI 2 "general_operand" "d,R,T")) (const_int 0))) (clobber (match_scratch:SI 0 "=d,d,d"))] - "s390_match_ccmode (insn, CCLmode)" + "s390_match_ccmode (insn, CCLmode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_cconly2" - [(set (reg 33) + [(set (reg 33) (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCLmode)" "@ - alr\\t%0,%2 - al\\t%0,%2 - aly\\t%0,%2" + alr\t%0,%2 + al\t%0,%2 + aly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*addsi3_sign" @@ -3331,8 +3409,8 @@ (clobber (reg:CC 33))] "" "@ - ah\\t%0,%2 - ahy\\t%0,%2" + ah\t%0,%2 + ahy\t%0,%2" [(set_attr "op_type" "RX,RXY")]) (define_insn "*addsi3_sub" @@ -3342,8 +3420,8 @@ (clobber (reg:CC 33))] "" "@ - ah\\t%0,%2 - ahy\\t%0,%2" + ah\t%0,%2 + ahy\t%0,%2" [(set_attr "op_type" "RX,RXY")]) (define_insn "addsi3" @@ -3353,10 +3431,10 @@ (clobber (reg:CC 33))] "" "@ - ar\\t%0,%2 - ahi\\t%0,%h2 - a\\t%0,%2 - ay\\t%0,%2" + ar\t%0,%2 + ahi\t%0,%h2 + a\t%0,%2 + ay\t%0,%2" [(set_attr "op_type" "RR,RI,RX,RXY")]) (define_insn "*la_31" @@ -3364,8 +3442,8 @@ (match_operand:QI 1 "address_operand" "U,W"))] "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" "@ - la\\t%0,%a1 - lay\\t%0,%a1" + la\t%0,%a1 + lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la")]) @@ -3401,8 +3479,8 @@ (const_int 2147483647)))] "!TARGET_64BIT" "@ - la\\t%0,%a1 - lay\\t%0,%a1" + la\t%0,%a1 + lay\t%0,%a1" [(set_attr "op_type" "RX,RXY") (set_attr "type" "la")]) @@ -3414,7 +3492,7 @@ "!TARGET_64BIT" "#" "&& reload_completed" - [(set (match_dup 0) + [(set (match_dup 0) (and:SI (match_dup 1) (const_int 2147483647)))] "" [(set_attr "op_type" "RX") @@ -3426,8 +3504,8 @@ (use (const_int 0))] "!TARGET_64BIT" "@ - la\\t%0,%a1 - lay\\t%0,%a1" + la\t%0,%a1 + lay\t%0,%a1" [(set_attr "op_type" "RX") (set_attr "type" "la")]) @@ -3436,11 +3514,10 @@ (match_operand:SI 1 "s390_plus_operand" "") (match_operand:SI 2 "register_operand" "=&a")])] "!TARGET_64BIT" - " { s390_expand_plus_operand (operands[0], operands[1], operands[2]); DONE; -}") +}) ; @@ -3463,8 +3540,35 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - adbr\\t%0,%2 - adb\\t%0,%2" + adbr\t%0,%2 + adb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*adddf3_cc" + [(set (reg 33) + (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (set (match_operand:DF 0 "register_operand" "=f,f") + (plus:DF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + adbr\t%0,%2 + adb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*adddf3_cconly" + [(set (reg 33) + (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (clobber (match_scratch:DF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + adbr\t%0,%2 + adb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimpd,fsimpd")]) @@ -3475,8 +3579,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - adr\\t%0,%2 - ad\\t%0,%2" + adr\t%0,%2 + ad\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimpd,fsimpd")]) @@ -3500,8 +3604,35 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - aebr\\t%0,%2 - aeb\\t%0,%2" + aebr\t%0,%2 + aeb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*addsf3_cc" + [(set (reg 33) + (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (set (match_operand:SF 0 "register_operand" "=f,f") + (plus:SF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + aebr\t%0,%2 + aeb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*addsf3_cconly" + [(set (reg 33) + (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (clobber (match_scratch:SF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + aebr\t%0,%2 + aeb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimps,fsimps")]) @@ -3512,8 +3643,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - aer\\t%0,%2 - ae\\t%0,%2" + aer\t%0,%2 + ae\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimps,fsimps")]) @@ -3533,12 +3664,12 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - sgfr\\t%0,%2 - sgf\\t%0,%2" + sgfr\t%0,%2 + sgf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cc" - [(set (reg 33) + [(set (reg 33) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) @@ -3546,20 +3677,20 @@ (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - slgfr\\t%0,%2 - slgf\\t%0,%2" + slgfr\t%0,%2 + slgf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero_cconly" - [(set (reg 33) + [(set (reg 33) (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) (const_int 0))) (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" "@ - slgfr\\t%0,%2 - slgf\\t%0,%2" + slgfr\t%0,%2 + slgf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_zero" @@ -3569,8 +3700,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - slgfr\\t%0,%2 - slgf\\t%0,%2" + slgfr\t%0,%2 + slgf\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cc" @@ -3582,8 +3713,8 @@ (minus:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode (insn, CCLmode)" "@ - slgr\\t%0,%2 - slg\\t%0,%2" + slgr\t%0,%2 + slg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_cconly" @@ -3594,8 +3725,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode (insn, CCLmode)" "@ - slgr\\t%0,%2 - slg\\t%0,%2" + slgr\t%0,%2 + slg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*subdi3_64" @@ -3605,8 +3736,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - sgr\\t%0,%2 - sg\\t%0,%2" + sgr\t%0,%2 + sg\t%0,%2" [(set_attr "op_type" "RRE,RRE")]) (define_insn_and_split "*subdi3_31" @@ -3664,9 +3795,9 @@ (minus:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCL2mode)" "@ - slr\\t%0,%2 - sl\\t%0,%2 - sly\\t%0,%2" + slr\t%0,%2 + sl\t%0,%2 + sly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_borrow_cconly" @@ -3677,9 +3808,9 @@ (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCL2mode)" "@ - slr\\t%0,%2 - sl\\t%0,%2 - sly\\t%0,%2" + slr\t%0,%2 + sl\t%0,%2 + sly\t%0,%2" [(set_attr "op_type" "RR,RX,RXE")]) (define_insn "*subsi3_cc" @@ -3691,9 +3822,9 @@ (minus:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCLmode)" "@ - slr\\t%0,%2 - sl\\t%0,%2 - sly\\t%0,%2" + slr\t%0,%2 + sl\t%0,%2 + sly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_cconly" @@ -3704,9 +3835,9 @@ (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCLmode)" "@ - slr\\t%0,%2 - sl\\t%0,%2 - sly\\t%0,%2" + slr\t%0,%2 + sl\t%0,%2 + sly\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*subsi3_sign" @@ -3716,8 +3847,8 @@ (clobber (reg:CC 33))] "" "@ - sh\\t%0,%2 - shy\\t%0,%2" + sh\t%0,%2 + shy\t%0,%2" [(set_attr "op_type" "RX,RXY")]) (define_insn "*subsi3_sub" @@ -3727,8 +3858,8 @@ (clobber (reg:CC 33))] "" "@ - sh\\t%0,%2 - shy\\t%0,%2" + sh\t%0,%2 + shy\t%0,%2" [(set_attr "op_type" "RX,RXY")]) (define_insn "subsi3" @@ -3738,9 +3869,9 @@ (clobber (reg:CC 33))] "" "@ - sr\\t%0,%2 - s\\t%0,%2 - sy\\t%0,%2" + sr\t%0,%2 + s\t%0,%2 + sy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) @@ -3764,8 +3895,35 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sdbr\\t%0,%2 - sdb\\t%0,%2" + sdbr\t%0,%2 + sdb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*subdf3_cc" + [(set (reg 33) + (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (set (match_operand:DF 0 "register_operand" "=f,f") + (plus:DF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sdbr\t%0,%2 + sdb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimpd,fsimpd")]) + +(define_insn "*subdf3_cconly" + [(set (reg 33) + (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") + (match_operand:DF 2 "general_operand" "f,R")) + (match_operand:DF 3 "const0_operand" ""))) + (clobber (match_scratch:DF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sdbr\t%0,%2 + sdb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimpd,fsimpd")]) @@ -3776,8 +3934,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - sdr\\t%0,%2 - sd\\t%0,%2" + sdr\t%0,%2 + sd\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimpd,fsimpd")]) @@ -3801,8 +3959,35 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sebr\\t%0,%2 - seb\\t%0,%2" + sebr\t%0,%2 + seb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*subsf3_cc" + [(set (reg 33) + (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (set (match_operand:SF 0 "register_operand" "=f,f") + (minus:SF (match_dup 1) (match_dup 2)))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sebr\t%0,%2 + seb\t%0,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fsimps,fsimps")]) + +(define_insn "*subsf3_cconly" + [(set (reg 33) + (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") + (match_operand:SF 2 "general_operand" "f,R")) + (match_operand:SF 3 "const0_operand" ""))) + (clobber (match_scratch:SF 0 "=f,f"))] + "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "@ + sebr\t%0,%2 + seb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fsimps,fsimps")]) @@ -3813,8 +3998,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - ser\\t%0,%2 - se\\t%0,%2" + ser\t%0,%2 + se\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fsimps,fsimps")]) @@ -3833,21 +4018,20 @@ (match_operand:DI 1 "register_operand" "0,0")))] "TARGET_64BIT" "@ - msgfr\\t%0,%2 - msgf\\t%0,%2" + msgfr\t%0,%2 + msgf\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "type" "imul")]) - (define_insn "muldi3" [(set (match_operand:DI 0 "register_operand" "=d,d,d") (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") (match_operand:DI 2 "general_operand" "d,K,m")))] "TARGET_64BIT" "@ - msgr\\t%0,%2 - mghi\\t%0,%h2 - msg\\t%0,%2" + msgr\t%0,%2 + mghi\t%0,%h2 + msg\t%0,%2" [(set_attr "op_type" "RRE,RI,RXY") (set_attr "type" "imul")]) @@ -3855,16 +4039,25 @@ ; mulsi3 instruction pattern(s). ; +(define_insn "*mulsi3_sign" + [(set (match_operand:SI 0 "register_operand" "=d") + (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) + (match_operand:SI 1 "register_operand" "0")))] + "" + "mh\t%0,%2" + [(set_attr "op_type" "RX") + (set_attr "type" "imul")]) + (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") (match_operand:SI 2 "general_operand" "d,K,R,T")))] "" "@ - msr\\t%0,%2 - mhi\\t%0,%h2 - ms\\t%0,%2 - msy\\t%0,%2" + msr\t%0,%2 + mhi\t%0,%h2 + ms\t%0,%2 + msy\t%0,%2" [(set_attr "op_type" "RRE,RI,RX,RXY") (set_attr "type" "imul")]) @@ -3872,40 +4065,36 @@ ; mulsidi3 instruction pattern(s). ; -(define_expand "mulsidi3" - [(set (match_operand:DI 0 "register_operand" "") - (mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")) - (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (mult:DI (sign_extend:DI + (match_operand:SI 1 "register_operand" "%0,0")) + (sign_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] "!TARGET_64BIT" - " -{ - rtx insn; + "@ + mr\t%0,%2 + m\t%0,%2" + [(set_attr "op_type" "RR,RX") + (set_attr "type" "imul")]) - emit_insn (gen_zero_extendsidi2 (operands[0], operands[1])); - insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); +; +; umulsidi3 instruction pattern(s). +; - REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, - gen_rtx_MULT (DImode, - gen_rtx_SIGN_EXTEND (DImode, operands[1]), - gen_rtx_SIGN_EXTEND (DImode, operands[2])), - REG_NOTES (insn)); - DONE; -}") - -(define_insn "mulsi_6432" - [(set (match_operand:DI 0 "register_operand" "=d,d") - (mult:DI (sign_extend:DI - (truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) - (sign_extend:DI - (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] - "!TARGET_64BIT" - "@ - mr\\t%0,%2 - m\\t%0,%2" - [(set_attr "op_type" "RR,RX") +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (mult:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "%0,0")) + (zero_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] + "!TARGET_64BIT && TARGET_CPU_ZARCH" + "@ + mlr\t%0,%2 + ml\t%0,%2" + [(set_attr "op_type" "RRE,RXY") (set_attr "type" "imul")]) - + ; ; muldf3 instruction pattern(s). ; @@ -3926,8 +4115,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - mdbr\\t%0,%2 - mdb\\t%0,%2" + mdbr\t%0,%2 + mdb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fmuld")]) @@ -3938,11 +4127,35 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - mdr\\t%0,%2 - md\\t%0,%2" + mdr\t%0,%2 + md\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fmuld")]) +(define_insn "*fmadddf" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") + (match_operand:DF 2 "nonimmediate_operand" "f,R")) + (match_operand:DF 3 "register_operand" "0,0")))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations" + "@ + madbr\t%0,%1,%2 + madb\t%0,%1,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fmuld")]) + +(define_insn "*fmsubdf" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") + (match_operand:DF 2 "nonimmediate_operand" "f,R")) + (match_operand:DF 3 "register_operand" "0,0")))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations" + "@ + msdbr\t%0,%1,%2 + msdb\t%0,%1,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fmuld")]) + ; ; mulsf3 instruction pattern(s). ; @@ -3963,8 +4176,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - meebr\\t%0,%2 - meeb\\t%0,%2" + meebr\t%0,%2 + meeb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fmuls")]) @@ -3975,11 +4188,34 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - mer\\t%0,%2 - me\\t%0,%2" + mer\t%0,%2 + me\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fmuls")]) +(define_insn "*fmaddsf" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") + (match_operand:SF 2 "nonimmediate_operand" "f,R")) + (match_operand:SF 3 "register_operand" "0,0")))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations" + "@ + maebr\t%0,%1,%2 + maeb\t%0,%1,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fmuls")]) + +(define_insn "*fmsubsf" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") + (match_operand:SF 2 "nonimmediate_operand" "f,R")) + (match_operand:SF 3 "register_operand" "0,0")))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && flag_unsafe_math_optimizations" + "@ + msebr\t%0,%1,%2 + mseb\t%0,%1,%2" + [(set_attr "op_type" "RRE,RXE") + (set_attr "type" "fmuls")]) ;; ;;- Divide and modulo instructions. @@ -3991,31 +4227,20 @@ (define_expand "divmoddi4" [(parallel [(set (match_operand:DI 0 "general_operand" "") - (div:DI (match_operand:DI 1 "general_operand" "") + (div:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "general_operand" ""))) (set (match_operand:DI 3 "general_operand" "") (mod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] "TARGET_64BIT" - " { - rtx insn, div_equal, mod_equal, equal; + rtx insn, div_equal, mod_equal; div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); - equal = gen_rtx_IOR (TImode, - gen_rtx_ZERO_EXTEND (TImode, div_equal), - gen_rtx_ASHIFT (TImode, - gen_rtx_ZERO_EXTEND (TImode, mod_equal), - GEN_INT (64))); operands[4] = gen_reg_rtx(TImode); - emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); - emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); - emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); - insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); - REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); + emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); REG_NOTES (insn) = @@ -4026,23 +4251,23 @@ gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); DONE; -}") +}) (define_insn "divmodtidi3" [(set (match_operand:TI 0 "register_operand" "=d,d") (ior:TI (zero_extend:TI - (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) + (div:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "general_operand" "d,m"))) (ashift:TI (zero_extend:TI - (mod:DI (truncate:DI (match_dup 1)) + (mod:DI (match_dup 1) (match_dup 2))) (const_int 64))))] "TARGET_64BIT" "@ - dsgr\\t%0,%2 - dsg\\t%0,%2" + dsgr\t%0,%2 + dsg\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "type" "idiv")]) @@ -4050,17 +4275,17 @@ [(set (match_operand:TI 0 "register_operand" "=d,d") (ior:TI (zero_extend:TI - (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) + (div:DI (match_operand:DI 1 "register_operand" "0,0") (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) (ashift:TI (zero_extend:TI - (mod:DI (truncate:DI (match_dup 1)) + (mod:DI (match_dup 1) (sign_extend:DI (match_dup 2)))) (const_int 64))))] "TARGET_64BIT" "@ - dsgfr\\t%0,%2 - dsgf\\t%0,%2" + dsgfr\t%0,%2 + dsgf\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "type" "idiv")]) @@ -4076,7 +4301,6 @@ (umod:DI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] "TARGET_64BIT" - " { rtx insn, div_equal, mod_equal, equal; @@ -4105,11 +4329,11 @@ gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); DONE; -}") +}) (define_insn "udivmodtidi3" [(set (match_operand:TI 0 "register_operand" "=d,d") - (ior:TI (zero_extend:TI + (ior:TI (zero_extend:TI (truncate:DI (udiv:TI (match_operand:TI 1 "register_operand" "0,0") (zero_extend:TI @@ -4121,8 +4345,8 @@ (const_int 64))))] "TARGET_64BIT" "@ - dlgr\\t%0,%2 - dlg\\t%0,%2" + dlgr\t%0,%2 + dlg\t%0,%2" [(set_attr "op_type" "RRE,RXY") (set_attr "type" "idiv")]) @@ -4138,7 +4362,6 @@ (mod:SI (match_dup 1) (match_dup 2)))]) (clobber (match_dup 4))] "!TARGET_64BIT" - " { rtx insn, div_equal, mod_equal, equal; @@ -4165,14 +4388,14 @@ gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); DONE; -}") +}) (define_insn "divmoddisi3" [(set (match_operand:DI 0 "register_operand" "=d,d") (ior:DI (zero_extend:DI (truncate:SI (div:DI (match_operand:DI 1 "register_operand" "0,0") - (sign_extend:DI + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) (ashift:DI (zero_extend:DI @@ -4181,8 +4404,8 @@ (const_int 32))))] "!TARGET_64BIT" "@ - dr\\t%0,%2 - d\\t%0,%2" + dr\t%0,%2 + d\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "idiv")]) @@ -4190,14 +4413,69 @@ ; udivsi3 and umodsi3 instruction pattern(s). ; +(define_expand "udivmodsi4" + [(parallel [(set (match_operand:SI 0 "general_operand" "") + (udiv:SI (match_operand:SI 1 "general_operand" "") + (match_operand:SI 2 "nonimmediate_operand" ""))) + (set (match_operand:SI 3 "general_operand" "") + (umod:SI (match_dup 1) (match_dup 2)))]) + (clobber (match_dup 4))] + "!TARGET_64BIT && TARGET_CPU_ZARCH" +{ + rtx insn, div_equal, mod_equal, equal; + + div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); + mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); + equal = gen_rtx_IOR (DImode, + gen_rtx_ZERO_EXTEND (DImode, div_equal), + gen_rtx_ASHIFT (DImode, + gen_rtx_ZERO_EXTEND (DImode, mod_equal), + GEN_INT (32))); + + operands[4] = gen_reg_rtx(DImode); + emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); + emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); + emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); + insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); + REG_NOTES (insn) = + gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); + + insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); + REG_NOTES (insn) = + gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); + + insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); + REG_NOTES (insn) = + gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); + + DONE; +}) + +(define_insn "udivmoddisi3" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (ior:DI (zero_extend:DI + (truncate:SI + (udiv:DI (match_operand:DI 1 "register_operand" "0,0") + (zero_extend:DI + (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) + (ashift:DI + (zero_extend:DI + (truncate:SI + (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) + (const_int 32))))] + "!TARGET_64BIT && TARGET_CPU_ZARCH" + "@ + dlr\t%0,%2 + dl\t%0,%2" + [(set_attr "op_type" "RRE,RXY") + (set_attr "type" "idiv")]) (define_expand "udivsi3" [(set (match_operand:SI 0 "register_operand" "=d") (udiv:SI (match_operand:SI 1 "general_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (match_dup 3))] - "!TARGET_64BIT" - " + "!TARGET_64BIT && !TARGET_CPU_ZARCH" { rtx insn, udiv_equal, umod_equal, equal; @@ -4226,32 +4504,32 @@ } else { - operands[2] = force_reg (SImode, operands[2]); - operands[2] = make_safe_from (operands[2], operands[0]); + operands[2] = force_reg (SImode, operands[2]); + operands[2] = make_safe_from (operands[2], operands[0]); emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], operands[2])); REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); - - insn = emit_move_insn (operands[0], + + insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[3])); REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, + gen_rtx_EXPR_LIST (REG_EQUAL, udiv_equal, REG_NOTES (insn)); } } else - { + { rtx label1 = gen_label_rtx (); rtx label2 = gen_label_rtx (); rtx label3 = gen_label_rtx (); - operands[1] = force_reg (SImode, operands[1]); - operands[1] = make_safe_from (operands[1], operands[0]); - operands[2] = force_reg (SImode, operands[2]); - operands[2] = make_safe_from (operands[2], operands[0]); + operands[1] = force_reg (SImode, operands[1]); + operands[1] = make_safe_from (operands[1], operands[0]); + operands[2] = force_reg (SImode, operands[2]); + operands[2] = make_safe_from (operands[2], operands[0]); emit_move_insn (operands[0], const0_rtx); emit_insn (gen_cmpsi (operands[2], operands[1])); @@ -4265,11 +4543,11 @@ operands[2])); REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); - - insn = emit_move_insn (operands[0], + + insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[3])); REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, + gen_rtx_EXPR_LIST (REG_EQUAL, udiv_equal, REG_NOTES (insn)); emit_jump (label3); emit_label (label1); @@ -4279,17 +4557,16 @@ emit_move_insn (operands[0], const1_rtx); emit_label (label3); } - emit_move_insn (operands[0], operands[0]); + emit_move_insn (operands[0], operands[0]); DONE; -}") +}) (define_expand "umodsi3" [(set (match_operand:SI 0 "register_operand" "=d") (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") (match_operand:SI 2 "nonimmediate_operand" ""))) (clobber (match_dup 3))] - "!TARGET_64BIT" - " + "!TARGET_64BIT && !TARGET_CPU_ZARCH" { rtx insn, udiv_equal, umod_equal, equal; @@ -4319,19 +4596,19 @@ } else { - operands[2] = force_reg (SImode, operands[2]); - operands[2] = make_safe_from (operands[2], operands[0]); + operands[2] = force_reg (SImode, operands[2]); + operands[2] = make_safe_from (operands[2], operands[0]); emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], operands[2])); REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); - - insn = emit_move_insn (operands[0], + + insn = emit_move_insn (operands[0], gen_highpart (SImode, operands[3])); REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, + gen_rtx_EXPR_LIST (REG_EQUAL, umod_equal, REG_NOTES (insn)); } } @@ -4341,12 +4618,12 @@ rtx label2 = gen_label_rtx (); rtx label3 = gen_label_rtx (); - operands[1] = force_reg (SImode, operands[1]); - operands[1] = make_safe_from (operands[1], operands[0]); - operands[2] = force_reg (SImode, operands[2]); - operands[2] = make_safe_from (operands[2], operands[0]); + operands[1] = force_reg (SImode, operands[1]); + operands[1] = make_safe_from (operands[1], operands[0]); + operands[2] = force_reg (SImode, operands[2]); + operands[2] = make_safe_from (operands[2], operands[0]); - emit_move_insn(operands[0], operands[1]); + emit_move_insn(operands[0], operands[1]); emit_insn (gen_cmpsi (operands[2], operands[1])); emit_jump_insn (gen_bgtu (label3)); emit_insn (gen_cmpsi (operands[2], const1_rtx)); @@ -4358,11 +4635,11 @@ operands[2])); REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); - - insn = emit_move_insn (operands[0], + + insn = emit_move_insn (operands[0], gen_highpart (SImode, operands[3])); REG_NOTES (insn) = - gen_rtx_EXPR_LIST (REG_EQUAL, + gen_rtx_EXPR_LIST (REG_EQUAL, umod_equal, REG_NOTES (insn)); emit_jump (label3); emit_label (label1); @@ -4373,7 +4650,7 @@ emit_label (label3); } DONE; -}") +}) ; ; divdf3 instruction pattern(s). @@ -4395,8 +4672,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - ddbr\\t%0,%2 - ddb\\t%0,%2" + ddbr\t%0,%2 + ddb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fdivd")]) @@ -4407,8 +4684,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - ddr\\t%0,%2 - dd\\t%0,%2" + ddr\t%0,%2 + dd\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fdivd")]) @@ -4432,8 +4709,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - debr\\t%0,%2 - deb\\t%0,%2" + debr\t%0,%2 + deb\t%0,%2" [(set_attr "op_type" "RRE,RXE") (set_attr "type" "fdivs")]) @@ -4444,8 +4721,8 @@ (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "@ - der\\t%0,%2 - de\\t%0,%2" + der\t%0,%2 + de\t%0,%2" [(set_attr "op_type" "RR,RX") (set_attr "type" "fdivs")]) @@ -4467,8 +4744,8 @@ (and:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - ngr\\t%0,%2 - ng\\t%0,%2" + ngr\t%0,%2 + ng\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_cconly" @@ -4479,8 +4756,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - ngr\\t%0,%2 - ng\\t%0,%2" + ngr\t%0,%2 + ng\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_ni" @@ -4489,20 +4766,19 @@ (match_operand:DI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" - "* { int part = s390_single_hi (operands[2], DImode, -1); operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); switch (part) { - case 0: return \"nihh\\t%0,%x2\"; - case 1: return \"nihl\\t%0,%x2\"; - case 2: return \"nilh\\t%0,%x2\"; - case 3: return \"nill\\t%0,%x2\"; + case 0: return "nihh\t%0,%x2"; + case 1: return "nihl\t%0,%x2"; + case 2: return "nilh\t%0,%x2"; + case 3: return "nill\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "anddi3" @@ -4512,8 +4788,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - ngr\\t%0,%2 - ng\\t%0,%2" + ngr\t%0,%2 + ng\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*anddi3_ss" @@ -4522,7 +4798,7 @@ (match_operand:DI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "nc\\t%O0(8,%R0),%1" + "nc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*anddi3_ss_inv" @@ -4531,7 +4807,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "nc\\t%O0(8,%R0),%1" + "nc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4547,9 +4823,9 @@ (and:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ - nr\\t%0,%2 - n\\t%0,%2 - ny\\t%0,%2" + nr\t%0,%2 + n\t%0,%2 + ny\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*andsi3_cconly" @@ -4560,9 +4836,9 @@ (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode)" "@ - nr\\t%0,%2 - n\\t%0,%2 - ny\\t%0,%2" + nr\t%0,%2 + n\t%0,%2 + ny\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*andsi3_ni" @@ -4570,19 +4846,18 @@ (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] - "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" - "* + "TARGET_ZARCH && s390_single_hi (operands[2], SImode, -1) >= 0" { int part = s390_single_hi (operands[2], SImode, -1); operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); switch (part) { - case 0: return \"nilh\\t%0,%x2\"; - case 1: return \"nill\\t%0,%x2\"; + case 0: return "nilh\t%0,%x2"; + case 1: return "nill\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "andsi3" @@ -4592,9 +4867,9 @@ (clobber (reg:CC 33))] "" "@ - nr\\t%0,%2 - n\\t%0,%2 - ny\\t%0,%2" + nr\t%0,%2 + n\t%0,%2 + ny\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*andsi3_ss" @@ -4603,7 +4878,7 @@ (match_operand:SI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "nc\\t%O0(4,%R0),%1" + "nc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*andsi3_ss_inv" @@ -4612,7 +4887,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "nc\\t%O0(4,%R0),%1" + "nc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4624,10 +4899,10 @@ (and:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ - nr\\t%0,%2 - nill\\t%0,%x2" + nr\t%0,%2 + nill\t%0,%x2" [(set_attr "op_type" "RR,RI")]) (define_insn "andhi3" @@ -4636,7 +4911,7 @@ (match_operand:HI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "nr\\t%0,%2" + "nr\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*andhi3_ss" @@ -4645,7 +4920,7 @@ (match_operand:HI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "nc\\t%O0(2,%R0),%1" + "nc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*andhi3_ss_inv" @@ -4654,7 +4929,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "nc\\t%O0(2,%R0),%1" + "nc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4666,10 +4941,10 @@ (and:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ - nr\\t%0,%2 - nill\\t%0,%b2" + nr\t%0,%2 + nill\t%0,%b2" [(set_attr "op_type" "RR,RI")]) (define_insn "andqi3" @@ -4678,7 +4953,7 @@ (match_operand:QI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "nr\\t%0,%2" + "nr\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*andqi3_ss" @@ -4688,9 +4963,9 @@ (clobber (reg:CC 33))] "" "@ - ni\\t%0,%b1 - niy\\t%0,%b1 - nc\\t%O0(1,%R0),%1" + ni\t%0,%b1 + niy\t%0,%b1 + nc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) (define_insn "*andqi3_ss_inv" @@ -4700,9 +4975,9 @@ (clobber (reg:CC 33))] "" "@ - ni\\t%0,%b1 - niy\\t%0,%b1 - nc\\t%O0(1,%R0),%1" + ni\t%0,%b1 + niy\t%0,%b1 + nc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) @@ -4723,8 +4998,8 @@ (ior:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - ogr\\t%0,%2 - og\\t%0,%2" + ogr\t%0,%2 + og\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_cconly" @@ -4735,8 +5010,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - ogr\\t%0,%2 - og\\t%0,%2" + ogr\t%0,%2 + og\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_oi" @@ -4745,20 +5020,19 @@ (match_operand:DI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" - "* { int part = s390_single_hi (operands[2], DImode, 0); operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); switch (part) { - case 0: return \"oihh\\t%0,%x2\"; - case 1: return \"oihl\\t%0,%x2\"; - case 2: return \"oilh\\t%0,%x2\"; - case 3: return \"oill\\t%0,%x2\"; + case 0: return "oihh\t%0,%x2"; + case 1: return "oihl\t%0,%x2"; + case 2: return "oilh\t%0,%x2"; + case 3: return "oill\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "iordi3" @@ -4768,8 +5042,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - ogr\\t%0,%2 - og\\t%0,%2" + ogr\t%0,%2 + og\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*iordi3_ss" @@ -4778,7 +5052,7 @@ (match_operand:DI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "oc\\t%O0(8,%R0),%1" + "oc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*iordi3_ss_inv" @@ -4787,7 +5061,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "oc\\t%O0(8,%R0),%1" + "oc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4803,9 +5077,9 @@ (ior:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ - or\\t%0,%2 - o\\t%0,%2 - oy\\t%0,%2" + or\t%0,%2 + o\t%0,%2 + oy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*iorsi3_cconly" @@ -4816,9 +5090,9 @@ (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode)" "@ - or\\t%0,%2 - o\\t%0,%2 - oy\\t%0,%2" + or\t%0,%2 + o\t%0,%2 + oy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*iorsi3_oi" @@ -4826,19 +5100,18 @@ (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") (match_operand:SI 2 "immediate_operand" "n"))) (clobber (reg:CC 33))] - "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" - "* + "TARGET_ZARCH && s390_single_hi (operands[2], SImode, 0) >= 0" { int part = s390_single_hi (operands[2], SImode, 0); operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); switch (part) { - case 0: return \"oilh\\t%0,%x2\"; - case 1: return \"oill\\t%0,%x2\"; + case 0: return "oilh\t%0,%x2"; + case 1: return "oill\t%0,%x2"; default: abort (); } -}" +} [(set_attr "op_type" "RI")]) (define_insn "iorsi3" @@ -4848,9 +5121,9 @@ (clobber (reg:CC 33))] "" "@ - or\\t%0,%2 - o\\t%0,%2 - oy\\t%0,%2" + or\t%0,%2 + o\t%0,%2 + oy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*iorsi3_ss" @@ -4859,7 +5132,7 @@ (match_operand:SI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "oc\\t%O0(4,%R0),%1" + "oc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*iorsi3_ss_inv" @@ -4868,7 +5141,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "oc\\t%O0(4,%R0),%1" + "oc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4880,10 +5153,10 @@ (ior:HI (match_operand:HI 1 "register_operand" "%0,0") (match_operand:HI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ - or\\t%0,%2 - oill\\t%0,%x2" + or\t%0,%2 + oill\t%0,%x2" [(set_attr "op_type" "RR,RI")]) (define_insn "iorhi3" @@ -4892,7 +5165,7 @@ (match_operand:HI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "or\\t%0,%2" + "or\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*iorhi3_ss" @@ -4901,7 +5174,7 @@ (match_operand:HI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "oc\\t%O0(2,%R0),%1" + "oc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*iorhi3_ss_inv" @@ -4910,7 +5183,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "oc\\t%O0(2,%R0),%1" + "oc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -4922,10 +5195,10 @@ (ior:QI (match_operand:QI 1 "register_operand" "%0,0") (match_operand:QI 2 "nonmemory_operand" "d,n"))) (clobber (reg:CC 33))] - "TARGET_64BIT" + "TARGET_ZARCH" "@ - or\\t%0,%2 - oill\\t%0,%b2" + or\t%0,%2 + oill\t%0,%b2" [(set_attr "op_type" "RR,RI")]) (define_insn "iorqi3" @@ -4934,7 +5207,7 @@ (match_operand:QI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "or\\t%0,%2" + "or\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*iorqi3_ss" @@ -4944,9 +5217,9 @@ (clobber (reg:CC 33))] "" "@ - oi\\t%0,%b1 - oiy\\t%0,%b1 - oc\\t%O0(1,%R0),%1" + oi\t%0,%b1 + oiy\t%0,%b1 + oc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) (define_insn "*iorqi3_ss_inv" @@ -4956,9 +5229,9 @@ (clobber (reg:CC 33))] "" "@ - oi\\t%0,%b1 - oiy\\t%0,%b1 - oc\\t%O0(1,%R0),%1" + oi\t%0,%b1 + oiy\t%0,%b1 + oc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) @@ -4979,8 +5252,8 @@ (xor:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - xgr\\t%0,%2 - xg\\t%0,%2" + xgr\t%0,%2 + xg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3_cconly" @@ -4991,8 +5264,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" "@ - xgr\\t%0,%2 - xr\\t%0,%2" + xgr\t%0,%2 + xr\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "xordi3" @@ -5002,8 +5275,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - xgr\\t%0,%2 - xg\\t%0,%2" + xgr\t%0,%2 + xg\t%0,%2" [(set_attr "op_type" "RRE,RXY")]) (define_insn "*xordi3_ss" @@ -5012,7 +5285,7 @@ (match_operand:DI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "xc\\t%O0(8,%R0),%1" + "xc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*xordi3_ss_inv" @@ -5021,7 +5294,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "xc\\t%O0(8,%R0),%1" + "xc\t%O0(8,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -5037,9 +5310,9 @@ (xor:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCTmode)" "@ - xr\\t%0,%2 - x\\t%0,%2 - xy\\t%0,%2" + xr\t%0,%2 + x\t%0,%2 + xy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*xorsi3_cconly" @@ -5050,9 +5323,9 @@ (clobber (match_scratch:SI 0 "=d,d,d"))] "s390_match_ccmode(insn, CCTmode)" "@ - xr\\t%0,%2 - x\\t%0,%2 - xy\\t%0,%2" + xr\t%0,%2 + x\t%0,%2 + xy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "xorsi3" @@ -5062,9 +5335,9 @@ (clobber (reg:CC 33))] "" "@ - xr\\t%0,%2 - x\\t%0,%2 - xy\\t%0,%2" + xr\t%0,%2 + x\t%0,%2 + xy\t%0,%2" [(set_attr "op_type" "RR,RX,RXY")]) (define_insn "*xorsi3_ss" @@ -5073,7 +5346,7 @@ (match_operand:SI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "xc\\t%O0(4,%R0),%1" + "xc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*xorsi3_ss_inv" @@ -5082,7 +5355,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "xc\\t%O0(4,%R0),%1" + "xc\t%O0(4,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -5095,7 +5368,7 @@ (match_operand:HI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "xr\\t%0,%2" + "xr\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*xorhi3_ss" @@ -5104,7 +5377,7 @@ (match_operand:HI 1 "s_imm_operand" "Q"))) (clobber (reg:CC 33))] "" - "xc\\t%O0(2,%R0),%1" + "xc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) (define_insn "*xorhi3_ss_inv" @@ -5113,7 +5386,7 @@ (match_dup 0))) (clobber (reg:CC 33))] "" - "xc\\t%O0(2,%R0),%1" + "xc\t%O0(2,%R0),%1" [(set_attr "op_type" "SS")]) ; @@ -5126,7 +5399,7 @@ (match_operand:QI 2 "nonmemory_operand" "d"))) (clobber (reg:CC 33))] "" - "xr\\t%0,%2" + "xr\t%0,%2" [(set_attr "op_type" "RR")]) (define_insn "*xorqi3_ss" @@ -5136,9 +5409,9 @@ (clobber (reg:CC 33))] "" "@ - xi\\t%0,%b1 - xiy\\t%0,%b1 - xc\\t%O0(1,%R0),%1" + xi\t%0,%b1 + xiy\t%0,%b1 + xc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) (define_insn "*xorqi3_ss_inv" @@ -5148,9 +5421,9 @@ (clobber (reg:CC 33))] "" "@ - xi\\t%0,%b1 - xiy\\t%0,%b1 - xc\\t%O0(1,%R0),%1" + xi\t%0,%b1 + xiy\t%0,%b1 + xc\t%O0(1,%R0),%1" [(set_attr "op_type" "SI,SIY,SS")]) @@ -5175,7 +5448,7 @@ (neg:DI (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_64BIT" - "lcgr\\t%0,%1" + "lcgr\t%0,%1" [(set_attr "op_type" "RR")]) (define_insn "*negdi2_31" @@ -5183,18 +5456,17 @@ (neg:DI (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "!TARGET_64BIT" - "* { rtx xop[1]; xop[0] = gen_label_rtx (); - output_asm_insn (\"lcr\\t%0,%1\", operands); - output_asm_insn (\"lcr\\t%N0,%N1\", operands); - output_asm_insn (\"je\\t%l0\", xop); - output_asm_insn (\"bctr\\t%0,0\", operands); - (*targetm.asm_out.internal_label) (asm_out_file, \"L\", + output_asm_insn ("lcr\t%0,%1", operands); + output_asm_insn ("lcr\t%N0,%N1", operands); + output_asm_insn ("je\t%l0", xop); + output_asm_insn ("bctr\t%0,0", operands); + targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (xop[0])); - return \"\"; -}" + return ""; +} [(set_attr "op_type" "NN") (set_attr "type" "other") (set_attr "length" "10")]) @@ -5208,7 +5480,7 @@ (neg:SI (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "" - "lcr\\t%0,%1" + "lcr\t%0,%1" [(set_attr "op_type" "RR")]) ; @@ -5228,7 +5500,7 @@ (neg:DF (match_operand:DF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcdbr\\t%0,%1" + "lcdbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "fsimpd")]) @@ -5237,7 +5509,7 @@ (neg:DF (match_operand:DF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lcdr\\t%0,%1" + "lcdr\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "fsimpd")]) @@ -5258,7 +5530,7 @@ (neg:SF (match_operand:SF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lcebr\\t%0,%1" + "lcebr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "fsimps")]) @@ -5267,7 +5539,7 @@ (neg:SF (match_operand:SF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lcer\\t%0,%1" + "lcer\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "fsimps")]) @@ -5285,7 +5557,7 @@ (abs:DI (match_operand:DI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "TARGET_64BIT" - "lpgr\\t%0,%1" + "lpgr\t%0,%1" [(set_attr "op_type" "RRE")]) ; @@ -5297,7 +5569,7 @@ (abs:SI (match_operand:SI 1 "register_operand" "d"))) (clobber (reg:CC 33))] "" - "lpr\\t%0,%1" + "lpr\t%0,%1" [(set_attr "op_type" "RR")]) ; @@ -5317,7 +5589,7 @@ (abs:DF (match_operand:DF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpdbr\\t%0,%1" + "lpdbr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "fsimpd")]) @@ -5326,7 +5598,7 @@ (abs:DF (match_operand:DF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lpdr\\t%0,%1" + "lpdr\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "fsimpd")]) @@ -5347,7 +5619,7 @@ (abs:SF (match_operand:SF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" - "lpebr\\t%0,%1" + "lpebr\t%0,%1" [(set_attr "op_type" "RRE") (set_attr "type" "fsimps")]) @@ -5356,11 +5628,57 @@ (abs:SF (match_operand:SF 1 "register_operand" "f"))) (clobber (reg:CC 33))] "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" - "lper\\t%0,%1" + "lper\t%0,%1" [(set_attr "op_type" "RR") (set_attr "type" "fsimps")]) ;; +;;- Negated absolute value instructions +;; + +; +; Integer +; + +(define_insn "*negabssi2" + [(set (match_operand:SI 0 "register_operand" "=d") + (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) + (clobber (reg:CC 33))] + "" + "lnr\t%0,%1" + [(set_attr "op_type" "RR")]) + +(define_insn "*negabsdi2" + [(set (match_operand:DI 0 "register_operand" "=d") + (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) + (clobber (reg:CC 33))] + "TARGET_64BIT" + "lngr\t%0,%1" + [(set_attr "op_type" "RRE")]) + +; +; Floating point +; + +(define_insn "*negabssf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) + (clobber (reg:CC 33))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "lnebr\t%0,%1" + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimps")]) + +(define_insn "*negabsdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (reg:CC 33))] + "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" + "lndbr\t%0,%1" + [(set_attr "op_type" "RRE") + (set_attr "type" "fsimpd")]) + +;; ;;- Square root instructions. ;; @@ -5373,8 +5691,8 @@ (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sqdbr\\t%0,%1 - sqdb\\t%0,%1" + sqdbr\t%0,%1 + sqdb\t%0,%1" [(set_attr "op_type" "RRE,RXE")]) ; @@ -5386,8 +5704,8 @@ (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "@ - sqebr\\t%0,%1 - sqeb\\t%0,%1" + sqebr\t%0,%1 + sqeb\t%0,%1" [(set_attr "op_type" "RRE,RXE")]) ;; @@ -5397,7 +5715,7 @@ ; ; one_cmpldi2 instruction pattern(s). ; - + (define_expand "one_cmpldi2" [(parallel [(set (match_operand:DI 0 "register_operand" "") @@ -5406,11 +5724,11 @@ (clobber (reg:CC 33))])] "TARGET_64BIT" "") - + ; ; one_cmplsi2 instruction pattern(s). ; - + (define_expand "one_cmplsi2" [(parallel [(set (match_operand:SI 0 "register_operand" "") @@ -5419,11 +5737,11 @@ (clobber (reg:CC 33))])] "" "") - + ; ; one_cmplhi2 instruction pattern(s). ; - + (define_expand "one_cmplhi2" [(parallel [(set (match_operand:HI 0 "register_operand" "") @@ -5432,11 +5750,11 @@ (clobber (reg:CC 33))])] "" "") - + ; ; one_cmplqi2 instruction pattern(s). ; - + (define_expand "one_cmplqi2" [(parallel [(set (match_operand:QI 0 "register_operand" "") @@ -5461,8 +5779,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ - rllg\\t%0,%1,%c2 - rllg\\t%0,%1,0(%2)" + rllg\t%0,%1,%c2 + rllg\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5474,10 +5792,10 @@ [(set (match_operand:SI 0 "register_operand" "=d,d") (rotate:SI (match_operand:SI 1 "register_operand" "d,d") (match_operand:SI 2 "nonmemory_operand" "J,a")))] - "TARGET_64BIT" + "TARGET_CPU_ZARCH" "@ - rll\\t%0,%1,%c2 - rll\\t%0,%1,0(%2)" + rll\t%0,%1,%c2 + rll\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5503,8 +5821,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "!TARGET_64BIT" "@ - sldl\\t%0,%c2 - sldl\\t%0,0(%2)" + sldl\t%0,%c2 + sldl\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5514,8 +5832,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ - sllg\\t%0,%1,%2 - sllg\\t%0,%1,0(%2)" + sllg\t%0,%1,%2 + sllg\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5541,8 +5859,8 @@ (ashiftrt:DI (match_dup 1) (match_dup 2)))] "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "@ - srda\\t%0,%c2 - srda\\t%0,0(%2)" + srda\t%0,%c2 + srda\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5554,8 +5872,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" "@ - srda\\t%0,%c2 - srda\\t%0,0(%2)" + srda\t%0,%c2 + srda\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5566,11 +5884,11 @@ (clobber (reg:CC 33))] "!TARGET_64BIT" "@ - srda\\t%0,%c2 - srda\\t%0,0(%2)" + srda\t%0,%c2 + srda\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) - + (define_insn "*ashrdi3_cc_64" [(set (reg 33) (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") @@ -5580,8 +5898,8 @@ (ashiftrt:DI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "@ - srag\\t%0,%1,%c2 - srag\\t%0,%1,0(%2)" + srag\t%0,%1,%c2 + srag\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5593,8 +5911,8 @@ (clobber (match_scratch:DI 0 "=d,d"))] "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "@ - srag\\t%0,%1,%c2 - srag\\t%0,%1,0(%2)" + srag\t%0,%1,%c2 + srag\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5605,8 +5923,8 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "@ - srag\\t%0,%1,%c2 - srag\\t%0,%1,0(%2)" + srag\t%0,%1,%c2 + srag\t%0,%1,0(%2)" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -5621,8 +5939,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "" "@ - sll\\t%0,%c2 - sll\\t%0,0(%2)" + sll\t%0,%c2 + sll\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5639,8 +5957,8 @@ (ashiftrt:SI (match_dup 1) (match_dup 2)))] "s390_match_ccmode(insn, CCSmode)" "@ - sra\\t%0,%c2 - sra\\t%0,0(%2)" + sra\t%0,%c2 + sra\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5653,8 +5971,8 @@ (clobber (match_scratch:SI 0 "=d,d"))] "s390_match_ccmode(insn, CCSmode)" "@ - sra\\t%0,%c2 - sra\\t%0,0(%2)" + sra\t%0,%c2 + sra\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5665,8 +5983,8 @@ (clobber (reg:CC 33))] "" "@ - sra\\t%0,%c2 - sra\\t%0,0(%2)" + sra\t%0,%c2 + sra\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5692,8 +6010,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "!TARGET_64BIT" "@ - srdl\\t%0,%c2 - srdl\\t%0,0(%2)" + srdl\t%0,%c2 + srdl\t%0,0(%2)" [(set_attr "op_type" "RS,RS") (set_attr "atype" "reg")]) @@ -5703,8 +6021,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "TARGET_64BIT" "@ - srlg\\t%0,%1,%c2 - srlg\\t%0,%1,0(%2)" + srlg\t%0,%1,%c2 + srlg\t%0,%1,0(%2)" [(set_attr "op_type" "RSE,RSE") (set_attr "atype" "reg")]) @@ -5718,8 +6036,8 @@ (match_operand:SI 2 "nonmemory_operand" "J,a")))] "" "@ - srl\\t%0,%c2 - srl\\t%0,0(%2)" + srl\t%0,%c2 + srl\t%0,0(%2)" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -5735,7 +6053,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bne" [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) @@ -5744,7 +6062,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bgt" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5753,7 +6071,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bgtu" [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) @@ -5762,7 +6080,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "blt" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5771,7 +6089,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bltu" [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) @@ -5780,7 +6098,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bge" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5789,7 +6107,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bgeu" [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) @@ -5798,7 +6116,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "ble" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5807,7 +6125,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bleu" [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) @@ -5816,7 +6134,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bunordered" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5825,7 +6143,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bordered" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5834,7 +6152,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "buneq" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5843,7 +6161,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bungt" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5852,7 +6170,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bunlt" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5861,7 +6179,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bunge" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5870,7 +6188,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bunle" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5879,7 +6197,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") (define_expand "bltgt" [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) @@ -5888,7 +6206,7 @@ (label_ref (match_operand 0 "" "")) (pc)))] "" - "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") + "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") ;; @@ -5897,26 +6215,25 @@ (define_insn "cjump" [(set (pc) - (if_then_else + (if_then_else (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "" - "* { if (get_attr_length (insn) == 4) - return \"j%C1\\t%l0\"; - else if (TARGET_64BIT) - return \"jg%C1\\t%l0\"; + return "j%C1\t%l0"; + else if (TARGET_CPU_ZARCH) + return "jg%C1\t%l0"; else abort (); -}" +} [(set_attr "op_type" "RI") (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -5928,14 +6245,13 @@ (match_operand 0 "address_operand" "U") (pc)))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RR) - return \"b%C1r\\t%0\"; + return "b%C1r\t%0"; else - return \"b%C1\\t%a0\"; -}" - [(set (attr "op_type") + return "b%C1\t%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") @@ -5950,24 +6266,23 @@ [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) - (pc) + (pc) (label_ref (match_operand 0 "" ""))))] "" - "* -{ +{ if (get_attr_length (insn) == 4) - return \"j%D1\\t%l0\"; - else if (TARGET_64BIT) - return \"jg%D1\\t%l0\"; + return "j%D1\t%l0"; + else if (TARGET_CPU_ZARCH) + return "jg%D1\t%l0"; else abort (); -}" +} [(set_attr "op_type" "RI") (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -5979,14 +6294,13 @@ (pc) (match_operand 0 "address_operand" "U")))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RR) - return \"b%D1r\\t%0\"; + return "b%D1r\t%0"; else - return \"b%D1\\t%a0\"; -}" - [(set (attr "op_type") + return "b%D1\t%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") @@ -5999,7 +6313,7 @@ (define_insn "trap" [(trap_if (const_int 1) (const_int 0))] "" - "j\\t.+2" + "j\t.+2" [(set_attr "op_type" "RX") (set_attr "type" "branch")]) @@ -6009,23 +6323,22 @@ [(match_dup 2) (const_int 0)]) (match_operand:SI 1 "general_operand" ""))] "" - " { enum machine_mode ccmode; - if (operands[1] != const0_rtx) FAIL; + if (operands[1] != const0_rtx) FAIL; - ccmode = s390_select_ccmode (GET_CODE (operands[0]), - s390_compare_op0, s390_compare_op1); + ccmode = s390_select_ccmode (GET_CODE (operands[0]), + s390_compare_op0, s390_compare_op1); operands[2] = gen_rtx_REG (ccmode, 33); operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); -}") +}) (define_insn "*trap" [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) (const_int 0))] "" - "j%C0\\t.+2"; + "j%C0\t.+2"; [(set_attr "op_type" "RI") (set_attr "type" "branch")]) @@ -6034,7 +6347,7 @@ ;; ;; This is all complicated by the fact that since this is a jump insn ;; we must handle our own output reloads. - + (define_expand "doloop_end" [(use (match_operand 0 "" "")) ; loop pseudo (use (match_operand 1 "" "")) ; iterations; zero if unknown @@ -6042,7 +6355,6 @@ (use (match_operand 3 "" "")) ; loop level (use (match_operand 4 "" ""))] ; label "" - " { if (GET_MODE (operands[0]) == SImode) emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); @@ -6052,7 +6364,7 @@ FAIL; DONE; -}") +}) (define_insn "doloop_si" [(set (pc) @@ -6066,21 +6378,20 @@ (clobber (match_scratch:SI 3 "=X,&d")) (clobber (reg:CC 33))] "" - "* { if (which_alternative != 0) - return \"#\"; + return "#"; else if (get_attr_length (insn) == 4) - return \"brct\\t%1,%l0\"; + return "brct\t%1,%l0"; else abort (); -}" +} [(set_attr "op_type" "RI") (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 10) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6097,14 +6408,13 @@ (clobber (match_scratch:SI 3 "=X,&d")) (clobber (reg:CC 33))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RR) - return \"bctr\\t%1,%0\"; + return "bctr\t%1,%0"; else - return \"bct\\t%1,%a0\"; -}" - [(set (attr "op_type") + return "bct\t%1,%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") @@ -6146,15 +6456,14 @@ (clobber (match_scratch:DI 3 "=X,&d")) (clobber (reg:CC 33))] "TARGET_64BIT" - "* { if (which_alternative != 0) - return \"#\"; + return "#"; else if (get_attr_length (insn) == 4) - return \"brctg\\t%1,%l0\"; + return "brctg\t%1,%l0"; else abort (); -}" +} [(set_attr "op_type" "RI") (set_attr "type" "branch") (set (attr "length") @@ -6173,14 +6482,13 @@ (clobber (match_scratch:DI 3 "=X,&d")) (clobber (reg:CC 33))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RRE) - return \"bctgr\\t%1,%0\"; + return "bctgr\t%1,%0"; else - return \"bctg\\t%1,%a0\"; -}" - [(set (attr "op_type") + return "bctg\t%1,%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RRE") (const_string "RXE"))) (set_attr "type" "branch") @@ -6221,21 +6529,20 @@ (define_insn "jump" [(set (pc) (label_ref (match_operand 0 "" "")))] "" - "* { if (get_attr_length (insn) == 4) - return \"j\\t%l0\"; - else if (TARGET_64BIT) - return \"jg\\t%l0\"; + return "j\t%l0"; + else if (TARGET_CPU_ZARCH) + return "jg\t%l0"; else abort (); -}" +} [(set_attr "op_type" "RI") (set_attr "type" "branch") (set (attr "length") (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) (const_int 4) - (ne (symbol_ref "TARGET_64BIT") (const_int 0)) + (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) (const_int 6) (eq (symbol_ref "flag_pic") (const_int 0)) (const_int 6)] (const_int 8)))]) @@ -6247,14 +6554,13 @@ (define_insn "indirect_jump" [(set (pc) (match_operand 0 "address_operand" "U"))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RR) - return \"br\\t%0\"; + return "br\t%0"; else - return \"b\\t%a0\"; -}" - [(set (attr "op_type") + return "b\t%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") @@ -6268,14 +6574,13 @@ [(set (pc) (match_operand 0 "address_operand" "U")) (use (label_ref (match_operand 1 "" "")))] "" - "* { if (get_attr_op_type (insn) == OP_TYPE_RR) - return \"br\\t%0\"; + return "br\t%0"; else - return \"b\\t%a0\"; -}" - [(set (attr "op_type") + return "b\t%a0"; +} + [(set (attr "op_type") (if_then_else (match_operand 0 "register_operand" "") (const_string "RR") (const_string "RX"))) (set_attr "type" "branch") @@ -6288,7 +6593,6 @@ (label_ref (match_operand 3 "" "")) (label_ref (match_operand 4 "" ""))] "" - " { rtx index = gen_reg_rtx (SImode); rtx base = gen_reg_rtx (Pmode); @@ -6319,7 +6623,7 @@ emit_jump_insn (gen_casesi_jump (target, operands[3])); DONE; -}") +}) ;; @@ -6338,7 +6642,6 @@ (match_operand 1 "" "") (match_operand 2 "" "")])] "" - " { int i; @@ -6357,13 +6660,13 @@ emit_insn (gen_blockage ()); DONE; -}") +}) ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. (define_insn "blockage" - [(unspec_volatile [(const_int 0)] 0)] + [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] "" "" [(set_attr "type" "none") @@ -6380,9 +6683,8 @@ (match_operand 1 "" "")) (use (match_operand 2 "" ""))] "" - " { - int plt_call = 0; + bool plt_call = false; rtx insn; /* Direct function calls need special treatment. */ @@ -6394,20 +6696,20 @@ replace the symbol itself with the PLT stub. */ if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) { - sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); + sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_CONST (Pmode, sym); - - plt_call = 1; + plt_call = true; } - /* Unless we can use the bras(l) insn, force the + /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) - { - rtx target = gen_reg_rtx (Pmode); - emit_move_insn (target, sym); - sym = target; - } + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) + { + if (flag_pic) + sym = legitimize_pic_address (sym, 0); + else + sym = force_reg (Pmode, sym); + } operands[0] = gen_rtx_MEM (QImode, sym); } @@ -6416,14 +6718,12 @@ insn = emit_call_insn (gen_call_exp (operands[0], operands[1], gen_rtx_REG (Pmode, RETURN_REGNUM))); - /* In 31-bit, we must load the GOT register even if the - compiler doesn't know about it, because the PLT glue - code uses it. In 64-bit, this is not necessary. */ - if (plt_call && !TARGET_64BIT) + /* 31-bit PLT stubs use the GOT register implicitly. */ + if (!TARGET_64BIT && plt_call) use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); - + DONE; -}") +}) (define_expand "call_exp" [(parallel [(call (match_operand 0 "" "") @@ -6432,62 +6732,40 @@ "" "") -(define_insn "brasl" - [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "brasl\\t%2,%0" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras" - [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "TARGET_SMALL_EXEC" - "bras\\t%2,%0" +(define_insn "*bras" + [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode" + "bras\t%2,%0" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_64" - [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "basr\\t%2,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "basr_31" - [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "!TARGET_64BIT" - "basr\\t%2,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_64" - [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:DI 2 "register_operand" "=r"))] - "TARGET_64BIT" - "bas\\t%2,%a0" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr")]) - -(define_insn "bas_31" - [(call (mem:QI (match_operand:QI 0 "address_operand" "U")) - (match_operand:SI 1 "const_int_operand" "n")) - (clobber (match_operand:SI 2 "register_operand" "=r"))] - "!TARGET_64BIT" - "bas\\t%2,%a0" - [(set_attr "op_type" "RX") +(define_insn "*brasl" + [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode" + "brasl\t%2,%0" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) +(define_insn "*basr" + [(call (mem:QI (match_operand 0 "address_operand" "U")) + (match_operand 1 "const_int_operand" "n")) + (clobber (match_operand 2 "register_operand" "=r"))] + "GET_MODE (operands[2]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%2,%0"; + else + return "bas\t%2,%a0"; +} + [(set (attr "op_type") + (if_then_else (match_operand 0 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ; ; call_value instruction pattern(s). @@ -6499,9 +6777,8 @@ (match_operand 2 "" ""))) (use (match_operand 3 "" ""))] "" - " { - int plt_call = 0; + bool plt_call = false; rtx insn; /* Direct function calls need special treatment. */ @@ -6513,19 +6790,19 @@ replace the symbol itself with the PLT stub. */ if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) { - sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); + sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_CONST (Pmode, sym); - - plt_call = 1; + plt_call = true; } - /* Unless we can use the bras(l) insn, force the + /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) { - rtx target = gen_reg_rtx (Pmode); - emit_move_insn (target, sym); - sym = target; + if (flag_pic) + sym = legitimize_pic_address (sym, 0); + else + sym = force_reg (Pmode, sym); } operands[1] = gen_rtx_MEM (QImode, sym); @@ -6536,14 +6813,12 @@ gen_call_value_exp (operands[0], operands[1], operands[2], gen_rtx_REG (Pmode, RETURN_REGNUM))); - /* In 31-bit, we must load the GOT register even if the - compiler doesn't know about it, because the PLT glue - code uses it. In 64-bit, this is not necessary. */ - if (plt_call && !TARGET_64BIT) + /* 31-bit PLT stubs use the GOT register implicitly. */ + if (!TARGET_64BIT && plt_call) use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); - + DONE; -}") +}) (define_expand "call_value_exp" [(parallel [(set (match_operand 0 "" "") @@ -6553,68 +6828,43 @@ "" "") -(define_insn "brasl_r" +(define_insn "*bras_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "brasl\\t%3,%1" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras_r" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "TARGET_SMALL_EXEC" - "bras\\t%3,%1" + (clobber (match_operand 3 "register_operand" "=r"))] + "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" + "bras\t%3,%1" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_r_64" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "basr\\t%3,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "basr_r_31" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "!TARGET_64BIT" - "basr\\t%3,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_r_64" +(define_insn "*brasl_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r"))] - "TARGET_64BIT" - "bas\\t%3,%a1" - [(set_attr "op_type" "RX") + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r"))] + "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" + "brasl\t%3,%1" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) -(define_insn "bas_r_31" +(define_insn "*basr_r" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r"))] - "!TARGET_64BIT" - "bas\\t%3,%a1" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr")]) - + (call (mem:QI (match_operand 1 "address_operand" "U")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r"))] + "GET_MODE (operands[3]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%3,%1"; + else + return "bas\t%3,%a1"; +} + [(set (attr "op_type") + (if_then_else (match_operand 1 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ;; ;;- Thread-local storage support. @@ -6625,8 +6875,8 @@ (unspec:DI [(const_int 0)] UNSPEC_TP))] "TARGET_64BIT" "@ - ear\\t%0,%%a0\;sllg\\t%0,%0,32\;ear\\t%0,%%a1 - stam\\t%%a0,%%a1,%0" + ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 + stam\t%%a0,%%a1,%0" [(set_attr "op_type" "NN,RS") (set_attr "atype" "reg,*") (set_attr "type" "o3,*") @@ -6637,8 +6887,8 @@ (unspec:SI [(const_int 0)] UNSPEC_TP))] "!TARGET_64BIT" "@ - ear\\t%0,%%a0 - stam\\t%%a0,%%a0,%0" + ear\t%0,%%a0 + stam\t%%a0,%%a0,%0" [(set_attr "op_type" "RRE,RS")]) (define_insn "set_tp_64" @@ -6646,8 +6896,8 @@ (clobber (match_scratch:SI 1 "=d,X"))] "TARGET_64BIT" "@ - sar\\t%%a1,%0\;srlg\\t%1,%0,32\;sar\\t%%a0,%1 - lam\\t%%a0,%%a1,%0" + sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 + lam\t%%a0,%%a1,%0" [(set_attr "op_type" "NN,RS") (set_attr "atype" "reg,*") (set_attr "type" "o3,*") @@ -6657,17 +6907,17 @@ [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] "!TARGET_64BIT" "@ - sar\\t%%a0,%0 - lam\\t%%a0,%%a0,%0" + sar\t%%a0,%0 + lam\t%%a0,%%a0,%0" [(set_attr "op_type" "RRE,RS")]) - + (define_insn "*tls_load_64" [(set (match_operand:DI 0 "register_operand" "=d") (unspec:DI [(match_operand:DI 1 "memory_operand" "m") (match_operand:DI 2 "" "")] UNSPEC_TLS_LOAD))] "TARGET_64BIT" - "lg\\t%0,%1%J2" + "lg\t%0,%1%J2" [(set_attr "op_type" "RXE")]) (define_insn "*tls_load_31" @@ -6677,8 +6927,8 @@ UNSPEC_TLS_LOAD))] "!TARGET_64BIT" "@ - l\\t%0,%1%J2 - ly\\t%0,%1%J2" + l\t%0,%1%J2 + ly\t%0,%1%J2" [(set_attr "op_type" "RX,RXY")]) (define_expand "call_value_tls" @@ -6686,7 +6936,6 @@ (call (const_int 0) (const_int 0))) (use (match_operand 1 "" ""))] "" - " { rtx insn, sym; @@ -6694,16 +6943,17 @@ abort (); sym = s390_tls_get_offset (); - sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); + sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); sym = gen_rtx_CONST (Pmode, sym); - /* Unless we can use the bras(l) insn, force the + /* Unless we can use the bras(l) insn, force the routine address into a register. */ - if (!TARGET_SMALL_EXEC && !TARGET_64BIT) + if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) { - rtx target = gen_reg_rtx (Pmode); - emit_move_insn (target, sym); - sym = target; + if (flag_pic) + sym = legitimize_pic_address (sym, 0); + else + sym = force_reg (Pmode, sym); } sym = gen_rtx_MEM (QImode, sym); @@ -6721,7 +6971,7 @@ CONST_OR_PURE_CALL_P (insn) = 1; DONE; -}") +}) (define_expand "call_value_tls_exp" [(parallel [(set (match_operand 0 "" "") @@ -6732,74 +6982,46 @@ "" "") -(define_insn "brasl_tls" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "brasl\\t%3,%1%J4" - [(set_attr "op_type" "RIL") - (set_attr "type" "jsr")]) - -(define_insn "bras_tls" +(define_insn "*bras_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "TARGET_SMALL_EXEC" - "bras\\t%3,%1%J4" + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" + "bras\t%3,%1%J4" [(set_attr "op_type" "RI") (set_attr "type" "jsr")]) -(define_insn "basr_tls_64" +(define_insn "*brasl_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:DI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "basr\\t%3,%1%J4" - [(set_attr "op_type" "RR") + (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" + "brasl\t%3,%1%J4" + [(set_attr "op_type" "RIL") (set_attr "type" "jsr")]) -(define_insn "basr_tls_31" +(define_insn "*basr_tls" [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:SI 1 "register_operand" "a")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "!TARGET_64BIT" - "basr\\t%3,%1%J4" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_tls_64" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:DI 3 "register_operand" "=r")) - (use (match_operand:DI 4 "" ""))] - "TARGET_64BIT" - "bas\\t%3,%a1%J4" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) - -(define_insn "bas_tls_31" - [(set (match_operand 0 "register_operand" "=df") - (call (mem:QI (match_operand:QI 1 "address_operand" "U")) - (match_operand:SI 2 "const_int_operand" "n"))) - (clobber (match_operand:SI 3 "register_operand" "=r")) - (use (match_operand:SI 4 "" ""))] - "!TARGET_64BIT" - "bas\\t%3,%a1%J4" - [(set_attr "op_type" "RX") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) + (call (mem:QI (match_operand 1 "address_operand" "U")) + (match_operand 2 "const_int_operand" "n"))) + (clobber (match_operand 3 "register_operand" "=r")) + (use (match_operand 4 "" ""))] + "GET_MODE (operands[3]) == Pmode" +{ + if (get_attr_op_type (insn) == OP_TYPE_RR) + return "basr\t%3,%1%J4"; + else + return "bas\t%3,%a1%J4"; +} + [(set (attr "op_type") + (if_then_else (match_operand 1 "register_operand" "") + (const_string "RR") (const_string "RX"))) + (set_attr "type" "jsr") + (set_attr "atype" "agen")]) ;; ;;- Miscellaneous instructions. @@ -6815,12 +7037,11 @@ (set (match_operand 0 "general_operand" "") (reg 15))] "" - " { rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); rtx chain = gen_rtx (MEM, Pmode, stack); rtx temp = gen_reg_rtx (Pmode); - + emit_move_insn (temp, chain); if (TARGET_64BIT) @@ -6830,9 +7051,9 @@ emit_move_insn (chain, temp); - emit_move_insn (operands[0], virtual_stack_dynamic_rtx); + emit_move_insn (operands[0], virtual_stack_dynamic_rtx); DONE; -}") +}) ; @@ -6840,35 +7061,28 @@ ; (define_expand "builtin_setjmp_setup" - [(unspec [(match_operand 0 "register_operand" "a")] 1)] + [(match_operand 0 "register_operand" "")] "" - " { rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); emit_move_insn (base, basereg); DONE; -}") +}) (define_expand "builtin_setjmp_receiver" - [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)] + [(match_operand 0 "" "")] "flag_pic" - " { - rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); - rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); - SYMBOL_REF_FLAGS (got) = SYMBOL_FLAG_LOCAL; - - emit_move_insn (gotreg, got); - emit_insn (gen_rtx_USE (VOIDmode, gotreg)); + s390_load_got (false); + emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); DONE; -}") +}) (define_expand "builtin_longjmp" - [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] + [(match_operand 0 "register_operand" "")] "" - " { /* The elements of the buffer are, in order: */ rtx fp = gen_rtx_MEM (Pmode, operands[0]); @@ -6876,7 +7090,7 @@ rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode))); rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); - rtx jmp = gen_rtx_REG (Pmode, 14); + rtx jmp = gen_reg_rtx (Pmode); emit_move_insn (jmp, lab); emit_move_insn (basereg, base); @@ -6888,7 +7102,7 @@ emit_insn (gen_rtx_USE (VOIDmode, basereg)); emit_indirect_jump (jmp); DONE; -}") +}) ;; These patterns say how to save and restore the stack pointer. We need not @@ -6918,17 +7132,15 @@ (set (match_dup 0) (match_operand 1 "register_operand" "")) (set (match_dup 3) (match_dup 2))] "" - " { operands[2] = gen_reg_rtx (Pmode); operands[3] = gen_rtx_MEM (Pmode, operands[0]); -}") +}) (define_expand "save_stack_nonlocal" [(match_operand 0 "memory_operand" "") (match_operand 1 "register_operand" "")] "" - " { rtx temp = gen_reg_rtx (Pmode); @@ -6941,13 +7153,12 @@ TARGET_64BIT ? TImode : DImode), operands[1]); DONE; -}") +}) (define_expand "restore_stack_nonlocal" [(match_operand 0 "register_operand" "") (match_operand 1 "memory_operand" "")] "" - " { rtx temp = gen_reg_rtx (Pmode); @@ -6960,7 +7171,7 @@ TARGET_64BIT ? TImode : DImode)); emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); DONE; -}") +}) ; @@ -6970,7 +7181,7 @@ (define_insn "nop" [(const_int 0)] "" - "lr\\t0,0" + "lr\t0,0" [(set_attr "op_type" "RR")]) @@ -6978,144 +7189,97 @@ ; Special literal pool access instruction pattern(s). ; -(define_insn "consttable_qi" - [(unspec_volatile [(match_operand:QI 0 "consttable_operand" "X")] 200)] +(define_insn "*pool_entry" + [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] + UNSPECV_POOL_ENTRY)] "" - "* { - assemble_integer (operands[0], 1, BITS_PER_UNIT, 1); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "1")]) - -(define_insn "consttable_hi" - [(unspec_volatile [(match_operand:HI 0 "consttable_operand" "X")] 201)] - "" - "* -{ - assemble_integer (operands[0], 2, 2*BITS_PER_UNIT, 1); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "2")]) - -(define_insn "consttable_si" - [(unspec_volatile [(match_operand:SI 0 "consttable_operand" "X")] 202)] - "" - "* -{ - if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[0])) - return \".long\\t%0\"; - - assemble_integer (operands[0], 4, 4*BITS_PER_UNIT, 1); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "4")]) - -(define_insn "consttable_di" - [(unspec_volatile [(match_operand:DI 0 "consttable_operand" "X")] 203)] - "" - "* -{ - assemble_integer (operands[0], 8, 8*BITS_PER_UNIT, 1); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "8")]) - -(define_insn "consttable_sf" - [(unspec_volatile [(match_operand:SF 0 "consttable_operand" "X")] 204)] - "" - "* -{ - REAL_VALUE_TYPE r; - - if (GET_CODE (operands[0]) != CONST_DOUBLE) - abort (); - - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); - assemble_real (r, SFmode, 4*BITS_PER_UNIT); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "4")]) - -(define_insn "consttable_df" - [(unspec_volatile [(match_operand:DF 0 "consttable_operand" "X")] 205)] - "" - "* -{ - REAL_VALUE_TYPE r; - - if (GET_CODE (operands[0]) != CONST_DOUBLE) - abort (); - - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); - assemble_real (r, DFmode, 8*BITS_PER_UNIT); - return \"\"; -}" - [(set_attr "op_type" "NN") - (set_attr "length" "8")]) + enum machine_mode mode = GET_MODE (PATTERN (insn)); + unsigned int align = GET_MODE_BITSIZE (mode); + s390_output_pool_entry (asm_out_file, operands[0], mode, align); + return ""; +} + [(set_attr "op_type" "NN") + (set (attr "length") + (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) (define_insn "pool_start_31" - [(unspec_volatile [(const_int 0)] 206)] - "!TARGET_64BIT" - ".align\\t4" + [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] + "!TARGET_CPU_ZARCH" + ".align\t4" [(set_attr "op_type" "NN") (set_attr "length" "2")]) (define_insn "pool_end_31" - [(unspec_volatile [(const_int 0)] 207)] - "!TARGET_64BIT" - ".align\\t2" + [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] + "!TARGET_CPU_ZARCH" + ".align\t2" [(set_attr "op_type" "NN") (set_attr "length" "2")]) (define_insn "pool_start_64" - [(unspec_volatile [(const_int 0)] 206)] - "TARGET_64BIT" - ".section\\t.rodata\;.align\\t8" + [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] + "TARGET_CPU_ZARCH" + ".section\t.rodata\;.align\t8" [(set_attr "op_type" "NN") (set_attr "length" "0")]) (define_insn "pool_end_64" - [(unspec_volatile [(const_int 0)] 207)] - "TARGET_64BIT" + [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] + "TARGET_CPU_ZARCH" ".previous" [(set_attr "op_type" "NN") (set_attr "length" "0")]) +(define_insn "main_base_31_small" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" + "basr\t%0,0" + [(set_attr "op_type" "RR") + (set_attr "type" "la")]) + +(define_insn "main_base_31_large" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) + (set (pc) (label_ref (match_operand 2 "" "")))] + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" + "bras\t%0,%2" + [(set_attr "op_type" "RI")]) + +(define_insn "main_base_64" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] + "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" + "larl\t%0,%1" + [(set_attr "op_type" "RIL") + (set_attr "type" "larl")]) + +(define_insn "main_pool" + [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)] + "" + "* abort ();" + [(set_attr "op_type" "NN")]) + (define_insn "reload_base_31" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(label_ref (match_operand 1 "" ""))] 210))] - "!TARGET_64BIT" - "basr\\t%0,0\;la\\t%0,%1-.(%0)" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] + "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" + "basr\t%0,0\;la\t%0,%1-.(%0)" [(set_attr "op_type" "NN") (set_attr "type" "la") (set_attr "length" "6")]) (define_insn "reload_base_64" - [(set (match_operand:DI 0 "register_operand" "=a") - (unspec:DI [(label_ref (match_operand 1 "" ""))] 210))] - "TARGET_64BIT" - "larl\\t%0,%1" + [(set (match_operand 0 "register_operand" "=a") + (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] + "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" + "larl\t%0,%1" [(set_attr "op_type" "RIL") (set_attr "type" "larl")]) -(define_insn "reload_anchor" - [(set (match_operand:SI 0 "register_operand" "=a") - (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 211))] - "!TARGET_64BIT" - "l\\t%0,0(%1)\;la\\t%0,0(%0,%1)" - [(set_attr "op_type" "NN") - (set_attr "type" "la") - (set_attr "atype" "agen") - (set_attr "length" "8")]) - (define_insn "pool" - [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 220)] + [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] "" "* abort ();" [(set_attr "op_type" "NN") @@ -7129,78 +7293,33 @@ (define_expand "prologue" [(use (const_int 0))] "" - " -{ - s390_emit_prologue (); - DONE; -}") + "s390_emit_prologue (); DONE;") (define_expand "epilogue" [(use (const_int 1))] "" - " -{ - s390_emit_epilogue (); - DONE; -}") + "s390_emit_epilogue (); DONE;") - -(define_insn "*return_si" +(define_insn "*return" [(return) - (use (match_operand:SI 0 "register_operand" "a"))] - "!TARGET_64BIT" - "br\\t%0" + (use (match_operand 0 "register_operand" "a"))] + "GET_MODE (operands[0]) == Pmode" + "br\t%0" [(set_attr "op_type" "RR") - (set_attr "type" "jsr") + (set_attr "type" "jsr") (set_attr "atype" "agen")]) -(define_insn "*return_di" - [(return) - (use (match_operand:DI 0 "register_operand" "a"))] - "TARGET_64BIT" - "br\\t%0" - [(set_attr "op_type" "RR") - (set_attr "type" "jsr") - (set_attr "atype" "agen")]) -(define_insn "literal_pool_31" - [(unspec_volatile [(const_int 0)] 300) - (set (match_operand:SI 0 "register_operand" "=a") - (label_ref (match_operand 1 "" ""))) - (use (label_ref (match_operand 2 "" "")))] - "" -{ - if (s390_nr_constants) - { - output_asm_insn ("bras\\t%0,%2", operands); - s390_output_constant_pool (operands[1], operands[2]); - } - else if (flag_pic) - { - /* We need the anchor label in any case. */ - (*targetm.asm_out.internal_label) (asm_out_file, "L", - CODE_LABEL_NUMBER (operands[1])); - } - - return ""; -} - [(set_attr "op_type" "NN") - (set_attr "type" "larl")]) +;; Instruction definition to extend a 31-bit pointer into a 64-bit +;; pointer. This is used for compatability. -(define_insn "literal_pool_64" - [(unspec_volatile [(const_int 0)] 300) - (set (match_operand:DI 0 "register_operand" "=a") - (label_ref (match_operand 1 "" ""))) - (use (label_ref (match_operand 2 "" "")))] - "" +(define_expand "ptr_extend" + [(set (match_operand:DI 0 "register_operand" "=r") + (match_operand:SI 1 "register_operand" "r"))] + "TARGET_64BIT" { - if (s390_nr_constants) - { - output_asm_insn ("larl\\t%0,%1", operands); - s390_output_constant_pool (operands[1], operands[2]); - } - - return ""; -} - [(set_attr "op_type" "NN") - (set_attr "type" "larl")]) + emit_insn (gen_anddi3 (operands[0], + gen_lowpart (DImode, operands[1]), + GEN_INT (0x7fffffff))); + DONE; +}) |