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Diffstat (limited to 'gcc/config/sparc/ultra1_2.md')
-rw-r--r-- | gcc/config/sparc/ultra1_2.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/sparc/ultra1_2.md b/gcc/config/sparc/ultra1_2.md index 84cbb4b622b..2194be7ad78 100644 --- a/gcc/config/sparc/ultra1_2.md +++ b/gcc/config/sparc/ultra1_2.md @@ -206,7 +206,7 @@ "us1_fpm + us1_fp_double + us1_slotany, nothing*3") ;; This is actually in theory dangerous, because it is possible -;; for the chip to prematurely dispatch the dependant instruction +;; for the chip to prematurely dispatch the dependent instruction ;; in the G stage, resulting in a 9 cycle stall. However I have never ;; been able to trigger this case myself even with hand written code, ;; so it must require some rare complicated pipeline state. |