diff options
Diffstat (limited to 'gcc/doc/md.texi')
| -rw-r--r-- | gcc/doc/md.texi | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 1aa8552c5d4..4a0bcfa1bf1 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -4028,6 +4028,40 @@ will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk} where @var{msk} is computed by element-wise evaluation of the vector comparison with a truth value of all-ones and a false value of all-zeros. +@cindex @code{vec_perm@var{m}} instruction pattern +@item @samp{vec_perm@var{m}} +Output a (variable) vector permutation. Operand 0 is the destination +to receive elements from operand 1 and operand 2, which are of mode +@var{m}. Operand 3 is the @dfn{selector}. It is an integral mode +vector of the same width and number of elements as mode @var{m}. + +The input elements are numbered from 0 in operand 1 through +@math{2*@var{N}-1} in operand 2. The elements of the selector must +be computed modulo @math{2*@var{N}}. Note that if +@code{rtx_equal_p(operand1, operand2)}, this can be implemented +with just operand 1 and selector elements modulo @var{N}. + +In order to make things easy for a number of targets, if there is no +@samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q} +where @var{q} is a vector of @code{QImode} of the same width as @var{m}, +the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to +mode @var{q}. + +@cindex @code{vec_perm_const@var{m}} instruction pattern +@item @samp{vec_perm_const@var{m}} +Like @samp{vec_perm} except that the permutation is a compile-time +constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}. + +Some targets cannot perform a permutation with a variable selector, +but can efficiently perform a constant permutation. Further, the +target hook @code{vec_perm_ok} is queried to determine if the +specific constant permutation is available efficiently; the named +pattern is never expanded without @code{vec_perm_ok} returning true. + +There is no need for a target to supply both @samp{vec_perm@var{m}} +and @samp{vec_perm_const@var{m}} if the former can trivially implement +the operation with, say, the vector constant loaded into a register. + @cindex @code{push@var{m}1} instruction pattern @item @samp{push@var{m}1} Output a push instruction. Operand 0 is value to push. Used only when @@ -4238,6 +4272,17 @@ are vectors with N signed/unsigned elements of size S@. Multiply the high/low elements of the two vectors, and put the N/2 products of size 2*S in the output vector (operand 0). +@cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern +@cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern +@cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern +@cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern +@item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}} +@itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}} +Signed/Unsigned widening shift left. The first input (operand 1) is a vector +with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift +the high/low elements of operand 1, and put the N/2 results of size 2*S in the +output vector (operand 0). + @cindex @code{mulhisi3} instruction pattern @item @samp{mulhisi3} Multiply operands 1 and 2, which have mode @code{HImode}, and store |