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2019-04-02 PR target/89902uros
PR target/89903 * config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Return false for variable DImode shifts. (dimode_scalar_chain::compute_convert_gain): Do not handle register count operand in variable DImode shifts. (dimode_scalar_chain::make_vector_copies): Remove support to copy count argument of a variable shift instruction to a vector register. (dimode_scalar_chain::convert_reg): Remove support to convert count argument of a variable shift instruction. testsuite/ChangeLog: PR target/89902 PR target/89903 * gcc.target/i386/pr70799-4.c: Remove. * gcc.target/i386/pr70799-5.c: Remove. * gcc.target/i386/pr89902.c: New test. * gcc.target/i386/pr89903.c: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270102 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vector float-int conversion builtinskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: New builtin function type definitions. Remove unused types. * config/s390/s390-builtins.def (s390_vcdgb, s390_vcdlgb) (s390_vcgdb, s390_vclgdb): Remove low-level builtin definitions. (s390_vec_float, s390_vec_signed, s390_vec_unsigned): New overloaded builtins. (s390_vcefb, s390_vcdgb, s390_vcelfb, s390_vcdlgb, s390_vcfeb) (s390_vcgdb, s390_vclfeb, s390_vclgdb): New low-level builtins. * config/s390/vecintrin.h (vec_float): New builtin macro definition. (vec_double, vec_signed, vec_unsigned): Define to use the new overloaded builtins. * config/s390/vx-builtins.md ("vec_double_s64", "vec_double_u64"): Remove expanders. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/vec-double-compile.c: New test. * gcc.target/s390/zvector/vec-float-compile.c: New test. * gcc.target/s390/zvector/vec-signed-compile.c: New test. * gcc.target/s390/zvector/vec-unsigned-compile.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270091 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vector string search builtinskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: New builtin function type definitions. * config/s390/s390-builtins.def (s390_vec_search_string_cc) (s390_vec_search_string_until_zero_cc): New overloaded builtins. (s390_vstrsb, s390_vstrsh, s390_vstrsf, s390_vstrszb) (s390_vstrszh, s390_vstrszf): New low-level builtins. * config/s390/s390.md (UNSPEC_VEC_VSTRS, UNSPEC_VEC_VSTRSCC): New constant definitions. * config/s390/vecintrin.h (vec_search_string_cc) (vec_search_string_until_zero_cc): New builtin name definitions. * config/s390/vx-builtins.md ("vstrs<mode>", "vstrsz<mode>"): New expanders. ("vec_vstrs<mode>"): New insn definition. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/vec-search-string-cc-1.c: New test. * gcc.target/s390/zvector/vec-search-string-cc-compile.c: New test. * gcc.target/s390/zvector/vec-search-string-until-zero-cc-1.c: New test. * gcc.target/s390/zvector/vec-search-string-until-zero-cc-compile.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270090 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vector shift double by bit builtinskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: Add new builtin function types. * config/s390/s390-builtins.def (s390_vec_sldb, s390_vec_srdb): New overloaded builtins. (s390_vec_sldb, s390_vec_srdb): New low-level builtins. and s390_vsrd. * config/s390/s390.md (UNSPEC_VEC_SLDB): Rename to ... (UNSPEC_VEC_SLDBYTE): ... this. (UNSPEC_VEC_SLDBIT, UNSPEC_VEC_SRDBIT): New constant definitions. * config/s390/vecintrin.h (vec_sldb, vec_srdb): New builtin name definitions. * config/s390/vx-builtins.md ("vec_sld<mode>", "vec_sldw<mode>"): Rename UNSPEC_VEC_SLDB to UNSPEC_VEC_SLDBYTE. ("vec_sldb<mode>", "vec_srdb<mode>"): New insn definitions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/vec-shift-left-double-by-bit-1.c: New test. * gcc.target/s390/zvector/vec-shift-right-double-by-bit-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270089 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vector load byte reversed element and replicatekrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> ("*vec_splats_bswap_vec<mode>", "*vec_splats_bswap_elem<mode>"): New insn definition. * config/s390/vx-builtins.md (V_HW_HSD): Move to ... * config/s390/vector.md (V_HW_HSD): ... here. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/replicate-bswap-1.c: New test. * gcc.target/s390/zvector/replicate-bswap-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270088 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vector load/store byte reversed element for builtinskrebbel
2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/vecintrin.h: Map vec_vster low-level builtins to vec_vler. * config/s390/vx-builtins.md ("*vec_insert_and_zero_bswap<mode>") ("*vec_set_bswap_elem<mode>", "*vec_set_bswap_vec<mode>") ("*vec_extract_bswap_vec<mode>", "*vec_extract_bswap_elem<mode>"): New insn definitions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/bswap-and-replicate-1.c: New test. * gcc.target/s390/zvector/get-element-bswap-1.c: New test. * gcc.target/s390/zvector/get-element-bswap-2.c: New test. * gcc.target/s390/zvector/get-element-bswap-3.c: New test. * gcc.target/s390/zvector/get-element-bswap-4.c: New test. * gcc.target/s390/zvector/set-element-bswap-1.c: New test. * gcc.target/s390/zvector/set-element-bswap-2.c: New test. * gcc.target/s390/zvector/set-element-bswap-3.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270086 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vec_reve element order reversal builtinskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: Add new builtin function type. * config/s390/s390-builtins.def: Add overloaded builtin s390_vec_reve and low-level builtins for s390_vler and s390_vster. * config/s390/s390.md (UNSPEC_VEC_ELTSWAP): New constant definition. * config/s390/vecintrin.h (vec_reve): New builtin name definition. * config/s390/vx-builtins.md (V_HW_HSD): New mode iterator. ("eltswap<mode>"): New expander. ("*eltswapv16qi", "*eltswap<mode>", "*eltswap<mode>_emu"): New insn definitions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/vec-reve-load-byte-z14.c: New test. * gcc.target/s390/zvector/vec-reve-load-byte.c: New test. * gcc.target/s390/zvector/vec-reve-load-halfword-z14.c: New test. * gcc.target/s390/zvector/vec-reve-load-halfword.c: New test. * gcc.target/s390/zvector/vec-reve-store-byte-z14.c: New test. * gcc.target/s390/zvector/vec-reve-store-byte.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270085 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: vec_revb vector byte swap builtinkrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: Add new builtin function types. * config/s390/s390-builtins.def: Add overloaded builtin s390_vec_revb. Add low-level builtins for vlbr and vstbr instructions. * config/s390/vecintrin.h (vec_revb): New builtin name definition. * config/s390/vector.md (VT_HW_HSDT): New mode iterator. ("bswap<mode>"): New expander. ("*bswap<mode>", "*bswap<mode>_emu"): New insn definitions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/zvector/vec-revb-load-double-z14.c: New test. * gcc.target/s390/zvector/vec-revb-load-double.c: New test. * gcc.target/s390/zvector/vec-revb-store-double-z14.c: New test. * gcc.target/s390/zvector/vec-revb-store-double.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270084 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: New vector builtins - preparationkrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtins.def (B_VXE2): New builtin flag definition. * config/s390/s390-c.c (s390_cpu_cpp_builtins_internal): Increment vector builtin version number in __VEC__. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270083 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Support 32 bit fp-int scalar convertskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390.md (VX_CONV_BFP, VX_CONV_INT): New mode iterators. (SFSI): New mode attribute. ("*fixuns_truncdfdi2_vx", "*fix_truncdfdi2_bfp_z13") ("*floatunsdidf2_z13", ): Add support for 32 bit conversions and rename to ... ("*fixuns_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_z13") ("*fix_trunc<VX_CONV_BFP:mode><VX_CONV_INT:mode>2_bfp_z13") ("*floatuns<VX_CONV_INT:mode><VX_CONV_BFP:mode>2_z13"): ... these. ("floatsi<mode>2"): Add wcefb instruction. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270082 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Support 32 bit fp-int vector convertskrebbel
gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390.md ("xde"): Extend mode attribute to vector types. * config/s390/vector.md (VX_VEC_CONV_BFP, VX_VEC_CONV_INT): New mode iterators. ("floatv2div2df2", "floatunsv2div2df2", "fix_truncv2dfv2di2") ("fixuns_truncv2dfv2di2"): Enhance with mode iterator to also support 32 bit fp-int conversions. Rename to ... ("float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2") ("floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2") ("fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2") ("fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2"): ... to these. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/arch13/fp-signedint-convert-1.c: New test. * gcc.target/s390/arch13/fp-unsignedint-convert-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270081 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Add support for new select instructionkrebbel
Compared to the load on condition instructions we already have the new select instruction allows to have a THEN and and ELSE source operand - but only for register to register loads. gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390.c (s390_rtx_costs): Do not add extra costs for if-then-else constructs if we can use the select instruction. * config/s390/s390.md ("*mov<mode>cc"): Add the new instructions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/arch13/sel-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270080 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Support new popcount instructionkrebbel
variant. The new arch13 popcount instruction counts bits in the entire 64 bit register instead of just in 8 bit portions. gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390.md ("*popcountdi_arch13_cc") ("*popcountdi_arch13_cconly", "*popcountdi_arch13"): New insn definition. ("*popcount<mode>", "popcountdi2", "popcountsi2", "popcounthi2"): Append _z196 to make it ... ("*popcount<mode>_z196", "popcountdi2_z196", "popcountsi2_z196") ("popcounthi2_z196"): ... this. ("popcountdi2_z196"): Remove TARGET_64BIT from the insn condition. ("popcountdi2", "popcountsi2", "popcounthi2"): New expanders. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/arch13/popcount-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270079 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Support new bit operationskrebbel
Make use of the new bit operation instructions when generating code for the arch13 level. gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390.c (s390_canonicalize_comparison): Convert certain compares for arch13 in order to make use of the condition code result produced by the new instructions. (s390_rtx_costs): Adjust the costs for nnrk, nngrk, nork, nogrk, nxrk, and nxgrk instruction patterns. * config/s390/s390.md (ANDOR, bitops_name, inv_bitops_name) (inv_no): Add new code iterator together with some attributes. ("*andc_split_<mode>"): Disable splitter for arch13. ("*<ANDOR:bitops_name>c<GPR:mode>_cc") ("*<ANDOR:bitops_name>c<GPR:mode>_cconly") ("*<ANDOR:bitops_name>c<GPR:mode>") ("*n<ANDOR:inv_bitops_name><GPR:mode>_cc") ("*n<ANDOR:inv_bitops_name><mode>_cconly") ("*n<ANDOR:inv_bitops_name><mode>", "*nxor<GPR:mode>_cc") ("*nxor<mode>_cconly", "*nxor<mode>"): New insn definitions. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/arch13/bitops-1.c: New test. * gcc.target/s390/arch13/bitops-2.c: New test. * gcc.target/s390/md/andc-splitter-1.c: Add -march=z14 build option and adjust line numbers. * gcc.target/s390/md/andc-splitter-2.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270078 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02S/390: arch13: Add arch13 as architecture optionkrebbel
This patch enables the command line options and provides the proper macros for checking. gcc/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * common/config/s390/s390-common.c (processor_flags_table): New entry for arch13. * config.gcc: Support arch13 with the --with-arch= configure flag. * config/s390/driver-native.c (s390_host_detect_local_cpu): * config/s390/s390-opts.h (enum processor_type): Add PROCESSOR_ARCH13. * config/s390/s390.c (s390_get_sched_attrmask) (s390_get_unit_mask): Add PROCESSOR_ARCH13. * config/s390/s390.h (enum processor_flags): Add PF_VXE2 and PF_ARCH13. * config/s390/s390.md (TARGET_CPU_ARCH13, TARGET_CPU_ARCH13_P) (TARGET_CPU_VXE2, TARGET_CPU_VXE2_P, TARGET_ARCH13) (TARGET_ARCH13_P, TARGET_VXE2, TARGET_VXE2_P): New macro definitions. * config/s390/s390.opt: Support arch13 as processor type in command line options. gcc/testsuite/ChangeLog: 2019-04-02 Andreas Krebbel <krebbel@linux.ibm.com> * gcc.target/s390/s390.exp: Run tests in arch13 subdir. * lib/target-supports.exp (check_effective_target_s390_vxe2): New runtime check for the vxe2 hardware feature on IBM Z. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270077 138bc75d-0d04-0410-961f-82ee72b054a4
2019-04-02 * config/sparc/linux64.h (ASAN_REJECT_SPEC): New macro.ebotcazou
(ASAN_CC1_SPEC): Use it in 64-bit mode. * config/sparc/sol2.h (ASAN_REJECT_SPEC): Remove superfluous colon. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270075 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-28 PR target/89865uros
* config/i386/i386.md (RMW operation with LEA peephole): Use LEAMODE mode attribute instead of SWI mode iterator for LEA pattern. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270004 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-28 PR target/89848uros
* config/i386/i386.c (dimode_scalar_chain::make_vector_copies): Also process XEXP (src, 0) of a shift insn. testsuite/ChangeLog: PR target/89848 * gcc.target/i386/pr89848.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@270003 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-27 PR target/85667uros
* config/i386/i386.c (ix86_function_value_1): Call the newly added function for 32-bit MS_ABI. (function_value_ms_32): New function. testsuite/ChangeLog: PR target/85667 * gcc.target/i386/pr85667-5.c: New testcase. * gcc.target/i386/pr85667-6.c: New testcase. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269979 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-27Fix scc clobber in movdi_symbol.ams
2019-03-27 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn.md (CC_SAVE_REG): New constant. (movdi): Call gen_movdi_symbol_save_scc. (gen_movdi_symbol_save_scc): New insn and split. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269970 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-27[RS6000] Rename NON_SPECIAL_REGS to GEN_OR_FLOAT_REGSamodra
* config/rs6000/rs6000.h: Rename NON_SPECIAL_REGS to GEN_OR_FLOAT_REGS throughout file. * config/rs6000/darwin.h: Likewise. * config/rs6000/rs6000.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269960 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-27[RS6000] Don't rely on rs6000_hard_regno_mode_ok being zeroamodra
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Always assign rs6000_hard_regno_mode_ok_p[m][r]. Formatting. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269959 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-26RISC-V: Add sifive-7 pipeline description.wilson
* config/riscv/generic.md (generic_alu, generic_load, generic_store) (generic_xfer, generic_branch, generic_imul, generic_idivsi) (generic_idivdi, generic_fmul_single, generic_fmul_double) (generic_fdiv, generic_fsqrt): Add check for generic tune. (generic_alu): Add auipc to type list. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New. (riscv_microarchitecture): Declare. * config/riscv/riscv-protos.h (riscv_store_data_bypass_p): Declare. * config/riscv/riscv.c (struct riscv_cpu_info): Add microarchitecture field. (riscv_microarchitecture): New. (sifive_7_tune_info): New. (riscv_cpu_info_table): Add microarchitecture value for rocket and size. Add sifive-3-series, sifive-5-series, and sifive-7-series entries. (riscv_store_data_bypass_p): New. (riscv_option_override): Set riscv_microarchitecture from cpu->microarchitecture. * config/riscv/riscv.md: Include sifive-7.md. (type): Add auipc. (tune): New. (auipc<mode>): Change type to auipc. (restore_stack_nonlocal): New. * config/riscv/sifive-7.md: New. * doc/invoke.texi (RISC-V Options): Update mtune docs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269954 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-26 PR target/89827uros
* config/i386/i386.c (dimode_scalar_chain::convert_reg): Also process XEXP (src, 0) of a shift insn. testsuite/ChangeLog: PR target/89827 * gcc.target/i386/pr89827.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269953 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-26[RS6000] Fix typosamodra
* config/rs6000/rs6000.c (rs6000_init_hard_regno_mode_ok): Correct rs6000_vector_mem init. Correct wI and wJ comment git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269932 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-25S/390: Cleanup builtin types filekrebbel
gcc/ChangeLog: 2019-03-25 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-builtin-types.def: Remove few unused types and fix sort order for others. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269909 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-25S/390: Improve debug output for builtin matchingkrebbel
gcc/ChangeLog: 2019-03-25 Andreas Krebbel <krebbel@linux.ibm.com> * config/s390/s390-c.c (s390_fn_types_compatible): Print the expected and found types with -mdebug during builtin matching. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269908 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-24rs6000: Make CSE'ing __tls_get_addr calls possiblesegher
CSE does not consider calls, not even const calls. This patch puts a REG_EQUAL note on the pseudo we assign the __tls_get_addr result to, so that those pseudos can be CSE'd and the extra calls deleted as dead code. CSE should really handle const calls directly, but it is stage 4. * config/rs6000/rs6000.c (rs6000_legitimize_tls_address): Add REG_EQUAL notes for the result of the __tls_get_addr calls. * config/rs6000/rs6000.md (unspec UNSPEC_TLS_GET_ADDR): New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269902 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-24 * config/bfin/bfin.md (movpdi): Fix length for alternative 1.law
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269899 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-23rs6000: Fix _mm_movemask_pi8 emulation for 32 bitsegher
* config/rs6000/xmmintrin.h (_mm_movemask_pi8): Implement for 32-bit big endian. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269891 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-23[AARCH64] Fix zero_extendsidi2_aarch64 type attributepinskia
2019-03-22 Andrew Pinski <apinski@marvell.com> * config/aarch64/aarch64.md (zero_extendsidi2_aarch64): Fix type attrribute for uxtw. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269886 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-22 PR rtl-optimization/87761law
* config/mips/mips-protos.h (mips_split_move): Add new argument. (mips_emit_move_or_split): Pass NULL for INSN into mips_split_move. (mips_split_move): Accept new INSN argument. Try to forward SRC into the next instruction. (mips_split_move_insn): Pass INSN through to mips_split_move. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269880 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-22[gcc]wschmidt
2019-03-22 Bill Schmidt <wschmidt@linux.ibm.com> * config/rs6000/mmintrin.h (_mm_sub_pi32): Fix typo. [gcc/testsuite] 2019-03-22 Bill Schmidt <wschmidt@linux.ibm.com> * gcc.target/powerpc/mmx-psubd-2.c: Test _m_psubd. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269871 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-22 * config/i386/sse.md (<avx512>_fmadd_<mode>_mask3<round_name>,jakub
<avx512>_fmsub_<mode>_mask3<round_name>, <avx512>_fnmadd_<mode>_mask3<round_name>, <avx512>_fnmsub_<mode>_mask3<round_name>, avx512f_vmfmadd_<mode>_mask3<round_name>, avx512f_vmfmsub_<mode>_mask3<round_name>, *avx512f_vmfnmadd_<mode>_mask3<round_name>): Use <round_nimm_predicate> instead of register_operand and %v instead of v for match_operand 1. (avx512f_vmfnmsub_<mode>_mask3<round_name>): Rename to ... (*avx512f_vmfnmsub_<mode>_mask3<round_name>): ... this. Use <round_nimm_predicate> instead of register_operand and %v instead of v for match_operand 1. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269870 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-22 * config/i386/sse.md (<avx512>_fmadd_<mode>_mask<round_name>,jakub
<avx512>_fmadd_<mode>_mask3<round_name>, <avx512>_fmsub_<mode>_mask<round_name>, <avx512>_fmsub_<mode>_mask3<round_name>, <avx512>_fnmadd_<mode>_mask<round_name>, <avx512>_fnmadd_<mode>_mask3<round_name>, <avx512>_fnmsub_<mode>_mask<round_name>, <avx512>_fnmsub_<mode>_mask3<round_name>, <avx512>_fmaddsub_<mode>_mask<round_name>, <avx512>_fmaddsub_<mode>_mask3<round_name>, <avx512>_fmsubadd_<mode>_mask<round_name>, <avx512>_fmsubadd_<mode>_mask3<round_name>): Use <round_nimm_predicate> instead of nonimmediate_operand. (fmai_vmfmadd_<mode><round_name>, fmai_vmfmsub_<mode><round_name>, fmai_vmfnmadd_<mode><round_name>, fmai_vmfnmsub_<mode><round_name>): Use register_operand instead of <round_nimm_predicate> for the operand that needs to match output. (*fmai_fmadd_<mode>, *fmai_fmsub_<mode>, *fmai_fnmadd_<mode><round_name>, *fmai_fnmsub_<mode><round_name>): Likewise. Formatting fixes. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269869 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-22 PR target/89784jakub
* config/i386/i386.c (enum ix86_builtins): Remove IX86_BUILTIN_VFMSUBSD3_MASK3 and IX86_BUILTIN_VFMSUBSS3_MASK3. * config/i386/i386-builtin.def (__builtin_ia32_vfmaddsd3_mask, __builtin_ia32_vfmaddsd3_mask3, __builtin_ia32_vfmaddsd3_maskz, __builtin_ia32_vfmsubsd3_mask3, __builtin_ia32_vfmaddss3_mask, __builtin_ia32_vfmaddss3_mask3, __builtin_ia32_vfmaddss3_maskz, __builtin_ia32_vfmsubss3_mask3): New builtins. * config/i386/sse.md (avx512f_vmfmadd_<mode>_mask<round_name>, avx512f_vmfmadd_<mode>_mask3<round_name>, avx512f_vmfmadd_<mode>_maskz_1<round_name>, *avx512f_vmfmsub_<mode>_mask<round_name>, avx512f_vmfmsub_<mode>_mask3<round_name>, *avx512f_vmfmasub_<mode>_maskz_1<round_name>, *avx512f_vmfnmadd_<mode>_mask<round_name>, *avx512f_vmfnmadd_<mode>_mask3<round_name>, *avx512f_vmfnmadd_<mode>_maskz_1<round_name>, *avx512f_vmfnmsub_<mode>_mask<round_name>, *avx512f_vmfnmsub_<mode>_mask3<round_name>, *avx512f_vmfnmasub_<mode>_maskz_1<round_name>): New define_insns. (avx512f_vmfmadd_<mode>_maskz<round_expand_name>): New define_expand. * config/i386/avx512fintrin.h (_mm_mask_fmadd_sd, _mm_mask_fmadd_ss, _mm_mask3_fmadd_sd, _mm_mask3_fmadd_ss, _mm_maskz_fmadd_sd, _mm_maskz_fmadd_ss, _mm_mask_fmsub_sd, _mm_mask_fmsub_ss, _mm_mask3_fmsub_sd, _mm_mask3_fmsub_ss, _mm_maskz_fmsub_sd, _mm_maskz_fmsub_ss, _mm_mask_fnmadd_sd, _mm_mask_fnmadd_ss, _mm_mask3_fnmadd_sd, _mm_mask3_fnmadd_ss, _mm_maskz_fnmadd_sd, _mm_maskz_fnmadd_ss, _mm_mask_fnmsub_sd, _mm_mask_fnmsub_ss, _mm_mask3_fnmsub_sd, _mm_mask3_fnmsub_ss, _mm_maskz_fnmsub_sd, _mm_maskz_fnmsub_ss, _mm_mask_fmadd_round_sd, _mm_mask_fmadd_round_ss, _mm_mask3_fmadd_round_sd, _mm_mask3_fmadd_round_ss, _mm_maskz_fmadd_round_sd, _mm_maskz_fmadd_round_ss, _mm_mask_fmsub_round_sd, _mm_mask_fmsub_round_ss, _mm_mask3_fmsub_round_sd, _mm_mask3_fmsub_round_ss, _mm_maskz_fmsub_round_sd, _mm_maskz_fmsub_round_ss, _mm_mask_fnmadd_round_sd, _mm_mask_fnmadd_round_ss, _mm_mask3_fnmadd_round_sd, _mm_mask3_fnmadd_round_ss, _mm_maskz_fnmadd_round_sd, _mm_maskz_fnmadd_round_ss, _mm_mask_fnmsub_round_sd, _mm_mask_fnmsub_round_ss, _mm_mask3_fnmsub_round_sd, _mm_mask3_fnmsub_round_ss, _mm_maskz_fnmsub_round_sd, _mm_maskz_fnmsub_round_ss): New intrinsics. * gcc.target/i386/sse-13.c (__builtin_ia32_vfmaddsd3_mask, __builtin_ia32_vfmaddsd3_mask3, __builtin_ia32_vfmaddsd3_maskz, __builtin_ia32_vfmsubsd3_mask3, __builtin_ia32_vfmaddss3_mask, __builtin_ia32_vfmaddss3_mask3, __builtin_ia32_vfmaddss3_maskz, __builtin_ia32_vfmsubss3_mask3): Define. * gcc.target/i386/sse-23.c (__builtin_ia32_vfmaddsd3_mask, __builtin_ia32_vfmaddsd3_mask3, __builtin_ia32_vfmaddsd3_maskz, __builtin_ia32_vfmsubsd3_mask3, __builtin_ia32_vfmaddss3_mask, __builtin_ia32_vfmaddss3_mask3, __builtin_ia32_vfmaddss3_maskz, __builtin_ia32_vfmsubss3_mask3): Define. * gcc.target/i386/avx-1.c (__builtin_ia32_vfmaddsd3_mask, __builtin_ia32_vfmaddsd3_mask3, __builtin_ia32_vfmaddsd3_maskz, __builtin_ia32_vfmsubsd3_mask3, __builtin_ia32_vfmaddss3_mask, __builtin_ia32_vfmaddss3_mask3, __builtin_ia32_vfmaddss3_maskz, __builtin_ia32_vfmsubss3_mask3): Define. * gcc.target/i386/sse-14.c: Add tests for _mm_mask{,3,z}_f{,n}m{add,sub}_round_s{s,d} builtins. * gcc.target/i386/sse-22.c: Likewise. 2019-03-22 Hongtao Liu <hongtao.liu@intel.com> * gcc.target/i386/avx512f-vfmaddXXXsd-1.c (avx512f_test): Add tests for _mm_mask{,3,z}_*. * gcc.target/i386/avx512f-vfmaddXXXss-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfmsubXXXsd-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfmsubXXXss-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfnmaddXXXsd-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfnmaddXXXss-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfnmsubXXXsd-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfnmsubXXXss-1.c (avx512f_test): Likewise. * gcc.target/i386/avx512f-vfmaddXXXsd-2.c: New test. * gcc.target/i386/avx512f-vfmaddXXXss-2.c: New test. * gcc.target/i386/avx512f-vfmsubXXXsd-2.c: New test. * gcc.target/i386/avx512f-vfmsubXXXss-2.c: New test. * gcc.target/i386/avx512f-vfnmaddXXXsd-2.c: New test. * gcc.target/i386/avx512f-vfnmaddXXXss-2.c: New test. * gcc.target/i386/avx512f-vfnmsubXXXsd-2.c: New test. * gcc.target/i386/avx512f-vfnmsubXXXss-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269868 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-20S/390: Fix PR89775. Stackpointer save/restore instructions removedkrebbel
Even if a global register is being clobbered in a function we usually do not save and restore it. However, we still have to do this if it is a special register. Most of the places in the backend handle this correctly but not the prologue/epilogue optimization. gcc/ChangeLog: 2019-03-20 Andreas Krebbel <krebbel@linux.ibm.com> PR target/89775 * config/s390/s390.c (global_not_special_regno_p): Move to make it available to ... (s390_optimize_register_info): Use global_not_special_regno_p to check for global regs. 2019-03-20 Jakub Jelinek <jakub@redhat.com> PR target/89775 * gcc.target/s390/pr89775-1.c: New test. * gcc.target/s390/pr89775-2.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269823 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-19RISC-V: Fix %lo overflow with BLKmode references.wilson
gcc/ PR target/89411 * config/riscv/riscv.c (riscv_valid_lo_sum_p): New arg x. New locals align, size, offset. Use them to handle a BLKmode reference. Update comment. (riscv_classify_address): Pass info->offset to riscv_valid_lo_sum_p. gcc/testsuite/ PR target/89411 * gcc.target/riscv/losum-overflow.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269813 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-19rs6000: Unaligned stfiwx on older CPUs (PR89746)segher
The "classic" PowerPCs (6xx/7xx) are not STRICT_ALIGNMENT, but their floating point units are. This is not normally a problem, the ABIs make everything FP aligned. The RTL patterns converting FP to integer however get a potentially unaligned destination, and we do not want to do an stfiwx on that on such older CPUs. This fixes it. It does not change anything for TARGET_MFCRF targets (POWER4 and later). It also won't change anything for strict-alignment targets, or CPUs without hardware FP of course, or CPUs that do not implement stfiwx (older 4xx/5xx/8xx). It does not change the corresponding fixuns* pattern, because that can not be enabled on any CPU that cannot handle unaligned FP well. PR target/89746 * config/rs6000/rs6000.md (fix_trunc<mode>si2_stfiwx): If we have a non-TARGET_MFCRF target, and the dest is memory but not 32-bit aligned, go via a stack temporary. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269802 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-19 PR target/89378jakub
* config/mips/mips.c (mips_expand_vec_cond_expr): Use gen_lowpart instead of gen_rtx_SUBREG. * config/mips/mips-msa.md (vec_extract<mode><unitmode>): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269801 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-19 PR target/89506jakub
* config/arm/arm.md (cmpsi2_addneg): Swap the alternatives and use subs for the first alternative except when operands[3] is 1. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269795 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-19 PR target/89726jakub
* config/i386/i386.c (ix86_expand_floorceildf_32): In ceil compensation use x2 += 1 instead of x2 -= -1 and when honoring signed zeros, do another copysign after the compensation. * gcc.target/i386/fpprec-1.c (x): Add 6 new constants. (expect_round, expect_rint, expect_floor, expect_ceil, expect_trunc): Add expected results for them. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269790 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18Implement circular print buffer.ams
2019-03-18 Andrew Stubbs <ams@codesourcery.com> gcc/ * config/gcn/gcn-run.c (struct output): Make next_output unsigned. Extend queue to 1024 entries. Add "consumed" field. (gomp_print_output): Remove print_index parameter. Add final parameter. Change limit to unsigned. Use consumed field to implement circular buffer. Detect interrupted print in final pass. Flush output at the end. (run): Update gomp_print_output usage. (main): Initialize kernargs->output_data.consumed. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269764 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18gcc/riscv: Correctly ignore empty C++ structs when flattening for ABIaburgess
This fixes PR target/89627. The RISC-V ABI document[1] says: For the purposes of this section, "struct" refers to a C struct with its hierarchy flattened, including any array fields. That is, struct { struct { float f[1]; } g[2]; } and struct { float f; float g; } are treated the same. Fields containing empty structs or unions are ignored while flattening, even in C++, unless they have nontrivial copy constructors or destructors. However, this flattening only applies when one of the fields of the flattened structure can be placed into a floating point register, otherwise no flattening occurs. Currently GCC fails to correctly consider that empty C++ structures have a non-zero size when constructing the arguments from a flattened structure, and as a result, trying to pass a C++ structure like this: struct sf { struct {} e; float f; }; Doesn't work correctly, GCC fails to take the offset of 'f' within 'sf' into account and will actually pass the space backing 'e' as the contents of 'f'. This patch fixes this so that 'f' will be passed correctly. A couple of new tests are added to cover this functionality. [1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md gcc/ChangeLog: PR target/89627 * config/riscv/riscv.c (riscv_pass_fpr_single): Add offset parameter, and make use of it. (riscv_get_arg_info): Pass offset to riscv_pass_fpr_single. gcc/testsuite/ChangeLog: PR target/89627 * g++.target/riscv/call-with-empty-struct-float.C: New file. * g++.target/riscv/call-with-empty-struct-int.C: New file. * g++.target/riscv/call-with-empty-struct.H: New file. * g++.target/riscv/riscv.exp: New file. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269760 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18[ARC] Enable code density frame option for elf targets.claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.opt (mcode-density-frame): Get the inital value from TARGET_CODE_DENSITY_FRAME_DEFAULT. * config/arc/elf.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define. * config/arc/linux.h (TARGET_CODE_DENSITY_FRAME_DEFAULT): Define. * config/arc/arc.md (pop_multi_fp_blink): Adjust constraints to match what the ops is doing. (push_multi_fp_blink): Likewise. * config/arc/arc.c (arc_override_options): Enable enter/leave when compiling for size and elf target. (arc_save_callee_enter): Adjust note to match what enter/leave operation does. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269758 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18[ARC] Fix tst_movb pattern.claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.md (tst_movb): Fix constraint. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269757 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18[ARC] Define TARGET_HAVE_SPECULATION_SAFE_VALUE.claziss
xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (TARGET_HAVE_SPECULATION_SAFE_VALUE): Define. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269756 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-18[ARC] Introduce ADJUST_REG_ALLOC_ORDER.claziss
The ARC port is changing the allocation order in the arc_conditional_register_usage function, but this is not the proper way. Thus, we employ ADJUST_REG_ALLOC_ORDER hook for this task. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc-protos.h (arc_adjust_reg_alloc_order): Declare. * config/arc/arc.c (arc_conditional_register_usage): Remove all reg_alloc_order references. (size_alloc_order): Define. (arc_adjust_reg_alloc_order): New function. * config/arc/arc.h (REG_ALLOC_ORDER): Proper define the register order. (ADJUST_REG_ALLOC_ORDER): Define. (HONOR_REG_ALLOC_ORDER): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269755 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-182019-03-18 Richard Biener <rguenther@suse.de>rguenth
PR target/87561 * config/i386/i386.c (ix86_add_stmt_cost): Pessimize strided loads and stores a bit more. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269754 138bc75d-0d04-0410-961f-82ee72b054a4
2019-03-182019-03-18 Richard Biener <rguenther@suse.de>rguenth
PR target/87561 * config/i386/i386.c (ix86_add_stmt_cost): Apply strided load pessimization to stores as well. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@269753 138bc75d-0d04-0410-961f-82ee72b054a4
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