1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
|
#ifndef ISR_TEST_H
#define ISR_TEST_H
#include <string.h>
#define ISR(N,...) \
__attribute__ ((used, externally_visible , ## __VA_ARGS__)) \
void __vector_##N (void); \
void __vector_##N (void)
#define SFR(ADDR) (*(unsigned char volatile*) (__AVR_SFR_OFFSET__ + (ADDR)))
#define CORE_SFRS SFR (0x38)
#define SREG SFR (0x3F)
#define SPL SFR (0x3D)
#define EIND SFR (0x3C)
#define RAMPZ SFR (0x3B)
#define RAMPY SFR (0x3A)
#define RAMPX SFR (0x39)
#define RAMPD SFR (0x38)
#ifdef __AVR_HAVE_JMP_CALL__
#define VEC_SIZE 4
#else
#define VEC_SIZE 2
#endif
#ifdef __AVR_TINY__
#define FIRST_REG 16
#else
#define FIRST_REG 0
#endif
#define CR "\n\t"
typedef struct
{
unsigned char sfrs[8];
unsigned char gprs[32 - FIRST_REG];
} regs_t;
regs_t reginfo1, reginfo2;
__attribute__((noinline))
static void clear_reginfo (void)
{
memset (reginfo1.sfrs, 0, sizeof (reginfo1.sfrs));
memset (reginfo2.sfrs, 0, sizeof (reginfo2.sfrs));
}
__attribute__((noinline))
static void compare_reginfo (unsigned long gpr_ignore)
{
signed char regno;
const unsigned char *preg1 = ®info1.gprs[0];
const unsigned char *preg2 = ®info2.gprs[0];
if (memcmp (®info1, ®info2, 8))
__builtin_abort();
gpr_ignore >>= FIRST_REG;
for (regno = FIRST_REG; regno < 32;
regno++, preg1++, preg2++, gpr_ignore >>= 1)
{
if (gpr_ignore & 1)
continue;
if (*preg1 != *preg2)
{
static signed char volatile failed_regno;
failed_regno = regno;
__builtin_abort();
}
}
}
/* STore GPR */
#define ST(regno,M) \
CR "sts %[" #M "]+8-%[first]+" #regno ", r" #regno
/* STore SFR */
#define ST_SFR(sfr, n_sfr, M) \
CR "in __tmp_reg__,%i[s_" #sfr "]" \
CR "sts %[" #M "]+" #n_sfr ", __tmp_reg__"
/* Named asm OPerand for SFR */
#define OP_SFR(sfr) \
, [s_ ## sfr] "n" (&(sfr))
/* Write funny value to SFR */
#define XX_SFR(sfr) \
CR "dec r31 $ out %i[s_" #sfr "], r31"
/* Write 0 to SFR */
#define OO_SFR(sfr) \
CR "out %i[s_" #sfr "], __zero_reg__"
/* Macros for SREG */
#define ST_SREG(M) ST_SFR (SREG,0,M)
#define OP_SREG OP_SFR (SREG)
#define XX_SREG XX_SFR (SREG)
/* Macros for EIND */
#if defined __AVR_HAVE_EIJMP_EICALL__
#define ST_EIND(M) ST_SFR (EIND,1,M)
#define OP_EIND OP_SFR (EIND)
#else
#define ST_EIND(M) /* empty */
#define OP_EIND /* empty */
#endif
/* Macros for RAMPX */
#if defined (__AVR_HAVE_RAMPX__)
#define ST_RAMPX(M) ST_SFR (RAMPX,2,M)
#define OP_RAMPX OP_SFR (RAMPX)
#define XX_RAMPX XX_SFR (RAMPX)
#define OO_RAMPX OO_SFR (RAMPX)
#else
#define ST_RAMPX(M) /* empty */
#define OP_RAMPX /* empty */
#define XX_RAMPX /* empty */
#define OO_RAMPX /* empty */
#endif
/* Macros for RAMPY */
#if defined (__AVR_HAVE_RAMPY__)
#define ST_RAMPY(M) ST_SFR (RAMPY,3,M)
#define OP_RAMPY OP_SFR (RAMPY)
#define XX_RAMPY XX_SFR (RAMPY)
#define OO_RAMPY OO_SFR (RAMPY)
#else
#define ST_RAMPY(M) /* empty */
#define OP_RAMPY /* empty */
#define XX_RAMPY /* empty */
#define OO_RAMPY /* empty */
#endif
/* Macros for RAMPZ */
#if defined (__AVR_HAVE_RAMPZ__)
#define ST_RAMPZ(M) ST_SFR (RAMPZ,4,M)
#define OP_RAMPZ OP_SFR (RAMPZ)
#define XX_RAMPZ XX_SFR (RAMPZ)
#define OO_RAMPZ OO_SFR (RAMPZ)
#else
#define ST_RAMPZ(M) /* empty */
#define OP_RAMPZ /* empty */
#define XX_RAMPZ /* empty */
#define OO_RAMPZ /* empty */
#endif
/* Macros for RAMPD */
#if defined (__AVR_HAVE_RAMPD__)
#define ST_RAMPD(M) ST_SFR (RAMPD,5,M)
#define OP_RAMPD OP_SFR (RAMPD)
#else
#define ST_RAMPD(M) /* empty */
#define OP_RAMPD /* empty */
#endif
/* Macros for all GPRs */
#if defined __AVR_TINY__
#define ST_REGS_LO(M) /* empty */
#else
#define ST_REGS_LO(M) \
ST(0,M) ST(1,M) ST(2,M) ST(3,M) \
ST(4,M) ST(5,M) ST(6,M) ST(7,M) \
ST(8,M) ST(9,M) ST(10,M) ST(11,M) \
ST(12,M) ST(13,M) ST(14,M) ST(15,M)
#endif /* AVR_TINY */
#define ST_REGS_HI(M) \
ST(16,M) ST(17,M) ST(18,M) ST(19,M) \
ST(20,M) ST(21,M) ST(22,M) ST(23,M) \
ST(24,M) ST(25,M) ST(26,M) ST(27,M) \
ST(28,M) ST(29,M) ST(30,M) ST(31,M)
__attribute__((unused,naked,noinline,noclone))
static void host_store1 (void)
{
__asm __volatile__
("nop"
CR ".global do_stores_before"
CR ".type do_stores_before,@function"
CR "do_stores_before:"
/* Funny values to some SFRs */
CR "ldi r31, 1 + 'Z'"
XX_RAMPZ
XX_RAMPY
XX_RAMPX
CR "dec __zero_reg__"
CR "clr r31"
XX_SREG
/* Must set I-flag due to RETI of ISR */
CR "sei"
/* Store core regs before ISR */
ST_RAMPX (mem1)
ST_RAMPY (mem1)
ST_RAMPZ (mem1)
ST_RAMPD (mem1)
ST_EIND (mem1)
ST_SREG (mem1)
CR "ldi r31, 0xaa"
CR "mov __tmp_reg__, r31"
CR "ldi r31, 31"
ST_REGS_LO (mem1)
ST_REGS_HI (mem1)
CR "ret"
: /* No outputs */
: [mem1] "i" (®info1), [first] "n" (FIRST_REG)
OP_RAMPX
OP_RAMPY
OP_RAMPZ
OP_RAMPD
OP_EIND
OP_SREG
: "memory", "r31");
}
__attribute__((unused,naked,noinline,noclone))
static void host_store2 (void)
{
__asm __volatile__
("nop"
CR ".global do_stores_after"
CR ".type do_stores_after,@function"
CR "do_stores_after:"
/* Store core regs after ISR */
ST_REGS_LO (mem2)
ST_REGS_HI (mem2)
ST_RAMPX (mem2)
ST_RAMPY (mem2)
ST_RAMPZ (mem2)
ST_RAMPD (mem2)
ST_EIND (mem2)
ST_SREG (mem2)
/* Undo funny values */
CR "clr __zero_reg__"
OO_RAMPX
OO_RAMPY
OO_RAMPZ
CR "ret"
: /* No outputs */
: [mem2] "i" (®info2), [first] "n" (FIRST_REG)
OP_RAMPX
OP_RAMPY
OP_RAMPZ
OP_RAMPD
OP_EIND
OP_SREG
: "memory");
}
#define MK_CALL_ISR(vecno) \
__asm __volatile__ \
(/* Funny values to some SFRs */ \
/* Must set I-flag due to RETI of ISR */ \
/* Store core regs before ISR */ \
CR "%~call do_stores_before" \
/* Execute ISR */ \
CR "%~call __vectors + %[vect]" \
/* Store core regs after ISR */ \
/* Undo funny values */ \
CR "%~call do_stores_after" \
: /* No outputs */ \
: [vect] "i" (VEC_SIZE * (vecno)) \
, "i" (host_store1) \
, "i" (host_store2) \
: "memory", "r31")
#define MK_RUN_ISR(N, IGMSK) \
\
__attribute__((noinline,noclone)) \
void run_isr_ ## N (void) \
{ \
clear_reginfo(); \
MK_CALL_ISR (N); \
compare_reginfo (IGMSK); \
}
#endif /* ISR_TEST_H */
|
