* gcc/config/spu/spu.h (ADDRESSES_NEVER_TRAP): Define.

	* gcc/rtlanal.c (rtx_addr_can_trap_p_1): Respect ADDRESSES_NEVER_TRAP.
	* gcc/doc/tm.texi (ADDRESSES_NEVER_TRAP): Document.

	* gcc/config/spu/spu.c (spu_split_load): Trust MEM_ALIGN.  When not
	optimizing, do not split load unless necessary.

	* gcc/config/spu/spu.md ("_abs<mode>2"): Do not split in split0 pass.


git-svn-id: https://gcc.gnu.org/svn/gcc/branches/cell-4_3-branch@142488 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 36 insertions, 2 deletions

diff --git a/ChangeLog.cell b/ChangeLog.cell
index d327b82e0fc..1c2de213de1 100644
--- a/ChangeLog.cell
+++ b/ChangeLog.cell
@@ -1,3 +1,14 @@
+2008-12-05  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* gcc/config/spu/spu.h (ADDRESSES_NEVER_TRAP): Define.
+	* gcc/rtlanal.c (rtx_addr_can_trap_p_1): Respect ADDRESSES_NEVER_TRAP.
+	* gcc/doc/tm.texi (ADDRESSES_NEVER_TRAP): Document.
+
+	* gcc/config/spu/spu.c (spu_split_load): Trust MEM_ALIGN.  When not
+	optimizing, do not split load unless necessary.
+
+	* gcc/config/spu/spu.md ("_abs<mode>2"): Do not split in split0 pass.
+
 2008-11-18  Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
 
 	Change constraint u to w to avoid conflict with a patch I have
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 2a1e996ca4f..7404bdfa1cc 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -4687,7 +4687,10 @@ spu_split_load (rtx * ops)
 
   rot = 0;
   rot_amt = 0;
-  if (GET_CODE (addr) == PLUS)
+
+  if (MEM_ALIGN (ops[1]) >= 128)
+    /* Address is already aligned; simply perform a TImode load.  */;
+  else if (GET_CODE (addr) == PLUS)
     {
       /* 8 cases:
          aligned reg   + aligned reg     => lqx
@@ -4798,6 +4801,14 @@ spu_split_load (rtx * ops)
       rot_amt = 0;
     }
 
+  /* If the source is properly aligned, we don't need to split this insn into
+     a TImode load plus a _spu_convert.  However, we want to perform the split
+     anyway when optimizing to make the MEMs look the same as those used for
+     stores so they are more easily merged.  When *not* optimizing, that will
+     not happen anyway, so we prefer to avoid generating the _spu_convert.  */
+  if (!rot && !rot_amt && !optimize)
+    return 0;
+
   load = gen_reg_rtx (TImode);
 
   mem = change_address (ops[1], TImode, copy_rtx (addr));
diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h
index 7064d228a91..813ac936386 100644
--- a/gcc/config/spu/spu.h
+++ b/gcc/config/spu/spu.h
@@ -654,3 +654,5 @@ extern GTY(()) rtx spu_expect_op1;
 
 #define SPLIT_BEFORE_CSE2 1
 
+#define ADDRESSES_NEVER_TRAP 1
+
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 5df0d2bec68..01d5e34c74b 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -1267,7 +1267,7 @@
    (use (match_operand:<F2I> 2 "spu_reg_operand" "r"))]
   ""
   "#"
-  ""
+  "split0_completed"
   [(set (match_dup:<F2I> 3)
 	(and:<F2I> (match_dup:<F2I> 4)
 		   (match_dup:<F2I> 2)))]
diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi
index 123928956dd..b2b9117299c 100644
--- a/gcc/doc/tm.texi
+++ b/gcc/doc/tm.texi
@@ -10418,3 +10418,8 @@ instructions, and the optimizations right after this pass (e.g., CSE and
 combine) are be able to optimize the split instructions.
 @end defmac
 
+@defmac ADDRESSES_NEVER_TRAP
+Define this macro if memory accesses will never cause a trap.
+This is the case for example on the Cell SPU processor.
+@end defmac
+ 
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 7c4d1abfd53..00255c3e903 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -265,6 +265,10 @@ rtx_varies_p (const_rtx x, bool for_alias)
 static int
 rtx_addr_can_trap_p_1 (const_rtx x, enum machine_mode mode, bool unaligned_mems)
 {
+#ifdef ADDRESSES_NEVER_TRAP
+  /* On some processors, like the SPU, memory accesses never trap.  */
+  return 0;
+#else
   enum rtx_code code = GET_CODE (x);
 
   switch (code)
@@ -344,6 +348,7 @@ rtx_addr_can_trap_p_1 (const_rtx x, enum machine_mode mode, bool unaligned_mems)
 
   /* If it isn't one of the case above, it can cause a trap.  */
   return 1;
+#endif
 }
 
 /* Return nonzero if the use of X as an address in a MEM can cause a trap.  */