diff options
| author | Paul Brook <paul@codesourcery.com> | 2006-03-21 14:59:07 +0000 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2006-03-21 14:59:07 +0000 |
| commit | 04d6d2f8fcbd73931d6f95d5322052f30984250e (patch) | |
| tree | d13d4171717b767281bb1cf91dcd2b78ec5a6d29 | |
| parent | 8f7bf5b6e8d1234ddb287479314cf88b57f5335a (diff) | |
2005-03-21 Paul Brook <paul@codesourcery.com>
* config/arm/thumb2.md (divsi3, udivsi3): New define_insn.
* config/arm/arm.c (arm_arch_hwdiv): Define.
(arm_override_options): Set arm_arch_hwdiv.
* config/arm/arm.h (arm_arch_hwdiv): Declare.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/csl/arm-4_1@112249 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | ChangeLog.csl | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 3 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 20 |
4 files changed, 34 insertions, 0 deletions
diff --git a/ChangeLog.csl b/ChangeLog.csl index aecf9961d6a..b1a97c72cc9 100644 --- a/ChangeLog.csl +++ b/ChangeLog.csl @@ -1,3 +1,10 @@ +2005-03-21 Paul Brook <paul@codesourcery.com> + + * gcc/config/arm/thumb2.md (divsi3, udivsi3): New define_insn. + * gcc/config/arm/arm.c (arm_arch_hwdiv): Define. + (arm_override_options): Set arm_arch_hwdiv. + * gcc/config/arm/arm.h (arm_arch_hwdiv): Declare. + 2006-03-13 Paul Brook <paul@codesourcery.com> Merge from csl/sourcerygxx-4_1 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 84053afdf89..fdf1bf2bb68 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -543,6 +543,9 @@ int arm_cpp_interwork = 0; /* Nonzero if chip supports Thumb 2. */ int arm_arch_thumb2; +/* Nonzero if chip supports integer division instruction. */ +int arm_arch_hwdiv; + /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from PRINT_OPERAND to PRINT_OPERAND_ADDRESS. */ @@ -1160,6 +1163,7 @@ arm_override_options (void) arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; + arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; /* V5 code we generate is completely interworking capable, so we turn off TARGET_INTERWORK here to avoid many tests later on. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 0191ccdb73e..7022fc2e91d 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -378,6 +378,9 @@ extern int arm_cpp_interwork; /* Nonzero if chip supports Thumb 2. */ extern int arm_arch_thumb2; +/* Nonzero if chip supports integer division instruction. */ +extern int arm_arch_hwdiv; + #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) #endif diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index a10cd71a4b7..5199216faa7 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1090,3 +1090,23 @@ [(set_attr "predicable" "yes") (set_attr "length" "2")] ) + +(define_insn "divsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (div:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_THUMB2 && arm_arch_hwdiv" + "sdiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") + (set_attr "length" "2")] +) + +(define_insn "udivsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (udiv:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_THUMB2 && arm_arch_hwdiv" + "udiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") + (set_attr "length" "2")] +) |