gcc/

	* config/arm/arm.c (arm_init_neon_builtins): Fix function types for
	floating-point bit-select builtin operations.
	* config/arm/neon.md (V_cmp_result): Add DI, V2DI modes.
	(neon_vbsl<mode>): Turn into expander, and rename previous version
	to...
	(neon_vbsl<mode>_internal): New name for above insn pattern. Fix
	order of arguments, and make mode of operand 1 integer for float
	variants.
	* config/arm/neon.ml (bit_select): Add type munging function for bit
	selection ops.
	(Vneg): Fix operand shape for vqnegq.
	(Vbsl): Use bit_select not notype_3 for type munging function.
	* config/arm/arm_neon.h: Regenerate.
	* doc/arm-neon-intrinsics.texi: Regenerate.
	* testsuite/gcc.target/arm/neon/*.c: Regenerate.



git-svn-id: https://gcc.gnu.org/svn/gcc/branches/csl/sourcerygxx-4_1@118167 138bc75d-0d04-0410-961f-82ee72b054a4

315 files changed, 445 insertions, 403 deletions

diff --git a/ChangeLog.csl b/ChangeLog.csl
index a806b39bfcb..ac3a4b4ab1c 100644
--- a/ChangeLog.csl
+++ b/ChangeLog.csl
@@ -1,3 +1,22 @@
+2006-10-29  Julian Brown  <julian@codesourcery.com>
+
+	gcc/
+	* config/arm/arm.c (arm_init_neon_builtins): Fix function types for
+	floating-point bit-select builtin operations.
+	* config/arm/neon.md (V_cmp_result): Add DI, V2DI modes.
+	(neon_vbsl<mode>): Turn into expander, and rename previous version
+	to...
+	(neon_vbsl<mode>_internal): New name for above insn pattern. Fix
+	order of arguments, and make mode of operand 1 integer for float
+	variants.
+	* config/arm/neon.ml (bit_select): Add type munging function for bit
+	selection ops.
+	(Vneg): Fix operand shape for vqnegq.
+	(Vbsl): Use bit_select not notype_3 for type munging function.
+	* config/arm/arm_neon.h: Regenerate.
+	* doc/arm-neon-intrinsics.texi: Regenerate.
+	* testsuite/gcc.target/arm/neon/*.c: Regenerate.
+
 2006-10-29  Joseph Myers  <joseph@codesourcery.com>
 
 	libstdc++-v3/
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 55dbe25dc3b..d30b193ed1a 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -14934,13 +14934,13 @@ arm_init_neon_builtins (void)
   TYPE4 (v8qi, v8qi, v8qi, v8qi);
   TYPE4 (v4hi, v4hi, v4hi, v4hi);
   TYPE4 (v2si, v2si, v2si, v2si);
-  TYPE4 (v2sf, v2sf, v2sf, v2sf);
+  TYPE4 (v2sf, v2si, v2sf, v2sf);
   TYPE4 (di, di, di, di);
 
   TYPE4 (v16qi, v16qi, v16qi, v16qi);
   TYPE4 (v8hi, v8hi, v8hi, v8hi);
   TYPE4 (v4si, v4si, v4si, v4si);
-  TYPE4 (v4sf, v4sf, v4sf, v4sf);
+  TYPE4 (v4sf, v4si, v4sf, v4sf);
   TYPE4 (v2di, v2di, v2di, v2di);
 
   /* Shift immediate operations.  */
@@ -16407,18 +16407,21 @@ arm_init_neon_builtins (void)
               break;
 
 	    case NEON_SELECT:
-              gcc_assert (mode0 == mode1 && mode1 == mode2);
+              gcc_assert (mode1 == mode2
+                          && (mode0 == mode1
+                              || (mode0 == V2SImode && mode1 == V2SFmode)
+                              || (mode0 == V4SImode && mode1 == V4SFmode)));
               switch (tmode)
                 {
                 case V8QImode: ftype = v8qi_ftype_v8qi_v8qi_v8qi; break;
                 case V4HImode: ftype = v4hi_ftype_v4hi_v4hi_v4hi; break;
                 case V2SImode: ftype = v2si_ftype_v2si_v2si_v2si; break;
-                case V2SFmode: ftype = v2sf_ftype_v2sf_v2sf_v2sf; break;
+                case V2SFmode: ftype = v2sf_ftype_v2si_v2sf_v2sf; break;
                 case DImode: ftype = di_ftype_di_di_di; break;
                 case V16QImode: ftype = v16qi_ftype_v16qi_v16qi_v16qi; break;
                 case V8HImode: ftype = v8hi_ftype_v8hi_v8hi_v8hi; break;
                 case V4SImode: ftype = v4si_ftype_v4si_v4si_v4si; break;
-                case V4SFmode: ftype = v4sf_ftype_v4sf_v4sf_v4sf; break;
+                case V4SFmode: ftype = v4sf_ftype_v4si_v4sf_v4sf; break;
                 case V2DImode: ftype = v2di_ftype_v2di_v2di_v2di; break;
                 default: gcc_unreachable ();
                 }
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 8fd86742d80..4c2797bb7e7 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -4636,22 +4636,22 @@ vqneg_s32 (int32x2_t __a)
   return __builtin_neon_vqnegv2si (__a, 1);
 }
 
-__extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-vqnegq_s8 (int8x8_t __a)
+__extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
+vqnegq_s8 (int8x16_t __a)
 {
-  return __builtin_neon_vqnegv8qi (__a, 1);
+  return __builtin_neon_vqnegv16qi (__a, 1);
 }
 
-__extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-vqnegq_s16 (int16x4_t __a)
+__extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
+vqnegq_s16 (int16x8_t __a)
 {
-  return __builtin_neon_vqnegv4hi (__a, 1);
+  return __builtin_neon_vqnegv8hi (__a, 1);
 }
 
-__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-vqnegq_s32 (int32x2_t __a)
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vqnegq_s32 (int32x4_t __a)
 {
-  return __builtin_neon_vqnegv2si (__a, 1);
+  return __builtin_neon_vqnegv4si (__a, 1);
 }
 
 __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
@@ -7259,33 +7259,33 @@ vrev16q_p8 (poly8x16_t __a)
 }
 
 __extension__ static __inline int8x8_t __attribute__ ((__always_inline__))
-vbsl_s8 (int8x8_t __a, int8x8_t __b, int8x8_t __c)
+vbsl_s8 (uint8x8_t __a, int8x8_t __b, int8x8_t __c)
 {
-  return __builtin_neon_vbslv8qi (__a, __b, __c);
+  return __builtin_neon_vbslv8qi ((int8x8_t) __a, __b, __c);
 }
 
 __extension__ static __inline int16x4_t __attribute__ ((__always_inline__))
-vbsl_s16 (int16x4_t __a, int16x4_t __b, int16x4_t __c)
+vbsl_s16 (uint16x4_t __a, int16x4_t __b, int16x4_t __c)
 {
-  return __builtin_neon_vbslv4hi (__a, __b, __c);
+  return __builtin_neon_vbslv4hi ((int16x4_t) __a, __b, __c);
 }
 
 __extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
-vbsl_s32 (int32x2_t __a, int32x2_t __b, int32x2_t __c)
+vbsl_s32 (uint32x2_t __a, int32x2_t __b, int32x2_t __c)
 {
-  return __builtin_neon_vbslv2si (__a, __b, __c);
+  return __builtin_neon_vbslv2si ((int32x2_t) __a, __b, __c);
 }
 
 __extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
-vbsl_s64 (int64x1_t __a, int64x1_t __b, int64x1_t __c)
+vbsl_s64 (uint64x1_t __a, int64x1_t __b, int64x1_t __c)
 {
-  return __builtin_neon_vbsldi (__a, __b, __c);
+  return __builtin_neon_vbsldi ((int64x1_t) __a, __b, __c);
 }
 
 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
-vbsl_f32 (float32x2_t __a, float32x2_t __b, float32x2_t __c)
+vbsl_f32 (uint32x2_t __a, float32x2_t __b, float32x2_t __c)
 {
-  return __builtin_neon_vbslv2sf (__a, __b, __c);
+  return __builtin_neon_vbslv2sf ((int32x2_t) __a, __b, __c);
 }
 
 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
@@ -7313,45 +7313,45 @@ vbsl_u64 (uint64x1_t __a, uint64x1_t __b, uint64x1_t __c)
 }
 
 __extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
-vbsl_p8 (poly8x8_t __a, poly8x8_t __b, poly8x8_t __c)
+vbsl_p8 (uint8x8_t __a, poly8x8_t __b, poly8x8_t __c)
 {
   return __builtin_neon_vbslv8qi ((int8x8_t) __a, (int8x8_t) __b, (int8x8_t) __c);
 }
 
 __extension__ static __inline poly16x4_t __attribute__ ((__always_inline__))
-vbsl_p16 (poly16x4_t __a, poly16x4_t __b, poly16x4_t __c)
+vbsl_p16 (uint16x4_t __a, poly16x4_t __b, poly16x4_t __c)
 {
   return __builtin_neon_vbslv4hi ((int16x4_t) __a, (int16x4_t) __b, (int16x4_t) __c);
 }
 
 __extension__ static __inline int8x16_t __attribute__ ((__always_inline__))
-vbslq_s8 (int8x16_t __a, int8x16_t __b, int8x16_t __c)
+vbslq_s8 (uint8x16_t __a, int8x16_t __b, int8x16_t __c)
 {
-  return __builtin_neon_vbslv16qi (__a, __b, __c);
+  return __builtin_neon_vbslv16qi ((int8x16_t) __a, __b, __c);
 }
 
 __extension__ static __inline int16x8_t __attribute__ ((__always_inline__))
-vbslq_s16 (int16x8_t __a, int16x8_t __b, int16x8_t __c)
+vbslq_s16 (uint16x8_t __a, int16x8_t __b, int16x8_t __c)
 {
-  return __builtin_neon_vbslv8hi (__a, __b, __c);
+  return __builtin_neon_vbslv8hi ((int16x8_t) __a, __b, __c);
 }
 
 __extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
-vbslq_s32 (int32x4_t __a, int32x4_t __b, int32x4_t __c)
+vbslq_s32 (uint32x4_t __a, int32x4_t __b, int32x4_t __c)
 {
-  return __builtin_neon_vbslv4si (__a, __b, __c);
+  return __builtin_neon_vbslv4si ((int32x4_t) __a, __b, __c);
 }
 
 __extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
-vbslq_s64 (int64x2_t __a, int64x2_t __b, int64x2_t __c)
+vbslq_s64 (uint64x2_t __a, int64x2_t __b, int64x2_t __c)
 {
-  return __builtin_neon_vbslv2di (__a, __b, __c);
+  return __builtin_neon_vbslv2di ((int64x2_t) __a, __b, __c);
 }
 
 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
-vbslq_f32 (float32x4_t __a, float32x4_t __b, float32x4_t __c)
+vbslq_f32 (uint32x4_t __a, float32x4_t __b, float32x4_t __c)
 {
-  return __builtin_neon_vbslv4sf (__a, __b, __c);
+  return __builtin_neon_vbslv4sf ((int32x4_t) __a, __b, __c);
 }
 
 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
@@ -7379,13 +7379,13 @@ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c)
 }
 
 __extension__ static __inline poly8x16_t __attribute__ ((__always_inline__))
-vbslq_p8 (poly8x16_t __a, poly8x16_t __b, poly8x16_t __c)
+vbslq_p8 (uint8x16_t __a, poly8x16_t __b, poly8x16_t __c)
 {
   return __builtin_neon_vbslv16qi ((int8x16_t) __a, (int8x16_t) __b, (int8x16_t) __c);
 }
 
 __extension__ static __inline poly16x8_t __attribute__ ((__always_inline__))
-vbslq_p16 (poly16x8_t __a, poly16x8_t __b, poly16x8_t __c)
+vbslq_p16 (uint16x8_t __a, poly16x8_t __b, poly16x8_t __c)
 {
   return __builtin_neon_vbslv8hi ((int16x8_t) __a, (int16x8_t) __b, (int16x8_t) __c);
 }
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index a1d5b2ff765..aafa53739c5 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -329,11 +329,12 @@
 				  (V4HI "V2SI") (V8HI "V4SI")
 				  (V2SI "DI")   (V4SI "V2DI")])
 
-;; Mode of result of comparison operations.
+;; Mode of result of comparison operations (and bit-select operand 1).
 (define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
 			        (V4HI "V4HI") (V8HI  "V8HI")
                                 (V2SI "V2SI") (V4SI  "V4SI")
-                                (V2SF "V2SI") (V4SF  "V4SI")])
+                                (V2SF "V2SI") (V4SF  "V4SI")
+                                (DI   "DI")   (V2DI  "V2DI")])
 
 ;; Get element type from double-width mode, for operations where we don't care
 ;; about signedness.
@@ -2632,23 +2633,35 @@
 
 ; vbsl_* intrinsics may compile to any of vbsl/vbif/vbit depending on register
 ; allocation. For an intrinsic of form:
-;   rD = vbsl_* (rN, rM, rS)
+;   rD = vbsl_* (rS, rN, rM)
 ; We can use any of:
 ;   vbsl rS, rN, rM  (if D = S)
 ;   vbit rD, rN, rS  (if D = M, so 1-bits in rS choose bits from rN, else rM)
 ;   vbif rD, rM, rS  (if D = N, so 0-bits in rS choose bits from rM, else rN)
 
-(define_insn "neon_vbsl<mode>"
+(define_insn "neon_vbsl<mode>_internal"
   [(set (match_operand:VDQX 0 "s_register_operand"		 "=w,w,w")
-	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" " w,w,0")
-		      (match_operand:VDQX 2 "s_register_operand" " w,0,w")
-                      (match_operand:VDQX 3 "s_register_operand" " 0,w,w")]
+	(unspec:VDQX [(match_operand:VDQX 1 "s_register_operand" " 0,w,w")
+		      (match_operand:VDQX 2 "s_register_operand" " w,w,0")
+                      (match_operand:VDQX 3 "s_register_operand" " w,0,w")]
                      UNSPEC_VBSL))]
   "TARGET_NEON"
   "@
-  vbsl\t%<V_reg>0, %<V_reg>1, %<V_reg>2
-  vbit\t%<V_reg>0, %<V_reg>1, %<V_reg>3
-  vbif\t%<V_reg>0, %<V_reg>2, %<V_reg>3")
+  vbsl\t%<V_reg>0, %<V_reg>2, %<V_reg>3
+  vbit\t%<V_reg>0, %<V_reg>2, %<V_reg>1
+  vbif\t%<V_reg>0, %<V_reg>3, %<V_reg>1")
+
+(define_expand "neon_vbsl<mode>"
+  [(set (match_operand:VDQX 0 "s_register_operand" "")
+        (unspec:VDQX [(match_operand:<V_cmp_result> 1 "s_register_operand" "")
+                      (match_operand:VDQX 2 "s_register_operand" "")
+                      (match_operand:VDQX 3 "s_register_operand" "")]
+                     UNSPEC_VBSL))]
+  "TARGET_NEON"
+{
+  /* We can't alias operands together if they have different modes.  */
+  operands[1] = gen_lowpart (<MODE>mode, operands[1]);
+})
 
 (define_insn "neon_vshl<mode>"
   [(set (match_operand:VDQIX 0 "s_register_operand" "=w")
diff --git a/gcc/config/arm/neon.ml b/gcc/config/arm/neon.ml
index 2347a480ba9..a2b00e2fdcf 100644
--- a/gcc/config/arm/neon.ml
+++ b/gcc/config/arm/neon.ml
@@ -678,6 +678,13 @@ let notype_1 = make_notype elts_same_1
 let notype_2 = make_notype elts_same_2
 let notype_3 = make_notype elts_same_3
 
+(* Bit-select operations (first operand is unsigned int).  *)
+
+let bit_select shape elt =
+  let vtype = type_for_elt shape elt
+  and itype = type_for_elt shape (unsigned_of_elt elt) in
+  Arity3 (vtype 0, itype 1, vtype 2, vtype 3), NoElts
+
 (* Common lists of supported element types.  *)
 
 let su_8_32 = [S8; S16; S32; U8; U16; U32]
@@ -914,7 +921,7 @@ let ops =
     Vneg, [], All (2, Dreg), "vneg", elts_same_1, [S8; S16; S32; F32];
     Vneg, [], All (2, Qreg), "vnegQ", elts_same_1, [S8; S16; S32; F32];
     Vneg, [Saturating], All (2, Dreg), "vqneg", elts_same_1, [S8; S16; S32];
-    Vneg, [Saturating], All (2, Dreg), "vqnegQ", elts_same_1, [S8; S16; S32];
+    Vneg, [Saturating], All (2, Qreg), "vqnegQ", elts_same_1, [S8; S16; S32];
     
     (* Bitwise not.  *)
     Vmvn, [], All (2, Dreg), "vmvn", notype_1, P8 :: su_8_32;
@@ -1258,12 +1265,12 @@ let ops =
     Vbsl,
       [Instruction_name ["vbsl"; "vbit"; "vbif"];
        Disassembles_as [Use_operands [| Dreg; Dreg; Dreg |]]],
-      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", notype_3,
+      Use_operands [| Dreg; Dreg; Dreg; Dreg |], "vbsl", bit_select,
       pf_su_8_64;
     Vbsl,
       [Instruction_name ["vbsl"; "vbit"; "vbif"];
        Disassembles_as [Use_operands [| Qreg; Qreg; Qreg |]]],
-      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", notype_3,
+      Use_operands [| Qreg; Qreg; Qreg; Qreg |], "vbslQ", bit_select,
       pf_su_8_64;
     
     (* Transpose elements.  **NOTE** ReturnPtr goes some of the way towards
diff --git a/gcc/doc/arm-neon-intrinsics.texi b/gcc/doc/arm-neon-intrinsics.texi
index 35435fc7c39..89fe5c045e9 100644
--- a/gcc/doc/arm-neon-intrinsics.texi
+++ b/gcc/doc/arm-neon-intrinsics.texi
@@ -4373,20 +4373,20 @@
 
 
 @itemize @bullet
-@item int32x2_t vqnegq_s32 (int32x2_t)
-@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
+@item int32x4_t vqnegq_s32 (int32x4_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item int16x4_t vqnegq_s16 (int16x4_t)
-@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
+@item int16x8_t vqnegq_s16 (int16x8_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item int8x8_t vqnegq_s8 (int8x8_t)
-@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
+@item int8x16_t vqnegq_s8 (int8x16_t)
+@*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
 @end itemize
 
 
@@ -7086,19 +7086,19 @@
 
 
 @itemize @bullet
-@item int32x2_t vbsl_s32 (int32x2_t, int32x2_t, int32x2_t)
+@item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
 
 @itemize @bullet
-@item int16x4_t vbsl_s16 (int16x4_t, int16x4_t, int16x4_t)
+@item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
 
 @itemize @bullet
-@item int8x8_t vbsl_s8 (int8x8_t, int8x8_t, int8x8_t)
+@item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
@@ -7110,25 +7110,25 @@
 
 
 @itemize @bullet
-@item int64x1_t vbsl_s64 (int64x1_t, int64x1_t, int64x1_t)
+@item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
 
 @itemize @bullet
-@item float32x2_t vbsl_f32 (float32x2_t, float32x2_t, float32x2_t)
+@item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
 
 @itemize @bullet
-@item poly16x4_t vbsl_p16 (poly16x4_t, poly16x4_t, poly16x4_t)
+@item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
 
 @itemize @bullet
-@item poly8x8_t vbsl_p8 (poly8x8_t, poly8x8_t, poly8x8_t)
+@item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
 @end itemize
 
@@ -7152,19 +7152,19 @@
 
 
 @itemize @bullet
-@item int32x4_t vbslq_s32 (int32x4_t, int32x4_t, int32x4_t)
+@item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item int16x8_t vbslq_s16 (int16x8_t, int16x8_t, int16x8_t)
+@item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item int8x16_t vbslq_s8 (int8x16_t, int8x16_t, int8x16_t)
+@item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
@@ -7176,25 +7176,25 @@
 
 
 @itemize @bullet
-@item int64x2_t vbslq_s64 (int64x2_t, int64x2_t, int64x2_t)
+@item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item float32x4_t vbslq_f32 (float32x4_t, float32x4_t, float32x4_t)
+@item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item poly16x8_t vbslq_p16 (poly16x8_t, poly16x8_t, poly16x8_t)
+@item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
 
 @itemize @bullet
-@item poly8x16_t vbslq_p8 (poly8x16_t, poly8x16_t, poly8x16_t)
+@item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
 @end itemize
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
index 5268e75f85c..29542d2c3ae 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQf32.c
@@ -10,11 +10,11 @@
 void test_vbslQf32 (void)
 {
   float32x4_t out_float32x4_t;
-  float32x4_t arg0_float32x4_t;
+  uint32x4_t arg0_uint32x4_t;
   float32x4_t arg1_float32x4_t;
   float32x4_t arg2_float32x4_t;
 
-  out_float32x4_t = vbslq_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x4_t);
+  out_float32x4_t = vbslq_f32 (arg0_uint32x4_t, arg1_float32x4_t, arg2_float32x4_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
index b95ecb92475..68c81d4ae17 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp16.c
@@ -10,11 +10,11 @@
 void test_vbslQp16 (void)
 {
   poly16x8_t out_poly16x8_t;
-  poly16x8_t arg0_poly16x8_t;
+  uint16x8_t arg0_uint16x8_t;
   poly16x8_t arg1_poly16x8_t;
   poly16x8_t arg2_poly16x8_t;
 
-  out_poly16x8_t = vbslq_p16 (arg0_poly16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
+  out_poly16x8_t = vbslq_p16 (arg0_uint16x8_t, arg1_poly16x8_t, arg2_poly16x8_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
index a9bc608d1ac..d3ecf02e7c8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQp8.c
@@ -10,11 +10,11 @@
 void test_vbslQp8 (void)
 {
   poly8x16_t out_poly8x16_t;
-  poly8x16_t arg0_poly8x16_t;
+  uint8x16_t arg0_uint8x16_t;
   poly8x16_t arg1_poly8x16_t;
   poly8x16_t arg2_poly8x16_t;
 
-  out_poly8x16_t = vbslq_p8 (arg0_poly8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
+  out_poly8x16_t = vbslq_p8 (arg0_uint8x16_t, arg1_poly8x16_t, arg2_poly8x16_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
index 371b3a98913..85d966025e8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs16.c
@@ -10,11 +10,11 @@
 void test_vbslQs16 (void)
 {
   int16x8_t out_int16x8_t;
-  int16x8_t arg0_int16x8_t;
+  uint16x8_t arg0_uint16x8_t;
   int16x8_t arg1_int16x8_t;
   int16x8_t arg2_int16x8_t;
 
-  out_int16x8_t = vbslq_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x8_t);
+  out_int16x8_t = vbslq_s16 (arg0_uint16x8_t, arg1_int16x8_t, arg2_int16x8_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
index 8adf19f7ed0..49368d94d0e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs32.c
@@ -10,11 +10,11 @@
 void test_vbslQs32 (void)
 {
   int32x4_t out_int32x4_t;
-  int32x4_t arg0_int32x4_t;
+  uint32x4_t arg0_uint32x4_t;
   int32x4_t arg1_int32x4_t;
   int32x4_t arg2_int32x4_t;
 
-  out_int32x4_t = vbslq_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x4_t);
+  out_int32x4_t = vbslq_s32 (arg0_uint32x4_t, arg1_int32x4_t, arg2_int32x4_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
index 2a7cd502c03..f887e1fb988 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs64.c
@@ -10,11 +10,11 @@
 void test_vbslQs64 (void)
 {
   int64x2_t out_int64x2_t;
-  int64x2_t arg0_int64x2_t;
+  uint64x2_t arg0_uint64x2_t;
   int64x2_t arg1_int64x2_t;
   int64x2_t arg2_int64x2_t;
 
-  out_int64x2_t = vbslq_s64 (arg0_int64x2_t, arg1_int64x2_t, arg2_int64x2_t);
+  out_int64x2_t = vbslq_s64 (arg0_uint64x2_t, arg1_int64x2_t, arg2_int64x2_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
index 8d8e7f8c225..32ca2bfff6c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslQs8.c
@@ -10,11 +10,11 @@
 void test_vbslQs8 (void)
 {
   int8x16_t out_int8x16_t;
-  int8x16_t arg0_int8x16_t;
+  uint8x16_t arg0_uint8x16_t;
   int8x16_t arg1_int8x16_t;
   int8x16_t arg2_int8x16_t;
 
-  out_int8x16_t = vbslq_s8 (arg0_int8x16_t, arg1_int8x16_t, arg2_int8x16_t);
+  out_int8x16_t = vbslq_s8 (arg0_uint8x16_t, arg1_int8x16_t, arg2_int8x16_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslf32.c b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
index 250a638477c..b1eda451a92 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslf32.c
@@ -10,11 +10,11 @@
 void test_vbslf32 (void)
 {
   float32x2_t out_float32x2_t;
-  float32x2_t arg0_float32x2_t;
+  uint32x2_t arg0_uint32x2_t;
   float32x2_t arg1_float32x2_t;
   float32x2_t arg2_float32x2_t;
 
-  out_float32x2_t = vbsl_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t);
+  out_float32x2_t = vbsl_f32 (arg0_uint32x2_t, arg1_float32x2_t, arg2_float32x2_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp16.c b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
index 42a412d28ce..220ec9c88ce 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp16.c
@@ -10,11 +10,11 @@
 void test_vbslp16 (void)
 {
   poly16x4_t out_poly16x4_t;
-  poly16x4_t arg0_poly16x4_t;
+  uint16x4_t arg0_uint16x4_t;
   poly16x4_t arg1_poly16x4_t;
   poly16x4_t arg2_poly16x4_t;
 
-  out_poly16x4_t = vbsl_p16 (arg0_poly16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
+  out_poly16x4_t = vbsl_p16 (arg0_uint16x4_t, arg1_poly16x4_t, arg2_poly16x4_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbslp8.c b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
index 1637314e227..580b0afddde 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbslp8.c
@@ -10,11 +10,11 @@
 void test_vbslp8 (void)
 {
   poly8x8_t out_poly8x8_t;
-  poly8x8_t arg0_poly8x8_t;
+  uint8x8_t arg0_uint8x8_t;
   poly8x8_t arg1_poly8x8_t;
   poly8x8_t arg2_poly8x8_t;
 
-  out_poly8x8_t = vbsl_p8 (arg0_poly8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
+  out_poly8x8_t = vbsl_p8 (arg0_uint8x8_t, arg1_poly8x8_t, arg2_poly8x8_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls16.c b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
index 52c20779f61..1960a82eea5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls16.c
@@ -10,11 +10,11 @@
 void test_vbsls16 (void)
 {
   int16x4_t out_int16x4_t;
-  int16x4_t arg0_int16x4_t;
+  uint16x4_t arg0_uint16x4_t;
   int16x4_t arg1_int16x4_t;
   int16x4_t arg2_int16x4_t;
 
-  out_int16x4_t = vbsl_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t);
+  out_int16x4_t = vbsl_s16 (arg0_uint16x4_t, arg1_int16x4_t, arg2_int16x4_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls32.c b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
index 2a957375e22..e6442121972 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls32.c
@@ -10,11 +10,11 @@
 void test_vbsls32 (void)
 {
   int32x2_t out_int32x2_t;
-  int32x2_t arg0_int32x2_t;
+  uint32x2_t arg0_uint32x2_t;
   int32x2_t arg1_int32x2_t;
   int32x2_t arg2_int32x2_t;
 
-  out_int32x2_t = vbsl_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t);
+  out_int32x2_t = vbsl_s32 (arg0_uint32x2_t, arg1_int32x2_t, arg2_int32x2_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls64.c b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
index a2d3adc02ca..abaf9eda078 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls64.c
@@ -10,11 +10,11 @@
 void test_vbsls64 (void)
 {
   int64x1_t out_int64x1_t;
-  int64x1_t arg0_int64x1_t;
+  uint64x1_t arg0_uint64x1_t;
   int64x1_t arg1_int64x1_t;
   int64x1_t arg2_int64x1_t;
 
-  out_int64x1_t = vbsl_s64 (arg0_int64x1_t, arg1_int64x1_t, arg2_int64x1_t);
+  out_int64x1_t = vbsl_s64 (arg0_uint64x1_t, arg1_int64x1_t, arg2_int64x1_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vbsls8.c b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
index 41bf3b19ecd..5ff53cd45fb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vbsls8.c
@@ -10,11 +10,11 @@
 void test_vbsls8 (void)
 {
   int8x8_t out_int8x8_t;
-  int8x8_t arg0_int8x8_t;
+  uint8x8_t arg0_uint8x8_t;
   int8x8_t arg1_int8x8_t;
   int8x8_t arg2_int8x8_t;
 
-  out_int8x8_t = vbsl_s8 (arg0_int8x8_t, arg1_int8x8_t, arg2_int8x8_t);
+  out_int8x8_t = vbsl_s8 (arg0_uint8x8_t, arg1_int8x8_t, arg2_int8x8_t);
 }
 
 /* { dg-final { scan-assembler "((vbsl)|(vbit)|(vbif))\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
index 36a5b1bfe46..4e4c3a44e72 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanef32.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanef32 (void)
   out_float32x4_t = vdupq_lane_f32 (arg0_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
index 6494928a8cd..66ac07e5d65 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep16.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanep16 (void)
   out_poly16x8_t = vdupq_lane_p16 (arg0_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
index 8f272524843..8d21ebc63b7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanep8.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanep8 (void)
   out_poly8x16_t = vdupq_lane_p8 (arg0_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
index db35924a871..ee2e3ab3adc 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes16.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanes16 (void)
   out_int16x8_t = vdupq_lane_s16 (arg0_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
index 28376219c7f..5bc43b1ec20 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes32.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanes32 (void)
   out_int32x4_t = vdupq_lane_s32 (arg0_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
index 1e5cfcaa611..7bc0bab86da 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_lanes8.c
@@ -15,5 +15,5 @@ void test_vdupQ_lanes8 (void)
   out_int8x16_t = vdupq_lane_s8 (arg0_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
index d9eed5ad292..e2827993351 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu16.c
@@ -15,5 +15,5 @@ void test_vdupQ_laneu16 (void)
   out_uint16x8_t = vdupq_lane_u16 (arg0_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
index 457212ad840..23aa613ad15 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu32.c
@@ -15,5 +15,5 @@ void test_vdupQ_laneu32 (void)
   out_uint32x4_t = vdupq_lane_u32 (arg0_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
index 35d9012eb44..c00781745d0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdupQ_laneu8.c
@@ -15,5 +15,5 @@ void test_vdupQ_laneu8 (void)
   out_uint8x16_t = vdupq_lane_u8 (arg0_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
index c6734bdf1bf..1636ef52f01 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanef32.c
@@ -15,5 +15,5 @@ void test_vdup_lanef32 (void)
   out_float32x2_t = vdup_lane_f32 (arg0_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
index 069b81b5a0d..c1eb8f46a2d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep16.c
@@ -15,5 +15,5 @@ void test_vdup_lanep16 (void)
   out_poly16x4_t = vdup_lane_p16 (arg0_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
index 74f1b726b0b..601337b5486 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanep8.c
@@ -15,5 +15,5 @@ void test_vdup_lanep8 (void)
   out_poly8x8_t = vdup_lane_p8 (arg0_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
index 0980078dff3..34cb2df9758 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes16.c
@@ -15,5 +15,5 @@ void test_vdup_lanes16 (void)
   out_int16x4_t = vdup_lane_s16 (arg0_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
index 4717b9a5964..664a6d0a924 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes32.c
@@ -15,5 +15,5 @@ void test_vdup_lanes32 (void)
   out_int32x2_t = vdup_lane_s32 (arg0_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
index 06ae38c24c1..555e78addf4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_lanes8.c
@@ -15,5 +15,5 @@ void test_vdup_lanes8 (void)
   out_int8x8_t = vdup_lane_s8 (arg0_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
index 6b87b7d038c..a6fe4f0a00e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu16.c
@@ -15,5 +15,5 @@ void test_vdup_laneu16 (void)
   out_uint16x4_t = vdup_lane_u16 (arg0_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
index 13b57ea2413..c434ef34454 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu32.c
@@ -15,5 +15,5 @@ void test_vdup_laneu32 (void)
   out_uint32x2_t = vdup_lane_u32 (arg0_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
index 4b11aa32757..6ed63b742cb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vdup_laneu8.c
@@ -15,5 +15,5 @@ void test_vdup_laneu8 (void)
   out_uint8x8_t = vdup_lane_u8 (arg0_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vdup\.8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
index bacee7404b9..c9a99d82d73 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanef32.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanef32 (void)
   out_float32_t = vgetq_lane_f32 (arg0_float32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
index 55a0e5c7caa..8ce34742cdc 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep16.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanep16 (void)
   out_poly16_t = vgetq_lane_p16 (arg0_poly16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
index e1551afcbb6..bb23b082cf1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanep8.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanep8 (void)
   out_poly8_t = vgetq_lane_p8 (arg0_poly8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
index 2611bb105f3..df02fc17250 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes16.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanes16 (void)
   out_int16_t = vgetq_lane_s16 (arg0_int16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
index 94739d9f625..0480943c1c1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes32.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanes32 (void)
   out_int32_t = vgetq_lane_s32 (arg0_int32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
index eb66ce61afb..d4653e38f81 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_lanes8.c
@@ -15,5 +15,5 @@ void test_vgetQ_lanes8 (void)
   out_int8_t = vgetq_lane_s8 (arg0_int8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
index 34fd4f951d6..0390cb1b350 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu16.c
@@ -15,5 +15,5 @@ void test_vgetQ_laneu16 (void)
   out_uint16_t = vgetq_lane_u16 (arg0_uint16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
index ad2ce416a96..a8132ab57a7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu32.c
@@ -15,5 +15,5 @@ void test_vgetQ_laneu32 (void)
   out_uint32_t = vgetq_lane_u32 (arg0_uint32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
index 164b7c025a0..4f18f1cd094 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vgetQ_laneu8.c
@@ -15,5 +15,5 @@ void test_vgetQ_laneu8 (void)
   out_uint8_t = vgetq_lane_u8 (arg0_uint8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
index de2ad877f58..3fda66a8a01 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanef32.c
@@ -15,5 +15,5 @@ void test_vget_lanef32 (void)
   out_float32_t = vget_lane_f32 (arg0_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.f32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
index d5329ab648d..caaed705771 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep16.c
@@ -15,5 +15,5 @@ void test_vget_lanep16 (void)
   out_poly16_t = vget_lane_p16 (arg0_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
index b94ca6255fe..e2f7318f1ca 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanep8.c
@@ -15,5 +15,5 @@ void test_vget_lanep8 (void)
   out_poly8_t = vget_lane_p8 (arg0_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
index e81b474c883..f008eabfa81 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes16.c
@@ -15,5 +15,5 @@ void test_vget_lanes16 (void)
   out_int16_t = vget_lane_s16 (arg0_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
index e568f472c04..2b08ff86ffe 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes32.c
@@ -15,5 +15,5 @@ void test_vget_lanes32 (void)
   out_int32_t = vget_lane_s32 (arg0_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
index 107d31d3e54..9e16e5ba0ce 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_lanes8.c
@@ -15,5 +15,5 @@ void test_vget_lanes8 (void)
   out_int8_t = vget_lane_s8 (arg0_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.s8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
index 5405ac40f23..af85b44ba1b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu16.c
@@ -15,5 +15,5 @@ void test_vget_laneu16 (void)
   out_uint16_t = vget_lane_u16 (arg0_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u16\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
index 01f831b2d8e..8c3da8b7779 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu32.c
@@ -15,5 +15,5 @@ void test_vget_laneu32 (void)
   out_uint32_t = vget_lane_u32 (arg0_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u32\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
index 59394656c9e..36ba56534d3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vget_laneu8.c
@@ -15,5 +15,5 @@ void test_vget_laneu8 (void)
   out_uint8_t = vget_lane_u8 (arg0_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.u8\[ 	\]+\[rR\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
index 5b044881f1b..0c06f31b65e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanef32 (void)
   out_float32x4_t = vld1q_lane_f32 (0, arg1_float32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
index 80930fbfd12..728a74f2e50 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanep16 (void)
   out_poly16x8_t = vld1q_lane_p16 (0, arg1_poly16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
index 29ee67419be..993db8fe031 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanep8.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanep8 (void)
   out_poly8x16_t = vld1q_lane_p8 (0, arg1_poly8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
index 88774f52eaa..6ecc5310f84 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanes16 (void)
   out_int16x8_t = vld1q_lane_s16 (0, arg1_int16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
index 0e722688685..6132caa80a1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanes32 (void)
   out_int32x4_t = vld1q_lane_s32 (0, arg1_int32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
index 3a8e2e51077..8604b5f8ac8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_lanes8.c
@@ -15,5 +15,5 @@ void test_vld1Q_lanes8 (void)
   out_int8x16_t = vld1q_lane_s8 (0, arg1_int8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
index dc4c62aa0a8..ccba9931002 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vld1Q_laneu16 (void)
   out_uint16x8_t = vld1q_lane_u16 (0, arg1_uint16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
index 45b2963541f..7827ff91a7f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vld1Q_laneu32 (void)
   out_uint32x4_t = vld1q_lane_u32 (0, arg1_uint32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
index e54e36d6f70..f43cfa49783 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1Q_laneu8.c
@@ -15,5 +15,5 @@ void test_vld1Q_laneu8 (void)
   out_uint8x16_t = vld1q_lane_u8 (0, arg1_uint8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
index 386fc747ad7..2e2bfe5ea9c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanef32.c
@@ -15,5 +15,5 @@ void test_vld1_lanef32 (void)
   out_float32x2_t = vld1_lane_f32 (0, arg1_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
index 6f97173e161..9ced64ac325 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep16.c
@@ -15,5 +15,5 @@ void test_vld1_lanep16 (void)
   out_poly16x4_t = vld1_lane_p16 (0, arg1_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
index ad59646c8a2..b0cd3bfd9fd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanep8.c
@@ -15,5 +15,5 @@ void test_vld1_lanep8 (void)
   out_poly8x8_t = vld1_lane_p8 (0, arg1_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
index 1d555d99056..3a0b738b588 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes16.c
@@ -15,5 +15,5 @@ void test_vld1_lanes16 (void)
   out_int16x4_t = vld1_lane_s16 (0, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
index 9f22dd797e9..90b790d377d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes32.c
@@ -15,5 +15,5 @@ void test_vld1_lanes32 (void)
   out_int32x2_t = vld1_lane_s32 (0, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
index 6efdf3b1437..890a7f9f104 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_lanes8.c
@@ -15,5 +15,5 @@ void test_vld1_lanes8 (void)
   out_int8x8_t = vld1_lane_s8 (0, arg1_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
index 2b1031e99b7..35090663ae4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu16.c
@@ -15,5 +15,5 @@ void test_vld1_laneu16 (void)
   out_uint16x4_t = vld1_lane_u16 (0, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
index 1b14a36d91b..108dc1e55d9 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu32.c
@@ -15,5 +15,5 @@ void test_vld1_laneu32 (void)
   out_uint32x2_t = vld1_lane_u32 (0, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
index 2c7a86308ff..7cfb5b53d92 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld1_laneu8.c
@@ -15,5 +15,5 @@ void test_vld1_laneu8 (void)
   out_uint8x8_t = vld1_lane_u8 (0, arg1_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
index f1a21796a5d..74f5a7050e6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vld2Q_lanef32 (void)
   out_float32x4x2_t = vld2q_lane_f32 (0, arg1_float32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
index 2fd327ab1f7..a21f5319ba2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vld2Q_lanep16 (void)
   out_poly16x8x2_t = vld2q_lane_p16 (0, arg1_poly16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
index 99470608dab..d9b60cdce75 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vld2Q_lanes16 (void)
   out_int16x8x2_t = vld2q_lane_s16 (0, arg1_int16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
index 8e47f302a83..ad68be41835 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vld2Q_lanes32 (void)
   out_int32x4x2_t = vld2q_lane_s32 (0, arg1_int32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
index 0faa13c84f1..175acbaad19 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vld2Q_laneu16 (void)
   out_uint16x8x2_t = vld2q_lane_u16 (0, arg1_uint16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
index 28a16943135..418a6d2e916 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vld2Q_laneu32 (void)
   out_uint32x4x2_t = vld2q_lane_u32 (0, arg1_uint32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
index a718c36ae1c..f5bb134c863 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanef32.c
@@ -15,5 +15,5 @@ void test_vld2_lanef32 (void)
   out_float32x2x2_t = vld2_lane_f32 (0, arg1_float32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
index 7112bc27681..44af4bedbec 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep16.c
@@ -15,5 +15,5 @@ void test_vld2_lanep16 (void)
   out_poly16x4x2_t = vld2_lane_p16 (0, arg1_poly16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
index 6664d748f7f..e2a40c3ac66 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanep8.c
@@ -15,5 +15,5 @@ void test_vld2_lanep8 (void)
   out_poly8x8x2_t = vld2_lane_p8 (0, arg1_poly8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
index 14d56d33174..3787831c53c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes16.c
@@ -15,5 +15,5 @@ void test_vld2_lanes16 (void)
   out_int16x4x2_t = vld2_lane_s16 (0, arg1_int16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
index 248eddfe2f8..3a40dc55a44 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes32.c
@@ -15,5 +15,5 @@ void test_vld2_lanes32 (void)
   out_int32x2x2_t = vld2_lane_s32 (0, arg1_int32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
index 5e58896e9c0..e6ea04e98ff 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_lanes8.c
@@ -15,5 +15,5 @@ void test_vld2_lanes8 (void)
   out_int8x8x2_t = vld2_lane_s8 (0, arg1_int8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
index 41000909429..13b35447c55 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu16.c
@@ -15,5 +15,5 @@ void test_vld2_laneu16 (void)
   out_uint16x4x2_t = vld2_lane_u16 (0, arg1_uint16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
index 0e996e5e75e..b763dc4802f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu32.c
@@ -15,5 +15,5 @@ void test_vld2_laneu32 (void)
   out_uint32x2x2_t = vld2_lane_u32 (0, arg1_uint32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
index 82f42cf034f..26feb75be4d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld2_laneu8.c
@@ -15,5 +15,5 @@ void test_vld2_laneu8 (void)
   out_uint8x8x2_t = vld2_lane_u8 (0, arg1_uint8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
index f6222249e76..47a71d6336b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vld3Q_lanef32 (void)
   out_float32x4x3_t = vld3q_lane_f32 (0, arg1_float32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
index 9b1a522a4f1..4237f96c5f3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vld3Q_lanep16 (void)
   out_poly16x8x3_t = vld3q_lane_p16 (0, arg1_poly16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
index 54ea8aa7abd..e84f28cd631 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vld3Q_lanes16 (void)
   out_int16x8x3_t = vld3q_lane_s16 (0, arg1_int16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
index ead4afc0156..8533c065531 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vld3Q_lanes32 (void)
   out_int32x4x3_t = vld3q_lane_s32 (0, arg1_int32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
index 80bf49c00c3..96b6a98f53d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vld3Q_laneu16 (void)
   out_uint16x8x3_t = vld3q_lane_u16 (0, arg1_uint16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
index f743d4ee446..8a866f81319 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vld3Q_laneu32 (void)
   out_uint32x4x3_t = vld3q_lane_u32 (0, arg1_uint32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
index 0037d037f2e..7c284f4b63c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanef32.c
@@ -15,5 +15,5 @@ void test_vld3_lanef32 (void)
   out_float32x2x3_t = vld3_lane_f32 (0, arg1_float32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
index 0532d73c8df..61a682a4000 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep16.c
@@ -15,5 +15,5 @@ void test_vld3_lanep16 (void)
   out_poly16x4x3_t = vld3_lane_p16 (0, arg1_poly16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
index 2a170e59fc6..c8b4cbbbe69 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanep8.c
@@ -15,5 +15,5 @@ void test_vld3_lanep8 (void)
   out_poly8x8x3_t = vld3_lane_p8 (0, arg1_poly8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
index 525821eda77..0a7bd0646cf 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes16.c
@@ -15,5 +15,5 @@ void test_vld3_lanes16 (void)
   out_int16x4x3_t = vld3_lane_s16 (0, arg1_int16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
index 54819283927..c3f1680d0e7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes32.c
@@ -15,5 +15,5 @@ void test_vld3_lanes32 (void)
   out_int32x2x3_t = vld3_lane_s32 (0, arg1_int32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
index d3a71346b25..11be2b48753 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_lanes8.c
@@ -15,5 +15,5 @@ void test_vld3_lanes8 (void)
   out_int8x8x3_t = vld3_lane_s8 (0, arg1_int8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
index 773e1c8cea9..62010a639eb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu16.c
@@ -15,5 +15,5 @@ void test_vld3_laneu16 (void)
   out_uint16x4x3_t = vld3_lane_u16 (0, arg1_uint16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
index 8891155b6a3..4102c7a9348 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu32.c
@@ -15,5 +15,5 @@ void test_vld3_laneu32 (void)
   out_uint32x2x3_t = vld3_lane_u32 (0, arg1_uint32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
index e7bc5aeaaef..07936a99ecd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld3_laneu8.c
@@ -15,5 +15,5 @@ void test_vld3_laneu8 (void)
   out_uint8x8x3_t = vld3_lane_u8 (0, arg1_uint8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
index dd2e53ca537..fb1a70f99eb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vld4Q_lanef32 (void)
   out_float32x4x4_t = vld4q_lane_f32 (0, arg1_float32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
index 2f93563195e..cc3e48143af 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vld4Q_lanep16 (void)
   out_poly16x8x4_t = vld4q_lane_p16 (0, arg1_poly16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
index a251a9e9f51..0903fe80ed3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vld4Q_lanes16 (void)
   out_int16x8x4_t = vld4q_lane_s16 (0, arg1_int16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
index bc5f7839d64..09bcd1326b2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vld4Q_lanes32 (void)
   out_int32x4x4_t = vld4q_lane_s32 (0, arg1_int32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
index 6cbc1735637..648f40f953b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vld4Q_laneu16 (void)
   out_uint16x8x4_t = vld4q_lane_u16 (0, arg1_uint16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
index 5e537170439..30054fafaeb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vld4Q_laneu32 (void)
   out_uint32x4x4_t = vld4q_lane_u32 (0, arg1_uint32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
index 55853de96ae..0ddd018a0bb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanef32.c
@@ -15,5 +15,5 @@ void test_vld4_lanef32 (void)
   out_float32x2x4_t = vld4_lane_f32 (0, arg1_float32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
index f87c7725397..68c255921f5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep16.c
@@ -15,5 +15,5 @@ void test_vld4_lanep16 (void)
   out_poly16x4x4_t = vld4_lane_p16 (0, arg1_poly16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
index 9b20711bdf6..5744f5dffc0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanep8.c
@@ -15,5 +15,5 @@ void test_vld4_lanep8 (void)
   out_poly8x8x4_t = vld4_lane_p8 (0, arg1_poly8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
index 004d4d4d789..436309230a9 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes16.c
@@ -15,5 +15,5 @@ void test_vld4_lanes16 (void)
   out_int16x4x4_t = vld4_lane_s16 (0, arg1_int16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
index db4d16c4469..9e69a1dcd2e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes32.c
@@ -15,5 +15,5 @@ void test_vld4_lanes32 (void)
   out_int32x2x4_t = vld4_lane_s32 (0, arg1_int32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
index 45eda061950..99d2353d361 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_lanes8.c
@@ -15,5 +15,5 @@ void test_vld4_lanes8 (void)
   out_int8x8x4_t = vld4_lane_s8 (0, arg1_int8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
index 407bd33100e..2234e8500bf 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu16.c
@@ -15,5 +15,5 @@ void test_vld4_laneu16 (void)
   out_uint16x4x4_t = vld4_lane_u16 (0, arg1_uint16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
index f8c6c757456..5f0ae1cd1d5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu32.c
@@ -15,5 +15,5 @@ void test_vld4_laneu32 (void)
   out_uint32x2x4_t = vld4_lane_u32 (0, arg1_uint32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
index b61b0b1f309..439fe05b0af 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vld4_laneu8.c
@@ -15,5 +15,5 @@ void test_vld4_laneu8 (void)
   out_uint8x8x4_t = vld4_lane_u8 (0, arg1_uint8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vld4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
index b419816e117..d90ff72e3bf 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanef32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_lanef32 (void)
   out_float32x4_t = vmlaq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
index a8c173f60cc..15164a0aefd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes16.c
@@ -17,5 +17,5 @@ void test_vmlaQ_lanes16 (void)
   out_int16x8_t = vmlaq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
index fd7861cda66..7ac9ba90da8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_lanes32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_lanes32 (void)
   out_int32x4_t = vmlaq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
index de1d813a0a2..cf5d636b36f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu16.c
@@ -17,5 +17,5 @@ void test_vmlaQ_laneu16 (void)
   out_uint16x8_t = vmlaq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
index 50221db5483..e6756e291b5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_laneu32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_laneu32 (void)
   out_uint32x4_t = vmlaq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
index 27acc1d7e1a..82a86e1e438 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nf32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_nf32 (void)
   out_float32x4_t = vmlaq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
index 1d73e157870..c3e09dc2b9d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns16.c
@@ -17,5 +17,5 @@ void test_vmlaQ_ns16 (void)
   out_int16x8_t = vmlaq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
index b0872110951..1e2f317d5b9 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_ns32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_ns32 (void)
   out_int32x4_t = vmlaq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
index d7bcd1167cf..1b1db551e7d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu16.c
@@ -17,5 +17,5 @@ void test_vmlaQ_nu16 (void)
   out_uint16x8_t = vmlaq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
index 35ea03509f4..f583f23ea5d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlaQ_nu32.c
@@ -17,5 +17,5 @@ void test_vmlaQ_nu32 (void)
   out_uint32x4_t = vmlaq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
index 1437c2e809f..4977f01e2ad 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanef32.c
@@ -17,5 +17,5 @@ void test_vmla_lanef32 (void)
   out_float32x2_t = vmla_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
index bed00f850ec..4802ac7b4e3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes16.c
@@ -17,5 +17,5 @@ void test_vmla_lanes16 (void)
   out_int16x4_t = vmla_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
index b0b6423d1ef..f301daaf75e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_lanes32.c
@@ -17,5 +17,5 @@ void test_vmla_lanes32 (void)
   out_int32x2_t = vmla_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
index e6b017bbaf8..105b08afe6a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu16.c
@@ -17,5 +17,5 @@ void test_vmla_laneu16 (void)
   out_uint16x4_t = vmla_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
index 8b8e121c130..f25941f3ade 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_laneu32.c
@@ -17,5 +17,5 @@ void test_vmla_laneu32 (void)
   out_uint32x2_t = vmla_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
index 6b63ab78a41..41e4919feab 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nf32.c
@@ -17,5 +17,5 @@ void test_vmla_nf32 (void)
   out_float32x2_t = vmla_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
index a1672a2c782..491dde57395 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns16.c
@@ -17,5 +17,5 @@ void test_vmla_ns16 (void)
   out_int16x4_t = vmla_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
index 2cda9767f83..4596a7eb71d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_ns32.c
@@ -17,5 +17,5 @@ void test_vmla_ns32 (void)
   out_int32x2_t = vmla_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
index 7f3af153519..eeaec90bf30 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu16.c
@@ -17,5 +17,5 @@ void test_vmla_nu16 (void)
   out_uint16x4_t = vmla_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
index 600c6313312..473c9c18594 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmla_nu32.c
@@ -17,5 +17,5 @@ void test_vmla_nu32 (void)
   out_uint32x2_t = vmla_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmla\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
index 1c050e75d06..87f4723870d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes16.c
@@ -17,5 +17,5 @@ void test_vmlal_lanes16 (void)
   out_int32x4_t = vmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
index fd7c8e5f723..82d59ce4274 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_lanes32.c
@@ -17,5 +17,5 @@ void test_vmlal_lanes32 (void)
   out_int64x2_t = vmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
index ef4b452f08d..16eb4be157e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu16.c
@@ -17,5 +17,5 @@ void test_vmlal_laneu16 (void)
   out_uint32x4_t = vmlal_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
index 672c93e8b5e..53688ff577a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_laneu32.c
@@ -17,5 +17,5 @@ void test_vmlal_laneu32 (void)
   out_uint64x2_t = vmlal_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
index 7ab392d2ec2..68fe2c19655 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns16.c
@@ -17,5 +17,5 @@ void test_vmlal_ns16 (void)
   out_int32x4_t = vmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
index 0e74821a939..501521d82bd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_ns32.c
@@ -17,5 +17,5 @@ void test_vmlal_ns32 (void)
   out_int64x2_t = vmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
index 7d47053f1b9..030f31ec046 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu16.c
@@ -17,5 +17,5 @@ void test_vmlal_nu16 (void)
   out_uint32x4_t = vmlal_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
index 43a7a4f11a2..76679179e2f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlal_nu32.c
@@ -17,5 +17,5 @@ void test_vmlal_nu32 (void)
   out_uint64x2_t = vmlal_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlal\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
index b38ad8c26ce..1be6b0fc012 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanef32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_lanef32 (void)
   out_float32x4_t = vmlsq_lane_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
index b91d0c06b45..3e00afc0b97 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes16.c
@@ -17,5 +17,5 @@ void test_vmlsQ_lanes16 (void)
   out_int16x8_t = vmlsq_lane_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
index b5c00c2b286..fa71c31d2cd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_lanes32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_lanes32 (void)
   out_int32x4_t = vmlsq_lane_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
index d2e68e717b8..90559f4af16 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu16.c
@@ -17,5 +17,5 @@ void test_vmlsQ_laneu16 (void)
   out_uint16x8_t = vmlsq_lane_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
index 5f0d70983b9..c01fddb036d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_laneu32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_laneu32 (void)
   out_uint32x4_t = vmlsq_lane_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
index 80fd26e5bcb..bc254397c66 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nf32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_nf32 (void)
   out_float32x4_t = vmlsq_n_f32 (arg0_float32x4_t, arg1_float32x4_t, arg2_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
index f15dadcc960..24443f786a9 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns16.c
@@ -17,5 +17,5 @@ void test_vmlsQ_ns16 (void)
   out_int16x8_t = vmlsq_n_s16 (arg0_int16x8_t, arg1_int16x8_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
index 8a9907432a8..c2307dd7905 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_ns32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_ns32 (void)
   out_int32x4_t = vmlsq_n_s32 (arg0_int32x4_t, arg1_int32x4_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
index 65e6f590484..f170b948281 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu16.c
@@ -17,5 +17,5 @@ void test_vmlsQ_nu16 (void)
   out_uint16x8_t = vmlsq_n_u16 (arg0_uint16x8_t, arg1_uint16x8_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
index 031e099d7b8..6a6ea9e66f2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsQ_nu32.c
@@ -17,5 +17,5 @@ void test_vmlsQ_nu32 (void)
   out_uint32x4_t = vmlsq_n_u32 (arg0_uint32x4_t, arg1_uint32x4_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
index a33fd645dfc..f5672d44009 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanef32.c
@@ -17,5 +17,5 @@ void test_vmls_lanef32 (void)
   out_float32x2_t = vmls_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
index 9b91b36971f..43f9a2487f6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes16.c
@@ -17,5 +17,5 @@ void test_vmls_lanes16 (void)
   out_int16x4_t = vmls_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
index 9b07b063119..5543f3f864e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_lanes32.c
@@ -17,5 +17,5 @@ void test_vmls_lanes32 (void)
   out_int32x2_t = vmls_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
index a1652151b61..9ae8567bca4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu16.c
@@ -17,5 +17,5 @@ void test_vmls_laneu16 (void)
   out_uint16x4_t = vmls_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
index 18695573633..fb486123e00 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_laneu32.c
@@ -17,5 +17,5 @@ void test_vmls_laneu32 (void)
   out_uint32x2_t = vmls_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
index ab004d00026..a6708c127b3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nf32.c
@@ -17,5 +17,5 @@ void test_vmls_nf32 (void)
   out_float32x2_t = vmls_n_f32 (arg0_float32x2_t, arg1_float32x2_t, arg2_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
index 90c59671a7d..7a7a1d49870 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns16.c
@@ -17,5 +17,5 @@ void test_vmls_ns16 (void)
   out_int16x4_t = vmls_n_s16 (arg0_int16x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
index 76c388f0d41..001b3a7508d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_ns32.c
@@ -17,5 +17,5 @@ void test_vmls_ns32 (void)
   out_int32x2_t = vmls_n_s32 (arg0_int32x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
index e708af8c17c..758c036aae2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu16.c
@@ -17,5 +17,5 @@ void test_vmls_nu16 (void)
   out_uint16x4_t = vmls_n_u16 (arg0_uint16x4_t, arg1_uint16x4_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
index dab6323c834..97343f4fcf0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmls_nu32.c
@@ -17,5 +17,5 @@ void test_vmls_nu32 (void)
   out_uint32x2_t = vmls_n_u32 (arg0_uint32x2_t, arg1_uint32x2_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmls\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
index af173e92389..c339703cb41 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes16.c
@@ -17,5 +17,5 @@ void test_vmlsl_lanes16 (void)
   out_int32x4_t = vmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
index 79c592c9d53..c74640fc2b4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_lanes32.c
@@ -17,5 +17,5 @@ void test_vmlsl_lanes32 (void)
   out_int64x2_t = vmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
index 8839078ff7b..24de26e7f61 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu16.c
@@ -17,5 +17,5 @@ void test_vmlsl_laneu16 (void)
   out_uint32x4_t = vmlsl_lane_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
index acad5e9b9d8..d6f7647cfc3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_laneu32.c
@@ -17,5 +17,5 @@ void test_vmlsl_laneu32 (void)
   out_uint64x2_t = vmlsl_lane_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
index 7152246a041..98bd29652f8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns16.c
@@ -17,5 +17,5 @@ void test_vmlsl_ns16 (void)
   out_int32x4_t = vmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
index 70a1afcc8cc..110d3024dab 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_ns32.c
@@ -17,5 +17,5 @@ void test_vmlsl_ns32 (void)
   out_int64x2_t = vmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
index 1dd5e2bf8cd..7c69482f738 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu16.c
@@ -17,5 +17,5 @@ void test_vmlsl_nu16 (void)
   out_uint32x4_t = vmlsl_n_u16 (arg0_uint32x4_t, arg1_uint16x4_t, arg2_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
index a8b1ed8eab3..8ab654d4fa5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmlsl_nu32.c
@@ -17,5 +17,5 @@ void test_vmlsl_nu32 (void)
   out_uint64x2_t = vmlsl_n_u32 (arg0_uint64x2_t, arg1_uint32x2_t, arg2_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmlsl\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
index 2411d9fc09b..c3776dae1ad 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanef32.c
@@ -16,5 +16,5 @@ void test_vmulQ_lanef32 (void)
   out_float32x4_t = vmulq_lane_f32 (arg0_float32x4_t, arg1_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
index c4c8bd56a2b..debe6467c0a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes16.c
@@ -16,5 +16,5 @@ void test_vmulQ_lanes16 (void)
   out_int16x8_t = vmulq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
index 30fc884ab19..3d930e2998e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_lanes32.c
@@ -16,5 +16,5 @@ void test_vmulQ_lanes32 (void)
   out_int32x4_t = vmulq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
index a24a810823a..72e684d2df2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu16.c
@@ -16,5 +16,5 @@ void test_vmulQ_laneu16 (void)
   out_uint16x8_t = vmulq_lane_u16 (arg0_uint16x8_t, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
index b68c1da79f9..bc2abb90ef2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_laneu32.c
@@ -16,5 +16,5 @@ void test_vmulQ_laneu32 (void)
   out_uint32x4_t = vmulq_lane_u32 (arg0_uint32x4_t, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
index 2baa68bf178..ba7362f82e0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nf32.c
@@ -16,5 +16,5 @@ void test_vmulQ_nf32 (void)
   out_float32x4_t = vmulq_n_f32 (arg0_float32x4_t, arg1_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
index 995ddad8168..5ea1b901b26 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns16.c
@@ -16,5 +16,5 @@ void test_vmulQ_ns16 (void)
   out_int16x8_t = vmulq_n_s16 (arg0_int16x8_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
index dbe0acc7a51..b81e3d43fb8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_ns32.c
@@ -16,5 +16,5 @@ void test_vmulQ_ns32 (void)
   out_int32x4_t = vmulq_n_s32 (arg0_int32x4_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
index 7874eaf3380..764445a919a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu16.c
@@ -16,5 +16,5 @@ void test_vmulQ_nu16 (void)
   out_uint16x8_t = vmulq_n_u16 (arg0_uint16x8_t, arg1_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
index 7a7aa0775c6..42579d55336 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmulQ_nu32.c
@@ -16,5 +16,5 @@ void test_vmulQ_nu32 (void)
   out_uint32x4_t = vmulq_n_u32 (arg0_uint32x4_t, arg1_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
index 16cf32a5f91..edec655f5f7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanef32.c
@@ -16,5 +16,5 @@ void test_vmul_lanef32 (void)
   out_float32x2_t = vmul_lane_f32 (arg0_float32x2_t, arg1_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
index 4a6b9e038fc..45ab4020d5b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes16.c
@@ -16,5 +16,5 @@ void test_vmul_lanes16 (void)
   out_int16x4_t = vmul_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
index 6ad3d7e3a21..7c9e250db87 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_lanes32.c
@@ -16,5 +16,5 @@ void test_vmul_lanes32 (void)
   out_int32x2_t = vmul_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
index ac5b83bec6b..cd39f3bd767 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu16.c
@@ -16,5 +16,5 @@ void test_vmul_laneu16 (void)
   out_uint16x4_t = vmul_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
index 67f5299445c..9ae934d29dd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_laneu32.c
@@ -16,5 +16,5 @@ void test_vmul_laneu32 (void)
   out_uint32x2_t = vmul_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
index 5a17822abee..7ffbdaaf1f1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nf32.c
@@ -16,5 +16,5 @@ void test_vmul_nf32 (void)
   out_float32x2_t = vmul_n_f32 (arg0_float32x2_t, arg1_float32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.f32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
index f067da7cd45..56de209c830 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns16.c
@@ -16,5 +16,5 @@ void test_vmul_ns16 (void)
   out_int16x4_t = vmul_n_s16 (arg0_int16x4_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
index 67267e3afc1..118a985b79f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_ns32.c
@@ -16,5 +16,5 @@ void test_vmul_ns32 (void)
   out_int32x2_t = vmul_n_s32 (arg0_int32x2_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
index b6a21422f00..b876df9284f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu16.c
@@ -16,5 +16,5 @@ void test_vmul_nu16 (void)
   out_uint16x4_t = vmul_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
index cf110ba240e..65d9c26e38c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmul_nu32.c
@@ -16,5 +16,5 @@ void test_vmul_nu32 (void)
   out_uint32x2_t = vmul_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmul\.i32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
index 96f2005554e..7e1a7cc72d5 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes16.c
@@ -16,5 +16,5 @@ void test_vmull_lanes16 (void)
   out_int32x4_t = vmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
index 1d6b1313f0b..2842cd23ea1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_lanes32.c
@@ -16,5 +16,5 @@ void test_vmull_lanes32 (void)
   out_int64x2_t = vmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
index a51d1feff6f..558e9fb2994 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu16.c
@@ -16,5 +16,5 @@ void test_vmull_laneu16 (void)
   out_uint32x4_t = vmull_lane_u16 (arg0_uint16x4_t, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
index 06401ef449e..dc53edbea26 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_laneu32.c
@@ -16,5 +16,5 @@ void test_vmull_laneu32 (void)
   out_uint64x2_t = vmull_lane_u32 (arg0_uint32x2_t, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
index b11805b73b5..e3f20992cb2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns16.c
@@ -16,5 +16,5 @@ void test_vmull_ns16 (void)
   out_int32x4_t = vmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
index 2fb0ad4a165..019a7b0894f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_ns32.c
@@ -16,5 +16,5 @@ void test_vmull_ns32 (void)
   out_int64x2_t = vmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
index 5d806c56ebc..c273a083bb2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu16.c
@@ -16,5 +16,5 @@ void test_vmull_nu16 (void)
   out_uint32x4_t = vmull_n_u16 (arg0_uint16x4_t, arg1_uint16_t);
 }
 
-/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.u16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
index 83733f781fe..47f08e89582 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vmull_nu32.c
@@ -16,5 +16,5 @@ void test_vmull_nu32 (void)
   out_uint64x2_t = vmull_n_u32 (arg0_uint32x2_t, arg1_uint32_t);
 }
 
-/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmull\.u32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
index 8dc8079edd8..5189cc93d55 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes16.c
@@ -16,5 +16,5 @@ void test_vqRdmulhQ_lanes16 (void)
   out_int16x8_t = vqrdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
index 69ec1111ea6..f1dbaa7ca74 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_lanes32.c
@@ -16,5 +16,5 @@ void test_vqRdmulhQ_lanes32 (void)
   out_int32x4_t = vqrdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
index ed45df426f4..45e61f93c44 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns16.c
@@ -16,5 +16,5 @@ void test_vqRdmulhQ_ns16 (void)
   out_int16x8_t = vqrdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
index 85715d483be..f709fa797c1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulhQ_ns32.c
@@ -16,5 +16,5 @@ void test_vqRdmulhQ_ns32 (void)
   out_int32x4_t = vqrdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
index a8b54c9eee9..df61af07157 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes16.c
@@ -16,5 +16,5 @@ void test_vqRdmulh_lanes16 (void)
   out_int16x4_t = vqrdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
index 21fa140db23..539c5582b99 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_lanes32.c
@@ -16,5 +16,5 @@ void test_vqRdmulh_lanes32 (void)
   out_int32x2_t = vqrdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
index 43b8bcd39b0..ae33dd1f445 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns16.c
@@ -16,5 +16,5 @@ void test_vqRdmulh_ns16 (void)
   out_int16x4_t = vqrdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
index a8f9798ebd9..3d112491857 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqRdmulh_ns32.c
@@ -16,5 +16,5 @@ void test_vqRdmulh_ns32 (void)
   out_int32x2_t = vqrdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqrdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
index 73606d31bf1..de2d1b75378 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes16.c
@@ -17,5 +17,5 @@ void test_vqdmlal_lanes16 (void)
   out_int32x4_t = vqdmlal_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
index 484408a2941..372af04406d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_lanes32.c
@@ -17,5 +17,5 @@ void test_vqdmlal_lanes32 (void)
   out_int64x2_t = vqdmlal_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
index 30be82bd9ad..f3e5887d1d0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns16.c
@@ -17,5 +17,5 @@ void test_vqdmlal_ns16 (void)
   out_int32x4_t = vqdmlal_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlal\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
index d50cdcbdc2b..d65da1f43b6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlal_ns32.c
@@ -17,5 +17,5 @@ void test_vqdmlal_ns32 (void)
   out_int64x2_t = vqdmlal_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlal\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
index abc75c97990..4db0977de26 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes16.c
@@ -17,5 +17,5 @@ void test_vqdmlsl_lanes16 (void)
   out_int32x4_t = vqdmlsl_lane_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
index 869ef85e96a..a69c149656a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_lanes32.c
@@ -17,5 +17,5 @@ void test_vqdmlsl_lanes32 (void)
   out_int64x2_t = vqdmlsl_lane_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
index d1494fef09e..3b53c524b7a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns16.c
@@ -17,5 +17,5 @@ void test_vqdmlsl_ns16 (void)
   out_int32x4_t = vqdmlsl_n_s16 (arg0_int32x4_t, arg1_int16x4_t, arg2_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlsl\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
index 7e69c2c528e..b337cfbc683 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmlsl_ns32.c
@@ -17,5 +17,5 @@ void test_vqdmlsl_ns32 (void)
   out_int64x2_t = vqdmlsl_n_s32 (arg0_int64x2_t, arg1_int32x2_t, arg2_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmlsl\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
index 7b1488add9d..ffa6f6ec801 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes16.c
@@ -16,5 +16,5 @@ void test_vqdmulhQ_lanes16 (void)
   out_int16x8_t = vqdmulhq_lane_s16 (arg0_int16x8_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
index 4d62aca3b7e..0bc311bc1f3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_lanes32.c
@@ -16,5 +16,5 @@ void test_vqdmulhQ_lanes32 (void)
   out_int32x4_t = vqdmulhq_lane_s32 (arg0_int32x4_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
index e4fdf148518..8c3e418b2f2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns16.c
@@ -16,5 +16,5 @@ void test_vqdmulhQ_ns16 (void)
   out_int16x8_t = vqdmulhq_n_s16 (arg0_int16x8_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
index 81aa6b1eaad..bb6d1d834a1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulhQ_ns32.c
@@ -16,5 +16,5 @@ void test_vqdmulhQ_ns32 (void)
   out_int32x4_t = vqdmulhq_n_s32 (arg0_int32x4_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
index d6cfeb83525..4826ade4846 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes16.c
@@ -16,5 +16,5 @@ void test_vqdmulh_lanes16 (void)
   out_int16x4_t = vqdmulh_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
index 3851404b3bd..c2d7801464d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_lanes32.c
@@ -16,5 +16,5 @@ void test_vqdmulh_lanes32 (void)
   out_int32x2_t = vqdmulh_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
index 7e4449f56d5..1393b26f6f1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns16.c
@@ -16,5 +16,5 @@ void test_vqdmulh_ns16 (void)
   out_int16x4_t = vqdmulh_n_s16 (arg0_int16x4_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
index d3ac25bd18f..b6499f9a848 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmulh_ns32.c
@@ -16,5 +16,5 @@ void test_vqdmulh_ns32 (void)
   out_int32x2_t = vqdmulh_n_s32 (arg0_int32x2_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmulh\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
index 22e2d7f2a53..6967291fec6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes16.c
@@ -16,5 +16,5 @@ void test_vqdmull_lanes16 (void)
   out_int32x4_t = vqdmull_lane_s16 (arg0_int16x4_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
index 064d7426ade..0612e4ea93d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_lanes32.c
@@ -16,5 +16,5 @@ void test_vqdmull_lanes32 (void)
   out_int64x2_t = vqdmull_lane_s32 (arg0_int32x2_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
index 9d519db21f8..3f822ec72ea 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns16.c
@@ -16,5 +16,5 @@ void test_vqdmull_ns16 (void)
   out_int32x4_t = vqdmull_n_s16 (arg0_int16x4_t, arg1_int16_t);
 }
 
-/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmull\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
index 7bd32db85a3..838165bbfee 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqdmull_ns32.c
@@ -16,5 +16,5 @@ void test_vqdmull_ns32 (void)
   out_int64x2_t = vqdmull_n_s32 (arg0_int32x2_t, arg1_int32_t);
 }
 
-/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqdmull\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
index fe93383af75..0b783382321 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs16.c
@@ -9,11 +9,11 @@
 
 void test_vqnegQs16 (void)
 {
-  int16x4_t out_int16x4_t;
-  int16x4_t arg0_int16x4_t;
+  int16x8_t out_int16x8_t;
+  int16x8_t arg0_int16x8_t;
 
-  out_int16x4_t = vqnegq_s16 (arg0_int16x4_t);
+  out_int16x8_t = vqnegq_s16 (arg0_int16x8_t);
 }
 
-/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqneg\.s16\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
index 92809367103..845d04a161b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs32.c
@@ -9,11 +9,11 @@
 
 void test_vqnegQs32 (void)
 {
-  int32x2_t out_int32x2_t;
-  int32x2_t arg0_int32x2_t;
+  int32x4_t out_int32x4_t;
+  int32x4_t arg0_int32x4_t;
 
-  out_int32x2_t = vqnegq_s32 (arg0_int32x2_t);
+  out_int32x4_t = vqnegq_s32 (arg0_int32x4_t);
 }
 
-/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqneg\.s32\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
index fdafe26af21..f9f4b59bf80 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vqnegQs8.c
@@ -9,11 +9,11 @@
 
 void test_vqnegQs8 (void)
 {
-  int8x8_t out_int8x8_t;
-  int8x8_t arg0_int8x8_t;
+  int8x16_t out_int8x16_t;
+  int8x16_t arg0_int8x16_t;
 
-  out_int8x8_t = vqnegq_s8 (arg0_int8x8_t);
+  out_int8x16_t = vqnegq_s8 (arg0_int8x16_t);
 }
 
-/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vqneg\.s8\[ 	\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
index 7f299b66fbe..85eddf2175e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanef32.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanef32 (void)
   out_float32x4_t = vsetq_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
index b0fa79b3282..6ddda055b20 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep16.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanep16 (void)
   out_poly16x8_t = vsetq_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
index fcde7f7765d..9103934d702 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanep8.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanep8 (void)
   out_poly8x16_t = vsetq_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
index 35ea9f31190..602559153cd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes16.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanes16 (void)
   out_int16x8_t = vsetq_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
index 0efbf6ac14c..1bf2f889038 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes32.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanes32 (void)
   out_int32x4_t = vsetq_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
index 15432a9ead1..2695cb8176b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_lanes8.c
@@ -16,5 +16,5 @@ void test_vsetQ_lanes8 (void)
   out_int8x16_t = vsetq_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
index ae152a8d726..03cb673d1cd 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu16.c
@@ -16,5 +16,5 @@ void test_vsetQ_laneu16 (void)
   out_uint16x8_t = vsetq_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
index 6d006342a9b..6f996c65842 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu32.c
@@ -16,5 +16,5 @@ void test_vsetQ_laneu32 (void)
   out_uint32x4_t = vsetq_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
index 0f089addcf5..5227b603524 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vsetQ_laneu8.c
@@ -16,5 +16,5 @@ void test_vsetQ_laneu8 (void)
   out_uint8x16_t = vsetq_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
index 743001ec936..39de233d08c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanef32.c
@@ -16,5 +16,5 @@ void test_vset_lanef32 (void)
   out_float32x2_t = vset_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
index d26762bcc31..1468afee1fe 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep16.c
@@ -16,5 +16,5 @@ void test_vset_lanep16 (void)
   out_poly16x4_t = vset_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
index 9724881e97f..06af3136003 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanep8.c
@@ -16,5 +16,5 @@ void test_vset_lanep8 (void)
   out_poly8x8_t = vset_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
index 1ec47acf693..8bd7696ecf6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes16.c
@@ -16,5 +16,5 @@ void test_vset_lanes16 (void)
   out_int16x4_t = vset_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
index 1eb46636488..fed49b30bc4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes32.c
@@ -16,5 +16,5 @@ void test_vset_lanes32 (void)
   out_int32x2_t = vset_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
index a0c6c5bcc79..593b8ceaeba 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_lanes8.c
@@ -16,5 +16,5 @@ void test_vset_lanes8 (void)
   out_int8x8_t = vset_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
index 2804de4325f..ed05dc7bc4d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu16.c
@@ -16,5 +16,5 @@ void test_vset_laneu16 (void)
   out_uint16x4_t = vset_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.16\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
index c4fa7808d07..96fbc865ccb 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu32.c
@@ -16,5 +16,5 @@ void test_vset_laneu32 (void)
   out_uint32x2_t = vset_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.32\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
index c7a1aa0d44e..ca943111f3c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vset_laneu8.c
@@ -16,5 +16,5 @@ void test_vset_laneu8 (void)
   out_uint8x8_t = vset_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vmov\.8\[ 	\]+\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[rR\]\[0-9\]+!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
index 9ced417f3b4..898d3df7e7c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanef32 (void)
   vst1q_lane_f32 (arg0_float32_t, arg1_float32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
index fe53911c8b2..f63975db9e0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanep16 (void)
   vst1q_lane_p16 (arg0_poly16_t, arg1_poly16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
index 4645f5a1e4d..bf35e6a5f39 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanep8.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanep8 (void)
   vst1q_lane_p8 (arg0_poly8_t, arg1_poly8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
index d8e461f205e..5e48e02fbfe 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanes16 (void)
   vst1q_lane_s16 (arg0_int16_t, arg1_int16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
index 4a6b977de64..2769a79465a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanes32 (void)
   vst1q_lane_s32 (arg0_int32_t, arg1_int32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
index a6c319aba2d..f4e27a868f8 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_lanes8.c
@@ -15,5 +15,5 @@ void test_vst1Q_lanes8 (void)
   vst1q_lane_s8 (arg0_int8_t, arg1_int8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
index a46119fc735..090bb649b20 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vst1Q_laneu16 (void)
   vst1q_lane_u16 (arg0_uint16_t, arg1_uint16x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
index 2d96a3f8878..468effaa28b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vst1Q_laneu32 (void)
   vst1q_lane_u32 (arg0_uint32_t, arg1_uint32x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
index e1556bf213b..c255c0335f1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu8.c
@@ -15,5 +15,5 @@ void test_vst1Q_laneu8 (void)
   vst1q_lane_u8 (arg0_uint8_t, arg1_uint8x16_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
index 4829ed9b65e..933c21ed745 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanef32.c
@@ -15,5 +15,5 @@ void test_vst1_lanef32 (void)
   vst1_lane_f32 (arg0_float32_t, arg1_float32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
index 7cea34e71a3..45f51890160 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep16.c
@@ -15,5 +15,5 @@ void test_vst1_lanep16 (void)
   vst1_lane_p16 (arg0_poly16_t, arg1_poly16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
index 65fc8b718a4..83793352451 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanep8.c
@@ -15,5 +15,5 @@ void test_vst1_lanep8 (void)
   vst1_lane_p8 (arg0_poly8_t, arg1_poly8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
index 89ed7da3e12..509c49facba 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes16.c
@@ -15,5 +15,5 @@ void test_vst1_lanes16 (void)
   vst1_lane_s16 (arg0_int16_t, arg1_int16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
index f3fbed6bfaf..333f778fdaf 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes32.c
@@ -15,5 +15,5 @@ void test_vst1_lanes32 (void)
   vst1_lane_s32 (arg0_int32_t, arg1_int32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
index 4654c70f5d5..0840835f64f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_lanes8.c
@@ -15,5 +15,5 @@ void test_vst1_lanes8 (void)
   vst1_lane_s8 (arg0_int8_t, arg1_int8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
index c07115fae39..f31f0734875 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu16.c
@@ -15,5 +15,5 @@ void test_vst1_laneu16 (void)
   vst1_lane_u16 (arg0_uint16_t, arg1_uint16x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.16\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
index 378996579f0..34d448c54e0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu32.c
@@ -15,5 +15,5 @@ void test_vst1_laneu32 (void)
   vst1_lane_u32 (arg0_uint32_t, arg1_uint32x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.32\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
index ab72ef7a76f..08ba1b81982 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst1_laneu8.c
@@ -15,5 +15,5 @@ void test_vst1_laneu8 (void)
   vst1_lane_u8 (arg0_uint8_t, arg1_uint8x8_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst1\.8\[ 	\]+((\\\{\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]\\\})|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])), \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
index 2116e6678e5..f2c4ebb819c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vst2Q_lanef32 (void)
   vst2q_lane_f32 (arg0_float32_t, arg1_float32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
index dafcb8ebd56..ed1a6f6376e 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vst2Q_lanep16 (void)
   vst2q_lane_p16 (arg0_poly16_t, arg1_poly16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
index 6dc25535650..fd65b819737 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vst2Q_lanes16 (void)
   vst2q_lane_s16 (arg0_int16_t, arg1_int16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
index f663fc837cf..e4e65c03bc7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vst2Q_lanes32 (void)
   vst2q_lane_s32 (arg0_int32_t, arg1_int32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
index 0476a000055..e49a32fb912 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vst2Q_laneu16 (void)
   vst2q_lane_u16 (arg0_uint16_t, arg1_uint16x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
index 21d1cac08d5..5b540a70a60 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vst2Q_laneu32 (void)
   vst2q_lane_u32 (arg0_uint32_t, arg1_uint32x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
index 2bbde24552c..e9ea0632f67 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanef32.c
@@ -15,5 +15,5 @@ void test_vst2_lanef32 (void)
   vst2_lane_f32 (arg0_float32_t, arg1_float32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
index 010602e8780..e35990aadf6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep16.c
@@ -15,5 +15,5 @@ void test_vst2_lanep16 (void)
   vst2_lane_p16 (arg0_poly16_t, arg1_poly16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
index f89e2246eea..253f15d012f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanep8.c
@@ -15,5 +15,5 @@ void test_vst2_lanep8 (void)
   vst2_lane_p8 (arg0_poly8_t, arg1_poly8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
index 3a5b0151c02..e33cc5d5a7a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes16.c
@@ -15,5 +15,5 @@ void test_vst2_lanes16 (void)
   vst2_lane_s16 (arg0_int16_t, arg1_int16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
index bcdef2e3db5..c1edbe10627 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes32.c
@@ -15,5 +15,5 @@ void test_vst2_lanes32 (void)
   vst2_lane_s32 (arg0_int32_t, arg1_int32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
index 850bece6d44..e7b04b96aba 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_lanes8.c
@@ -15,5 +15,5 @@ void test_vst2_lanes8 (void)
   vst2_lane_s8 (arg0_int8_t, arg1_int8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
index 64eaf3f4cf4..30e5c5d49f2 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu16.c
@@ -15,5 +15,5 @@ void test_vst2_laneu16 (void)
   vst2_lane_u16 (arg0_uint16_t, arg1_uint16x4x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
index 4cc682f7772..1bbb09a54b0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu32.c
@@ -15,5 +15,5 @@ void test_vst2_laneu32 (void)
   vst2_lane_u32 (arg0_uint32_t, arg1_uint32x2x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
index 9e45d9a1c83..37009c5bcee 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst2_laneu8.c
@@ -15,5 +15,5 @@ void test_vst2_laneu8 (void)
   vst2_lane_u8 (arg0_uint8_t, arg1_uint8x8x2_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst2\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
index 138e45b1235..2270b3b2a69 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vst3Q_lanef32 (void)
   vst3q_lane_f32 (arg0_float32_t, arg1_float32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
index 0e4830c2aa3..e52ad3100c0 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vst3Q_lanep16 (void)
   vst3q_lane_p16 (arg0_poly16_t, arg1_poly16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
index 7c752e94ca6..4344836edd4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vst3Q_lanes16 (void)
   vst3q_lane_s16 (arg0_int16_t, arg1_int16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
index 23410426005..97b3f6309c1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vst3Q_lanes32 (void)
   vst3q_lane_s32 (arg0_int32_t, arg1_int32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
index 294acf3e318..2742321cd22 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vst3Q_laneu16 (void)
   vst3q_lane_u16 (arg0_uint16_t, arg1_uint16x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
index 58312278e1a..03897505bf7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vst3Q_laneu32 (void)
   vst3q_lane_u32 (arg0_uint32_t, arg1_uint32x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
index f5bb8df4b4c..c9ee7b63184 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanef32.c
@@ -15,5 +15,5 @@ void test_vst3_lanef32 (void)
   vst3_lane_f32 (arg0_float32_t, arg1_float32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
index 5a140ac2250..4987e3f1bd4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep16.c
@@ -15,5 +15,5 @@ void test_vst3_lanep16 (void)
   vst3_lane_p16 (arg0_poly16_t, arg1_poly16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
index 7bc57fd8be7..d0154e5f88d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanep8.c
@@ -15,5 +15,5 @@ void test_vst3_lanep8 (void)
   vst3_lane_p8 (arg0_poly8_t, arg1_poly8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
index 8c1d12667fa..e1b66399bb9 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes16.c
@@ -15,5 +15,5 @@ void test_vst3_lanes16 (void)
   vst3_lane_s16 (arg0_int16_t, arg1_int16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
index 107ddc5c2a3..85697d01153 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes32.c
@@ -15,5 +15,5 @@ void test_vst3_lanes32 (void)
   vst3_lane_s32 (arg0_int32_t, arg1_int32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
index a201ad3ef7c..94d46049a77 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_lanes8.c
@@ -15,5 +15,5 @@ void test_vst3_lanes8 (void)
   vst3_lane_s8 (arg0_int8_t, arg1_int8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
index 55e6ac8126a..05d8fd883d1 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu16.c
@@ -15,5 +15,5 @@ void test_vst3_laneu16 (void)
   vst3_lane_u16 (arg0_uint16_t, arg1_uint16x4x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
index 2bc18be5761..74aac1cccfa 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu32.c
@@ -15,5 +15,5 @@ void test_vst3_laneu32 (void)
   vst3_lane_u32 (arg0_uint32_t, arg1_uint32x2x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
index 675055b7ead..14c6c7e7749 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst3_laneu8.c
@@ -15,5 +15,5 @@ void test_vst3_laneu8 (void)
   vst3_lane_u8 (arg0_uint8_t, arg1_uint8x8x3_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst3\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
index 5504f994236..42c608d1f2f 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanef32.c
@@ -15,5 +15,5 @@ void test_vst4Q_lanef32 (void)
   vst4q_lane_f32 (arg0_float32_t, arg1_float32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
index 5a2889928fd..d5bb66e6b69 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanep16.c
@@ -15,5 +15,5 @@ void test_vst4Q_lanep16 (void)
   vst4q_lane_p16 (arg0_poly16_t, arg1_poly16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
index 4ecc9aaa22f..5ab89e1e309 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes16.c
@@ -15,5 +15,5 @@ void test_vst4Q_lanes16 (void)
   vst4q_lane_s16 (arg0_int16_t, arg1_int16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
index b5cf952156c..703494a3566 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_lanes32.c
@@ -15,5 +15,5 @@ void test_vst4Q_lanes32 (void)
   vst4q_lane_s32 (arg0_int32_t, arg1_int32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
index 35cbafde219..47cd12991f4 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu16.c
@@ -15,5 +15,5 @@ void test_vst4Q_laneu16 (void)
   vst4q_lane_u16 (arg0_uint16_t, arg1_uint16x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
index ddd176192d4..f5a06f24982 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4Q_laneu32.c
@@ -15,5 +15,5 @@ void test_vst4Q_laneu32 (void)
   vst4q_lane_u32 (arg0_uint32_t, arg1_uint32x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
index 34a3729b0f2..a5bc41df47a 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanef32.c
@@ -15,5 +15,5 @@ void test_vst4_lanef32 (void)
   vst4_lane_f32 (arg0_float32_t, arg1_float32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
index 43a0d57f017..0a494fceb8c 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep16.c
@@ -15,5 +15,5 @@ void test_vst4_lanep16 (void)
   vst4_lane_p16 (arg0_poly16_t, arg1_poly16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
index 5894da3b4f7..d5eab38b149 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanep8.c
@@ -15,5 +15,5 @@ void test_vst4_lanep8 (void)
   vst4_lane_p8 (arg0_poly8_t, arg1_poly8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
index 25f856d953f..02f1280b77b 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes16.c
@@ -15,5 +15,5 @@ void test_vst4_lanes16 (void)
   vst4_lane_s16 (arg0_int16_t, arg1_int16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
index 03122dd27a1..f4246c65a6d 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes32.c
@@ -15,5 +15,5 @@ void test_vst4_lanes32 (void)
   vst4_lane_s32 (arg0_int32_t, arg1_int32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
index 9ce251295a8..f7532d20bd3 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_lanes8.c
@@ -15,5 +15,5 @@ void test_vst4_lanes8 (void)
   vst4_lane_s8 (arg0_int8_t, arg1_int8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
index c88df487c4c..426ae8cbcb6 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu16.c
@@ -15,5 +15,5 @@ void test_vst4_laneu16 (void)
   vst4_lane_u16 (arg0_uint16_t, arg1_uint16x4x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.16\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
index 0ffe8d09a87..e073e875bc7 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu32.c
@@ -15,5 +15,5 @@ void test_vst4_laneu32 (void)
   vst4_lane_u32 (arg0_uint32_t, arg1_uint32x2x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.32\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
 
diff --git a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
index c9d1fee512d..0846f663287 100644
--- a/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
+++ b/gcc/testsuite/gcc.target/arm/neon/vst4_laneu8.c
@@ -15,5 +15,5 @@ void test_vst4_laneu8 (void)
   vst4_lane_u8 (arg0_uint8_t, arg1_uint8x8x4_t, 1);
 }
 
-/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\], \[dD\]\[0-9\]+\\\[\[0-9\]\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { scan-assembler "vst4\.8\[ 	\]+\\\{((\[dD\]\[0-9\]+\\\[\[0-9\]+\\\]-\[dD\]\[0-9\]+\\\[\[0-9\]+\\\])|(\[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\], \[dD\]\[0-9\]+\\\[\[0-9\]+\\\]))\\\}, \\\[\[rR\]\[0-9\]+\\\]!?\(\[ 	\]+@\[a-zA-Z0-9 \]+\)?\n" } } */