Convert all of Sparc scheduling to DFA

	* config/sparc/sparc.md: Kill all define_function_unit
	directives and replace with DFA equivalent.
	* config/sparc/sparc.c (ultrasparc_adjust_cost,
	mark_ultrasparc_pipeline_state, ultra_cmove_results_ready_p,
	ultra_fpmode_conflict_exists, ultra_find_type,
	ultra_build_types_avail, ultra_flush_pipeline,
	ultra_rescan_pipeline_state, ultrasparc_sched_reorder,
	ultrasparc_variable_issue, ultrasparc_sched_init,
	sparc_variable_issue, sparc_sched_reorder, ultra_code_from_mask,
	ultra_schedule_insn, ultra_code_names, ultra_pipe_hist,
	ultra_cur_hist, ultra_cycles_elapsed): Kill.
	(sparc_use_dfa_pipeline_interface, sparc_use_sched_lookahead,
	ultrasparc_store_bypass_p): New.
	* config/sparc/sparc-protos.h (ultrasparc_store_bypass_p):
	Declare.


git-svn-id: https://gcc.gnu.org/svn/gcc/branches/dfa-branch@45802 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 806 insertions, 1791 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5f0ca9635c1..93d5c64d5ee 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,22 @@
+2001-09-25  David S. Miller  <davem@redhat.com>
+
+	Convert all of Sparc scheduling to DFA
+	* config/sparc/sparc.md: Kill all define_function_unit
+	directives and replace with DFA equivalent.
+	* config/sparc/sparc.c (ultrasparc_adjust_cost,
+	mark_ultrasparc_pipeline_state, ultra_cmove_results_ready_p,
+	ultra_fpmode_conflict_exists, ultra_find_type,
+	ultra_build_types_avail, ultra_flush_pipeline,
+	ultra_rescan_pipeline_state, ultrasparc_sched_reorder,
+	ultrasparc_variable_issue, ultrasparc_sched_init,
+	sparc_variable_issue, sparc_sched_reorder, ultra_code_from_mask,
+	ultra_schedule_insn, ultra_code_names, ultra_pipe_hist,
+	ultra_cur_hist, ultra_cycles_elapsed): Kill.
+	(sparc_use_dfa_pipeline_interface, sparc_use_sched_lookahead,
+	ultrasparc_store_bypass_p): New.
+	* config/sparc/sparc-protos.h (ultrasparc_store_bypass_p):
+	Declare.
+
 2001-09-24  David S. Miller  <davem@redhat.com>
 
 	* haifa-sched.c (ready_remove): Fix thinko, we want to copy around
@@ -15,6 +34,11 @@
 	(generate): Remove printing meease about creation of
 	automata.
 
+2001-09-05  David S. Miller  <davem@redhat.com>
+
+	* config/sparc/linux.h: Set CPLUSPLUS_CPP_SPEC.
+	* config/sparc/linux64.h: Likewise.
+
 2001-08-31  Vladimir Makarov  <vmakarov@redhat.com>
 
 	* haifa-sched.c (insn_cost, schedule_insn, queue_to_ready,
diff --git a/gcc/config/sparc/linux.h b/gcc/config/sparc/linux.h
index f85409b66c9..44aa462ca61 100644
--- a/gcc/config/sparc/linux.h
+++ b/gcc/config/sparc/linux.h
@@ -70,6 +70,10 @@ Boston, MA 02111-1307, USA.  */
 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
 "
 
+/* The GNU C++ standard library requires that these macros be defined.  */
+#undef CPLUSPLUS_CPP_SPEC
+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
+
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (sparc GNU/Linux with ELF)");
 
diff --git a/gcc/config/sparc/linux64.h b/gcc/config/sparc/linux64.h
index d72f57f08ce..675b81d9c03 100644
--- a/gcc/config/sparc/linux64.h
+++ b/gcc/config/sparc/linux64.h
@@ -124,6 +124,10 @@ Boston, MA 02111-1307, USA.  */
 
 #endif
 
+/* The GNU C++ standard library requires that these macros be defined.  */
+#undef CPLUSPLUS_CPP_SPEC
+#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
+
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (sparc64 GNU/Linux with ELF)");
 
diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h
index fe658296fb5..44cf2326f51 100644
--- a/gcc/config/sparc/sparc-protos.h
+++ b/gcc/config/sparc/sparc-protos.h
@@ -118,6 +118,8 @@ extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *));
 extern int sparc_check_64 PARAMS ((rtx, rtx));
 extern int sparc_return_peephole_ok PARAMS ((rtx, rtx));
 extern rtx gen_df_reg PARAMS ((rtx, int));
+/* Used for DFA scheduling when cpu is ultrasparc.  */
+extern int ultrasparc_store_bypass_p PARAMS ((rtx, rtx));
 #endif /* RTX_CODE */
 
 #endif /* __SPARC_PROTOS_H__ */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index ca412b73fd1..bca2463f090 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -142,21 +142,13 @@ static int function_arg_slotno	PARAMS ((const CUMULATIVE_ARGS *,
 
 static int supersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
 static int hypersparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
-static int ultrasparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
 
 static void sparc_output_addr_vec PARAMS ((rtx));
 static void sparc_output_addr_diff_vec PARAMS ((rtx));
 static void sparc_output_deferred_case_vectors PARAMS ((void));
 static void sparc_add_gc_roots    PARAMS ((void));
-static void mark_ultrasparc_pipeline_state PARAMS ((void *));
 static int check_return_regs PARAMS ((rtx));
 static int epilogue_renumber PARAMS ((rtx *, int));
-static int ultra_cmove_results_ready_p PARAMS ((rtx));
-static int ultra_fpmode_conflict_exists PARAMS ((enum machine_mode));
-static rtx *ultra_find_type PARAMS ((int, rtx *, int));
-static void ultra_build_types_avail PARAMS ((rtx *, int));
-static void ultra_flush_pipeline PARAMS ((void));
-static void ultra_rescan_pipeline_state PARAMS ((rtx *, int));
 static int set_extends PARAMS ((rtx));
 static void output_restore_regs PARAMS ((FILE *, int));
 static void sparc_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
@@ -169,15 +161,11 @@ static void sparc_nonflat_function_prologue PARAMS ((FILE *, HOST_WIDE_INT,
 						     int));
 static void sparc_elf_asm_named_section PARAMS ((const char *, unsigned int));
 
-static void ultrasparc_sched_reorder PARAMS ((FILE *, int, rtx *, int));
-static int ultrasparc_variable_issue PARAMS ((rtx));
-static void ultrasparc_sched_init PARAMS ((void));
-
 static int sparc_adjust_cost PARAMS ((rtx, rtx, rtx, int));
 static int sparc_issue_rate PARAMS ((void));
-static int sparc_variable_issue PARAMS ((FILE *, int, rtx, int));
 static void sparc_sched_init PARAMS ((FILE *, int, int));
-static int sparc_sched_reorder PARAMS ((FILE *, int, rtx *, int *, int));
+static int sparc_use_dfa_pipeline_interface PARAMS ((void));
+static int sparc_use_sched_lookahead PARAMS ((void));
 
 /* Option handling.  */
 
@@ -210,12 +198,12 @@ enum processor_type sparc_cpu;
 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
 #undef TARGET_SCHED_ISSUE_RATE
 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
-#undef TARGET_SCHED_VARIABLE_ISSUE
-#define TARGET_SCHED_VARIABLE_ISSUE sparc_variable_issue
 #undef TARGET_SCHED_INIT
 #define TARGET_SCHED_INIT sparc_sched_init
-#undef TARGET_SCHED_REORDER
-#define TARGET_SCHED_REORDER sparc_sched_reorder
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
+#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
+#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
 
 struct gcc_target targetm = TARGET_INITIALIZER;
 
@@ -7185,158 +7173,6 @@ hypersparc_adjust_cost (insn, link, dep_insn, cost)
 }
 
 static int
-ultrasparc_adjust_cost (insn, link, dep_insn, cost)
-     rtx insn;
-     rtx link;
-     rtx dep_insn;
-     int cost;
-{
-  enum attr_type insn_type, dep_type;
-  rtx pat = PATTERN(insn);
-  rtx dep_pat = PATTERN (dep_insn);
-
-  if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
-    return cost;
-
-  insn_type = get_attr_type (insn);
-  dep_type = get_attr_type (dep_insn);
-
-  /* Nothing issues in parallel with integer multiplies, so
-     mark as zero cost since the scheduler can not do anything
-     about it.  */
-  if (insn_type == TYPE_IMUL)
-    return 0;
-
-#define SLOW_FP(dep_type) \
-(dep_type == TYPE_FPSQRTS || dep_type == TYPE_FPSQRTD || \
- dep_type == TYPE_FPDIVS || dep_type == TYPE_FPDIVD)
-
-  switch (REG_NOTE_KIND (link))
-    {
-    case 0:
-      /* Data dependency; DEP_INSN writes a register that INSN reads some
-	 cycles later.  */
-
-      if (dep_type == TYPE_CMOVE)
-	{
-	  /* Instructions that read the result of conditional moves cannot
-	     be in the same group or the following group.  */
-	  return cost + 1;
-	}
-
-      switch (insn_type)
-	{
-	  /* UltraSPARC can dual issue a store and an instruction setting
-	     the value stored, except for divide and square root.  */
-	case TYPE_FPSTORE:
-	  if (! SLOW_FP (dep_type))
-	    return 0;
-	  return cost;
-
-	case TYPE_STORE:
-	  if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
-	    return cost;
-
-	  if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
-	    /* The dependency between the two instructions is on the data
-	       that is being stored.  Assume that the address of the store
-	       is not also dependent.  */
-	    return 0;
-	  return cost;
-
-	case TYPE_LOAD:
-	case TYPE_SLOAD:
-	case TYPE_FPLOAD:
-	  /* A load does not return data until at least 11 cycles after
-	     a store to the same location.  3 cycles are accounted for
-	     in the load latency; add the other 8 here.  */
-	  if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
-	    {
-	      /* If the addresses are not equal this may be a false
-		 dependency because pointer aliasing could not be
-		 determined.  Add only 2 cycles in that case.  2 is
-		 an arbitrary compromise between 8, which would cause
-		 the scheduler to generate worse code elsewhere to
-		 compensate for a dependency which might not really
-		 exist, and 0.  */
-	      if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
-		  || GET_CODE (SET_SRC (pat)) != MEM
-		  || GET_CODE (SET_DEST (dep_pat)) != MEM
-		  || ! rtx_equal_p (XEXP (SET_SRC (pat), 0),
-				    XEXP (SET_DEST (dep_pat), 0)))
-		return cost + 2;
-
-	      return cost + 8;
-	    }
-	  return cost;
-
-	case TYPE_BRANCH:
-	  /* Compare to branch latency is 0.  There is no benefit from
-	     separating compare and branch.  */
-	  if (dep_type == TYPE_COMPARE)
-	    return 0;
-	  /* Floating point compare to branch latency is less than
-	     compare to conditional move.  */
-	  if (dep_type == TYPE_FPCMP)
-	    return cost - 1;
-	  return cost;
-
-	case TYPE_FPCMOVE:
-	  /* FMOVR class instructions can not issue in the same cycle
-	     or the cycle after an instruction which writes any
-	     integer register.  Model this as cost 2 for dependent
-	     instructions.  */
-	  if ((dep_type == TYPE_IALU || dep_type == TYPE_UNARY
-	       || dep_type == TYPE_BINARY)
-	      && cost < 2)
-	    return 2;
-	  /* Otherwise check as for integer conditional moves. */
-
-	case TYPE_CMOVE:
-	  /* Conditional moves involving integer registers wait until
-	     3 cycles after loads return data.  The interlock applies
-	     to all loads, not just dependent loads, but that is hard
-	     to model.  */
-	  if (dep_type == TYPE_LOAD || dep_type == TYPE_SLOAD)
-	    return cost + 3;
-	  return cost;
-
-	default:
-	  break;
-	}
-      break;
-
-    case REG_DEP_ANTI:
-      /* Divide and square root lock destination registers for full latency. */
-      if (! SLOW_FP (dep_type))
-	return 0;
-      break;
-
-    case REG_DEP_OUTPUT:
-      /* IEU and FPU instruction that have the same destination
-	 register cannot be grouped together.  */
-      return cost + 1;
-
-    default:
-      break;
-    }
-
-  /* Other costs not accounted for:
-     - Single precision floating point loads lock the other half of
-       the even/odd register pair.
-     - Several hazards associated with ldd/std are ignored because these
-       instructions are rarely generated for V9.
-     - The floating point pipeline can not have both a single and double
-       precision operation active at the same time.  Format conversions
-       and graphics instructions are given honorary double precision status.
-     - call and jmpl are always the first instruction in a group.  */
-
-  return cost;
-
-#undef SLOW_FP
-}
-
-static int
 sparc_adjust_cost(insn, link, dep, cost)
      rtx insn;
      rtx link;
@@ -7352,776 +7188,110 @@ sparc_adjust_cost(insn, link, dep, cost)
     case PROCESSOR_SPARCLITE86X:
       cost = hypersparc_adjust_cost (insn, link, dep, cost);
       break;
-    case PROCESSOR_ULTRASPARC:
-      cost = ultrasparc_adjust_cost (insn, link, dep, cost);
-      break;
     default:
       break;
     }
   return cost;
 }
 
-/* This describes the state of the UltraSPARC pipeline during
-   instruction scheduling.  */
-
-#define TMASK(__x)	((unsigned)1 << ((int)(__x)))
-#define UMASK(__x)	((unsigned)1 << ((int)(__x)))
-
-enum ultra_code { NONE=0, /* no insn at all				*/
-		  IEU0,   /* shifts and conditional moves		*/
-		  IEU1,   /* condition code setting insns, calls+jumps	*/
-		  IEUN,   /* all other single cycle ieu insns		*/
-		  LSU,    /* loads and stores				*/
-		  CTI,    /* branches					*/
-		  FPM,    /* FPU pipeline 1, multiplies and divides	*/
-		  FPA,    /* FPU pipeline 2, all other operations	*/
-		  SINGLE, /* single issue instructions			*/
-		  NUM_ULTRA_CODES };
-
-static enum ultra_code ultra_code_from_mask PARAMS ((int));
-static void ultra_schedule_insn PARAMS ((rtx *, rtx *, int, enum ultra_code));
-
-static const char *ultra_code_names[NUM_ULTRA_CODES] = {
-  "NONE", "IEU0", "IEU1", "IEUN", "LSU", "CTI",
-  "FPM", "FPA", "SINGLE" };
-
-struct ultrasparc_pipeline_state {
-  /* The insns in this group.  */
-  rtx group[4];
-
-  /* The code for each insn.  */
-  enum ultra_code codes[4];
-
-  /* Which insns in this group have been committed by the
-     scheduler.  This is how we determine how many more
-     can issue this cycle.  */
-  char commit[4];
-
-  /* How many insns in this group.  */
-  char group_size;
-
-  /* Mask of free slots still in this group.  */
-  char free_slot_mask;
-
-  /* The slotter uses the following to determine what other
-     insn types can still make their way into this group.  */
-  char contents [NUM_ULTRA_CODES];
-  char num_ieu_insns;
-};
-
-#define ULTRA_NUM_HIST	8
-static struct ultrasparc_pipeline_state ultra_pipe_hist[ULTRA_NUM_HIST];
-static int ultra_cur_hist;
-static int ultra_cycles_elapsed;
-
-#define ultra_pipe	(ultra_pipe_hist[ultra_cur_hist])
-
-/* Given TYPE_MASK compute the ultra_code it has.  */
-static enum ultra_code
-ultra_code_from_mask (type_mask)
-     int type_mask;
-{
-  if (type_mask & (TMASK (TYPE_SHIFT) | TMASK (TYPE_CMOVE)))
-    return IEU0;
-  else if (type_mask & (TMASK (TYPE_COMPARE) |
-			TMASK (TYPE_CALL) |
-			TMASK (TYPE_SIBCALL) |
-			TMASK (TYPE_UNCOND_BRANCH)))
-    return IEU1;
-  else if (type_mask & (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-			TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY)))
-    return IEUN;
-  else if (type_mask & (TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
-			TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
-			TMASK (TYPE_FPSTORE)))
-    return LSU;
-  else if (type_mask & (TMASK (TYPE_FPMUL) | TMASK (TYPE_FPDIVS) |
-			TMASK (TYPE_FPDIVD) | TMASK (TYPE_FPSQRTS) |
-			TMASK (TYPE_FPSQRTD)))
-    return FPM;
-  else if (type_mask & (TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
-			TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)))
-    return FPA;
-  else if (type_mask & TMASK (TYPE_BRANCH))
-    return CTI;
-
-  return SINGLE;
-}
-
-/* Check INSN (a conditional move) and make sure that it's
-   results are available at this cycle.  Return 1 if the
-   results are in fact ready.  */
-static int
-ultra_cmove_results_ready_p (insn)
-     rtx insn;
+static void
+sparc_sched_init (dump, sched_verbose, max_ready)
+     FILE *dump ATTRIBUTE_UNUSED;
+     int sched_verbose ATTRIBUTE_UNUSED;
+     int max_ready ATTRIBUTE_UNUSED;
 {
-  struct ultrasparc_pipeline_state *up;
-  int entry, slot;
-
-  /* If this got dispatched in the previous
-     group, the results are not ready.  */
-  entry = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
-  up = &ultra_pipe_hist[entry];
-  slot = 4;
-  while (--slot >= 0)
-    if (up->group[slot] == insn)
-      return 0;
-
-  return 1;
 }
-
-/* Walk backwards in pipeline history looking for FPU
-   operations which use a mode different than FPMODE and
-   will create a stall if an insn using FPMODE were to be
-   dispatched this cycle.  */
+  
 static int
-ultra_fpmode_conflict_exists (fpmode)
-     enum machine_mode fpmode;
+sparc_use_dfa_pipeline_interface ()
 {
-  int hist_ent;
-  int hist_lim;
-
-  hist_ent = (ultra_cur_hist - 1) & (ULTRA_NUM_HIST - 1);
-  if (ultra_cycles_elapsed < 4)
-    hist_lim = ultra_cycles_elapsed;
-  else
-    hist_lim = 4;
-  while (hist_lim > 0)
-    {
-      struct ultrasparc_pipeline_state *up = &ultra_pipe_hist[hist_ent];
-      int slot = 4;
-
-      while (--slot >= 0)
-	{
-	  rtx insn = up->group[slot];
-	  enum machine_mode this_mode;
-	  rtx pat;
-
-	  if (! insn
-	      || GET_CODE (insn) != INSN
-	      || (pat = PATTERN (insn)) == 0
-	      || GET_CODE (pat) != SET)
-	    continue;
-
-	  this_mode = GET_MODE (SET_DEST (pat));
-	  if ((this_mode != SFmode
-	       && this_mode != DFmode)
-	      || this_mode == fpmode)
-	    continue;
-
-	  /* If it is not FMOV, FABS, FNEG, FDIV, or FSQRT then
-	     we will get a stall.  Loads and stores are independant
-	     of these rules.  */
-	  if (GET_CODE (SET_SRC (pat)) != ABS
-	      && GET_CODE (SET_SRC (pat)) != NEG
-	      && ((TMASK (get_attr_type (insn)) &
-		   (TMASK (TYPE_FPDIVS) | TMASK (TYPE_FPDIVD) |
-		    TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPSQRTS) |
-		    TMASK (TYPE_FPSQRTD) |
-                    TMASK (TYPE_LOAD) | TMASK (TYPE_STORE))) == 0))
-	    return 1;
-	}
-      hist_lim--;
-      hist_ent = (hist_ent - 1) & (ULTRA_NUM_HIST - 1);
-    }
-
-  /* No conflicts, safe to dispatch.  */
+  if ((1 << sparc_cpu) &
+      ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
+       (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
+       (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701)))
+    return 1;
   return 0;
 }
 
-/* Find an instruction in LIST which has one of the
-   type attributes enumerated in TYPE_MASK.  START
-   says where to begin the search.
-
-   NOTE: This scheme depends upon the fact that we
-         have less than 32 distinct type attributes.  */
-
-static int ultra_types_avail;
-
-static rtx *
-ultra_find_type (type_mask, list, start)
-     int type_mask;
-     rtx *list;
-     int start;
+static int
+sparc_use_sched_lookahead ()
 {
-  int i;
-
-  /* Short circuit if no such insn exists in the ready
-     at the moment.  */
-  if ((type_mask & ultra_types_avail) == 0)
-    return 0;
-
-  for (i = start; i >= 0; i--)
-    {
-      rtx insn = list[i];
-
-      if (recog_memoized (insn) >= 0
-	  && (TMASK(get_attr_type (insn)) & type_mask))
-	{
-	  enum machine_mode fpmode = SFmode;
-	  rtx pat = 0;
-	  int slot;
-	  int check_depend = 0;
-	  int check_fpmode_conflict = 0;
-
-	  if (GET_CODE (insn) == INSN
-	      && (pat = PATTERN(insn)) != 0
-	      && GET_CODE (pat) == SET
-	      && !(type_mask & (TMASK (TYPE_STORE) |
-				TMASK (TYPE_FPSTORE))))
-	    {
-	      check_depend = 1;
-	      if (GET_MODE (SET_DEST (pat)) == SFmode
-		  || GET_MODE (SET_DEST (pat)) == DFmode)
-		{
-		  fpmode = GET_MODE (SET_DEST (pat));
-		  check_fpmode_conflict = 1;
-		}
-	    }
-
-	  slot = 4;
-	  while(--slot >= 0)
-	    {
-	      rtx slot_insn = ultra_pipe.group[slot];
-	      rtx slot_pat;
-
-	      /* Already issued, bad dependency, or FPU
-		 mode conflict.  */
-	      if (slot_insn != 0
-		  && (slot_pat = PATTERN (slot_insn)) != 0
-		  && ((insn == slot_insn)
-		      || (check_depend == 1
-			  && GET_CODE (slot_insn) == INSN
-			  && GET_CODE (slot_pat) == SET
-			  && ((GET_CODE (SET_DEST (slot_pat)) == REG
-			       && GET_CODE (SET_SRC (pat)) == REG
-			       && REGNO (SET_DEST (slot_pat)) ==
-			            REGNO (SET_SRC (pat)))
-			      || (GET_CODE (SET_DEST (slot_pat)) == SUBREG
-				  && GET_CODE (SET_SRC (pat)) == SUBREG
-				  && REGNO (SUBREG_REG (SET_DEST (slot_pat))) ==
-				       REGNO (SUBREG_REG (SET_SRC (pat)))
-				  && SUBREG_BYTE (SET_DEST (slot_pat)) ==
-				       SUBREG_BYTE (SET_SRC (pat)))))
-		      || (check_fpmode_conflict == 1
-			  && GET_CODE (slot_insn) == INSN
-			  && GET_CODE (slot_pat) == SET
-			  && (GET_MODE (SET_DEST (slot_pat)) == SFmode
-			      || GET_MODE (SET_DEST (slot_pat)) == DFmode)
-			  && GET_MODE (SET_DEST (slot_pat)) != fpmode)))
-		goto next;
-	    }
-
-	  /* Check for peculiar result availability and dispatch
-	     interference situations.  */
-	  if (pat != 0
-	      && ultra_cycles_elapsed > 0)
-	    {
-	      rtx link;
-
-	      for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
-		{
-		  rtx link_insn = XEXP (link, 0);
-		  if (GET_CODE (link_insn) == INSN
-		      && recog_memoized (link_insn) >= 0
-		      && (TMASK (get_attr_type (link_insn)) &
-			  (TMASK (TYPE_CMOVE) | TMASK (TYPE_FPCMOVE)))
-		      && ! ultra_cmove_results_ready_p (link_insn))
-		    goto next;
-		}
-
-	      if (check_fpmode_conflict
-		  && ultra_fpmode_conflict_exists (fpmode))
-		goto next;
-	    }
-
-	  return &list[i];
-	}
-    next:
-      ;
-    }
+  if (sparc_cpu == PROCESSOR_ULTRASPARC)
+    return 12;
+  if ((1 << sparc_cpu) &
+      ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
+       (1 << PROCESSOR_SPARCLITE86X)))
+    return 6;
   return 0;
 }
 
-static void
-ultra_build_types_avail (ready, n_ready)
-  rtx *ready;
-  int n_ready;
-{
-  int i = n_ready - 1;
+/* Make sure that the dependency between OUT_INSN and
+   IN_INSN (a store) is on the store data not the address
+   operand(s) of the store.  */
 
-  ultra_types_avail = 0;
-  while(i >= 0)
-    {
-      rtx insn = ready[i];
-
-      if (recog_memoized (insn) >= 0)
-	ultra_types_avail |= TMASK (get_attr_type (insn));
-
-      i -= 1;
-    }
-}
+int
+ultrasparc_store_bypass_p (out_insn, in_insn)
+     rtx out_insn, in_insn;
+{
+  rtx out_pat, in_pat;
+  unsigned int regno;
 
-/* Place insn pointed to my IP into the pipeline.
-   Make element THIS of READY be that insn if it
-   is not already.  TYPE indicates the pipeline class
-   this insn falls into.  */
-static void
-ultra_schedule_insn (ip, ready, this, type)
-     rtx *ip;
-     rtx *ready;
-     int this;
-     enum ultra_code type;
-{
-  int pipe_slot;
-  char mask = ultra_pipe.free_slot_mask;
-  rtx temp;
+  if (recog_memoized (in_insn) < 0)
+    return 0;
 
-  /* Obtain free slot.  */
-  for (pipe_slot = 0; pipe_slot < 4; pipe_slot++)
-    if ((mask & (1 << pipe_slot)) != 0)
-      break;
-  if (pipe_slot == 4)
+  if (get_attr_type (in_insn) != TYPE_STORE
+      && get_attr_type (in_insn) != TYPE_FPSTORE)
     abort ();
 
-  /* In it goes, and it hasn't been committed yet.  */
-  ultra_pipe.group[pipe_slot] = *ip;
-  ultra_pipe.codes[pipe_slot] = type;
-  ultra_pipe.contents[type] = 1;
-  if (UMASK (type) &
-      (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
-    ultra_pipe.num_ieu_insns += 1;
+  out_pat = PATTERN (out_insn);
+  in_pat = PATTERN (in_insn);
 
-  ultra_pipe.free_slot_mask = (mask & ~(1 << pipe_slot));
-  ultra_pipe.group_size += 1;
-  ultra_pipe.commit[pipe_slot] = 0;
+  if ((GET_CODE (out_pat) != SET
+       && GET_CODE (out_pat) != PARALLEL)
+      || GET_CODE (in_pat) != SET)
+    abort ();
 
-  /* Update ready list.  */
-  temp = *ip;
-  while (ip != &ready[this])
+  if (GET_CODE (SET_SRC (in_pat)) == REG)
     {
-      ip[0] = ip[1];
-      ++ip;
+      regno = REGNO (SET_SRC (in_pat));
     }
-  *ip = temp;
-}
-
-/* Advance to the next pipeline group.  */
-static void
-ultra_flush_pipeline ()
-{
-  ultra_cur_hist = (ultra_cur_hist + 1) & (ULTRA_NUM_HIST - 1);
-  ultra_cycles_elapsed += 1;
-  memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
-  ultra_pipe.free_slot_mask = 0xf;
-}
-
-/* Init our data structures for this current block.  */
-static void
-ultrasparc_sched_init ()
-{
-  memset ((char *) ultra_pipe_hist, 0, sizeof ultra_pipe_hist);
-  ultra_cur_hist = 0;
-  ultra_cycles_elapsed = 0;
-  ultra_pipe.free_slot_mask = 0xf;
-}
-
-static void
-sparc_sched_init (dump, sched_verbose, max_ready)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     int max_ready ATTRIBUTE_UNUSED;
-{
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)
-    ultrasparc_sched_init ();
-}
-  
-/* INSN has been scheduled, update pipeline commit state
-   and return how many instructions are still to be
-   scheduled in this group.  */
-static int
-ultrasparc_variable_issue (insn)
-     rtx insn;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i, left_to_fire;
-
-  left_to_fire = 0;
-  for (i = 0; i < 4; i++)
+  else if (GET_CODE (SET_SRC (in_pat)) == SUBREG)
     {
-      if (up->group[i] == 0)
-	continue;
-
-      if (up->group[i] == insn)
-	{
-	  up->commit[i] = 1;
-	}
-      else if (! up->commit[i])
-	left_to_fire++;
+      regno = REGNO (SUBREG_REG (SET_SRC (in_pat)));
     }
-
-  return left_to_fire;
-}
-
-static int
-sparc_variable_issue (dump, sched_verbose, insn, cim)
-     FILE *dump ATTRIBUTE_UNUSED;
-     int sched_verbose ATTRIBUTE_UNUSED;
-     rtx insn;
-     int cim;
-{
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)
-    return ultrasparc_variable_issue (insn);
   else
-    return cim - 1;
-}
-
-/* In actual_hazard_this_instance, we may have yanked some
-   instructions from the ready list due to conflict cost
-   adjustments.  If so, and such an insn was in our pipeline
-   group, remove it and update state.  */
-static void
-ultra_rescan_pipeline_state (ready, n_ready)
-     rtx *ready;
-     int n_ready;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i;
+    return 0;
 
-  for (i = 0; i < 4; i++)
+  if (GET_CODE (out_pat) == PARALLEL)
     {
-      rtx insn = up->group[i];
-      int j;
+      int i;
 
-      if (! insn)
-	continue;
+      for (i = 0; i < XVECLEN (out_pat, 0); i++)
+	{
+	  rtx exp = XVECEXP (out_pat, 0, i);
 
-      /* If it has been committed, then it was removed from
-	 the ready list because it was actually scheduled,
-	 and that is not the case we are searching for here.  */
-      if (up->commit[i] != 0)
-	continue;
+	  if (GET_CODE (exp) != SET)
+	    return 0;
 
-      for (j = n_ready - 1; j >= 0; j--)
-	if (ready[j] == insn)
-	  break;
+	  if (GET_CODE (SET_DEST (exp)) == REG
+	      && regno == REGNO (SET_DEST (exp)))
+	    return 1;
 
-      /* If we didn't find it, toss it.  */
-      if (j < 0)
-	{
-	  enum ultra_code ucode = up->codes[i];
-
-	  up->group[i] = 0;
-	  up->codes[i] = NONE;
-	  up->contents[ucode] = 0;
-	  if (UMASK (ucode) &
-	      (UMASK (IEUN) | UMASK (IEU0) | UMASK (IEU1)))
-	    up->num_ieu_insns -= 1;
-
-	  up->free_slot_mask |= (1 << i);
-	  up->group_size -= 1;
-	  up->commit[i] = 0;
+	  if (GET_CODE (SET_DEST (exp)) == SUBREG
+	      && regno == REGNO (SUBREG_REG (SET_DEST (exp))))
+	    return 1;
 	}
     }
-}
-
-static void
-ultrasparc_sched_reorder (dump, sched_verbose, ready, n_ready)
-     FILE *dump;
-     int sched_verbose;
-     rtx *ready;
-     int n_ready;
-{
-  struct ultrasparc_pipeline_state *up = &ultra_pipe;
-  int i, this_insn;
-
-  if (sched_verbose)
+  else if (GET_CODE (SET_DEST (out_pat)) == REG)
     {
-      int n;
-
-      fprintf (dump, "\n;;\tUltraSPARC Looking at [");
-      for (n = n_ready - 1; n >= 0; n--)
-	{
-	  rtx insn = ready[n];
-	  enum ultra_code ucode;
-
-	  if (recog_memoized (insn) < 0)
-	    continue;
-	  ucode = ultra_code_from_mask (TMASK (get_attr_type (insn)));
-	  if (n != 0)
-	    fprintf (dump, "%s(%d) ",
-		     ultra_code_names[ucode],
-		     INSN_UID (insn));
-	  else
-	    fprintf (dump, "%s(%d)",
-		     ultra_code_names[ucode],
-		     INSN_UID (insn));
-	}
-      fprintf (dump, "]\n");
+      return regno == REGNO (SET_DEST (out_pat));
     }
-
-  this_insn = n_ready - 1;
-
-  /* Skip over junk we don't understand.  */
-  while ((this_insn >= 0)
-	 && recog_memoized (ready[this_insn]) < 0)
-    this_insn--;
-
-  ultra_build_types_avail (ready, this_insn + 1);
-
-  while (this_insn >= 0) {
-    int old_group_size = up->group_size;
-
-    if (up->group_size != 0)
-      {
-	int num_committed;
-
-	num_committed = (up->commit[0] + up->commit[1] +
-			 up->commit[2] + up->commit[3]);
-	/* If nothing has been commited from our group, or all of
-	   them have.  Clear out the (current cycle's) pipeline
-	   state and start afresh.  */
-	if (num_committed == 0
-	    || num_committed == up->group_size)
-	  {
-	    ultra_flush_pipeline ();
-	    up = &ultra_pipe;
-	    old_group_size = 0;
-	  }
-	else
-	  {
-	    /* OK, some ready list insns got requeued and thus removed
-	       from the ready list.  Account for this fact.  */
-	    ultra_rescan_pipeline_state (ready, n_ready);
-
-	    /* Something "changed", make this look like a newly
-	       formed group so the code at the end of the loop
-	       knows that progress was in fact made.  */
-	    if (up->group_size != old_group_size)
-	      old_group_size = 0;
-	  }
-      }
-
-    if (up->group_size == 0)
-      {
-	/* If the pipeline is (still) empty and we have any single
-	   group insns, get them out now as this is a good time.  */
-	rtx *ip = ultra_find_type ((TMASK (TYPE_RETURN) | TMASK (TYPE_ADDRESS) |
-				    TMASK (TYPE_IMUL) | TMASK (TYPE_CMOVE) |
-				    TMASK (TYPE_MULTI) | TMASK (TYPE_MISC)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, SINGLE);
-	    break;
-	  }
-
-	/* If we are not in the process of emptying out the pipe, try to
-	   obtain an instruction which must be the first in it's group.  */
-	ip = ultra_find_type ((TMASK (TYPE_CALL) |
-			       TMASK (TYPE_SIBCALL) |
-			       TMASK (TYPE_CALL_NO_DELAY_SLOT) |
-			       TMASK (TYPE_UNCOND_BRANCH)),
-			      ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, IEU1);
-	    this_insn--;
-	  }
-	else if ((ip = ultra_find_type ((TMASK (TYPE_FPDIVS) |
-					 TMASK (TYPE_FPDIVD) |
-					 TMASK (TYPE_FPSQRTS) |
-					 TMASK (TYPE_FPSQRTD)),
-					ready, this_insn)) != 0)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPM);
-	    this_insn--;
-	  }
-      }
-
-    /* Try to fill the integer pipeline.  First, look for an IEU0 specific
-       operation.  We can't do more IEU operations if the first 3 slots are
-       all full or we have dispatched two IEU insns already.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2
-	&& up->contents[IEU0] == 0
-	&& up->contents[IEUN] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK(TYPE_SHIFT), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, IEU0);
-	    this_insn--;
-	  }
-      }
-
-    /* If we can, try to find an IEU1 specific or an unnamed
-       IEU instruction.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-				    TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY) |
-				    (up->contents[IEU1] == 0 ? TMASK (TYPE_COMPARE) : 0)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    rtx insn = *ip;
-
-	    ultra_schedule_insn (ip, ready, this_insn,
-				 (!up->contents[IEU1]
-				  && get_attr_type (insn) == TYPE_COMPARE)
-				 ? IEU1 : IEUN);
-	    this_insn--;
-	  }
-      }
-
-    /* If only one IEU insn has been found, try to find another unnamed
-       IEU operation or an IEU1 specific one.  */
-    if ((up->free_slot_mask & 0x7) != 0
-	&& up->num_ieu_insns < 2)
-      {
-	rtx *ip;
-	int tmask = (TMASK (TYPE_IALU) | TMASK (TYPE_BINARY) |
-		     TMASK (TYPE_MOVE) | TMASK (TYPE_UNARY));
-
-	if (!up->contents[IEU1])
-	  tmask |= TMASK (TYPE_COMPARE);
-	ip = ultra_find_type (tmask, ready, this_insn);
-	if (ip)
-	  {
-	    rtx insn = *ip;
-
-	    ultra_schedule_insn (ip, ready, this_insn,
-				 (!up->contents[IEU1]
-				  && get_attr_type (insn) == TYPE_COMPARE)
-				 ? IEU1 : IEUN);
-	    this_insn--;
-	  }
-      }
-
-    /* Try for a load or store, but such an insn can only be issued
-       if it is within' one of the first 3 slots.  */
-    if ((up->free_slot_mask & 0x7) != 0
-        && up->contents[LSU] == 0)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_LOAD) | TMASK (TYPE_SLOAD) |
-				   TMASK (TYPE_STORE) | TMASK (TYPE_FPLOAD) |
-				   TMASK (TYPE_FPSTORE)), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, LSU);
-	    this_insn--;
-	  }
-      }
-
-    /* Now find FPU operations, first FPM class.  But not divisions or
-       square-roots because those will break the group up.  Unlike all
-       the previous types, these can go in any slot.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[FPM] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK (TYPE_FPMUL), ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPM);
-	    this_insn--;
-	  }
-      }
-    
-    /* Continue on with FPA class if we have not filled the group already.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[FPA] == 0)
-      {
-	rtx *ip = ultra_find_type ((TMASK (TYPE_FPMOVE) | TMASK (TYPE_FPCMOVE) |
-				    TMASK (TYPE_FP) | TMASK (TYPE_FPCMP)),
-				   ready, this_insn);
-	if (ip)
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, FPA);
-	    this_insn--;
-	  }
-      }
-
-    /* Finally, maybe stick a branch in here.  */
-    if (up->free_slot_mask != 0
-	&& up->contents[CTI] == 0)
-      {
-	rtx *ip = ultra_find_type (TMASK (TYPE_BRANCH), ready, this_insn);
-
-	/* Try to slip in a branch only if it is one of the
-	   next 2 in the ready list.  */
-	if (ip && ((&ready[this_insn] - ip) < 2))
-	  {
-	    ultra_schedule_insn (ip, ready, this_insn, CTI);
-	    this_insn--;
-	  }
-      }
-
-    up->group_size = 0;
-    for (i = 0; i < 4; i++)
-      if ((up->free_slot_mask & (1 << i)) == 0)
-	up->group_size++;
-
-    /* See if we made any progress...  */
-    if (old_group_size != up->group_size)
-      break;
-
-    /* Clean out the (current cycle's) pipeline state
-       and try once more.  If we placed no instructions
-       into the pipeline at all, it means a real hard
-       conflict exists with some earlier issued instruction
-       so we must advance to the next cycle to clear it up.  */
-    if (up->group_size == 0)
-      {
-	ultra_flush_pipeline ();
-	up = &ultra_pipe;
-      }
-    else
-      {
-	memset ((char *) &ultra_pipe, 0, sizeof ultra_pipe);
-	ultra_pipe.free_slot_mask = 0xf;
-      }
-  }
-
-  if (sched_verbose)
+  else if (GET_CODE (SET_DEST (out_pat)) == SUBREG)
     {
-      int n, gsize;
-
-      fprintf (dump, ";;\tUltraSPARC Launched   [");
-      gsize = up->group_size;
-      for (n = 0; n < 4; n++)
-	{
-	  rtx insn = up->group[n];
-
-	  if (! insn)
-	    continue;
-
-	  gsize -= 1;
-	  if (gsize != 0)
-	    fprintf (dump, "%s(%d) ",
-		     ultra_code_names[up->codes[n]],
-		     INSN_UID (insn));
-	  else
-	    fprintf (dump, "%s(%d)",
-		     ultra_code_names[up->codes[n]],
-		     INSN_UID (insn));
-	}
-      fprintf (dump, "]\n");
+      return regno == REGNO (SUBREG_REG (SET_DEST (out_pat)));
     }
-}
 
-static int
-sparc_sched_reorder (dump, sched_verbose, ready, n_readyp, clock)
-     FILE *dump;
-     int sched_verbose;
-     rtx *ready;
-     int *n_readyp;
-     int clock ATTRIBUTE_UNUSED;
-{
-  if (sparc_cpu == PROCESSOR_ULTRASPARC)
-    ultrasparc_sched_reorder (dump, sched_verbose, ready, *n_readyp);
-  return sparc_issue_rate ();
+  return 0;
 }
 
 static int                                                           
@@ -8732,21 +7902,6 @@ sparc_function_block_profiler_exit(file)
     abort ();
 }
 
-/* Mark ARG, which is really a struct ultrasparc_pipline_state *, for
-   GC.  */
-
-static void
-mark_ultrasparc_pipeline_state (arg)
-     void *arg;
-{
-  struct ultrasparc_pipeline_state *ups;
-  size_t i;
-
-  ups = (struct ultrasparc_pipeline_state *) arg;
-  for (i = 0; i < sizeof (ups->group) / sizeof (rtx); ++i)
-    ggc_mark_rtx (ups->group[i]);
-}
-
 /* Called to register all of our global variables with the garbage
    collector.  */
 
@@ -8760,8 +7915,6 @@ sparc_add_gc_roots ()
   ggc_add_rtx_root (&get_pc_symbol, 1);
   ggc_add_rtx_root (&sparc_addr_diff_list, 1);
   ggc_add_rtx_root (&sparc_addr_list, 1);
-  ggc_add_root (ultra_pipe_hist, ARRAY_SIZE (ultra_pipe_hist),
-		sizeof (ultra_pipe_hist[0]), &mark_ultrasparc_pipeline_state);
 }
 
 static void
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index ee40b6b118e..3ed8b07cd0e 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -80,52 +80,20 @@
   (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
 	(const_string "arch32bit"))))
 
-;; Insn type.  Used to default other attribute values.
-
-;; type "unary" insns have one input operand (1) and one output operand (0)
-;; type "binary" insns have two input operands (1,2) and one output (0)
-;; type "compare" insns have one or two input operands (0,1) and no output
-;; type "call_no_delay_slot" is a call followed by an unimp instruction.
+;; Insn type.
 
 (define_attr "type"
-  "move,unary,binary,compare,load,sload,store,ialu,shift,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,address,imul,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
-  (const_string "binary"))
-
-;; Set true if insn uses call-clobbered intermediate register.
-(define_attr "use_clobbered" "false,true"
-  (if_then_else (and (eq_attr "type" "address")
-		     (match_operand 0 "clobbered_register" ""))
-	 	(const_string "true")
-		(const_string "false")))
+  "ialu,compare,shift,load,sload,store,uncond_branch,branch,call,sibcall,call_no_delay_slot,return,imul,idiv,fpload,fpstore,fp,fpmove,fpcmove,fpcmp,fpmul,fpdivs,fpdivd,fpsqrts,fpsqrtd,cmove,multi,misc"
+  (const_string "ialu"))
 
 ;; Length (in # of insns).
-(define_attr "length" ""
-  (cond [(eq_attr "type" "load,sload,fpload")
-	 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "store,fpstore")
-	 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
-
-	 (eq_attr "type" "address") (const_int 2)
-
-	 (eq_attr "type" "binary")
-	 (if_then_else (ior (match_operand 2 "arith_operand" "")
-			    (match_operand 2 "arith_double_operand" ""))
-		       (const_int 1) (const_int 3))
+(define_attr "length" "" (const_int 1))
 
-	 (eq_attr "type" "multi") (const_int 2)
-
-	 (eq_attr "type" "move,unary")
-	 (if_then_else (ior (match_operand 1 "arith_operand" "")
-			    (match_operand 1 "arith_double_operand" ""))
-		       (const_int 1) (const_int 2))]
-
-	(const_int 1)))
+;; FP precision.
+(define_attr "fptype" "single,double" (const_string "single"))
 
 (define_asm_attributes
-  [(set_attr "length" "1")
+  [(set_attr "length" "2")
    (set_attr "type" "multi")])
 
 ;; Attributes for instruction and branch scheduling
@@ -136,10 +104,6 @@
 	 (eq_attr "type" "load,fpload,store,fpstore")
 	 	(if_then_else (eq_attr "length" "1")
 			      (const_string "true")
-			      (const_string "false"))
-	 (eq_attr "type" "address")
-	 	(if_then_else (eq_attr "use_clobbered" "false")
-			      (const_string "true")
 			      (const_string "false"))]
 	(if_then_else (eq_attr "length" "1")
 		      (const_string "true")
@@ -161,7 +125,7 @@
   (symbol_ref "eligible_for_return_delay (insn)"))
 
 (define_attr "in_return_delay" "false,true"
-  (if_then_else (and (and (and (eq_attr "type" "move,load,sload,store,binary,ialu")
+  (if_then_else (and (and (and (eq_attr "type" "ialu,load,sload,store")
 			       (eq_attr "length" "1"))
 			  (eq_attr "leaf_function" "false"))
 		     (eq_attr "eligible_for_return_delay" "false"))
@@ -210,347 +174,389 @@
   [(eq_attr "in_uncond_branch_delay" "true")
    (nil) (nil)])
    
-;; Function units of the SPARC
-
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {issue-delay} [{conflict-list}])
-
-;; The integer ALU.
-;; (Noted only for documentation; units that take one cycle do not need to
-;; be specified.)
+;; DFA scheduling on the SPARC
 
-;; On the sparclite, integer multiply takes 1, 3, or 5 cycles depending on
-;; the inputs.
+;;(define_automaton "cypress_0,cypress_1,supersparc_0,supersparc_1,hypersparc_0,hypersparc_1,sparclet,ultrasparc_0,ultrasparc_1")
+(define_automaton "cypress_0,cypress_1,supersparc_0,supersparc_1,hypersparc_0,hypersparc_1,sparclet,ultrasparc_0,ultrasparc_1")
 
-;; (define_function_unit "alu" 1 0
-;;  (eq_attr "type" "unary,binary,move,address") 1 0)
+;; Cypress scheduling
 
-;; ---- cypress CY7C602 scheduling:
-;; Memory with load-delay of 1 (i.e., 2 cycle load).
+(define_cpu_unit "cyp_memory, cyp_fpalu" "cypress_0")
+(define_cpu_unit "cyp_fpmds" "cypress_1")
 
-(define_function_unit "memory" 1 0 
+(define_insn_reservation "cyp_load" 2
   (and (eq_attr "cpu" "cypress")
     (eq_attr "type" "load,sload,fpload"))
-  2 2)
-
-;; SPARC has two floating-point units: the FP ALU,
-;; and the FP MUL/DIV/SQRT unit.
-;; Instruction timings on the CY7C602 are as follows
-;; FABSs	4
-;; FADDs/d	5/5
-;; FCMPs/d	4/4
-;; FDIVs/d	23/37
-;; FMOVs	4
-;; FMULs/d	5/7
-;; FNEGs	4
-;; FSQRTs/d	34/63
-;; FSUBs/d	5/5
-;; FdTOi/s	5/5
-;; FsTOi/d	5/5
-;; FiTOs/d	9/5
-
-;; The CY7C602 can only support 2 fp isnsn simultaneously.
-;; More insns cause the chip to stall.
-
-(define_function_unit "fp_alu" 1 0
+  "cyp_memory, nothing")
+
+(define_insn_reservation "cyp_fp_alu" 5
   (and (eq_attr "cpu" "cypress")
     (eq_attr "type" "fp,fpmove"))
-  5 5)
+  "cyp_fpalu, nothing*3")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "cyp_fp_mult" 7
   (and (eq_attr "cpu" "cypress")
     (eq_attr "type" "fpmul"))
-  7 7)
+  "cyp_fpmds, nothing*5")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "cyp_fp_div" 37
   (and (eq_attr "cpu" "cypress")
     (eq_attr "type" "fpdivs,fpdivd"))
-  37 37)
+  "cyp_fpmds, nothing*35")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "cyp_fp_sqrt" 63
   (and (eq_attr "cpu" "cypress")
     (eq_attr "type" "fpsqrts,fpsqrtd"))
-  63 63)
+  "cyp_fpmds, nothing*61")
+
+;; SuperSPARC scheduling
+
+(define_cpu_unit "ss_memory, ss_shift, ss_iwport0, ss_iwport1" "supersparc_0")
+(define_cpu_unit "ss_fpalu" "supersparc_0")
+(define_cpu_unit "ss_fpmds" "supersparc_1")
 
-;; ----- The TMS390Z55 scheduling
-;; The Supersparc can issue 1 - 3 insns per cycle: up to two integer,
-;; one ld/st, one fp.
-;; Memory delivers its result in one cycle to IU, zero cycles to FP
+(define_reservation "ss_iwport" "(ss_iwport0 | ss_iwport1)")
 
-(define_function_unit "memory" 1 0
+(define_insn_reservation "ss_iuload" 1
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "load,sload"))
-  1 1)
+  "ss_memory")
 
-(define_function_unit "memory" 1 0
+;; Ok, fpu loads deliver the result in zero cycles.  But we
+;; have to show the ss_memory reservation somehow, thus...
+(define_insn_reservation "ss_fpload" 0
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fpload"))
-  0 1)
+  "ss_memory")
 
-(define_function_unit "memory" 1 0
+(define_bypass 0 "ss_fpload" "ss_fp_alu,ss_fp_mult,ss_fp_divs,ss_fp_divd,ss_fp_sqrt")
+
+(define_insn_reservation "ss_store" 1
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "store,fpstore"))
-  1 1)
+  "ss_memory")
 
-(define_function_unit "shift" 1 0
+(define_insn_reservation "ss_ialu_shift" 1
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "shift"))
-  1 1)
-
-;; There are only two write ports to the integer register file
-;; A store also uses a write port
+  "ss_shift + ss_iwport")
 
-(define_function_unit "iwport" 2 0
+(define_insn_reservation "ss_ialu_any" 1
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "load,sload,store,shift,ialu"))
-  1 1)
-
-;; Timings; throughput/latency
-;; FADD     1/3    add/sub, format conv, compar, abs, neg
-;; FMUL     1/3
-;; FDIVs    4/6
-;; FDIVd    7/9
-;; FSQRTs   6/8
-;; FSQRTd  10/12
-;; IMUL     4/4
-
-(define_function_unit "fp_alu" 1 0
+  "ss_iwport")
+
+(define_insn_reservation "ss_fp_alu" 3
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fp,fpmove,fpcmp"))
-  3 1)
+  "ss_fpalu, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "ss_fp_mult" 3
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fpmul"))
-  3 1)
+  "ss_fpmds, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "ss_fp_divs" 6
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fpdivs"))
-  6 4)
+  "ss_fpmds*4, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "ss_fp_divd" 9
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fpdivd"))
-  9 7)
+  "ss_fpmds*7, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "ss_fp_sqrt" 12
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "fpsqrts,fpsqrtd"))
-  12 10)
+  "ss_fpmds*10, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "ss_imul" 4
   (and (eq_attr "cpu" "supersparc")
     (eq_attr "type" "imul"))
-  4 4)
+  "ss_fpmds*4")
+
+;; HyperSPARC/sparclite86x scheduling
 
-;; ----- hypersparc/sparclite86x scheduling
-;; The Hypersparc can issue 1 - 2 insns per cycle.  The dual issue cases are:
-;; L-Ld/St I-Int F-Float B-Branch LI/LF/LB/II/IF/IB/FF/FB
-;; II/FF case is only when loading a 32 bit hi/lo constant
-;; Single issue insns include call, jmpl, u/smul, u/sdiv, lda, sta, fcmp
-;; Memory delivers its result in one cycle to IU
+(define_cpu_unit "hs_memory,hs_branch,hs_shift,hs_fpalu" "hypersparc_0")
+(define_cpu_unit "hs_fpmds" "hypersparc_1")
 
-(define_function_unit "memory" 1 0
+(define_insn_reservation "hs_load" 1
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "load,sload,fpload"))
-  1 1)
+  "hs_memory")
 
-(define_function_unit "memory" 1 0
+(define_insn_reservation "hs_store" 2
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "store,fpstore"))
-  2 1)
+  "hs_memory, nothing")
 
-(define_function_unit "sparclite86x_branch" 1 0
+(define_insn_reservation "hs_slbranch" 1
   (and (eq_attr "cpu" "sparclite86x")
     (eq_attr "type" "branch"))
-  1 1)
+  "hs_branch")
 
-;; integer multiply insns 
-(define_function_unit "sparclite86x_shift" 1 0
+(define_insn_reservation "hs_slshift" 1
   (and (eq_attr "cpu" "sparclite86x")
     (eq_attr "type" "shift"))
-  1 1)
+  "hs_shift")
 
-(define_function_unit "fp_alu" 1 0
+(define_insn_reservation "hs_fp_alu" 1
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "fp,fpmove,fpcmp"))
-  1 1)
+  "hs_fpalu")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "hs_fp_mult" 1
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "fpmul"))
-  1 1)
+  "hs_fpmds")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "hs_fp_divs" 8
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "fpdivs"))
-  8 6)
+  "hs_fpmds*6, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "hs_fp_divd" 12
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "fpdivd"))
-  12 10)
+  "hs_fpmds*10, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "hs_fp_sqrt" 17
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "fpsqrts,fpsqrtd"))
-  17 15)
+  "hs_fpmds*15, nothing*2")
 
-(define_function_unit "fp_mds" 1 0
+(define_insn_reservation "hs_imul" 17
   (and (ior (eq_attr "cpu" "hypersparc") (eq_attr "cpu" "sparclite86x"))
     (eq_attr "type" "imul"))
-  17 15)
+  "hs_fpmds*15, nothing*2")
 
-;; ----- sparclet tsc701 scheduling
-;; The tsc701 issues 1 insn per cycle.
-;; Results may be written back out of order.
+;; Sparclet tsc701 scheduling
 
-;; Loads take 2 extra cycles to complete and 4 can be buffered at a time.
+(define_cpu_unit "sl_load0,sl_load1,sl_load2,sl_load3" "sparclet")
+(define_cpu_unit "sl_store,sl_imul" "sparclet")
 
-(define_function_unit "tsc701_load" 4 1
-  (and (eq_attr "cpu" "tsc701")
-    (eq_attr "type" "load,sload"))
-  3 1)
+(define_reservation "sl_load_any" "(sl_load0 | sl_load1 | sl_load2 | sl_load3)")
+(define_reservation "sl_load_all" "(sl_load0 + sl_load1 + sl_load2 + sl_load3)")
 
-;; Stores take 2(?) extra cycles to complete.
-;; It is desirable to not have any memory operation in the following 2 cycles.
-;; (??? or 2 memory ops in the case of std).
+(define_insn_reservation "sl_ld" 3
+  (and (eq_attr "cpu" "tsc701")
+   (eq_attr "type" "load,sload"))
+  "sl_load_any, sl_load_any, sl_load_any")
 
-(define_function_unit "tsc701_store" 1 0
+(define_insn_reservation "sl_st" 3
   (and (eq_attr "cpu" "tsc701")
     (eq_attr "type" "store"))
-  3 3
-  [(eq_attr "type" "load,sload,store")])
+  "(sl_store+sl_load_all)*3")
 
-;; The multiply unit has a latency of 5.
-(define_function_unit "tsc701_mul" 1 0
+(define_insn_reservation "sl_imul" 5
   (and (eq_attr "cpu" "tsc701")
     (eq_attr "type" "imul"))
-  5 5)
-
-;; ----- The UltraSPARC-1 scheduling
-;; UltraSPARC has two integer units.  Shift instructions can only execute
-;; on IE0.  Condition code setting instructions, call, and jmpl (including
-;; the ret and retl pseudo-instructions) can only execute on IE1.
-;; Branch on register uses IE1, but branch on condition code does not.
-;; Conditional moves take 2 cycles.  No other instruction can issue in the
-;; same cycle as a conditional move.
-;; Multiply and divide take many cycles during which no other instructions
-;; can issue.
-;; Memory delivers its result in two cycles (except for signed loads,
-;; which take one cycle more).  One memory instruction can be issued per
-;; cycle.
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "load,fpload"))
-  2 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "sload"))
-  3 1)
-
-(define_function_unit "memory" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "store,fpstore"))
-  1 1)
-
-(define_function_unit "ieuN" 2 0
+  "sl_imul*5")
+
+;; UltraSPARC-I/II scheduling
+
+(define_cpu_unit "us1_fdivider,us1_fpm" "ultrasparc_0");
+(define_cpu_unit "us1_fpa,us1_load_writeback" "ultrasparc_1")
+(define_cpu_unit "us1_fps_0,us1_fps_1,us1_fpd_0,us1_fpd_1" "ultrasparc_1")
+(define_cpu_unit "us1_slot0,us1_slot1,us1_slot2,us1_slot3" "ultrasparc_1")
+(define_cpu_unit "us1_ieu0,us1_ieu1,us1_cti,us1_lsu" "ultrasparc_1")
+
+(define_reservation "us1_slot012" "(us1_slot0 | us1_slot1 | us1_slot2)")
+(define_reservation "us1_slotany" "(us1_slot0 | us1_slot1 | us1_slot2 | us1_slot3)")
+(define_reservation "us1_single_issue" "us1_slot0 + us1_slot1 + us1_slot2 + us1_slot3")
+
+(define_reservation "us1_fp_single" "(us1_fps_0 | us1_fps_1)")
+(define_reservation "us1_fp_double" "(us1_fpd_0 | us1_fpd_1)")
+;; This is a simplified representation of the issue at hand.
+;; For most cases, going from one FP precision type insn to another
+;; just breaks up the insn group.  However for some cases, such
+;; a situation causes the second insn to stall 2 more cycles.
+(exclusion_set "us1_fps_0,us1_fps_1" "us1_fpd_0,us1_fpd_1")
+
+;; If we have to schedule an ieu1 specific instruction and we want
+;; to reserve the ieu0 unit as well, we must reserve it first.  So for
+;; example we could not schedule this sequence:
+;;	COMPARE		IEU1
+;;	IALU		IEU0
+;; but we could schedule them together like this:
+;;	IALU		IEU0
+;;	COMPARE		IEU1
+;; This basically requires that ieu0 is reserved before ieu1 when
+;; it is required that both be reserved.
+(absence_set "us1_ieu0" "us1_ieu1")
+
+;; This defines the slotting order.  Most IEU instructions can only
+;; execute in the first three slots, FPU and branches can go into
+;; any slot.  We represent instructions which "break the group"
+;; as requiring reservation of us1_slot0.
+(absence_set "us1_slot0" "us1_slot1,us1_slot2,us1_slot3")
+(absence_set "us1_slot1" "us1_slot2,us1_slot3")
+(absence_set "us1_slot2" "us1_slot3")
+
+(define_insn_reservation "us1_simple_ieuN" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "ialu,binary,move,unary,shift,compare,call,sibcall,call_no_delay_slot,uncond_branch"))
-  1 1)
+    (eq_attr "type" "ialu"))
+  "(us1_ieu0 | us1_ieu1) + us1_slot012")
 
-(define_function_unit "ieu0" 1 0
+(define_insn_reservation "us1_simple_ieu0" 1
   (and (eq_attr "cpu" "ultrasparc")
     (eq_attr "type" "shift"))
-  1 1)
+  "us1_ieu0 + us1_slot012")
 
-(define_function_unit "ieu0" 1 0
+(define_insn_reservation "us1_simple_ieu1" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "cmove"))
-  2 1)
+    (eq_attr "type" "compare"))
+  "us1_ieu1 + us1_slot012")
 
-(define_function_unit "ieu1" 1 0
+(define_insn_reservation "us1_cmove" 2
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "compare,call,sibcall,call_no_delay_slot,uncond_branch"))
-  1 1)
+    (eq_attr "type" "cmove"))
+  "us1_single_issue, nothing")
 
-(define_function_unit "cti" 1 0
+(define_insn_reservation "us1_imul" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "branch"))
-  1 1)
-
-;; Timings; throughput/latency
-;; FMOV     1/1    fmov, fabs, fneg
-;; FMOVcc   1/2
-;; FADD     1/3    add/sub, format conv, compar
-;; FMUL     1/3
-;; FDIVs    12/12
-;; FDIVd    22/22
-;; FSQRTs   12/12
-;; FSQRTd   22/22
-;; FCMP takes 1 cycle to branch, 2 cycles to conditional move.
-;;
-;; FDIV{s,d}/FSQRT{s,d} are given their own unit since they only
-;; use the FPM multiplier for final rounding 3 cycles before the
-;; end of their latency and we have no real way to model that.
-;;
-;; ??? This is really bogus because the timings really depend upon
-;; who uses the result.  We should record who the user is with
-;; more descriptive 'type' attribute names and account for these
-;; issues in ultrasparc_adjust_cost. 
+    (eq_attr "type" "imul"))
+  "us1_single_issue")
 
-(define_function_unit "fadd" 1 0
+(define_insn_reservation "us1_idiv" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpmove"))
-  1 1)
+    (eq_attr "type" "idiv"))
+  "us1_single_issue")
 
-(define_function_unit "fadd" 1 0
+;; For loads, the "delayed return mode" behavior of the chip
+;; is represented using the us1_load_writeback resource.
+(define_insn_reservation "us1_load" 2
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmove"))
-  2 1)
+    (eq_attr "type" "load,fpload"))
+  "us1_lsu + us1_slot012, us1_load_writeback")
 
-(define_function_unit "fadd" 1 0
+(define_insn_reservation "us1_load_signed" 3
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fp"))
-  3 1)
+    (eq_attr "type" "sload"))
+  "us1_lsu + us1_slot012, nothing, us1_load_writeback")
 
-(define_function_unit "fadd" 1 0
+(define_insn_reservation "us1_store" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmp"))
-  2 1)
+    (eq_attr "type" "store,fpstore"))
+  "us1_lsu + us1_slot012")
 
-(define_function_unit "fmul" 1 0
+(define_insn_reservation "us1_branch" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpmul"))
-  3 1)
+    (eq_attr "type" "branch"))
+  "us1_cti + us1_slotany")
 
-(define_function_unit "fadd" 1 0
+(define_insn_reservation "us1_call_jmpl" 1
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpcmove"))
-  2 1)
-
-(define_function_unit "fdiv" 1 0
+    (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch"))
+  "us1_cti + us1_ieu1 + us1_slot0")
+
+(define_insn_reservation "us1_fmov_single" 1
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpmove"))
+       (eq_attr "fptype" "single"))
+  "us1_fpa + us1_fp_single + us1_slotany")
+
+(define_insn_reservation "us1_fmov_double" 1
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpmove"))
+       (eq_attr "fptype" "double"))
+  "us1_fpa + us1_fp_double + us1_slotany")
+
+(define_insn_reservation "us1_fcmov_single" 2
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpcmove"))
+       (eq_attr "fptype" "single"))
+  "us1_fpa + us1_fp_single + us1_slotany, nothing")
+
+(define_insn_reservation "us1_fcmov_double" 2
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpcmove"))
+       (eq_attr "fptype" "double"))
+  "us1_fpa + us1_fp_double + us1_slotany, nothing")
+
+(define_insn_reservation "us1_faddsub_single" 4
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fp"))
+       (eq_attr "fptype" "single"))
+  "us1_fpa + us1_fp_single + us1_slotany, nothing*3")
+
+(define_insn_reservation "us1_faddsub_double" 4
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fp"))
+       (eq_attr "fptype" "double"))
+  "us1_fpa + us1_fp_double + us1_slotany, nothing*3")
+
+(define_insn_reservation "us1_fpcmp_single" 1
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpcmp"))
+       (eq_attr "fptype" "single"))
+  "us1_fpa + us1_fp_single + us1_slotany")
+
+(define_insn_reservation "us1_fpcmp_double" 1
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpcmp"))
+       (eq_attr "fptype" "double"))
+  "us1_fpa + us1_fp_double + us1_slotany")
+
+(define_insn_reservation "us1_fmult_single" 4
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpmul"))
+       (eq_attr "fptype" "single"))
+  "us1_fpm + us1_fp_single + us1_slotany, nothing*3")
+
+(define_insn_reservation "us1_fmult_double" 4
+  (and (and (eq_attr "cpu" "ultrasparc")
+            (eq_attr "type" "fpmul"))
+       (eq_attr "fptype" "double"))
+  "us1_fpm + us1_fp_double + us1_slotany, nothing*3")
+
+;; This is actually in theory dangerous, because it is possible
+;; for the chip to prematurely dispatch the dependant instruction
+;; in the G stage, resulting in a 9 cycle stall.  However I have never
+;; been able to trigger this case myself even with hand written code,
+;; so it must require some rare complicated pipeline state.
+(define_bypass 3
+   "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double"
+   "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
+
+;; Floating point divide and square root use the multiplier unit
+;; for final rounding 3 cycles before the divide/sqrt is complete.
+
+(define_insn_reservation "us1_fdivs"
+  13
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpdivs"))
-  12 12)
+    (eq_attr "type" "fpdivs,fpsqrts"))
+  "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*8, (us1_fpm + us1_fdivider), us1_fdivider*2"
+  )
 
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpdivd"))
-  22 22)
+(define_bypass
+  12
+  "us1_fdivs"
+  "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
 
-(define_function_unit "fdiv" 1 0
+(define_insn_reservation "us1_fdivd"
+  23
   (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpsqrts"))
-  12 12)
+    (eq_attr "type" "fpdivd,fpsqrtd"))
+  "(us1_fpm + us1_fdivider + us1_slot0), us1_fdivider*18, (us1_fpm + us1_fdivider), us1_fdivider*2"
+  )
+(define_bypass
+  22
+  "us1_fdivd"
+  "us1_faddsub_single,us1_faddsub_double,us1_fmult_single,us1_fmult_double")
+
+;; Any store may multi issue with the insn creating the source
+;; data as long as that creating insn is not an FPU div/sqrt.
+;; We need a special guard function because this bypass does
+;; not apply to the address inputs of the store.
+(define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store"
+   "ultrasparc_store_bypass_p")
+
+;; An integer branch may execute in the same cycle as the compare
+;; creating the condition codes.
+(define_bypass 0 "us1_simple_ieu1" "us1_branch")
 
-(define_function_unit "fdiv" 1 0
-  (and (eq_attr "cpu" "ultrasparc")
-    (eq_attr "type" "fpsqrtd"))
-  22 22)
 
 ;; Compare instructions.
 ;; This controls RTL generation and register allocation.
@@ -675,7 +681,8 @@
     return \"fcmped\\t%0, %1, %2\";
   return \"fcmped\\t%1, %2\";
 }"
-  [(set_attr "type" "fpcmp")])
+  [(set_attr "type" "fpcmp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*cmptf_fpe"
   [(set (match_operand:CCFPE 0 "fcc_reg_operand" "=c")
@@ -714,7 +721,8 @@
     return \"fcmpd\\t%0, %1, %2\";
   return \"fcmpd\\t%1, %2\";
 }"
-  [(set_attr "type" "fpcmp")])
+  [(set_attr "type" "fpcmp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*cmptf_fp"
   [(set (match_operand:CCFP 0 "fcc_reg_operand" "=c")
@@ -1157,8 +1165,7 @@
    (clobber (reg:CC 100))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1180,8 +1187,7 @@
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1202,8 +1208,7 @@
 		       (const_int 0))))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1224,8 +1229,7 @@
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -1287,8 +1291,7 @@
    (clobber (reg:CC 100))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1310,8 +1313,7 @@
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1332,8 +1334,7 @@
 		       (const_int 0))))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")]) 
+  [(set_attr "length" "2")]) 
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -1354,8 +1355,7 @@
 	       (const_int 0)))]
   "TARGET_ARCH64"
   "#"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -1475,16 +1475,14 @@
 	(ltu:SI (reg:CC 100) (const_int 0)))]
   ""
   "addx\\t%%g0, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*neg_sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
   ""
   "subx\\t%%g0, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 ;; ??? Combine should canonicalize these next two to the same pattern.
 (define_insn "*neg_sltu_minus_x"
@@ -1493,8 +1491,7 @@
 		  (match_operand:SI 1 "arith_operand" "rI")))]
   ""
   "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*neg_sltu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1502,24 +1499,21 @@
 			 (match_operand:SI 1 "arith_operand" "rI"))))]
   ""
   "subx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(geu:SI (reg:CC 100) (const_int 0)))]
   ""
   "subx\\t%%g0, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*neg_sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
   ""
   "addx\\t%%g0, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 ;; We can also do (x + ((unsigned) i >= 0)) and related, so put them in.
 ;; ??? The addx/subx insns use the 32 bit carry flag so there are no DImode
@@ -1531,8 +1525,7 @@
 		 (match_operand:SI 1 "arith_operand" "rI")))]
   ""
   "addx\\t%%g0, %1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*sltu_plus_x_plus_y"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1541,8 +1534,7 @@
 			  (match_operand:SI 2 "arith_operand" "rI"))))]
   ""
   "addx\\t%1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*x_minus_sltu"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1550,8 +1542,7 @@
 		  (ltu:SI (reg:CC 100) (const_int 0))))]
   ""
   "subx\\t%1, 0, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 ;; ??? Combine should canonicalize these next two to the same pattern.
 (define_insn "*x_minus_y_minus_sltu"
@@ -1561,8 +1552,7 @@
 		  (ltu:SI (reg:CC 100) (const_int 0))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*x_minus_sltu_plus_y"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1571,8 +1561,7 @@
 			   (match_operand:SI 2 "arith_operand" "rI"))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*sgeu_plus_x"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1580,8 +1569,7 @@
 		 (match_operand:SI 1 "register_operand" "r")))]
   ""
   "subx\\t%1, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*x_minus_sgeu"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1589,11 +1577,10 @@
 		  (geu:SI (reg:CC 100) (const_int 0))))]
   ""
   "addx\\t%1, -1, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_split
-  [(set (match_operand:SI 0 "register_operand" "=r")
+  [(set (match_operand:SI 0 "register_operand" "")
 	(match_operator:SI 2 "noov_compare_op"
 			   [(match_operand 1 "icc_or_fcc_reg_operand" "")
 			    (const_int 0)]))]
@@ -2087,14 +2074,15 @@
 	(unspec [(match_operand 1 "" "") (match_operand 2 "" "")] 2))]
   "flag_pic && REGNO (operands[0]) == 23"
   "sethi\\t%%hi(%a1-4), %0\\n\\tcall\\t%a2\\n\\tadd\\t%0, %%lo(%a1+4), %0"
-  [(set_attr "length" "3")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "3")])
 
 ;; Currently unused...
 ;; (define_insn "get_pc_via_rdpc"
 ;;   [(set (match_operand 0 "register_operand" "=r") (pc))]
 ;;   "TARGET_V9"
 ;;   "rd\\t%%pc, %0"
-;;   [(set_attr "type" "move")])
+;;   [(set_attr "type" "misc")])
 
 
 ;; Move instructions
@@ -2165,8 +2153,7 @@
    mov\\t%1, %0
    ldub\\t%1, %0
    stb\\t%r1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,load,store")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
@@ -2228,9 +2215,7 @@
   [(set (match_operand:HI 0 "register_operand" "=r")
 	(match_operand:HI 1 "const64_high_operand" ""))]
   "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*movhi_insn"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
@@ -2242,8 +2227,7 @@
    sethi\\t%%hi(%a1), %0
    lduh\\t%1, %0
    sth\\t%r1, %0"
-  [(set_attr "type" "move,move,load,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,*,load,store")])
 
 ;; We always work with constants here.
 (define_insn "*movhi_lo_sum"
@@ -2251,9 +2235,7 @@
 	(ior:HI (match_operand:HI 1 "arith_operand" "%r")
                 (match_operand:HI 2 "arith_operand" "I")))]
   ""
-  "or\\t%1, %2, %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %2, %0")
 
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
@@ -2333,9 +2315,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operand:SI 1 "const64_high_operand" ""))]
   "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*movsi_insn"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
@@ -2352,25 +2332,20 @@
    st\\t%r1, %0
    st\\t%1, %0
    fzeros\\t%0"
-  [(set_attr "type" "move,fpmove,move,move,load,fpload,store,fpstore,fpmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,fpmove,*,*,load,fpload,store,fpstore,fpmove")])
 
 (define_insn "*movsi_lo_sum"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "immediate_operand" "in")))]
   ""
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 (define_insn "*movsi_high"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (match_operand:SI 1 "immediate_operand" "in")))]
   ""
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
 ;; so that CSE won't optimize the address computation away.
@@ -2379,17 +2354,13 @@
         (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
                    (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
   "flag_pic"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 (define_insn "movsi_high_pic"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
   "flag_pic && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_expand "movsi_pic_label_ref"
   [(set (match_dup 3) (high:SI
@@ -2423,9 +2394,7 @@
         (unspec:SI [(match_operand:SI 1 "label_ref_operand" "")
 		    (match_operand:SI 2 "" "")] 5)))]
   "flag_pic"
-  "sethi\\t%%hi(%a2-(%a1-.)), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a2-(%a1-.)), %0")
 
 (define_insn "*movsi_lo_sum_pic_label_ref"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2433,9 +2402,7 @@
         (unspec:SI [(match_operand:SI 2 "label_ref_operand" "")
 		    (match_operand:SI 3 "" "")] 5)))]
   "flag_pic"
-  "or\\t%1, %%lo(%a3-(%a2-.)), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a3-(%a2-.)), %0")
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
@@ -2552,7 +2519,7 @@
    #
    #"
   [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,*,*,*")
-   (set_attr "length" "1,1,2,2,2,2,1,1,2,2,2")])
+   (set_attr "length" "*,*,2,2,2,2,*,*,2,2,2")])
 
 ;; The following are generated by sparc_emit_set_const64
 (define_insn "*movdi_sp64_dbl"
@@ -2560,9 +2527,7 @@
         (match_operand:DI 1 "const64_operand" ""))]
   "(TARGET_ARCH64
     && HOST_BITS_PER_WIDE_INT != 64)"
-  "mov\\t%1, %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "mov\\t%1, %0")
 
 ;; This is needed to show CSE exactly which bits are set
 ;; in a 64-bit register by sethi instructions.
@@ -2570,9 +2535,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(match_operand:DI 1 "const64_high_operand" ""))]
   "TARGET_ARCH64"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*movdi_insn_sp64_novis"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m")
@@ -2589,8 +2552,8 @@
    fmovd\\t%1, %0
    ldd\\t%1, %0
    std\\t%1, %0"
-  [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
+   (set_attr "fptype" "*,*,*,*,*,double,*,*")])
 
 (define_insn "*movdi_insn_sp64_vis"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?m,b")
@@ -2608,8 +2571,8 @@
    ldd\\t%1, %0
    std\\t%1, %0
    fzero\\t%0"
-  [(set_attr "type" "move,move,move,load,store,fpmove,fpload,fpstore,fpmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore,fpmove")
+   (set_attr "fptype" "*,*,*,*,*,double,*,*,double")])
 
 (define_expand "movdi_pic_label_ref"
   [(set (match_dup 3) (high:DI
@@ -2643,9 +2606,7 @@
           (unspec:DI [(match_operand:DI 1 "label_ref_operand" "")
                       (match_operand:DI 2 "" "")] 5)))]
   "TARGET_ARCH64 && flag_pic"
-  "sethi\\t%%hi(%a2-(%a1-.)), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a2-(%a1-.)), %0")
 
 (define_insn "*movdi_lo_sum_pic_label_ref"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2653,9 +2614,7 @@
         (unspec:DI [(match_operand:DI 2 "label_ref_operand" "")
                     (match_operand:DI 3 "" "")] 5)))]
   "TARGET_ARCH64 && flag_pic"
-  "or\\t%1, %%lo(%a3-(%a2-.)), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a3-(%a2-.)), %0")
 
 ;; Sparc-v9 code model support insns.  See sparc_emit_set_symbolic_const64
 ;; in sparc.c to see what is going on here... PIC stuff comes first.
@@ -2665,160 +2624,123 @@
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "immediate_operand" "in")] 0)))]
   "TARGET_ARCH64 && flag_pic"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 (define_insn "movdi_high_pic"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand 1 "" "")] 0)))]
   "TARGET_ARCH64 && flag_pic && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*sethi_di_medlow_embmedany_pic"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (match_operand:DI 1 "sp64_medium_pic_operand" "")))]
   "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*sethi_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
   "TARGET_CM_MEDLOW && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "*losum_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDLOW"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 (define_insn "seth44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 6)))]
   "TARGET_CM_MEDMID"
-  "sethi\\t%%h44(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%h44(%a1), %0")
 
 (define_insn "setm44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 7)))]
   "TARGET_CM_MEDMID"
-  "or\\t%1, %%m44(%a2), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "or\\t%1, %%m44(%a2), %0")
 
 (define_insn "setl44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDMID"
-  "or\\t%1, %%l44(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%l44(%a2), %0")
 
 (define_insn "sethh"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 9)))]
   "TARGET_CM_MEDANY"
-  "sethi\\t%%hh(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hh(%a1), %0")
 
 (define_insn "setlm"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")] 10)))]
   "TARGET_CM_MEDANY"
-  "sethi\\t%%lm(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%lm(%a1), %0")
 
 (define_insn "sethm"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")] 18)))]
   "TARGET_CM_MEDANY"
-  "or\\t%1, %%hm(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%hm(%a2), %0")
 
 (define_insn "setlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
   "TARGET_CM_MEDANY"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 (define_insn "embmedany_sethi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")] 11)))]
   "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "embmedany_losum"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "data_segment_operand" "")))]
   "TARGET_CM_EMBMEDANY"
-  "add\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "add\\t%1, %%lo(%a2), %0")
 
 (define_insn "embmedany_brsum"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 11))]
   "TARGET_CM_EMBMEDANY"
-  "add\\t%1, %_, %0"
-  [(set_attr "length" "1")])
+  "add\\t%1, %_, %0")
 
 (define_insn "embmedany_textuhi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 13)))]
   "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%uhi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%uhi(%a1), %0")
 
 (define_insn "embmedany_texthi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")] 14)))]
   "TARGET_CM_EMBMEDANY && check_pic (1)"
-  "sethi\\t%%hi(%a1), %0"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+  "sethi\\t%%hi(%a1), %0")
 
 (define_insn "embmedany_textulo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")] 15)))]
   "TARGET_CM_EMBMEDANY"
-  "or\\t%1, %%ulo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%ulo(%a2), %0")
 
 (define_insn "embmedany_textlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "text_segment_operand" "")))]
   "TARGET_CM_EMBMEDANY"
-  "or\\t%1, %%lo(%a2), %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "or\\t%1, %%lo(%a2), %0")
 
 ;; Now some patterns to help reload out a bit.
 (define_expand "reload_indi"
@@ -3038,8 +2960,7 @@
       abort();
     }
 }"
-  [(set_attr "type" "fpmove,move,move,move,*,load,fpload,fpstore,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
 
 (define_insn "*movsf_insn_vis"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
@@ -3087,8 +3008,7 @@
       abort();
     }
 }"
-  [(set_attr "type" "fpmove,fpmove,move,move,move,*,load,fpload,fpstore,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmove,fpmove,*,*,*,*,load,fpload,fpstore,store")])
 
 ;; Exactly the same as above, except that all `f' cases are deleted.
 ;; This is necessary to prevent reload from ever trying to use a `f' reg
@@ -3134,8 +3054,7 @@
       abort();
     }
 }"
-  [(set_attr "type" "move,move,move,*,load,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,*,*,*,load,store")])
 
 (define_insn "*movsf_lo_sum"
   [(set (match_operand:SF 0 "register_operand" "=r")
@@ -3151,9 +3070,7 @@
   REAL_VALUE_TO_TARGET_SINGLE (r, i);
   operands[2] = GEN_INT (i);
   return \"or\\t%1, %%lo(%a2), %0\";
-}"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+}")
 
 (define_insn "*movsf_high"
   [(set (match_operand:SF 0 "register_operand" "=r")
@@ -3168,9 +3085,7 @@
   REAL_VALUE_TO_TARGET_SINGLE (r, i);
   operands[1] = GEN_INT (i);
   return \"sethi\\t%%hi(%1), %0\";
-}"
-  [(set_attr "type" "move")
-   (set_attr "length" "1")])
+}")
 
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
@@ -3324,7 +3239,7 @@
   #
   #"
  [(set_attr "type" "fpload,fpstore,load,store,*,*,*,*,*,*")
-  (set_attr "length" "1,1,1,1,2,2,2,2,2,2")])
+  (set_attr "length" "*,*,*,*,2,2,2,2,2,2")])
 
 (define_insn "*movdf_no_e_insn_sp32"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,o,r,o")
@@ -3342,7 +3257,7 @@
   #
   #"
   [(set_attr "type" "load,store,*,*,*")
-   (set_attr "length" "1,1,2,2,2")])
+   (set_attr "length" "*,*,2,2,2")])
 
 (define_insn "*movdf_no_e_insn_v9_sp32"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=U,T,T,r,o")
@@ -3360,7 +3275,7 @@
   #
   #"
   [(set_attr "type" "load,store,store,*,*")
-   (set_attr "length" "1,1,1,2,2")])
+   (set_attr "length" "*,*,*,2,2")])
 
 ;; We have available v9 double floats but not 64-bit
 ;; integer registers and no VIS.
@@ -3385,7 +3300,8 @@
   #
   #"
   [(set_attr "type" "fpmove,load,store,store,load,store,*,*,*")
-   (set_attr "length" "1,1,1,1,1,1,2,2,2")])
+   (set_attr "length" "*,*,*,*,*,*,2,2,2")
+   (set_attr "fptype" "double,*,*,*,*,*,*,*,*")])
 
 ;; We have available v9 double floats but not 64-bit
 ;; integer registers but we have VIS.
@@ -3410,7 +3326,8 @@
   #
   #"
   [(set_attr "type" "fpmove,fpmove,load,store,store,load,store,*,*,*")
-   (set_attr "length" "1,1,1,1,1,1,1,2,2,2")])
+   (set_attr "length" "*,*,*,*,*,*,*,2,2,2")
+   (set_attr "fptype" "double,double,*,*,*,*,*,*,*,*")])
 
 ;; We have available both v9 double floats and 64-bit
 ;; integer registers. No VIS though.
@@ -3431,8 +3348,9 @@
   ldx\\t%1, %0
   stx\\t%r1, %0
   #"
-  [(set_attr "type" "fpmove,load,store,move,load,store,*")
-   (set_attr "length" "1,1,1,1,1,1,2")])
+  [(set_attr "type" "fpmove,load,store,*,load,store,*")
+   (set_attr "length" "*,*,*,*,*,*,2")
+   (set_attr "fptype" "double,*,*,*,*,*,*")])
 
 ;; We have available both v9 double floats and 64-bit
 ;; integer registers. And we have VIS.
@@ -3454,8 +3372,9 @@
   ldx\\t%1, %0
   stx\\t%r1, %0
   #"
-  [(set_attr "type" "fpmove,fpmove,load,store,move,load,store,*")
-   (set_attr "length" "1,1,1,1,1,1,1,2")])
+  [(set_attr "type" "fpmove,fpmove,load,store,*,load,store,*")
+   (set_attr "length" "*,*,*,*,*,*,*,2")
+   (set_attr "fptype" "double,double,*,*,*,*,*,*")])
 
 (define_insn "*movdf_no_e_insn_sp64"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
@@ -3469,8 +3388,7 @@
   mov\\t%1, %0
   ldx\\t%1, %0
   stx\\t%r1, %0"
-  [(set_attr "type" "move,load,store")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,load,store")])
 
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
@@ -3800,7 +3718,7 @@
   #
   #"
   [(set_attr "type" "fpmove,fpload,fpstore,*,*")
-   (set_attr "length" "1,1,1,2,2")])
+   (set_attr "length" "*,*,*,2,2")])
 
 (define_insn "*movtf_insn_hq_vis_sp64"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=e,e,m,eo,r,o")
@@ -3820,7 +3738,7 @@
   #
   #"
   [(set_attr "type" "fpmove,fpload,fpstore,*,*,*")
-   (set_attr "length" "1,1,1,2,2,2")])
+   (set_attr "length" "*,*,*,2,2,2")])
 
 ;; Now we allow the integer register cases even when
 ;; only arch64 is true.
@@ -4213,8 +4131,7 @@
   "@
    mov%C1\\t%x2, %3, %0
    mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movhi_cc_sp64"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -4227,8 +4144,7 @@
   "@
    mov%C1\\t%x2, %3, %0
    mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movsi_cc_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4241,8 +4157,7 @@
   "@
    mov%C1\\t%x2, %3, %0
    mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 ;; ??? The constraints of operands 3,4 need work.
 (define_insn "*movdi_cc_sp64"
@@ -4256,8 +4171,7 @@
   "@
    mov%C1\\t%x2, %3, %0
    mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movdi_cc_sp64_trunc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4270,8 +4184,7 @@
   "@
    mov%C1\\t%x2, %3, %0
    mov%c1\\t%x2, %4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movsf_cc_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4284,8 +4197,7 @@
   "@
    fmovs%C1\\t%x2, %3, %0
    fmovs%c1\\t%x2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpcmove")])
 
 (define_insn "movdf_cc_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e,e")
@@ -4299,7 +4211,7 @@
    fmovd%C1\\t%x2, %3, %0
    fmovd%c1\\t%x2, %4, %0"
   [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "*movtf_cc_hq_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -4312,8 +4224,7 @@
   "@
    fmovq%C1\\t%x2, %3, %0
    fmovq%c1\\t%x2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpcmove")])
 
 (define_insn "*movtf_cc_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -4324,16 +4235,15 @@
                          (match_operand:TF 4 "register_operand" "0,e")))]
   "TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
   "#"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+  [(set (match_operand:TF 0 "register_operand" "")
 	(if_then_else:TF (match_operator 1 "comparison_operator"
-				[(match_operand 2 "icc_or_fcc_reg_operand" "X,X")
+				[(match_operand 2 "icc_or_fcc_reg_operand" "")
 				 (const_int 0)])
-                         (match_operand:TF 3 "register_operand" "e,0")
-                         (match_operand:TF 4 "register_operand" "0,e")))]
+                         (match_operand:TF 3 "register_operand" "")
+                         (match_operand:TF 4 "register_operand" "")))]
   "reload_completed && TARGET_V9 && TARGET_FPU && !TARGET_HARD_QUAD"
   [(clobber (const_int 0))]
   "
@@ -4386,8 +4296,7 @@
   "@
    movr%D1\\t%2, %r3, %0
    movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movhi_cc_reg_sp64"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
@@ -4400,8 +4309,7 @@
   "@
    movr%D1\\t%2, %r3, %0
    movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movsi_cc_reg_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4414,8 +4322,7 @@
   "@
    movr%D1\\t%2, %r3, %0
    movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 ;; ??? The constraints of operands 3,4 need work.
 (define_insn "*movdi_cc_reg_sp64"
@@ -4429,8 +4336,7 @@
   "@
    movr%D1\\t%2, %r3, %0
    movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movdi_cc_reg_sp64_trunc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4443,8 +4349,7 @@
   "@
    movr%D1\\t%2, %r3, %0
    movr%d1\\t%2, %r4, %0"
-  [(set_attr "type" "cmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "cmove")])
 
 (define_insn "*movsf_cc_reg_sp64"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
@@ -4457,8 +4362,7 @@
   "@
    fmovrs%D1\\t%2, %3, %0
    fmovrs%d1\\t%2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpcmove")])
 
 (define_insn "movdf_cc_reg_sp64"
   [(set (match_operand:DF 0 "register_operand" "=e,e")
@@ -4472,7 +4376,7 @@
    fmovrd%D1\\t%2, %3, %0
    fmovrd%d1\\t%2, %4, %0"
   [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "*movtf_cc_reg_hq_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -4485,8 +4389,7 @@
   "@
    fmovrq%D1\\t%2, %3, %0
    fmovrq%d1\\t%2, %4, %0"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpcmove")])
 
 (define_insn "*movtf_cc_reg_sp64"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -4497,16 +4400,15 @@
                          (match_operand:TF 4 "register_operand" "0,e")))]
   "TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
   "#"
-  [(set_attr "type" "fpcmove")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
+  [(set (match_operand:TF 0 "register_operand" "")
 	(if_then_else:TF (match_operator 1 "v9_regcmp_op"
-				[(match_operand:DI 2 "register_operand" "r,r")
+				[(match_operand:DI 2 "register_operand" "")
 				 (const_int 0)])
-                         (match_operand:TF 3 "register_operand" "e,0")
-                         (match_operand:TF 4 "register_operand" "0,e")))]
+                         (match_operand:TF 3 "register_operand" "")
+                         (match_operand:TF 4 "register_operand" "")))]
   "reload_completed && TARGET_ARCH64 && TARGET_FPU && ! TARGET_HARD_QUAD"
   [(clobber (const_int 0))]
   "
@@ -4584,8 +4486,7 @@
 	(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
   ""
   "lduh\\t%1, %0"
-  [(set_attr "type" "load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "load")])
 
 (define_expand "zero_extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -4600,8 +4501,7 @@
   "@
    and\\t%1, 0xff, %0
    ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,load")])
 
 (define_expand "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4616,8 +4516,7 @@
   "@
    and\\t%1, 0xff, %0
    ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,load")])
 
 (define_expand "zero_extendqidi2"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -4632,8 +4531,7 @@
   "@
    and\\t%1, 0xff, %0
    ldub\\t%1, %0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,load")])
 
 (define_expand "zero_extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -4664,8 +4562,7 @@
 	(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_ARCH64"
   "lduh\\t%1, %0"
-  [(set_attr "type" "load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "load")])
 
 
 ;; ??? Write truncdisi pattern using sra?
@@ -4683,16 +4580,14 @@
   "@
    srl\\t%1, 0, %0
    lduw\\t%1, %0"
-  [(set_attr "type" "shift,load")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift,load")])
 
 (define_insn "*zero_extendsidi2_insn_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
   "! TARGET_ARCH64"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -4735,8 +4630,7 @@
 		    (const_int 0)))]
   ""
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_qi"
   [(set (reg:CC 100)
@@ -4744,8 +4638,7 @@
 		    (const_int 0)))]
   ""
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extendqisi2_set"
   [(set (reg:CC 100)
@@ -4755,8 +4648,7 @@
 	(zero_extend:SI (match_dup 1)))]
   ""
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extendqisi2_andcc_set"
   [(set (reg:CC 100)
@@ -4767,8 +4659,7 @@
 	(zero_extend:SI (subreg:QI (match_dup 1) 0)))]
   ""
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extendqidi2"
   [(set (reg:CCX 100)
@@ -4776,8 +4667,7 @@
 		     (const_int 0)))]
   "TARGET_ARCH64"
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_qi_sp64"
   [(set (reg:CCX 100)
@@ -4785,8 +4675,7 @@
 		     (const_int 0)))]
   "TARGET_ARCH64"
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extendqidi2_set"
   [(set (reg:CCX 100)
@@ -4796,8 +4685,7 @@
 	(zero_extend:DI (match_dup 1)))]
   "TARGET_ARCH64"
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extendqidi2_andcc_set"
   [(set (reg:CCX 100)
@@ -4808,8 +4696,7 @@
 	(zero_extend:DI (subreg:QI (match_dup 1) 0)))]
   "TARGET_ARCH64"
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; Similarly, handle {SI,DI}->QI mode truncation followed by a compare.
 
@@ -4819,8 +4706,7 @@
 		    (const_int 0)))]
   ""
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_siqi_trunc_set"
   [(set (reg:CC 100)
@@ -4830,8 +4716,7 @@
 	(subreg:QI (match_dup 1) 3))]
   ""
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_diqi_trunc"
   [(set (reg:CC 100)
@@ -4839,8 +4724,7 @@
 		    (const_int 0)))]
   "TARGET_ARCH64"
   "andcc\\t%0, 0xff, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_diqi_trunc_set"
   [(set (reg:CC 100)
@@ -4850,8 +4734,7 @@
 	(subreg:QI (match_dup 1) 7))]
   "TARGET_ARCH64"
   "andcc\\t%1, 0xff, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;;- sign extension instructions
 
@@ -4888,8 +4771,7 @@
 	(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
   ""
   "ldsh\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "sload")])
 
 (define_expand "extendqihi2"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -4929,8 +4811,7 @@
 	(sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
   ""
   "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "sload")])
 
 (define_expand "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -4961,8 +4842,7 @@
 	(sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
   ""
   "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "sload")])
 
 (define_expand "extendqidi2"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -4993,8 +4873,7 @@
 	(sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
   "TARGET_ARCH64"
   "ldsb\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "sload")])
 
 (define_expand "extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -5025,8 +4904,7 @@
 	(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
   "TARGET_ARCH64"
   "ldsh\\t%1, %0"
-  [(set_attr "type" "sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "sload")])
 
 (define_expand "extendsidi2"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -5041,8 +4919,7 @@
   "@
   sra\\t%1, 0, %0
   ldsw\\t%1, %0"
-  [(set_attr "type" "shift,sload")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift,sload")])
 
 ;; Special pattern for optimizing bit-field compares.  This is needed
 ;; because combine uses this as a canonical form.
@@ -5072,8 +4949,7 @@
   operands[1] = GEN_INT (mask);
   return \"andcc\\t%0, %1, %%g0\";
 }"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_zero_extract_sp64"
   [(set (reg:CCX 100)
@@ -5101,8 +4977,7 @@
   operands[1] = GEN_INT (mask);
   return \"andcc\\t%0, %1, %%g0\";
 }"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; Conversions between float, double and long double.
 
@@ -5113,7 +4988,7 @@
   "TARGET_FPU"
   "fstod\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "extendsftf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5148,8 +5023,7 @@
 	 (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fstoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "extenddftf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5184,8 +5058,7 @@
 	 (match_operand:DF 1 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fdtoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_insn "truncdfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -5194,7 +5067,7 @@
   "TARGET_FPU"
   "fdtos\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "trunctfsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -5228,8 +5101,7 @@
 	 (match_operand:TF 1 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fqtos\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "trunctfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -5263,8 +5135,7 @@
 	 (match_operand:TF 1 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fqtod\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 ;; Conversion between fixed point and floating point.
 
@@ -5274,7 +5145,7 @@
   "TARGET_FPU"
   "fitos\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "floatsidf2"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -5282,7 +5153,7 @@
   "TARGET_FPU"
   "fitod\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "floatsitf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5315,8 +5186,7 @@
 	(float:TF (match_operand:SI 1 "register_operand" "f")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fitoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "floatunssitf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5349,7 +5219,7 @@
   "TARGET_V9 && TARGET_FPU"
   "fxtos\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -5357,7 +5227,7 @@
   "TARGET_V9 && TARGET_FPU"
   "fxtod\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "floatditf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5390,8 +5260,7 @@
 	(float:TF (match_operand:DI 1 "register_operand" "e")))]
   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
   "fxtoq\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "floatunsditf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -5425,7 +5294,7 @@
   "TARGET_FPU"
   "fstoi\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
@@ -5433,7 +5302,7 @@
   "TARGET_FPU"
   "fdtoi\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "fix_trunctfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
@@ -5465,8 +5334,7 @@
 	(fix:SI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fqtoi\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "fixuns_trunctfsi2"
   [(set (match_operand:SI 0 "register_operand" "=f")
@@ -5498,7 +5366,7 @@
   "TARGET_V9 && TARGET_FPU"
   "fstox\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=e")
@@ -5506,7 +5374,7 @@
   "TARGET_V9 && TARGET_FPU"
   "fdtox\\t%1, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_expand "fix_trunctfdi2"
   [(set (match_operand:DI 0 "register_operand" "=e")
@@ -5538,8 +5406,7 @@
 	(fix:DI (fix:TF (match_operand:TF 1 "register_operand" "e"))))]
   "TARGET_V9 && TARGET_FPU && TARGET_HARD_QUAD"
   "fqtox\\t%1, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "fixuns_trunctfdi2"
   [(set (match_operand:DI 0 "register_operand" "=f")
@@ -5612,9 +5479,9 @@
   [(set_attr "length" "2")])
 
 (define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
-		 (match_operand:DI 2 "arith_double_operand" "rHI")))
+  [(set (match_operand:DI 0 "register_operand" "")
+	(plus:DI (match_operand:DI 1 "arith_double_operand" "")
+		 (match_operand:DI 2 "arith_double_operand" "")))
    (clobber (reg:CC 100))]
   "! TARGET_ARCH64 && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
@@ -5648,9 +5515,9 @@
 }")
 
 (define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(minus:DI (match_operand:DI 1 "arith_double_operand" "r")
-		  (match_operand:DI 2 "arith_double_operand" "rHI")))
+  [(set (match_operand:DI 0 "register_operand" "")
+	(minus:DI (match_operand:DI 1 "arith_double_operand" "")
+		  (match_operand:DI 2 "arith_double_operand" "")))
    (clobber (reg:CC 100))]
   "! TARGET_ARCH64 && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
@@ -5691,8 +5558,7 @@
 		 (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
   ""
   "addx\\t%1, %2, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*addx_extend_sp32"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5701,8 +5567,7 @@
                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -5723,8 +5588,7 @@
                                  (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "TARGET_ARCH64"
   "addx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "subx"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -5733,8 +5597,7 @@
 		  (ltu:SI (reg:CC_NOOV 100) (const_int 0))))]
   ""
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*subx_extend_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5743,8 +5606,7 @@
                                   (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "TARGET_ARCH64"
   "subx\\t%r1, %2, %0"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "*subx_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5753,13 +5615,12 @@
                                   (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
-                                            (match_operand:SI 2 "arith_operand" "rI"))
+  [(set (match_operand:DI 0 "register_operand" "")
+	(zero_extend:DI (minus:SI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
+                                            (match_operand:SI 2 "arith_operand" ""))
                                   (ltu:SI (reg:CC_NOOV 100) (const_int 0)))))]
   "! TARGET_ARCH64 && reload_completed"
   [(set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 2))
@@ -5775,8 +5636,7 @@
    (clobber (reg:CC 100))]
   "! TARGET_ARCH64"
   "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -5801,9 +5661,7 @@
 	(plus:DI (match_operand:DI 1 "arith_double_operand" "%r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
-  "add\\t%1, %2, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+  "add\\t%1, %2, %0")
 
 (define_expand "addsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -5833,8 +5691,7 @@
   "@
    add\\t%1, %2, %0
    fpadd32s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,fp")])
 
 (define_insn "*cmp_cc_plus"
   [(set (reg:CC_NOOV 100)
@@ -5843,8 +5700,7 @@
 			 (const_int 0)))]
   ""
   "addcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_plus"
   [(set (reg:CCX_NOOV 100)
@@ -5853,8 +5709,7 @@
 			  (const_int 0)))]
   "TARGET_ARCH64"
   "addcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_plus_set"
   [(set (reg:CC_NOOV 100)
@@ -5865,8 +5720,7 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "addcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_plus_set"
   [(set (reg:CCX_NOOV 100)
@@ -5877,8 +5731,7 @@
 	(plus:DI (match_dup 1) (match_dup 2)))]
   "TARGET_ARCH64"
   "addcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_expand "subdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -5979,8 +5832,7 @@
    (clobber (reg:CC 100))]
   "! TARGET_ARCH64"
   "#"
-  [(set_attr "type" "multi")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6005,9 +5857,7 @@
 	(minus:DI (match_operand:DI 1 "register_operand" "r")
 		  (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
-  "sub\\t%1, %2, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+  "sub\\t%1, %2, %0")
 
 (define_expand "subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -6033,8 +5883,7 @@
   "@
    sub\\t%1, %2, %0
    fpsub32s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,fp")])
 
 (define_insn "*cmp_minus_cc"
   [(set (reg:CC_NOOV 100)
@@ -6043,8 +5892,7 @@
 			 (const_int 0)))]
   ""
   "subcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_minus_ccx"
   [(set (reg:CCX_NOOV 100)
@@ -6053,8 +5901,7 @@
 			  (const_int 0)))]
   "TARGET_ARCH64"
   "subcc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "cmp_minus_cc_set"
   [(set (reg:CC_NOOV 100)
@@ -6065,8 +5912,7 @@
 	(minus:SI (match_dup 1) (match_dup 2)))]
   ""
   "subcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_minus_ccx_set"
   [(set (reg:CCX_NOOV 100)
@@ -6077,8 +5923,7 @@
 	(minus:DI (match_dup 1) (match_dup 2)))]
   "TARGET_ARCH64"
   "subcc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; Integer Multiply/Divide.
 
@@ -6091,8 +5936,7 @@
 		 (match_operand:SI 2 "arith_operand" "rI")))]
   "TARGET_HARD_MUL"
   "smul\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 (define_expand "muldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -6114,8 +5958,7 @@
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
   "mulx\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 ;; V8plus wide multiply.
 ;; XXX
@@ -6146,7 +5989,8 @@
   else
     return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
 }"
-  [(set_attr "length" "9,8")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "9,8")])
 
 (define_insn "*cmp_mul_set"
   [(set (reg:CC 100)
@@ -6157,8 +6001,7 @@
 	(mult:SI (match_dup 1) (match_dup 2)))]
   "TARGET_V8 || TARGET_SPARCLITE || TARGET_DEPRECATED_V8_INSNS"
   "smulcc\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 (define_expand "mulsidi3"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6196,7 +6039,8 @@
   "@
    smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
    smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2,3")])
 
 ;; XXX
 (define_insn "const_mulsidi3_v8plus"
@@ -6208,7 +6052,8 @@
   "@
    smul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
    smul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2,3")])
 
 ;; XXX
 (define_insn "*mulsidi3_sp32"
@@ -6220,7 +6065,10 @@
 {
   return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
 }"
-  [(set (attr "length")
+  [(set (attr "type")
+	(if_then_else (eq_attr "isa" "sparclet")
+		      (const_string "imul") (const_string "multi")))
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
@@ -6230,7 +6078,7 @@
 		 (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "smul\\t%1, %2, %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 ;; Extra pattern, because sign_extend of a constant isn't valid.
 
@@ -6244,7 +6092,10 @@
 {
   return TARGET_SPARCLET ? \"smuld\\t%1, %2, %L0\" : \"smul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
 }"
-  [(set (attr "length")
+  [(set (attr "type")
+	(if_then_else (eq_attr "isa" "sparclet")
+		      (const_string "imul") (const_string "multi")))
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
@@ -6254,7 +6105,7 @@
 		 (match_operand:SI 2 "small_int" "I")))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "smul\\t%1, %2, %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 (define_expand "smulsi3_highpart"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6298,7 +6149,8 @@
   "@
    smul\\t%1, %2, %0\;srlx\\t%0, %3, %0
    smul\\t%1, %2, %4\;srlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; The combiner changes TRUNCATE in the previous pattern to SUBREG.
 ;; XXX
@@ -6315,7 +6167,8 @@
   "@
    smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
    smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "const_smulsi3_highpart_v8plus"
@@ -6329,7 +6182,8 @@
   "@
    smul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
    smul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "*smulsi3_highpart_sp32"
@@ -6340,7 +6194,8 @@
 		      (const_int 32))))]
   "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "const_smulsi3_highpart"
@@ -6351,7 +6206,8 @@
 		      (const_int 32))))]
   "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_expand "umulsidi3"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6387,7 +6243,8 @@
   "@
    umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
    umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2,3")])
 
 ;; XXX
 (define_insn "*umulsidi3_sp32"
@@ -6399,7 +6256,10 @@
 {
   return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
 }"
-  [(set (attr "length")
+  [(set (attr "type")
+        (if_then_else (eq_attr "isa" "sparclet")
+                      (const_string "imul") (const_string "multi")))
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
@@ -6409,7 +6269,7 @@
 		 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "umul\\t%1, %2, %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 ;; Extra pattern, because sign_extend of a constant isn't valid.
 
@@ -6423,7 +6283,10 @@
 {
   return TARGET_SPARCLET ? \"umuld\\t%1, %2, %L0\" : \"umul\\t%1, %2, %L0\\n\\trd\\t%%y, %H0\";
 }"
-  [(set (attr "length")
+  [(set (attr "type")
+	(if_then_else (eq_attr "isa" "sparclet")
+		      (const_string "imul") (const_string "multi")))
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "sparclet")
 		      (const_int 1) (const_int 2)))])
 
@@ -6433,7 +6296,7 @@
 		 (match_operand:SI 2 "uns_small_int" "")))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "umul\\t%1, %2, %0"
-  [(set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 ;; XXX
 (define_insn "const_umulsidi3_v8plus"
@@ -6445,7 +6308,8 @@
   "@
    umul\\t%1, %2, %L0\\n\\tsrlx\\t%L0, 32, %H0
    umul\\t%1, %2, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0"
-  [(set_attr "length" "2,3")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2,3")])
 
 (define_expand "umulsi3_highpart"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6489,7 +6353,8 @@
   "@
    umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
    umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "const_umulsi3_highpart_v8plus"
@@ -6503,7 +6368,8 @@
   "@
    umul\\t%1, %2, %0\\n\\tsrlx\\t%0, %3, %0
    umul\\t%1, %2, %4\\n\\tsrlx\\t%4, %3, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "*umulsi3_highpart_sp32"
@@ -6514,7 +6380,8 @@
 		      (const_int 32))))]
   "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; XXX
 (define_insn "const_umulsi3_highpart"
@@ -6525,7 +6392,8 @@
 		      (const_int 32))))]
   "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; The v8 architecture specifies that there must be 3 instructions between
 ;; a y register write and a use of it for correct results.
@@ -6568,7 +6436,8 @@
     else
       return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tld\\t%2, %3\\n\\tnop\\n\\tnop\\n\\tsdiv\\t%1, %3, %0\";
 }"
-  [(set (attr "length")
+  [(set_attr "type" "multi")
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
 		      (const_int 4) (const_int 7)))])
 
@@ -6579,14 +6448,16 @@
    (use (match_operand:SI 3 "register_operand" "r"))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "wr\\t%%g0, %3, %%y\\n\\tsdiv\\t%1, %2, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "divdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(div:DI (match_operand:DI 1 "register_operand" "r")
 		(match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
-  "sdivx\\t%1, %2, %0")
+  "sdivx\\t%1, %2, %0"
+  [(set_attr "type" "idiv")])
 
 (define_insn "*cmp_sdiv_cc_set"
   [(set (reg:CC 100)
@@ -6604,7 +6475,8 @@
   else
     return \"sra\\t%1, 31, %3\\n\\twr\\t%3, 0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tsdivcc\\t%1, %2, %0\";
 }"
-  [(set (attr "length")
+  [(set_attr "type" "multi")
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
 		      (const_int 3) (const_int 6)))])
 
@@ -6636,7 +6508,8 @@
       return \"ld\\t%1, %0\\n\\tnop\\n\\tnop\\n\\tudiv\\t%0, %2, %0\";
     }
 }"
-  [(set_attr "length" "5")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "5")])
 
 (define_insn "udivsi3_sp64"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -6644,14 +6517,16 @@
 		 (match_operand:SI 2 "input_operand" "rI")))]
   "TARGET_DEPRECATED_V8_INSNS && TARGET_ARCH64"
   "wr\\t%%g0, 0, %%y\\n\\tudiv\\t%1, %2, %0"
-  [(set_attr "length" "2")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "udivdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(udiv:DI (match_operand:DI 1 "register_operand" "r")
 		 (match_operand:DI 2 "arith_double_operand" "rHI")))]
   "TARGET_ARCH64"
-  "udivx\\t%1, %2, %0")
+  "udivx\\t%1, %2, %0"
+  [(set_attr "type" "idiv")])
 
 (define_insn "*cmp_udiv_cc_set"
   [(set (reg:CC 100)
@@ -6669,7 +6544,8 @@
   else
     return \"wr\\t%%g0, %%g0, %%y\\n\\tnop\\n\\tnop\\n\\tnop\\n\\tudivcc\\t%1, %2, %0\";
 }"
-  [(set (attr "length")
+  [(set_attr "type" "multi")
+   (set (attr "length")
 	(if_then_else (eq_attr "isa" "v9")
 		      (const_int 2) (const_int 5)))])
 
@@ -6682,8 +6558,7 @@
 		 (match_operand:SI 3 "register_operand" "0")))]
   "TARGET_SPARCLET"
   "smac\\t%1, %2, %0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 (define_insn "*smacdi"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -6694,8 +6569,7 @@
 		 (match_operand:DI 3 "register_operand" "0")))]
   "TARGET_SPARCLET"
   "smacd\\t%1, %2, %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 (define_insn "*umacdi"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -6706,8 +6580,7 @@
 		 (match_operand:DI 3 "register_operand" "0")))]
   "TARGET_SPARCLET"
   "umacd\\t%1, %2, %L0"
-  [(set_attr "type" "imul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "imul")])
 
 ;;- Boolean instructions
 ;; We define DImode `and' so with DImode `not' we can get
@@ -6728,8 +6601,9 @@
   "@
   #
   fand\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_insn "*anddi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r,b")
@@ -6739,8 +6613,8 @@
   "@
    and\\t%1, %2, %0
    fand\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -6750,8 +6624,7 @@
   "@
    and\\t%1, %2, %0
    fands\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6813,8 +6686,9 @@
   "@
    #
    fandnot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6846,8 +6720,8 @@
   "@
    andn\\t%2, %1, %0
    fandnot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*and_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -6857,8 +6731,7 @@
   "@
    andn\\t%2, %1, %0
    fandnot1s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_expand "iordi3"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6875,8 +6748,9 @@
   "@
   #
   for\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_insn "*iordi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r,b")
@@ -6886,8 +6760,8 @@
   "@
   or\\t%1, %2, %0
   for\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -6897,8 +6771,7 @@
   "@
    or\\t%1, %2, %0
    fors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -6923,8 +6796,9 @@
   "@
    #
    fornot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "2,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6956,8 +6830,8 @@
   "@
   orn\\t%2, %1, %0
   fornot1\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*or_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -6967,8 +6841,7 @@
   "@
    orn\\t%2, %1, %0
    fornot1s\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_expand "xordi3"
   [(set (match_operand:DI 0 "register_operand" "")
@@ -6985,8 +6858,9 @@
   "@
   #
   fxor\\t%1, %2, %0"
-  [(set_attr "length" "2,1")
-   (set_attr "type" "ialu,fp")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_insn "*xordi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r,b")
@@ -6996,8 +6870,8 @@
   "@
   xor\\t%r1, %2, %0
   fxor\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*xordi3_sp64_dbl"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -7005,9 +6879,7 @@
 		(match_operand:DI 2 "const64_operand" "")))]
   "(TARGET_ARCH64
     && HOST_BITS_PER_WIDE_INT != 64)"
-  "xor\\t%1, %2, %0"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "xor\\t%1, %2, %0")
 
 (define_insn "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -7017,8 +6889,7 @@
   "@
    xor\\t%r1, %2, %0
    fxors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "")
@@ -7060,8 +6931,9 @@
   "@
    #
    fxnor\\t%1, %2, %0"
-  [(set_attr "length" "2,1")
-   (set_attr "type" "ialu,fp")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -7093,8 +6965,8 @@
   "@
   xnor\\t%r1, %2, %0
   fxnor\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "*xor_not_si"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -7104,8 +6976,7 @@
   "@
    xnor\\t%r1, %2, %0
    fxnors\\t%1, %2, %0"
-  [(set_attr "type" "ialu,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 ;; These correspond to the above in the case where we also (or only)
 ;; want to set the condition code.  
@@ -7119,8 +6990,7 @@
 	 (const_int 0)))]
   ""
   "%A2cc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_arith_op"
   [(set (reg:CCX 100)
@@ -7131,8 +7001,7 @@
 	 (const_int 0)))]
   "TARGET_ARCH64"
   "%A2cc\\t%0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_arith_op_set"
   [(set (reg:CC 100)
@@ -7145,8 +7014,7 @@
 	(match_operator:SI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
   "GET_CODE (operands[3]) == GET_CODE (operands[4])"
   "%A3cc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_arith_op_set"
   [(set (reg:CCX 100)
@@ -7159,8 +7027,7 @@
 	(match_operator:DI 4 "cc_arithop" [(match_dup 1) (match_dup 2)]))]
   "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
   "%A3cc\\t%1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_xor_not"
   [(set (reg:CC 100)
@@ -7170,8 +7037,7 @@
 	 (const_int 0)))]
   ""
   "xnorcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_xor_not"
   [(set (reg:CCX 100)
@@ -7181,8 +7047,7 @@
 	 (const_int 0)))]
   "TARGET_ARCH64"
   "xnorcc\\t%r0, %1, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_xor_not_set"
   [(set (reg:CC 100)
@@ -7194,8 +7059,7 @@
 	(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
   ""
   "xnorcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_xor_not_set"
   [(set (reg:CCX 100)
@@ -7207,8 +7071,7 @@
 	(not:DI (xor:DI (match_dup 1) (match_dup 2))))]
   "TARGET_ARCH64"
   "xnorcc\\t%r1, %2, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_arith_op_not"
   [(set (reg:CC 100)
@@ -7219,8 +7082,7 @@
 	 (const_int 0)))]
   ""
   "%B2cc\\t%r1, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_arith_op_not"
   [(set (reg:CCX 100)
@@ -7231,8 +7093,7 @@
 	 (const_int 0)))]
   "TARGET_ARCH64"
   "%B2cc\\t%r1, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_arith_op_not_set"
   [(set (reg:CC 100)
@@ -7246,8 +7107,7 @@
 			    [(not:SI (match_dup 1)) (match_dup 2)]))]
   "GET_CODE (operands[3]) == GET_CODE (operands[4])"
   "%B3cc\\t%r2, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_arith_op_not_set"
   [(set (reg:CCX 100)
@@ -7261,8 +7121,7 @@
 			    [(not:DI (match_dup 1)) (match_dup 2)]))]
   "TARGET_ARCH64 && GET_CODE (operands[3]) == GET_CODE (operands[4])"
   "%B3cc\\t%r2, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; We cannot use the "neg" pseudo insn because the Sun assembler
 ;; does not know how to make it work for constants.
@@ -7293,8 +7152,7 @@
    (clobber (reg:CC 100))]
   "TARGET_ARCH32"
   "#"
-  [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+  [(set_attr "length" "2")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -7317,17 +7175,13 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))]
   "TARGET_ARCH64"
-  "sub\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
+  "sub\\t%%g0, %1, %0")
 
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
         (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
   ""
-  "sub\\t%%g0, %1, %0"
-  [(set_attr "type" "unary")
-   (set_attr "length" "1")])
+  "sub\\t%%g0, %1, %0")
 
 (define_insn "*cmp_cc_neg"
   [(set (reg:CC_NOOV 100)
@@ -7335,8 +7189,7 @@
 			 (const_int 0)))]
   ""
   "subcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_neg"
   [(set (reg:CCX_NOOV 100)
@@ -7344,8 +7197,7 @@
 			  (const_int 0)))]
   "TARGET_ARCH64"
   "subcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_set_neg"
   [(set (reg:CC_NOOV 100)
@@ -7355,8 +7207,7 @@
 	(neg:SI (match_dup 1)))]
   ""
   "subcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_set_neg"
   [(set (reg:CCX_NOOV 100)
@@ -7366,8 +7217,7 @@
 	(neg:DI (match_dup 1)))]
   "TARGET_ARCH64"
   "subcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; We cannot use the "not" pseudo insn because the Sun assembler
 ;; does not know how to make it work for constants.
@@ -7384,8 +7234,9 @@
   "@
    #
    fnot1\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "2,1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "length" "2,*")
+   (set_attr "fptype" "double")])
 
 (define_split
   [(set (match_operand:DI 0 "register_operand" "")
@@ -7413,8 +7264,8 @@
   "@
    xnor\\t%%g0, %1, %0
    fnot1\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "*,fp")
+   (set_attr "fptype" "double")])
 
 (define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
@@ -7423,8 +7274,7 @@
   "@
   xnor\\t%%g0, %1, %0
   fnot1s\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "*,fp")])
 
 (define_insn "*cmp_cc_not"
   [(set (reg:CC 100)
@@ -7432,8 +7282,7 @@
 		    (const_int 0)))]
   ""
   "xnorcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_not"
   [(set (reg:CCX 100)
@@ -7441,8 +7290,7 @@
 		     (const_int 0)))]
   "TARGET_ARCH64"
   "xnorcc\\t%%g0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_set_not"
   [(set (reg:CC 100)
@@ -7452,8 +7300,7 @@
 	(not:SI (match_dup 1)))]
   ""
   "xnorcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_ccx_set_not"
   [(set (reg:CCX 100)
@@ -7463,8 +7310,7 @@
 	(not:DI (match_dup 1)))]
   "TARGET_ARCH64"
   "xnorcc\\t%%g0, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 ;; Floating point arithmetic instructions.
 
@@ -7516,8 +7362,7 @@
 		 (match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "faddq\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_insn "adddf3"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -7526,7 +7371,7 @@
   "TARGET_FPU"
   "faddd\\t%1, %2, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -7534,8 +7379,7 @@
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
   "fadds\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "subtf3"
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
@@ -7585,8 +7429,7 @@
 		  (match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fsubq\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_insn "subdf3"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -7595,7 +7438,7 @@
   "TARGET_FPU"
   "fsubd\\t%1, %2, %0"
   [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "subsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -7603,8 +7446,7 @@
 		  (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
   "fsubs\\t%1, %2, %0"
-  [(set_attr "type" "fp")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fp")])
 
 (define_expand "multf3"
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
@@ -7654,8 +7496,7 @@
 		 (match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fmulq\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmul")])
 
 (define_insn "muldf3"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -7664,7 +7505,7 @@
   "TARGET_FPU"
   "fmuld\\t%1, %2, %0"
   [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -7672,8 +7513,7 @@
 		 (match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
   "fmuls\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmul")])
 
 (define_insn "*muldf3_extend"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -7682,7 +7522,7 @@
   "(TARGET_V8 || TARGET_V9) && TARGET_FPU"
   "fsmuld\\t%1, %2, %0"
   [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "*multf3_extend"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -7690,8 +7530,7 @@
 		 (float_extend:TF (match_operand:DF 2 "register_operand" "e"))))]
   "(TARGET_V8 || TARGET_V9) && TARGET_FPU && TARGET_HARD_QUAD"
   "fdmulq\\t%1, %2, %0"
-  [(set_attr "type" "fpmul")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmul")])
 
 (define_expand "divtf3"
   [(set (match_operand:TF 0 "nonimmediate_operand" "")
@@ -7742,8 +7581,7 @@
 		(match_operand:TF 2 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fdivq\\t%1, %2, %0"
-  [(set_attr "type" "fpdivd")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpdivd")])
 
 (define_insn "divdf3"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -7752,7 +7590,7 @@
   "TARGET_FPU"
   "fdivd\\t%1, %2, %0"
   [(set_attr "type" "fpdivd")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "divsf3"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -7760,8 +7598,7 @@
 		(match_operand:SF 2 "register_operand" "f")))]
   "TARGET_FPU"
   "fdivs\\t%1, %2, %0"
-  [(set_attr "type" "fpdivs")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpdivs")])
 
 (define_expand "negtf2"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -7778,8 +7615,8 @@
   "@
   fnegs\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")])
 
 (define_split
   [(set (match_operand:TF 0 "register_operand" "")
@@ -7810,8 +7647,9 @@
   "@
   fnegd\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")
+   (set_attr "fptype" "double")])
 
 (define_split
   [(set (match_operand:TF 0 "register_operand" "")
@@ -7844,8 +7682,8 @@
   "@
   fnegs\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")])
 
 (define_split
   [(set (match_operand:DF 0 "register_operand" "")
@@ -7871,15 +7709,14 @@
   "TARGET_FPU && TARGET_V9"
   "fnegd\\t%1, %0"
   [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_FPU"
   "fnegs\\t%1, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmove")])
 
 (define_expand "abstf2"
   [(set (match_operand:TF 0 "register_operand" "")
@@ -7895,12 +7732,12 @@
   "@
   fabss\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")])
 
 (define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+	(abs:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_FPU
    && ! TARGET_V9
    && reload_completed
@@ -7927,7 +7764,7 @@
   fabsd\\t%0, %0
   fabsq\\t%1, %0"
   [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double,*")])
 
 (define_insn "*abstf2_v9"
   [(set (match_operand:TF 0 "register_operand" "=e,e")
@@ -7936,12 +7773,13 @@
   "@
   fabsd\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")
+   (set_attr "fptype" "double,*")])
 
 (define_split
-  [(set (match_operand:TF 0 "register_operand" "=e,e")
-	(abs:TF (match_operand:TF 1 "register_operand" "0,e")))]
+  [(set (match_operand:TF 0 "register_operand" "")
+	(abs:TF (match_operand:TF 1 "register_operand" "")))]
   "TARGET_FPU
    && TARGET_V9
    && reload_completed
@@ -7970,12 +7808,12 @@
   "@
   fabss\\t%0, %0
   #"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1,2")])
+  [(set_attr "type" "fpmove,*")
+   (set_attr "length" "*,2")])
 
 (define_split
-  [(set (match_operand:DF 0 "register_operand" "=e,e")
-	(abs:DF (match_operand:DF 1 "register_operand" "0,e")))]
+  [(set (match_operand:DF 0 "register_operand" "")
+	(abs:DF (match_operand:DF 1 "register_operand" "")))]
   "TARGET_FPU
    && ! TARGET_V9
    && reload_completed
@@ -7997,15 +7835,14 @@
   "TARGET_FPU && TARGET_V9"
   "fabsd\\t%1, %0"
   [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "abssf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(abs:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_FPU"
   "fabss\\t%1, %0"
-  [(set_attr "type" "fpmove")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpmove")])
 
 (define_expand "sqrttf2"
   [(set (match_operand:TF 0 "register_operand" "=e")
@@ -8045,8 +7882,7 @@
 	(sqrt:TF (match_operand:TF 1 "register_operand" "e")))]
   "TARGET_FPU && TARGET_HARD_QUAD"
   "fsqrtq\\t%1, %0"
-  [(set_attr "type" "fpsqrtd")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpsqrtd")])
 
 (define_insn "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "=e")
@@ -8054,15 +7890,14 @@
   "TARGET_FPU"
   "fsqrtd\\t%1, %0"
   [(set_attr "type" "fpsqrtd")
-   (set_attr "length" "1")])
+   (set_attr "fptype" "double")])
 
 (define_insn "sqrtsf2"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
   "TARGET_FPU"
   "fsqrts\\t%1, %0"
-  [(set_attr "type" "fpsqrts")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpsqrts")])
 
 ;;- arithmetic shift instructions
 
@@ -8079,8 +7914,7 @@
 
   return \"sll\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; We special case multiplication by two, as add can be done
 ;; in both ALUs, while shift only in IEU0 on UltraSPARC.
@@ -8089,9 +7923,7 @@
         (ashift:SI (match_operand:SI 1 "register_operand" "r")
                    (const_int 1)))]
   ""
-  "add\\t%1, %1, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+  "add\\t%1, %1, %0")
 
 (define_expand "ashldi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8116,9 +7948,7 @@
 	(ashift:DI (match_operand:DI 1 "register_operand" "r")
 		   (const_int 1)))]
   "TARGET_ARCH64"
-  "add\\t%1, %1, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+  "add\\t%1, %1, %0")
 
 (define_insn "*ashldi3_sp64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8133,8 +7963,7 @@
 
   return \"sllx\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; XXX UGH!
 (define_insn "ashldi3_v8plus"
@@ -8144,7 +7973,8 @@
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
   "*return sparc_v8plus_shift (operands, insn, \"sllx\");"
-  [(set_attr "length" "5,5,6")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "5,5,6")])
 
 ;; Optimize (1LL<<x)-1
 ;; XXX this also needs to be fixed to handle equal subregs
@@ -8161,7 +7991,8 @@
 ;    return \"mov\\t1, %L0\;sllx\\t%L0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
 ;  return \"mov\\t1, %H0\;sllx\\t%H0, %1, %L0\;sub\\t%L0, 1, %L0\;srlx\\t%L0, 32, %H0\";
 ;}"
-;  [(set_attr "length" "4")])
+;  [(set_attr "type" "multi")
+;   (set_attr "length" "4")])
 
 (define_insn "*cmp_cc_ashift_1"
   [(set (reg:CC_NOOV 100)
@@ -8170,8 +8001,7 @@
 			 (const_int 0)))]
   ""
   "addcc\\t%0, %0, %%g0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "*cmp_cc_set_ashift_1"
   [(set (reg:CC_NOOV 100)
@@ -8182,8 +8012,7 @@
 	(ashift:SI (match_dup 1) (const_int 1)))]
   ""
   "addcc\\t%1, %1, %0"
-  [(set_attr "type" "compare")
-   (set_attr "length" "1")])
+  [(set_attr "type" "compare")])
 
 (define_insn "ashrsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8198,8 +8027,7 @@
 
   return \"sra\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_insn "*ashrsi3_extend"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8207,8 +8035,7 @@
 				     (match_operand:SI 2 "arith_operand" "r"))))]
   "TARGET_ARCH64"
   "sra\\t%1, %2, %0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; This handles the case as above, but with constant shift instead of
 ;; register. Combiner "simplifies" it for us a little bit though.
@@ -8230,8 +8057,7 @@
 
   return \"sra\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8262,8 +8088,7 @@
 
   return \"srax\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; XXX
 (define_insn "ashrdi3_v8plus"
@@ -8273,7 +8098,8 @@
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
   "*return sparc_v8plus_shift (operands, insn, \"srax\");"
-  [(set_attr "length" "5,5,6")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "5,5,6")])
 
 (define_insn "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8288,8 +8114,7 @@
 
   return \"srl\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; This handles the case where
 ;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))),
@@ -8307,8 +8132,7 @@
 	   && GET_CODE (operands[3]) == CONST_INT
            && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff))"
   "srl\\t%1, %2, %0"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; This handles the case where
 ;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32))
@@ -8330,8 +8154,7 @@
 
   return \"srl\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_expand "lshrdi3"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -8362,8 +8185,7 @@
 
   return \"srlx\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; XXX
 (define_insn "lshrdi3_v8plus"
@@ -8373,7 +8195,8 @@
    (clobber (match_scratch:SI 3 "=X,X,&h"))]
   "TARGET_V8PLUS"
   "*return sparc_v8plus_shift (operands, insn, \"srlx\");"
-  [(set_attr "length" "5,5,6")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "5,5,6")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8392,8 +8215,7 @@
 
   return \"srax\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8412,8 +8234,7 @@
 
   return \"srlx\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8431,8 +8252,7 @@
 
   return \"srax\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -8450,8 +8270,7 @@
 
   return \"srlx\\t%1, %2, %0\";
 }"
-  [(set_attr "type" "shift")
-   (set_attr "length" "1")])
+  [(set_attr "type" "shift")])
 
 ;; Unconditional and other jump instructions
 ;; On the Sparc, by setting the annul bit on an unconditional branch, the
@@ -8915,7 +8734,8 @@
 	       (match_operand:SI 1 "register_operand" "r")] 1)]
   "! TARGET_ARCH64"
   "cmp\\t%1, 0\;be,a\\t.+8\;add\\t%0, 4, %0"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "3")])
 
 (define_insn "return"
   [(return)
@@ -8935,9 +8755,7 @@
 (define_insn "nop"
   [(const_int 0)]
   ""
-  "nop"
-  [(set_attr "type" "ialu")
-   (set_attr "length" "1")])
+  "nop")
 
 (define_expand "indirect_jump"
   [(set (pc) (match_operand 0 "address_operand" "p"))]
@@ -9024,14 +8842,13 @@
   [(unspec_volatile [(const_int 0)] 1)]
   ""
   "* return TARGET_V9 ? \"flushw\" : \"ta\\t3\";"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn "goto_handler_and_restore"
   [(unspec_volatile [(match_operand 0 "register_operand" "=r")] 2)]
   "GET_MODE (operands[0]) == Pmode"
   "jmp\\t%0+0\\n\\trestore"
-  [(set_attr "type" "misc")
+  [(set_attr "type" "multi")
    (set_attr "length" "2")])
 
 ;;(define_insn "goto_handler_and_restore_v9"
@@ -9042,7 +8859,7 @@
 ;;  "@
 ;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
 ;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;;  [(set_attr "type" "misc")
+;;  [(set_attr "type" "multi")
 ;;   (set_attr "length" "2,3")])
 ;;
 ;;(define_insn "*goto_handler_and_restore_v9_sp64"
@@ -9053,7 +8870,7 @@
 ;;  "@
 ;;   return\\t%0+0\\n\\tmov\\t%2, %Y1
 ;;   sethi\\t%%hi(%2), %1\\n\\treturn\\t%0+0\\n\\tor\\t%Y1, %%lo(%2), %Y1"
-;;  [(set_attr "type" "misc")
+;;  [(set_attr "type" "multi")
 ;;   (set_attr "length" "2,3")])
 
 ;; For __builtin_setjmp we need to flush register windows iff the function
@@ -9068,6 +8885,10 @@
   DONE;
 }")
 
+;; ??? Should set length to zero when !current_function_calls_alloca,
+;; ??? but there is no easy way to get at that definition.  It would
+;; ??? require including function.h into sparc-protos.h and that is
+;; ??? likely not a good idea. -DaveM
 (define_insn "do_builtin_setjmp_setup"
   [(unspec_volatile [(const_int 0)] 5)]
   ""
@@ -9079,8 +8900,7 @@
     return \"flushw\";
   return \"ta\\t3\";
 }"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 ;; Pattern for use after a setjmp to store FP and the return register
 ;; into the stack area.
@@ -9331,7 +9151,8 @@
   else
     return \"ret\\n\\trestore %%g0, %1, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_hi"
   [(set (match_operand:HI 0 "restore_operand" "")
@@ -9348,7 +9169,8 @@
   else
     return \"ret\;restore %%g0, %1, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_si"
   [(set (match_operand:SI 0 "restore_operand" "")
@@ -9365,7 +9187,8 @@
   else
     return \"ret\;restore %%g0, %1, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; The following pattern is only generated by delayed-branch scheduling,
 ;; when the insn winds up in the epilogue.  This can happen not only when
@@ -9385,7 +9208,8 @@
   else
     return \"ret\;restore %%g0, %1, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_df_no_fpu"
   [(set (match_operand:DF 0 "restore_operand" "=r")
@@ -9399,7 +9223,8 @@
   else
     return \"ret\;restore %%g0, %1, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_addsi"
   [(set (match_operand:SI 0 "restore_operand" "")
@@ -9419,7 +9244,8 @@
   else
     return \"ret\;restore %r1, %2, %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_losum_si"
   [(set (match_operand:SI 0 "restore_operand" "")
@@ -9437,7 +9263,8 @@
   else
     return \"ret\;restore %r1, %%lo(%a2), %Y0\";
 }"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_di"
   [(set (match_operand:DI 0 "restore_operand" "")
@@ -9445,7 +9272,8 @@
    (return)]
   "TARGET_ARCH64 && ! TARGET_EPILOGUE"
   "ret\;restore %%g0, %1, %Y0"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_adddi"
   [(set (match_operand:DI 0 "restore_operand" "")
@@ -9454,7 +9282,8 @@
    (return)]
   "TARGET_ARCH64 && ! TARGET_EPILOGUE"
   "ret\;restore %r1, %2, %Y0"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 (define_insn "*return_losum_di"
   [(set (match_operand:DI 0 "restore_operand" "")
@@ -9463,7 +9292,8 @@
    (return)]
   "TARGET_ARCH64 && ! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
   "ret\;restore %r1, %%lo(%a2), %Y0"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; The following pattern is only generated by delayed-branch scheduling,
 ;; when the insn winds up in the epilogue.
@@ -9473,7 +9303,8 @@
    (return)]
   "! TARGET_EPILOGUE"
   "ret\;fmovs\\t%0, %%f0"
-  [(set_attr "type" "multi")])
+  [(set_attr "type" "multi")
+   (set_attr "length" "2")])
 
 ;; Now peepholes to do a call followed by a jump.
 
@@ -9552,8 +9383,7 @@
   [(trap_if (const_int 1) (const_int 5))]
   ""
   "ta\\t5"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_expand "conditional_trap"
   [(trap_if (match_operator 0 "noov_compare_op"
@@ -9569,13 +9399,11 @@
 	    (match_operand:SI 1 "arith_operand" "rM"))]
   ""
   "t%C0\\t%1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])
 
 (define_insn ""
   [(trap_if (match_operator 0 "noov_compare_op" [(reg:CCX 100) (const_int 0)])
 	    (match_operand:SI 1 "arith_operand" "rM"))]
   "TARGET_V9"
   "t%C0\\t%%xcc, %1"
-  [(set_attr "type" "misc")
-   (set_attr "length" "1")])
+  [(set_attr "type" "misc")])