diff options
author | Aldy Hernandez <aldyh@redhat.com> | 2004-11-10 01:25:37 +0000 |
---|---|---|
committer | Aldy Hernandez <aldyh@redhat.com> | 2004-11-10 01:25:37 +0000 |
commit | 64b6f142520ef86f5dc7b93a8d3484184d475d1d (patch) | |
tree | d4a049b019bfa45692e2b2902bfd4cbf335b9737 | |
parent | 97bf2c4e7d3e708319a1fa1a879cb7cef7d46636 (diff) |
* config/rs6000/rs6000.md (fix_truncdfsi2): Handle e500
doubles.
(floatunssidf2): Same.
(floatsidf2): Same.
("extendsfdf2"): New expander.
(*extendsfdf2_fpr): Rename.
(*truncdfsf2_fpr): Same.
(*negdf2_fpr): Same.
(*absdf2_fpr): Same.
(*nabsdf2_fpr): Same.
(*adddf3_fpr): Same.
(*subdf3_fpr): Same.
(*muldf3_fpr): Same.
(*divdf3_fpr): Same.
* config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment.
("spe_fix_truncdfsi2"): Same.
(spe_floatunssidf2): Same.
(spe_floatsidf2): Same.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/gcc-3_4-e500-branch@90380 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog.e500 | 22 | ||||
-rw-r--r-- | gcc/config/rs6000/rs6000.md | 44 | ||||
-rw-r--r-- | gcc/config/rs6000/spe.md | 4 |
3 files changed, 55 insertions, 15 deletions
diff --git a/gcc/ChangeLog.e500 b/gcc/ChangeLog.e500 index d26234b3b24..b5ac9ed980e 100644 --- a/gcc/ChangeLog.e500 +++ b/gcc/ChangeLog.e500 @@ -1,3 +1,25 @@ +2004-11-09 Aldy Hernandez <aldyh@redhat.com> + + * config/rs6000/rs6000.md (fix_truncdfsi2): Handle e500 + doubles. + (floatunssidf2): Same. + (floatsidf2): Same. + ("extendsfdf2"): New expander. + (*extendsfdf2_fpr): Rename. + (*truncdfsf2_fpr): Same. + (*negdf2_fpr): Same. + (*absdf2_fpr): Same. + (*nabsdf2_fpr): Same. + (*adddf3_fpr): Same. + (*subdf3_fpr): Same. + (*muldf3_fpr): Same. + (*divdf3_fpr): Same. + + * config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment. + ("spe_fix_truncdfsi2"): Same. + (spe_floatunssidf2): Same. + (spe_floatsidf2): Same. + 2004-10-28 Aldy Hernandez <aldyh@redhat.com> * expr.c (emit_group_store): Fix undefine reference to MEM_P. diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index be4992ae88f..3f4dd047b39 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -4372,7 +4372,13 @@ ;; this case, we just lose precision that we would have otherwise gotten but ;; is not guaranteed. Perhaps this should be tightened up at some point. -(define_insn "extendsfdf2" +(define_expand "extendsfdf2" + [(set (match_operand:DF 0 "gpc_reg_operand" "") + (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" + "") + +(define_insn "*extendsfdf2_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS" @@ -4391,7 +4397,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_truncdfsf2" +(define_insn "*truncdfsf2_fpr" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS" @@ -4787,7 +4793,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_negdf2" +(define_insn "*negdf2_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS" @@ -4800,14 +4806,14 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_absdf2" +(define_insn "*absdf2_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "TARGET_HARD_FLOAT && TARGET_FPRS" "fabs %0,%1" [(set_attr "type" "fp")]) -(define_insn "fpr_nabsdf2" +(define_insn "*nabsdf2_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] "TARGET_HARD_FLOAT && TARGET_FPRS" @@ -4821,7 +4827,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_adddf3" +(define_insn "*adddf3_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")))] @@ -4836,7 +4842,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_subdf3" +(define_insn "*subdf3_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")))] @@ -4851,7 +4857,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_muldf3" +(define_insn "*muldf3_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")))] @@ -4866,7 +4872,7 @@ "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" "") -(define_insn "fpr_divdf3" +(define_insn "*divdf3_fpr" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")))] @@ -5037,6 +5043,11 @@ "TARGET_HARD_FLOAT && TARGET_FPRS" " { + if (TARGET_E500_DOUBLE) + { + emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); + DONE; + } if (TARGET_POWERPC64) { rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); @@ -5116,9 +5127,14 @@ (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "TARGET_HARD_FLOAT && TARGET_FPRS" + "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" " { + if (TARGET_E500_DOUBLE) + { + emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); + DONE; + } if (TARGET_POWERPC64) { rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); @@ -5185,9 +5201,15 @@ (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) (clobber (match_dup 2)) (clobber (match_dup 3))])] - "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" + "(TARGET_POWER2 || TARGET_POWERPC) + && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" " { + if (TARGET_E500_DOUBLE) + { + emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); + DONE; + } operands[2] = gen_reg_rtx (DImode); operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); }") diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md index 096e5e7d455..66fc9feb84f 100644 --- a/gcc/config/rs6000/spe.md +++ b/gcc/config/rs6000/spe.md @@ -93,7 +93,6 @@ "efdctuiz %0,%1" [(set_attr "type" "fp")]) -;; FIXME: fix expander. (define_insn "spe_extendsfdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=r") (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] @@ -115,7 +114,6 @@ "efsctsiz %0,%1" [(set_attr "type" "fp")]) -;; FIXME: fix expander. (define_insn "spe_fix_truncdfsi2" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] @@ -130,7 +128,6 @@ "efscfui %0,%1" [(set_attr "type" "fp")]) -;; FIXME: fix expander. (define_insn "spe_floatunssidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=r") (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] @@ -145,7 +142,6 @@ "efscfsi %0,%1" [(set_attr "type" "fp")]) -;; FIXME: fix expander. (define_insn "spe_floatsidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=r") (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] |