2006-05-05 Daniel Jacobowitz <dan@codesourcery.com>csl/sourcerygxx/3.4.4-19

	* gcc/config/mips/linux.h (MD_FALLBACK_FRAME_STATE_FOR): Support
	N32 and N64.

2006-05-05  Joseph Myers  <joseph@codesourcery.com>

	* gcc/testsuite/gcc.dg/20030121-1.c,
	gcc/fixinc/tests/base/internal/math_core.h: Fix SVN conversion
	errors.
	* gcc/testsuite/gcc.c-torture/execute/loop-2f.x,
	gcc/testsuite/gcc.c-torture/execute/loop-2g.x: New.  XFAIL on
	mips*-*-linux*.
	* gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C: Expect excess
	errors on mips*-*-linux*.
	* gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C: XFAIL execution
	on mips*-*-linux*.
	* gcc/testsuite/gcc.dg/builtins-18.c: Expect excess errors on
	mips*-*-linux*.
	* gcc/config/mips/mips.md (clzdi2): Restrict to TARGET_64BIT.

2006-05-05  Paul Brook  <paul@codesourcery.com>

	* gcc/testsuite/gcc.dg/20050629-1.c: Add missing close comment.

2006-05-05  Richard Sandiford  <richard@codesourcery.com>

	* gcc/reload1.c (inherit_piecemeal_p): New function.
	(emit_reload_insns): When reloading a group of hard registers, use
	inherit_piecemeal_p to decide whether the values of individual hard
	registers can be inherited.
	* gcc/testsuite/gcc.dg/torture/mips-hilo-2.c: New test.


git-svn-id: https://gcc.gnu.org/svn/gcc/branches/csl-gxxpro-3_4-branch@113578 138bc75d-0d04-0410-961f-82ee72b054a4

13 files changed, 158 insertions, 7 deletions

diff --git a/ChangeLog.csl b/ChangeLog.csl
index a7d4858a60c..ba323aa6920 100644
--- a/ChangeLog.csl
+++ b/ChangeLog.csl
@@ -1,3 +1,36 @@
+2006-05-05  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gcc/config/mips/linux.h (MD_FALLBACK_FRAME_STATE_FOR): Support
+	N32 and N64.
+
+2006-05-05  Joseph Myers  <joseph@codesourcery.com>
+
+	* gcc/testsuite/gcc.dg/20030121-1.c,
+	gcc/fixinc/tests/base/internal/math_core.h: Fix SVN conversion
+	errors.
+	* gcc/testsuite/gcc.c-torture/execute/loop-2f.x,
+	gcc/testsuite/gcc.c-torture/execute/loop-2g.x: New.  XFAIL on
+	mips*-*-linux*.
+	* gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C: Expect excess
+	errors on mips*-*-linux*.
+	* gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C: XFAIL execution
+	on mips*-*-linux*.
+	* gcc/testsuite/gcc.dg/builtins-18.c: Expect excess errors on
+	mips*-*-linux*.
+	* gcc/config/mips/mips.md (clzdi2): Restrict to TARGET_64BIT.
+
+2006-05-05  Paul Brook  <paul@codesourcery.com>
+
+	* gcc/testsuite/gcc.dg/20050629-1.c: Add missing close comment.
+
+2006-05-05  Richard Sandiford  <richard@codesourcery.com>
+
+	* gcc/reload1.c (inherit_piecemeal_p): New function.
+	(emit_reload_insns): When reloading a group of hard registers, use
+	inherit_piecemeal_p to decide whether the values of individual hard
+	registers can be inherited.
+	* gcc/testsuite/gcc.dg/torture/mips-hilo-2.c: New test.
+
 2006-04-30  Mark Mitchell  <mark@codesourcery.com>
 
 	Backport:
diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
index 5ec957f84c9..0c9ef4e8084 100644
--- a/gcc/config/mips/linux.h
+++ b/gcc/config/mips/linux.h
@@ -232,6 +232,24 @@ typedef struct _sig_ucontext {
         } *rt_ = (CONTEXT)->ra;                                      \
         sc_ = &rt_->uc.uc_mcontext;                                  \
       }                                                              \
+    else if (*(pc_ + 0) == 0x24021843)                               \
+      {                                                              \
+        struct rt_sigframe {                                         \
+          u_int32_t  trampoline[2];                                \
+          struct siginfo info;                                       \
+          _sig_ucontext_t uc;                                        \
+        } *rt_ = (CONTEXT)->ra;                                      \
+        sc_ = &rt_->uc.uc_mcontext;                                  \
+      }                                                              \
+    else if (*(pc_ + 0) == 0x2402145b)                               \
+      {                                                              \
+        struct rt_sigframe {                                         \
+          u_int32_t  trampoline[2];                                \
+          struct siginfo info;                                       \
+          _sig_ucontext_t uc;                                        \
+        } *rt_ = (CONTEXT)->ra;                                      \
+        sc_ = &rt_->uc.uc_mcontext;                                  \
+      }                                                              \
     else                                                             \
       break;                                                         \
                                                                      \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 7ceb3af333f..b2929694aaf 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2784,7 +2784,7 @@ dsrl\t%3,%3,1\n\
 (define_insn "clzdi2"
   [(set (match_operand:DI 0 "register_operand" "=d")
 	(clz:DI (match_operand:DI 1 "register_operand" "d")))]
-  "ISA_HAS_DCLZ_DCLO"
+  "TARGET_64BIT && ISA_HAS_DCLZ_DCLO"
   "dclz\t%0,%1"
   [(set_attr "type" "arith")
    (set_attr "mode" "DI")])
diff --git a/gcc/fixinc/tests/base/internal/math_core.h b/gcc/fixinc/tests/base/internal/math_core.h
index e69de29bb2d..f39ac3f90cf 100644
--- a/gcc/fixinc/tests/base/internal/math_core.h
+++ b/gcc/fixinc/tests/base/internal/math_core.h
@@ -0,0 +1,30 @@
+/*  DO NOT EDIT THIS FILE.
+
+    It has been auto-edited by fixincludes from:
+
+	"fixinc/tests/inc/internal/math_core.h"
+
+    This had to be done to correct non-standard usages in the
+    original, manufacturer supplied header file.  */
+
+
+
+#if defined( IRIX___GENERIC1_CHECK )
+extern int isnan(double);
+extern int isnanf(float);
+extern int isnanl(long double);
+#define isnan(x) (sizeof(x) == sizeof(double) ? _isnan(x) \
+               : sizeof(x) == sizeof(float) ? _isnanf(x) \
+               : _isnanl(x))
+
+
+#endif  /* IRIX___GENERIC1_CHECK */
+
+
+#if defined( IRIX___GENERIC2_CHECK )
+#define isless(x,y) \
+  ((sizeof(x)<=4 && sizeof(y)<=4) ? _islessf(x,y) \
+   : (sizeof(x)<=8 && sizeof(y)<=8) ? _isless(x,y) \
+   : _islessl(x,y))
+
+#endif  /* IRIX___GENERIC2_CHECK */
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 26f62aa2ee5..44c2a2c08f8 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -416,6 +416,7 @@ static void emit_output_reload_insns (struct insn_chain *, struct reload *,
 				      int);
 static void do_input_reload (struct insn_chain *, struct reload *, int);
 static void do_output_reload (struct insn_chain *, struct reload *, int);
+static bool inherit_piecemeal_p (int, int);
 static void emit_reload_insns (struct insn_chain *);
 static void delete_output_reload (rtx, int, int);
 static void delete_address_reloads (rtx, rtx);
@@ -6920,6 +6921,27 @@ do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
   emit_output_reload_insns (chain, rld + j, j);
 }
 
+/* Reload number R reloads from or to a group of hard registers starting at
+   register REGNO.  Return true if it can be treated for inheritance purposes
+   like a group of reloads, each one reloading a single hard register.
+   The caller has already checked that the spill register and REGNO use
+   the same number of registers to store the reload value.  */
+
+static bool
+inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
+{
+#ifdef CANNOT_CHANGE_MODE_CLASS
+  return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
+				     GET_MODE (rld[r].reg_rtx),
+				     reg_raw_mode[reload_spill_index[r]])
+	  && !REG_CANNOT_CHANGE_MODE_P (regno,
+					GET_MODE (rld[r].reg_rtx),
+					reg_raw_mode[regno]));
+#else
+  return true;
+#endif
+}
+
 /* Output insns to reload values in and out of the chosen reload regs.  */
 
 static void
@@ -7101,11 +7123,16 @@ emit_reload_insns (struct insn_chain *chain)
 		  int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
 			     : HARD_REGNO_NREGS (nregno,
 						 GET_MODE (rld[r].reg_rtx)));
+		  bool piecemeal;
 
 		  spill_reg_store[i] = new_spill_reg_store[i];
 		  spill_reg_stored_to[i] = out;
 		  reg_last_reload_reg[nregno] = rld[r].reg_rtx;
 
+		  piecemeal = (nregno < FIRST_PSEUDO_REGISTER
+			       && nr == nnr
+			       && inherit_piecemeal_p (r, nregno));
+
 		  /* If NREGNO is a hard register, it may occupy more than
 		     one register.  If it does, say what is in the
 		     rest of the registers assuming that both registers
@@ -7115,7 +7142,7 @@ emit_reload_insns (struct insn_chain *chain)
 		  if (nregno < FIRST_PSEUDO_REGISTER)
 		    for (k = 1; k < nnr; k++)
 		      reg_last_reload_reg[nregno + k]
-			= (nr == nnr
+			= (piecemeal
 			   ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
 			   : 0);
 
@@ -7124,7 +7151,7 @@ emit_reload_insns (struct insn_chain *chain)
 		    {
 		      CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
 		      reg_reloaded_contents[i + k]
-			= (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
+			= (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
 			   ? nregno
 			   : nregno + k);
 		      reg_reloaded_insn[i + k] = insn;
@@ -7149,6 +7176,7 @@ emit_reload_insns (struct insn_chain *chain)
 		  int nregno;
 		  int nnr;
 		  rtx in;
+		  bool piecemeal;
 
 		  if (GET_CODE (rld[r].in) == REG
 		      && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
@@ -7165,10 +7193,14 @@ emit_reload_insns (struct insn_chain *chain)
 
 		  reg_last_reload_reg[nregno] = rld[r].reg_rtx;
 
+		  piecemeal = (nregno < FIRST_PSEUDO_REGISTER
+			       && nr == nnr
+			       && inherit_piecemeal_p (r, nregno));
+
 		  if (nregno < FIRST_PSEUDO_REGISTER)
 		    for (k = 1; k < nnr; k++)
 		      reg_last_reload_reg[nregno + k]
-			= (nr == nnr
+			= (piecemeal
 			   ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
 			   : 0);
 
@@ -7184,7 +7216,7 @@ emit_reload_insns (struct insn_chain *chain)
 		    {
 		      CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
 		      reg_reloaded_contents[i + k]
-			= (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
+			= (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
 			   ? nregno
 			   : nregno + k);
 		      reg_reloaded_insn[i + k] = insn;
diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C b/gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C
index d4bdc212e18..4501a4ed173 100644
--- a/gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C
+++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrflags.C
@@ -1,4 +1,5 @@
 // { dg-do run  }
+// { dg-excess-errors "" { xfail mips*-*-linux* } }
 // Test rtti pointer flags
 // Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 // Contributed by Nathan Sidwell 15 Apr 2000 <nathan@nathan@codesourcery.com>
diff --git a/gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C b/gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C
index 2d2467548ea..39fb84af29a 100644
--- a/gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C
+++ b/gcc/testsuite/g++.old-deja/g++.eh/catchptr1.C
@@ -1,4 +1,4 @@
-// { dg-do run  }
+// { dg-do run { xfail mips*-*-linux* } }
 // Test pointer chain catching
 // Copyright (C) 2000, 2002 Free Software Foundation, Inc.
 // Contributed by Nathan Sidwell 9 Apr 2000 <nathan@nathan@codesourcery.com>
diff --git a/gcc/testsuite/gcc.c-torture/execute/loop-2f.x b/gcc/testsuite/gcc.c-torture/execute/loop-2f.x
new file mode 100644
index 00000000000..aa7645fad99
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/loop-2f.x
@@ -0,0 +1,2 @@
+set torture_execute_xfail "mips*-*-linux*"
+return 0
diff --git a/gcc/testsuite/gcc.c-torture/execute/loop-2g.x b/gcc/testsuite/gcc.c-torture/execute/loop-2g.x
new file mode 100644
index 00000000000..aa7645fad99
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/loop-2g.x
@@ -0,0 +1,2 @@
+set torture_execute_xfail "mips*-*-linux*"
+return 0
diff --git a/gcc/testsuite/gcc.dg/20030121-1.c b/gcc/testsuite/gcc.dg/20030121-1.c
index e69de29bb2d..212d875cbd2 100644
--- a/gcc/testsuite/gcc.dg/20030121-1.c
+++ b/gcc/testsuite/gcc.dg/20030121-1.c
@@ -0,0 +1,8 @@
+/* { dg-do compile { target powerpc*-*-darwin* } } */
+/* { dg-options "-O2 -force_cpusubtype_ALL -mpowerpc64" } */
+
+long long (*y)(int t);
+long long get_alias_set (int t)
+{
+  return y(t);
+}
diff --git a/gcc/testsuite/gcc.dg/20050629-1.c b/gcc/testsuite/gcc.dg/20050629-1.c
index 3aa78dbfdf5..490760ddf16 100644
--- a/gcc/testsuite/gcc.dg/20050629-1.c
+++ b/gcc/testsuite/gcc.dg/20050629-1.c
@@ -1,4 +1,4 @@
-/* { dg-options "-O2 -funswitch-loops" }
+/* { dg-options "-O2 -funswitch-loops" } */
 
 void f(int type){
     int tmp;
diff --git a/gcc/testsuite/gcc.dg/builtins-18.c b/gcc/testsuite/gcc.dg/builtins-18.c
index a47de8b609e..121e87b67a0 100644
--- a/gcc/testsuite/gcc.dg/builtins-18.c
+++ b/gcc/testsuite/gcc.dg/builtins-18.c
@@ -7,6 +7,7 @@
 
 /* { dg-do link } */
 /* { dg-options "-O2 -ffast-math" } */
+/* { dg-excess-errors "" { xfail mips*-*-linux-* } } */
 
 #include "builtins-config.h"
 
diff --git a/gcc/testsuite/gcc.dg/torture/mips-hilo-2.c b/gcc/testsuite/gcc.dg/torture/mips-hilo-2.c
new file mode 100644
index 00000000000..a8db6176682
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/torture/mips-hilo-2.c
@@ -0,0 +1,24 @@
+/* Due to a reload inheritance bug, the asm statement in f() would be passed
+   the low part of u.ll on little-endian 32-bit targets.  */
+/* { dg-do run { target mips*-*-* } } */
+
+unsigned int g;
+
+unsigned long long f (unsigned int x)
+{
+  union { unsigned long long ll; unsigned int parts[2]; } u;
+
+  u.ll = ((unsigned long long) x * x);
+  asm ("mflo\t%0" : "=r" (g) : "l" (u.parts[1]));
+  return u.ll;
+}
+
+int main ()
+{
+  union { unsigned long long ll; unsigned int parts[2]; } u;
+
+  u.ll = f (0x12345678);
+  if (g != u.parts[1])
+    abort ();
+  exit (0);
+}