diff options
| author | Uros Bizjak <ubizjak@gmail.com> | 2012-05-04 17:48:56 +0000 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2012-05-04 17:48:56 +0000 |
| commit | 5c6d51aa1db21dff0931cfd66e7fb296ef26c924 (patch) | |
| tree | 0d4c0bc9ae1ef5825e826e1237ffad2e76b563ed | |
| parent | c40b98e982bef40c73df9b342d5074bd4eb5c167 (diff) | |
Backport from mainline
2012-05-04 Uros Bizjak <ubizjak@gmail.com>
PR target/53228
* config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE.
(TARGET_CMOV): Rename from TARGET_CMOVE.
(TARGET_CMOVE): New define.
* config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV.
Do not set TARGET_CMOVE here.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/gcc-4_6-branch@187171 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 10 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 9 |
3 files changed, 21 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8b13279ea97..096aef8d575 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2012-05-04 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2012-05-04 Uros Bizjak <ubizjak@gmail.com> + + PR target/53228 + * config/i386/i386.h (X86_ARCH_CMOV): Rename from X86_ARCH_CMOVE. + (TARGET_CMOV): Rename from TARGET_CMOVE. + (TARGET_CMOVE): New define. + * config/i386/i386.c (ix86_option_override_internal): Use TARGET_CMOV. + Do not set TARGET_CMOVE here. + 2012-05-03 Michael Meissner <meissner@linux.vnet.ibm.com> Backport from the mainline diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index b8022a89424..8c27488ebf9 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -2095,7 +2095,7 @@ unsigned char ix86_arch_features[X86_ARCH_LAST]; /* Feature tests against the various architecture variations, used to create ix86_arch_features based on the processor mask. */ static unsigned int initial_ix86_arch_features[X86_ARCH_LAST] = { - /* X86_ARCH_CMOVE: Conditional move was added for pentiumpro. */ + /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */ ~(m_386 | m_486 | m_PENT | m_K6), /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */ @@ -3812,7 +3812,7 @@ ix86_option_override_internal (bool main_args_p) -mtune (rather than -march) points us to a processor that has them. However, the VIA C3 gives a SIGILL, so we only do that for i686 and higher processors. */ - if (TARGET_CMOVE + if (TARGET_CMOV && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))) x86_prefetch_sse = true; break; @@ -4182,12 +4182,6 @@ ix86_option_override_internal (bool main_args_p) target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS; } - /* For sane SSE instruction set generation we need fcomi instruction. - It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic - expands to a sequence that includes conditional move. */ - if (TARGET_SSE || TARGET_RDRND) - TARGET_CMOVE = 1; - /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */ { char *p; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index b342930f84a..281f9e12765 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -424,7 +424,7 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; /* Feature tests against the various architecture variations. */ enum ix86_arch_indices { - X86_ARCH_CMOVE, /* || TARGET_SSE */ + X86_ARCH_CMOV, X86_ARCH_CMPXCHG, X86_ARCH_CMPXCHG8B, X86_ARCH_XADD, @@ -435,12 +435,17 @@ enum ix86_arch_indices { extern unsigned char ix86_arch_features[X86_ARCH_LAST]; -#define TARGET_CMOVE ix86_arch_features[X86_ARCH_CMOVE] +#define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] +/* For sane SSE instruction set generation we need fcomi instruction. + It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic + expands to a sequence that includes conditional move. */ +#define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) + #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) extern int x86_prefetch_sse; |