diff options
| author | Michael Meissner <meissner@linux.vnet.ibm.com> | 2014-12-11 23:44:49 +0000 |
|---|---|---|
| committer | Michael Meissner <meissner@linux.vnet.ibm.com> | 2014-12-11 23:44:49 +0000 |
| commit | a92368752be5b142ba4a07dd0bcb8ad539767daa (patch) | |
| tree | 367667c19184e51cd481e26deac6cab9cecbd47f | |
| parent | 3c2c5072d550ec16fcc9e26f20a60915952016d1 (diff) | |
| parent | 22027ba0fa00ca5181cb44f08535d8d3de33dd0e (diff) | |
Merge up to ibm/gcc-4_9-branch, subversion id 218646
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/gcc-4_9-addr@218648 138bc75d-0d04-0410-961f-82ee72b054a4
154 files changed, 3730 insertions, 666 deletions
diff --git a/ChangeLog b/ChangeLog index 4a457e42f65..21a9792f1ea 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,10 @@ +2014-12-04 Tobias Burnus <burnus@net-b.de> + + * configure.ac: Permit also ISL 0.14 with CLooG. + * Makefile.def: Make more dependent on mpfr, mpc, isl, and cloog. + * Makefile.in: Regenerate. + * configure: Regenerate. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/Makefile.def b/Makefile.def index ec2b0f27810..cd99dd43af6 100644 --- a/Makefile.def +++ b/Makefile.def @@ -296,6 +296,10 @@ dependencies = { module=all-build-fixincludes; on=all-build-libiberty; }; // Host modules specific to gcc. dependencies = { module=configure-gcc; on=configure-intl; }; dependencies = { module=configure-gcc; on=all-gmp; }; +dependencies = { module=configure-gcc; on=all-mpfr; }; +dependencies = { module=configure-gcc; on=all-mpc; }; +dependencies = { module=configure-gcc; on=all-isl; }; +dependencies = { module=configure-gcc; on=all-cloog; }; dependencies = { module=configure-gcc; on=all-lto-plugin; }; dependencies = { module=configure-gcc; on=all-binutils; }; dependencies = { module=configure-gcc; on=all-gas; }; diff --git a/Makefile.in b/Makefile.in index bf06dce8a2e..6dd58025eb8 100644 --- a/Makefile.in +++ b/Makefile.in @@ -46988,6 +46988,38 @@ configure-stage3-gcc: maybe-all-stage3-gmp configure-stage4-gcc: maybe-all-stage4-gmp configure-stageprofile-gcc: maybe-all-stageprofile-gmp configure-stagefeedback-gcc: maybe-all-stagefeedback-gmp +configure-gcc: maybe-all-mpfr + +configure-stage1-gcc: maybe-all-stage1-mpfr +configure-stage2-gcc: maybe-all-stage2-mpfr +configure-stage3-gcc: maybe-all-stage3-mpfr +configure-stage4-gcc: maybe-all-stage4-mpfr +configure-stageprofile-gcc: maybe-all-stageprofile-mpfr +configure-stagefeedback-gcc: maybe-all-stagefeedback-mpfr +configure-gcc: maybe-all-mpc + +configure-stage1-gcc: maybe-all-stage1-mpc +configure-stage2-gcc: maybe-all-stage2-mpc +configure-stage3-gcc: maybe-all-stage3-mpc +configure-stage4-gcc: maybe-all-stage4-mpc +configure-stageprofile-gcc: maybe-all-stageprofile-mpc +configure-stagefeedback-gcc: maybe-all-stagefeedback-mpc +configure-gcc: maybe-all-isl + +configure-stage1-gcc: maybe-all-stage1-isl +configure-stage2-gcc: maybe-all-stage2-isl +configure-stage3-gcc: maybe-all-stage3-isl +configure-stage4-gcc: maybe-all-stage4-isl +configure-stageprofile-gcc: maybe-all-stageprofile-isl +configure-stagefeedback-gcc: maybe-all-stagefeedback-isl +configure-gcc: maybe-all-cloog + +configure-stage1-gcc: maybe-all-stage1-cloog +configure-stage2-gcc: maybe-all-stage2-cloog +configure-stage3-gcc: maybe-all-stage3-cloog +configure-stage4-gcc: maybe-all-stage4-cloog +configure-stageprofile-gcc: maybe-all-stageprofile-cloog +configure-stagefeedback-gcc: maybe-all-stagefeedback-cloog configure-gcc: maybe-all-lto-plugin configure-stage1-gcc: maybe-all-stage1-lto-plugin diff --git a/configure b/configure index d1c67e5e1cb..d769d93ccf9 100755 --- a/configure +++ b/configure @@ -6024,6 +6024,55 @@ $as_echo "$gcc_cv_isl" >&6; } fi + if test "${gcc_cv_isl}" = no ; then + + if test "${ENABLE_ISL_CHECK}" = yes ; then + _isl_saved_CFLAGS=$CFLAGS + _isl_saved_LDFLAGS=$LDFLAGS + _isl_saved_LIBS=$LIBS + + CFLAGS="${_isl_saved_CFLAGS} ${islinc} ${gmpinc}" + LDFLAGS="${_isl_saved_LDFLAGS} ${isllibs}" + LIBS="${_isl_saved_LIBS} -lisl" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking for version 0.14 of ISL" >&5 +$as_echo_n "checking for version 0.14 of ISL... " >&6; } + if test "$cross_compiling" = yes; then : + gcc_cv_isl=yes +else + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <isl/version.h> + #include <string.h> +int +main () +{ +if (strncmp (isl_version (), "isl-0.14", strlen ("isl-0.14")) != 0) + return 1; + + ; + return 0; +} +_ACEOF +if ac_fn_c_try_run "$LINENO"; then : + gcc_cv_isl=yes +else + gcc_cv_isl=no +fi +rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ + conftest.$ac_objext conftest.beam conftest.$ac_ext +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_isl" >&5 +$as_echo "$gcc_cv_isl" >&6; } + + CFLAGS=$_isl_saved_CFLAGS + LDFLAGS=$_isl_saved_LDFLAGS + LIBS=$_isl_saved_LIBS + fi + + + fi fi fi diff --git a/configure.ac b/configure.ac index 1bab68041d4..2aee14a6504 100644 --- a/configure.ac +++ b/configure.ac @@ -1658,6 +1658,9 @@ if test "x$with_isl" != "xno" && ISL_CHECK_VERSION(0,11) if test "${gcc_cv_isl}" = no ; then ISL_CHECK_VERSION(0,12) + if test "${gcc_cv_isl}" = no ; then + ISL_CHECK_VERSION(0,14) + fi fi fi dnl Only execute fail-action, if ISL has been requested. diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0253fc2237f..48bb653809e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,520 @@ +2014-12-11 Renlin Li <renlin.li@arm.com> + + Backport from mainline + 2014-12-11 Renlin Li <renlin.li@arm.com> + + * config/aarch64/aarch64.c (aarch64_parse_cpu): Don't define + selected_tune. + (aarch64_override_options): Use selected_cpu's tuning. + +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New + built-in definition. + (XVCVUXDDP_SCALE): Likewise. + (XVCVDPSXDS_SCALE): Likewise. + (XVCVDPUXDS_SCALE): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVCVSXDDP_SCALE, + VSX_BUILTIN_XVCVUXDDP_SCALE, VSX_BUILTIN_XVCVDPSXDS_SCALE, and + VSX_BUILTIN_XVCVDPUXDS_SCALE. + * config/rs6000/rs6000-protos.h (rs6000_scale_v2df): New + prototype. + * config/rs6000/rs6000.c (real.h): New include. + (rs6000_scale_v2df): New function. + * config/rs6000/vsx.md (UNSPEC_VSX_XVCVSXDDP): New unspec. + (UNSPEC_VSX_XVCVUXDDP): Likewise. + (UNSPEC_VSX_XVCVDPSXDS): Likewise. + (UNSPEC_VSX_XVCVDPUXDS): Likewise. + (vsx_xvcvsxddp_scale): New define_expand. + (vsx_xvcvsxddp): New define_insn. + (vsx_xvcvuxddp_scale): New define_expand. + (vsx_xvcvuxddp): New define_insn. + (vsx_xvcvdpsxds_scale): New define_expand. + (vsx_xvcvdpsxds): New define_insn. + (vsx_xvcvdpuxds_scale): New define_expand. + (vsx_xvcvdpuxds): New define_insn. + * doc/extend.texi (vec_ctf): Add new prototypes. + (vec_cts): Likewise. + (vec_ctu): Likewise. + (vec_splat): Likewise. + (vec_div): Likewise. + (vec_mul): Likewise. + + Backport from mainline + 2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.h (vec_xl): New #define. + (vec_xst): Likewise. + * config/rs6000/rs6000-builtin.def (XXSPLTD_V2DF): New built-in. + (XXSPLTD_V2DI): Likewise. + (DIV_V2DI): Likewise. + (UDIV_V2DI): Likewise. + (MUL_V2DI): Likewise. + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add + entries for VSX_BUILTIN_XVRDPI, VSX_BUILTIN_DIV_V2DI, + VSX_BUILTIN_UDIV_V2DI, VSX_BUILTIN_MUL_V2DI, + VSX_BUILTIN_XXSPLTD_V2DF, and VSX_BUILTIN_XXSPLTD_V2DI). + * config/rs6000/vsx.md (UNSPEC_VSX_XXSPLTD): New unspec. + (UNSPEC_VSX_DIVSD): Likewise. + (UNSPEC_VSX_DIVUD): Likewise. + (UNSPEC_VSX_MULSD): Likewise. + (vsx_mul_v2di): New insn-and-split. + (vsx_div_v2di): Likewise. + (vsx_udiv_v2di): Likewise. + (vsx_xxspltd_<mode>): New insn. + + Backport from mainline + 2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.h (vec_cpsgn): New #define. + (vec_mergee): Likewise. + (vec_mergeo): Likewise. + (vec_cntlz): Likewise. + * config/rs600/rs6000-c.c (altivec_overloaded_builtins): Add new + entries for VEC_AND, VEC_ANDC, VEC_MERGEH, VEC_MERGEL, VEC_NOR, + VEC_OR, VEC_PACKSU, VEC_XOR, VEC_PERM, VEC_SEL, VEC_VCMPGT_P, + VMRGEW, and VMRGOW. + * doc/extend.texi: Document various forms of vec_cpsgn, + vec_splats, vec_and, vec_andc, vec_mergeh, vec_mergel, vec_nor, + vec_or, vec_perm, vec_sel, vec_sub, vec_xor, vec_all_eq, + vec_all_ge, vec_all_gt, vec_all_le, vec_all_lt, vec_all_ne, + vec_any_eq, vec_any_ge, vec_any_gt, vec_any_le, vec_any_lt, + vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz. + + Backport from mainline + 2014-07-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * config/rs6000/altivec.md (unspec enum): Fix typo in UNSPEC_VSLDOI. + (altivec_vsldoi_<mode>): Likewise. + + +2014-12-10 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/62021 + * omp-low.c (simd_clone_adjust_return_type): Use + vector of pointer_sized_int_node types instead vector of pointer + types. + (simd_clone_adjust_argument_types): Likewise. + +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline: + 2014-12-09 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR middle-end/64225 + * tree-ssa-reassoc.c (acceptable_pow_call): Disable transformation + for BUILT_IN_POW when flag_errno_math is present. + +2014-12-10 Marek Polacek <polacek@redhat.com> + + Backport from mainline + 2014-12-10 Marek Polacek <polacek@redhat.com> + + PR tree-optimization/61686 + * tree-ssa-reassoc.c (range_entry_cmp): Use q->high instead of + p->high. + +2014-12-09 David Edelsohn <dje.gcc@gmail.com> + + Backport from mainline + 2014-12-05 David Edelsohn <dje.gcc@gmail.com> + + * config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_LOCAL): Append + alignment to section name. Increase default alignment to + word. + +2014-12-09 Uros Bizjak <ubizjak@gmail.com> + + PR bootstrap/64213 + Revert: + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-09 Richard Biener <rguenther@suse.de> + + PR tree-optimization/64191 + * tree-vect-stmts.c (vect_stmt_relevant_p): Clobbers are + not relevant (nor are their uses). + +2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/50751 + * config/sh/sh.md (extendqihi2): Allow only for TARGET_SH1. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-12-02 H.J. Lu <hongjiu.lu@intel.com> + + PR target/64108 + * config/i386/i386.c (decide_alg): Stop only if there aren't + any usable algorithms. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * combine.c (setup_incoming_promotions): Pass the argument + before any promotions happen to promote_function_mode. + +2014-12-04 Tobias Burnus <burnus@net-b.de> + + * configure.ac + (ac_has_isl_schedule_constraints_compute_schedule): + New check. + * graphite-clast-to-gimple.c: For ISL 0.14, include deprecate headers. + * graphite-interchange.c: Ditto. + * graphite-poly.c: Ditto. + * graphite-sese-to-poly.c: Ditto. + * graphite-optimize-isl.c (getScheduleForBandList): Ditto. + Conditionally use ISL 0.13+ functions. + * config.in: Regenerate. + * configure: Regenerate. + +2014-12-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/56493 + * convert.c (convert_to_real, convert_to_expr, convert_to_complex): + Handle COMPOUND_EXPR. + +2014-12-03 Jakub Jelinek <jakub@redhat.com> + + PR c/59708 + * expmed.c (expand_widening_mult): Return const0_rtx if + coeff is 0. + +2014-12-03 Martin Jambor <mjambor@suse.cz> + + PR ipa/64153 + * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Check + type sizes before view_converting. + +2014-12-03 Shanyao Chen <chenshanyao@huawei.com> + + Backport from mainline + 2014-11-20 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + PR target/59593 + * config/arm/arm.md (*movhi_insn): Use right formatting + for immediate. + + 2014-11-19 Felix Yang <felix.yang@huawei.com> + Shanyao Chen <chenshanyao@huawei.com> + + PR target/59593 + * config/arm/arm.md (define_attr "arch"): Add v6t2. + (define_attr "arch_enabled"): Add test for the above. + (*movhi_insn_arch4): Add new alternative. + +2014-12-03 Renlin Li <Renlin.Li@arm.com> + + Backported from mainline + 2014-12-03 Renlin Li <Renlin.Li@arm.com> + + PR middle-end/63762 + PR target/63661 + * ira.c (ira): Update preferred class. + +2014-12-02 Uros Bizjak <ubizjak@gmail.com> + + PR target/64113 + * config/alpha/alpha.md (call_value_osf_tlsgd): Do not split insn + using post-reload splitter. Use peephole2 pass instead. + (call_value_osf_tlsldm): Ditto. + (TLS_CALL): New int iterator. + (tls): New int attribute. + (call_value_osf_<tls>): Merge insn pattern from call_value_osf_tlsgd + and call_value_tlsldm using TLS_CALL int iterator. + +2014-12-02 Ulrich Weigand <Ulrich.Weigand@de.ibm.com> + + PR target/64115 + * config/rs6000/rs6000.c (rs6000_delegitimize_address): Remove + invalid UNSPEC_TOCREL sanity check under ENABLE_CHECKING. + +2014-12-01 Richard Biener <rguenther@suse.de> + + PR middle-end/64111 + * tree.c (int_cst_hash_hash): Use TYPE_UID instead of + htab_hash_pointer to not break PCH. + +2014-12-01 Martin Jambor <mjambor@suse.cz> + + PR ipa/63551 + * ipa-inline-analysis.c (evaluate_conditions_for_known_args): Convert + value of the argument to the type of the value in the condition. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-27 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/64067 + * expr.c (expand_expr_addr_expr_1) <case COMPOUND_LITERAL_EXPR>: + Handle it by returning address of COMPOUND_LITERAL_EXPR_DECL + not only if modifier is EXPAND_INITIALIZER, but whenever + COMPOUND_LITERAL_EXPR_DECL is non-NULL and TREE_STATIC. + + 2014-11-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63915 + * tree-vect-stmts.c (vectorizable_simd_clone_call): Pass + true instead of false as last argument to gsi_replace. + + PR sanitizer/63913 + * ubsan.c: Include tree-eh.h. + (instrument_bool_enum_load): Handle loads that can throw. + + 2014-10-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/63659 + * ree.c (update_reg_equal_equiv_notes): New function. + (combine_set_extension, transform_ifelse): Use it. + +2014-11-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + Backport from mainline. + 2014-11-28 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + * config/arm/t-aprofile (MULTILIB_MATCHES): New entry for + -march=armv8-a+crc. + +2014-11-26 Richard Biener <rguenther@suse.de> + + PR middle-end/63738 + * tree-data-ref.c (split_constant_offset_1): Do not follow + SSA edges for SSA names with SSA_NAME_OCCURS_IN_ABNORMAL_PHI. + +2014-11-26 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-11-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62238 + * tree-predcom.c (ref_at_iteration): Unshare the expression + before gimplifying it. + + 2014-11-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61927 + * tree-vect-loop.c (vect_analyze_loop_2): Revert ordering + of group and pattern analysis to the one in GCC 4.8. + + 2014-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63605 + * fold-const.c (fold_binary_loc): Properly use element_precision + for types that may not be scalar. + + 2014-10-28 Richard Biener <rguenther@suse.de> + + PR middle-end/63665 + * fold-const.c (fold_comparison): Properly guard simplifying + against INT_MAX/INT_MIN with !TYPE_OVERFLOW_WRAPS. + +2014-11-25 Rohit <rohitarulraj@freescale.com> + + PR bootstrap/63703 + * config/rs6000/darwin.h (REGISTER_NAMES): Update based on 32 newly + added GCC hard register numbers for SPE high registers. + +2014-11-23 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-23 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/53976 + * config/sh/sh_optimize_sett_clrt.cc + (sh_optimize_sett_clrt::find_last_ccreg_values): Return bool instead + of void. Abort at complex edges. + (sh_optimize_sett_clrt::execute): Do nothing if find_last_ccreg_values + returned false. + +2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/63783 + PR target/51244 + * config/sh/sh_treg_combine.cc (sh_treg_combine::make_not_reg_insn): + Do not emit bitwise not insn. Emit logical not insn sequence instead. + Adjust related comments throughout the file. + +2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-20 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/60111 + * config/sh/sh.c: Use signed char for signed field. + +2014-11-21 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + PR target/63673 + * config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Allow + the base pointer of vec_vsx_ld and vec_vsx_st to take a pointer to + double. + +2014-11-21 Richard Biener <rguenther@suse.de> + + PR tree-optimization/61750 + * tree-ssa-forwprop.c (simplify_vce): Verify type sizes + match for the resulting VIEW_CONVERT_EXPR. + +2014-11-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/63947 + * config/i386/i386.c (put_condition_code) <case LTU, case GEU>: + Output "b" and "nb" suffix for FP mode. + +2014-11-19 Tom de Vries <tom@codesourcery.com> + + Backport from mainline + PR tree-optimization/62167 + * tree-ssa-tail-merge.c (stmt_local_def): Handle statements with vuse + conservatively. + (gimple_equal_p): Don't use vn_valueize to compare for lhs equality of + assigns. + +2014-11-16 Eric Botcazou <ebotcazou@adacore.com> + + * doc/tm.texi.in (TARGET_FLAGS_REGNUM): Move around. + * doc/tm.texi: Regenerate. + +2014-11-14 Felix Yang <felix.yang@huawei.com> + + Backport from mainline + 2014-11-14 Felix Yang <felix.yang@huawei.com> + Jiji Jiang <jiangjiji@huawei.com> + + * config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): Use + VALL mode iterator instead of VALLDI. + +2014-11-13 Teresa Johnson <tejohnson@google.com> + + PR tree-optimization/63841 + * tree-ssa-strlen.c (strlen_optimize_stmt): Ignore clobbers. + +2014-11-13 Christophe Lyon <christophe.lyon@linaro.org> + + Backport from mainline + 2014-11-02 Michael Collison <michael.collison@linaro.org> + + * config/arm/arm.h (CLZ_DEFINED_VALUE_AT_ZERO) : Update + to support vector modes. + (CTZ_DEFINED_VALUE_AT_ZERO): Ditto. + +2014-11-13 Eric Botcazou <ebotcazou@adacore.com> + + * doc/tm.texi.in (SELECT_CC_MODE): Update example. + (REVERSIBLE_CC_MODE): Fix example. + (REVERSE_CONDITION): Fix typo. + * doc/tm.texi: Regenerate. + +2014-11-12 Jakub Jelinek <jakub@redhat.com> + + PR ipa/63838 + * ipa-pure-const.c (propagate_nothrow): Walk w->indirect_calls + chain instead of node->indirect_calls. + +2014-11-11 Eric Botcazou <ebotcazou@adacore.com> + + PR target/61535 + * config/sparc/sparc.c (function_arg_vector_value): Deal with vectors + smaller than 8 bytes. + (sparc_function_arg_1): Tweak. + (sparc_function_value_1): Tweak. + +2014-11-08 Eric Botcazou <ebotcazou@adacore.com> + + * config/arm/arm.c (arm_set_return_address): Mark the store as frame + related, if any. + (thumb_set_return_address): Likewise. + +2014-11-07 Daniel Hellstrom <daniel@gaisler.com> + + * config.gcc (sparc-*-rtems*): Clean away unused t-elf. + * config/sparc/t-rtems: Add leon3v7 and muser-mode multilibs. + +2014-11-07 Marek Polacek <polacek@redhat.com> + + Backported from mainline + 2014-10-23 Marek Polacek <polacek@redhat.com> + + * c-ubsan.c (ubsan_instrument_shift): Perform the MINUS_EXPR + in unsigned type. + +2014-11-06 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/pa.md (trap): New insn. Add "trap" to attribute type. + Don't allow trap insn in in_branch_delay, in_nullified_branch_delay + or in_call_delay. + +2014-11-06 Daniel Hellstrom <daniel@gaisler.com> + + * config.gcc (sparc*-*-*): Accept mcpu=leon3v7 processor. + * doc/invoke.texi (SPARC options): Add mcpu=leon3v7 comment. + * config/sparc/leon.md (leon3_load, leon_store, leon_fp_*): Handle + leon3v7 as leon3. + * config/sparc/sparc-opts.h (enum processor_type): Add LEON3V7. + * config/sparc/sparc.c (sparc_option_override): Add leon3v7 support. + * config/sparc/sparc.h (TARGET_CPU_leon3v7): New define. + * config/sparc/sparc.md (cpu): Add leon3v7. + * config/sparc/sparc.opt (enum processor_type): Add leon3v7. + +2014-11-05 Uros Bizjak <ubizjak@gmail.com> + + PR target/63538 + * config/i386/i386.c (in_large_data_p): Reject automatic variables. + (ix86_encode_section_info): Do not check for non-automatic varibles + when setting SYMBOL_FLAG_FAR_ADDR flag. + (x86_64_elf_select_section): Do not check ix86_cmodel here. + (x86_64_elf_unique_section): Ditto. + (x86_elf_aligned_common): Emit tab before .largecomm. + +2014-11-05 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline: + 2014-10-20 Uros Bizjak <ubizjak@gmail.com> + + * varasm.c (const_alias_set): Remove. + (init_varasm_once): Remove initialization of const_alias_set. + (build_constant_desc): Do not set alias set to const_alias_set. + + Backport from mainline: + 2014-10-14 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/63475 + * alias.c (true_dependence_1): Always use get_addr to extract + true address operands from x_addr and mem_addr. Use extracted + address operands to check for references with alignment ANDs. + Use extracted address operands with find_base_term and + base_alias_check. For noncanonicalized operands call canon_rtx with + extracted address operand. + (write_dependence_1): Ditto. + (may_alias_p): Ditto. Remove unused calls to canon_rtx. + + Backport from mainline: + 2014-10-10 Uros Bizjak <ubizjak@gmail.com> + + PR rtl-optimization/63483 + * alias.c (true_dependence_1): Do not exit early for MEM_READONLY_P + references when alignment ANDs are involved. + (write_dependence_p): Ditto. + (may_alias_p): Ditto. + 2014-10-31 DJ Delorie <dj@redhat.com> * expmed.c (strict_volatile_bitfield_p): Fix off-by-one error. @@ -192,8 +709,8 @@ Backport from mainline 2014-06-24 Max Ostapenko <m.ostapenko@partner.samsung.com> - * asan.c (instrument_strlen_call): Do not instrument first byte in strlen - if already instrumented. + * asan.c (instrument_strlen_call): Do not instrument first byte in + strlen if already instrumented. 2014-10-16 Yury Gribov <y.gribov@samsung.com> diff --git a/gcc/ChangeLog.ibm b/gcc/ChangeLog.ibm index ce883de7db3..6a599ac53c7 100644 --- a/gcc/ChangeLog.ibm +++ b/gcc/ChangeLog.ibm @@ -1,3 +1,8 @@ +2014-12-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + Merge up to 218639. + * REVISION: Update subversion id. + 2014-11-03 Peter Bergner <bergner@vnet.ibm.com> Merge up to 217046. diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 9aa02d64239..5cdf66d2a5f 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,8 @@ +2014-12-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + Merge up to ibm/gcc-4_9-branch, subversion id 218646. + * REVISION: Update subversion id. + 2014-12-09 Michael Meissner <meissner@linux.vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_secondary_reload): Clear entire diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index 8b4471af482..f40a662095f 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20141103 +20141211 diff --git a/gcc/REVISION b/gcc/REVISION index 161c73bf886..3042fe51c76 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -[ibm/gcc-4_9-addr merged from gcc-4_9-branch, revision 217046, merged from at8 branch 218285] +[ibm/gcc-4_9-addr merged from gcc-4_9-branch, revision 217046, merged from at8 branch 218646] diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index de30982006c..ea5a7bebf5a 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,27 @@ +2014-11-24 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/trans.c (push_range_check_info): Replace early test + with assertion. + (Raise_Error_to_gnu): Do not call push_range_check_info if the loop + stack is empty. + * gcc-interface/utils.c (convert_to_fat_pointer): Fix formatting. + * gcc-interface/utils2.c (gnat_invariant_expr): Deal with padded types + and revert latest change. + +2014-11-22 Eric Botcazou <ebotcazou@adacore.com> + + Backport from mainline + 2014-11-20 Vincent Celier <celier@adacore.com> + + PR ada/47500 + * back_end.adb (Scan_Back_End_Switches): Skip switch -G and + its argument. + +2014-11-11 Simon Wright <simon@pushface.org> + + PR ada/42978 + * mlib-utl.adb (ar): Output the options passed to ranlib. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/gcc/ada/back_end.adb b/gcc/ada/back_end.adb index bb442ad5e53..53146c891cc 100644 --- a/gcc/ada/back_end.adb +++ b/gcc/ada/back_end.adb @@ -210,9 +210,10 @@ package body Back_End is Last : constant Natural := Switch_Last (Switch_Chars); begin - -- Skip -o or internal GCC switches together with their argument + -- Skip -o, -G or internal GCC switches together with their argument. if Switch_Chars (First .. Last) = "o" + or else Switch_Chars (First .. Last) = "G" or else Is_Internal_GCC_Switch (Switch_Chars) then Next_Arg := Next_Arg + 1; diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 03bf098b0e3..30a166611e5 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -2424,9 +2424,6 @@ push_range_check_info (tree var) struct loop_info_d *iter = NULL; unsigned int i; - if (vec_safe_is_empty (gnu_loop_stack)) - return NULL; - var = remove_conversions (var, false); if (TREE_CODE (var) != VAR_DECL) @@ -2435,6 +2432,8 @@ push_range_check_info (tree var) if (decl_function_context (var) != current_function_decl) return NULL; + gcc_assert (vec_safe_length (gnu_loop_stack) > 0); + for (i = vec_safe_length (gnu_loop_stack) - 1; vec_safe_iterate (gnu_loop_stack, i, &iter); i--) @@ -5165,6 +5164,7 @@ Raise_Error_to_gnu (Node_Id gnat_node, tree *gnu_result_type_p) the original checks reinstated, and a run time selection. The former loop will be suitable for vectorization. */ if (flag_unswitch_loops + && !vec_safe_is_empty (gnu_loop_stack) && (!gnu_low_bound || (gnu_low_bound = gnat_invariant_expr (gnu_low_bound))) && (!gnu_high_bound diff --git a/gcc/ada/gcc-interface/utils.c b/gcc/ada/gcc-interface/utils.c index 15b72366bf5..820d2cec979 100644 --- a/gcc/ada/gcc-interface/utils.c +++ b/gcc/ada/gcc-interface/utils.c @@ -4371,8 +4371,7 @@ convert_to_fat_pointer (tree type, tree expr) { /* The template type can still be dummy at this point so we build an empty constructor. The middle-end will fill it in with zeros. */ - t = build_constructor (template_type, - NULL); + t = build_constructor (template_type, NULL); TREE_CONSTANT (t) = TREE_STATIC (t) = 1; null_bounds = build_unary_op (ADDR_EXPR, NULL_TREE, t); SET_TYPE_NULL_BOUNDS (ptr_template_type, null_bounds); diff --git a/gcc/ada/gcc-interface/utils2.c b/gcc/ada/gcc-interface/utils2.c index dd4151b5bc5..da52f418585 100644 --- a/gcc/ada/gcc-interface/utils2.c +++ b/gcc/ada/gcc-interface/utils2.c @@ -2784,7 +2784,13 @@ gnat_invariant_expr (tree expr) || (TREE_CODE (expr) == VAR_DECL && TREE_READONLY (expr))) && decl_function_context (expr) == current_function_decl && DECL_INITIAL (expr)) - expr = remove_conversions (DECL_INITIAL (expr), false); + { + expr = DECL_INITIAL (expr); + /* Look into CONSTRUCTORs built to initialize padded types. */ + if (TYPE_IS_PADDING_P (TREE_TYPE (expr))) + expr = convert (TREE_TYPE (TYPE_FIELDS (TREE_TYPE (expr))), expr); + expr = remove_conversions (expr, false); + } if (TREE_CONSTANT (expr)) return fold_convert (type, expr); @@ -2840,7 +2846,7 @@ object: if (!TREE_READONLY (t)) return NULL_TREE; - if (TREE_CODE (t) == CONSTRUCTOR || TREE_CODE (t) == PARM_DECL) + if (TREE_CODE (t) == PARM_DECL) return fold_convert (type, expr); if (TREE_CODE (t) == VAR_DECL diff --git a/gcc/ada/mlib-utl.adb b/gcc/ada/mlib-utl.adb index 756add1d4ac..7e2d56b75e2 100644 --- a/gcc/ada/mlib-utl.adb +++ b/gcc/ada/mlib-utl.adb @@ -282,6 +282,10 @@ package body MLib.Utl is if not Opt.Quiet_Output then Write_Str (Ranlib_Name.all); Write_Char (' '); + for J in Ranlib_Options'Range loop + Write_Str (Ranlib_Options (J).all); + Write_Char (' '); + end loop; Write_Line (Arguments (Ar_Options'Length + 1).all); end if; diff --git a/gcc/alias.c b/gcc/alias.c index 434ae7ad304..99add2627d0 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -2517,6 +2517,7 @@ static int true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, const_rtx x, rtx x_addr, bool mem_canonicalized) { + rtx true_mem_addr; rtx base; int ret; @@ -2536,17 +2537,9 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; - /* Read-only memory is by definition never modified, and therefore can't - conflict with anything. We don't expect to find read-only set on MEM, - but stupid user tricks can produce them, so don't die. */ - if (MEM_READONLY_P (x)) - return 0; - - /* If we have MEMs referring to different address spaces (which can - potentially overlap), we cannot easily tell from the addresses - whether the references overlap. */ - if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) - return 1; + if (! x_addr) + x_addr = XEXP (x, 0); + x_addr = get_addr (x_addr); if (! mem_addr) { @@ -2554,22 +2547,23 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, if (mem_mode == VOIDmode) mem_mode = GET_MODE (mem); } + true_mem_addr = get_addr (mem_addr); - if (! x_addr) - { - x_addr = XEXP (x, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - if (! mem_canonicalized) - mem_addr = get_addr (mem_addr); - } - } + /* Read-only memory is by definition never modified, and therefore can't + conflict with anything. However, don't assume anything when AND + addresses are involved and leave to the code below to determine + dependence. We don't expect to find read-only set on MEM, but + stupid user tricks can produce them, so don't die. */ + if (MEM_READONLY_P (x) + && GET_CODE (x_addr) != AND + && GET_CODE (true_mem_addr) != AND) + return 0; + + /* If we have MEMs referring to different address spaces (which can + potentially overlap), we cannot easily tell from the addresses + whether the references overlap. */ + if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) + return 1; base = find_base_term (x_addr); if (base && (GET_CODE (base) == LABEL_REF @@ -2577,14 +2571,14 @@ true_dependence_1 (const_rtx mem, enum machine_mode mem_mode, rtx mem_addr, && CONSTANT_POOL_ADDRESS_P (base)))) return 0; - rtx mem_base = find_base_term (mem_addr); - if (! base_alias_check (x_addr, base, mem_addr, mem_base, + rtx mem_base = find_base_term (true_mem_addr); + if (! base_alias_check (x_addr, base, true_mem_addr, mem_base, GET_MODE (x), mem_mode)) return 0; x_addr = canon_rtx (x_addr); if (!mem_canonicalized) - mem_addr = canon_rtx (mem_addr); + mem_addr = canon_rtx (true_mem_addr); if ((ret = memrefs_conflict_p (GET_MODE_SIZE (mem_mode), mem_addr, SIZE_FOR_MODE (x), x_addr, 0)) != -1) @@ -2637,6 +2631,7 @@ write_dependence_p (const_rtx mem, bool mem_canonicalized, bool x_canonicalized, bool writep) { rtx mem_addr; + rtx true_mem_addr, true_x_addr; rtx base; int ret; @@ -2657,8 +2652,20 @@ write_dependence_p (const_rtx mem, || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; - /* A read from read-only memory can't conflict with read-write memory. */ - if (!writep && MEM_READONLY_P (mem)) + if (!x_addr) + x_addr = XEXP (x, 0); + true_x_addr = get_addr (x_addr); + + mem_addr = XEXP (mem, 0); + true_mem_addr = get_addr (mem_addr); + + /* A read from read-only memory can't conflict with read-write memory. + Don't assume anything when AND addresses are involved and leave to + the code below to determine dependence. */ + if (!writep + && MEM_READONLY_P (mem) + && GET_CODE (true_x_addr) != AND + && GET_CODE (true_mem_addr) != AND) return 0; /* If we have MEMs referring to different address spaces (which can @@ -2667,24 +2674,7 @@ write_dependence_p (const_rtx mem, if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; - mem_addr = XEXP (mem, 0); - if (!x_addr) - { - x_addr = XEXP (x, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - if (!mem_canonicalized) - mem_addr = get_addr (mem_addr); - } - } - - base = find_base_term (mem_addr); + base = find_base_term (true_mem_addr); if (! writep && base && (GET_CODE (base) == LABEL_REF @@ -2692,18 +2682,18 @@ write_dependence_p (const_rtx mem, && CONSTANT_POOL_ADDRESS_P (base)))) return 0; - rtx x_base = find_base_term (x_addr); - if (! base_alias_check (x_addr, x_base, mem_addr, base, GET_MODE (x), - GET_MODE (mem))) + rtx x_base = find_base_term (true_x_addr); + if (! base_alias_check (true_x_addr, x_base, true_mem_addr, base, + GET_MODE (x), GET_MODE (mem))) return 0; if (!x_canonicalized) { - x_addr = canon_rtx (x_addr); + x_addr = canon_rtx (true_x_addr); x_mode = GET_MODE (x); } if (!mem_canonicalized) - mem_addr = canon_rtx (mem_addr); + mem_addr = canon_rtx (true_mem_addr); if ((ret = memrefs_conflict_p (SIZE_FOR_MODE (mem), mem_addr, GET_MODE_SIZE (x_mode), x_addr, 0)) != -1) @@ -2771,10 +2761,20 @@ may_alias_p (const_rtx mem, const_rtx x) || MEM_ALIAS_SET (mem) == ALIAS_SET_MEMORY_BARRIER) return 1; + x_addr = XEXP (x, 0); + x_addr = get_addr (x_addr); + + mem_addr = XEXP (mem, 0); + mem_addr = get_addr (mem_addr); + /* Read-only memory is by definition never modified, and therefore can't - conflict with anything. We don't expect to find read-only set on MEM, - but stupid user tricks can produce them, so don't die. */ - if (MEM_READONLY_P (x)) + conflict with anything. However, don't assume anything when AND + addresses are involved and leave to the code below to determine + dependence. We don't expect to find read-only set on MEM, but + stupid user tricks can produce them, so don't die. */ + if (MEM_READONLY_P (x) + && GET_CODE (x_addr) != AND + && GET_CODE (mem_addr) != AND) return 0; /* If we have MEMs referring to different address spaces (which can @@ -2783,28 +2783,12 @@ may_alias_p (const_rtx mem, const_rtx x) if (MEM_ADDR_SPACE (mem) != MEM_ADDR_SPACE (x)) return 1; - x_addr = XEXP (x, 0); - mem_addr = XEXP (mem, 0); - if (!((GET_CODE (x_addr) == VALUE - && GET_CODE (mem_addr) != VALUE - && reg_mentioned_p (x_addr, mem_addr)) - || (GET_CODE (x_addr) != VALUE - && GET_CODE (mem_addr) == VALUE - && reg_mentioned_p (mem_addr, x_addr)))) - { - x_addr = get_addr (x_addr); - mem_addr = get_addr (mem_addr); - } - rtx x_base = find_base_term (x_addr); rtx mem_base = find_base_term (mem_addr); if (! base_alias_check (x_addr, x_base, mem_addr, mem_base, GET_MODE (x), GET_MODE (mem_addr))) return 0; - x_addr = canon_rtx (x_addr); - mem_addr = canon_rtx (mem_addr); - if (nonoverlapping_memrefs_p (mem, x, true)) return 0; diff --git a/gcc/c-family/c-ubsan.c b/gcc/c-family/c-ubsan.c index e89ebc1873b..2c0d009a2a8 100644 --- a/gcc/c-family/c-ubsan.c +++ b/gcc/c-family/c-ubsan.c @@ -98,19 +98,19 @@ ubsan_instrument_shift (location_t loc, enum tree_code code, tree op1_utype = unsigned_type_for (type1); HOST_WIDE_INT op0_prec = TYPE_PRECISION (type0); tree uprecm1 = build_int_cst (op1_utype, op0_prec - 1); - tree precm1 = build_int_cst (type1, op0_prec - 1); t = fold_convert_loc (loc, op1_utype, op1); t = fold_build2 (GT_EXPR, boolean_type_node, t, uprecm1); /* For signed x << y, in C99/C11, the following: - (unsigned) x >> (precm1 - y) + (unsigned) x >> (uprecm1 - y) if non-zero, is undefined. */ if (code == LSHIFT_EXPR && !TYPE_UNSIGNED (type0) && flag_isoc99) { - tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1); + tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1, + fold_convert (op1_utype, op1)); tt = fold_convert_loc (loc, unsigned_type_for (type0), op0); tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x); tt = fold_build2 (NE_EXPR, boolean_type_node, tt, @@ -118,13 +118,14 @@ ubsan_instrument_shift (location_t loc, enum tree_code code, } /* For signed x << y, in C++11/C++14, the following: - x < 0 || ((unsigned) x >> (precm1 - y)) + x < 0 || ((unsigned) x >> (uprecm1 - y)) if > 1, is undefined. */ if (code == LSHIFT_EXPR && !TYPE_UNSIGNED (TREE_TYPE (op0)) && (cxx_dialect == cxx11 || cxx_dialect == cxx1y)) { - tree x = fold_build2 (MINUS_EXPR, integer_type_node, precm1, op1); + tree x = fold_build2 (MINUS_EXPR, unsigned_type_node, uprecm1, + fold_convert (op1_utype, op1)); tt = fold_convert_loc (loc, unsigned_type_for (type0), op0); tt = fold_build2 (RSHIFT_EXPR, TREE_TYPE (tt), tt, x); tt = fold_build2 (GT_EXPR, boolean_type_node, tt, diff --git a/gcc/config.gcc b/gcc/config.gcc index 9d3fa57699c..90d4f71ed76 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2662,7 +2662,7 @@ sparc-*-elf*) ;; sparc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h" - tmake_file="${tmake_file} sparc/t-sparc sparc/t-elf sparc/t-rtems" + tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems" ;; sparc-*-linux*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h" @@ -3205,6 +3205,9 @@ if test x$with_cpu = x ; then *-leon[3-9]*) with_cpu=leon3 ;; + *-leon[3-9]v7*) + with_cpu=leon3v7 + ;; *) with_cpu="`echo ${target} | sed 's/-.*$//'`" ;; @@ -3993,7 +3996,7 @@ case "${target}" in case ${val} in "" | sparc | sparcv9 | sparc64 \ | v7 | cypress \ - | v8 | supersparc | hypersparc | leon | leon3 \ + | v8 | supersparc | hypersparc | leon | leon3 | leon3v7 \ | sparclite | f930 | f934 | sparclite86x \ | sparclet | tsc701 \ | v9 | ultrasparc | ultrasparc3 | niagara | niagara2 \ diff --git a/gcc/config.in b/gcc/config.in index 1e8532567c7..71cf0c93b91 100644 --- a/gcc/config.in +++ b/gcc/config.in @@ -1211,6 +1211,12 @@ #endif +/* Define if isl_schedule_constraints_compute_schedule exists. */ +#ifndef USED_FOR_TARGET +#undef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#endif + + /* Define to 1 if you have the `kill' function. */ #ifndef USED_FOR_TARGET #undef HAVE_KILL diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 851e77a0205..30e9f60e92f 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4565,8 +4565,8 @@ }) (define_insn "*aarch64_simd_ld1r<mode>" - [(set (match_operand:VALLDI 0 "register_operand" "=w") - (vec_duplicate:VALLDI + [(set (match_operand:VALL 0 "register_operand" "=w") + (vec_duplicate:VALL (match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))] "TARGET_SIMD" "ld1r\\t{%0.<Vtype>}, %1" diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 52c04717e8e..3adf54e5b8a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5152,7 +5152,6 @@ aarch64_parse_cpu (void) if (strlen (cpu->name) == len && strncmp (cpu->name, str, len) == 0) { selected_cpu = cpu; - selected_tune = cpu; aarch64_isa_flags = selected_cpu->flags; if (ext != NULL) @@ -5248,9 +5247,8 @@ aarch64_override_options (void) gcc_assert (selected_cpu); - /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!selected_tune) - selected_tune = &all_cores[selected_cpu->core]; + selected_tune = selected_cpu; aarch64_tune_flags = selected_tune->flags; aarch64_tune = selected_tune->core; diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 795b4df3fbf..1179d572da6 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -5984,16 +5984,38 @@ [(set_attr "type" "jsr") (set_attr "length" "*,*,8")]) -(define_insn_and_split "call_value_osf_tlsgd" +(define_int_iterator TLS_CALL + [UNSPEC_TLSGD_CALL + UNSPEC_TLSLDM_CALL]) + +(define_int_attr tls + [(UNSPEC_TLSGD_CALL "tlsgd") + (UNSPEC_TLSLDM_CALL "tlsldm")]) + +(define_insn "call_value_osf_<tls>" [(set (match_operand 0) (call (mem:DI (match_operand:DI 1 "symbolic_operand")) (const_int 0))) - (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSGD_CALL) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) (use (reg:DI 29)) (clobber (reg:DI 26))] "HAVE_AS_TLS" - "#" - "&& reload_completed" + "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" + [(set_attr "type" "jsr") + (set_attr "length" "16")]) + +;; We must use peep2 instead of a split because we need accurate life +;; information for $gp. +(define_peephole2 + [(parallel + [(set (match_operand 0) + (call (mem:DI (match_operand:DI 1 "symbolic_operand")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))])] + "HAVE_AS_TLS && reload_completed + && peep2_regno_dead_p (1, 29)" [(set (match_dup 3) (unspec:DI [(match_dup 5) (match_dup 1) @@ -6001,10 +6023,9 @@ (parallel [(set (match_dup 0) (call (mem:DI (match_dup 3)) (const_int 0))) - (set (match_dup 5) - (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) + (use (match_dup 5)) (use (match_dup 1)) - (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL)) + (use (unspec [(match_dup 2)] TLS_CALL)) (clobber (reg:DI 26))]) (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] @@ -6012,19 +6033,18 @@ operands[3] = gen_rtx_REG (Pmode, 27); operands[4] = GEN_INT (alpha_next_sequence_number++); operands[5] = pic_offset_table_rtx; -} - [(set_attr "type" "multi")]) +}) -(define_insn_and_split "call_value_osf_tlsldm" - [(set (match_operand 0) - (call (mem:DI (match_operand:DI 1 "symbolic_operand")) - (const_int 0))) - (unspec [(match_operand:DI 2 "const_int_operand")] UNSPEC_TLSLDM_CALL) - (use (reg:DI 29)) - (clobber (reg:DI 26))] - "HAVE_AS_TLS" - "#" - "&& reload_completed" +(define_peephole2 + [(parallel + [(set (match_operand 0) + (call (mem:DI (match_operand:DI 1 "symbolic_operand")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))])] + "HAVE_AS_TLS && reload_completed + && !peep2_regno_dead_p (1, 29)" [(set (match_dup 3) (unspec:DI [(match_dup 5) (match_dup 1) @@ -6035,7 +6055,7 @@ (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) (use (match_dup 1)) - (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL)) + (use (unspec [(match_dup 2)] TLS_CALL)) (clobber (reg:DI 26))]) (set (match_dup 5) (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] @@ -6043,8 +6063,7 @@ operands[3] = gen_rtx_REG (Pmode, 27); operands[4] = GEN_INT (alpha_next_sequence_number++); operands[5] = pic_offset_table_rtx; -} - [(set_attr "type" "multi")]) +}) (define_insn "*call_value_osf_1" [(set (match_operand 0) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 439a4dea505..5e2571c5ed4 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28492,7 +28492,11 @@ arm_set_return_address (rtx source, rtx scratch) addr = plus_constant (Pmode, addr, delta); } - emit_move_insn (gen_frame_mem (Pmode, addr), source); + /* The store needs to be marked as frame related in order to prevent + DSE from deleting it as dead if it is based on fp. */ + rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source); + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM)); } } @@ -28544,7 +28548,11 @@ thumb_set_return_address (rtx source, rtx scratch) else addr = plus_constant (Pmode, addr, delta); - emit_move_insn (gen_frame_mem (Pmode, addr), source); + /* The store needs to be marked as frame related in order to prevent + DSE from deleting it as dead if it is based on fp. */ + rtx insn = emit_move_insn (gen_frame_mem (Pmode, addr), source); + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNUM)); } else emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index c60d9a44f86..c0f218470c3 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2138,9 +2138,10 @@ extern int making_const_table; ? reverse_condition_maybe_unordered (code) \ : reverse_condition (code)) -/* The arm5 clz instruction returns 32. */ -#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) -#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ + ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) #define CC_STATUS_INIT \ do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 2a57d6eb04e..81193874396 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -125,9 +125,10 @@ ; This can be "a" for ARM, "t" for either of the Thumbs, "32" for ; TARGET_32BIT, "t1" or "t2" to specify a specific Thumb mode. "v6" ; for ARM or Thumb-2 with arm_arch6, and nov6 for ARM without -; arm_arch6. This attribute is used to compute attribute "enabled", -; use type "any" to enable an alternative in all cases. -(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" +; arm_arch6. "v6t2" for Thumb-2 with arm_arch6. This attribute is +; used to compute attribute "enabled", use type "any" to enable an +; alternative in all cases. +(define_attr "arch" "any,a,t,32,t1,t2,v6,nov6,v6t2,neon_for_64bits,avoid_neon_for_64bits,iwmmxt,iwmmxt2" (const_string "any")) (define_attr "arch_enabled" "no,yes" @@ -162,6 +163,10 @@ (match_test "TARGET_32BIT && !arm_arch6")) (const_string "yes") + (and (eq_attr "arch" "v6t2") + (match_test "TARGET_32BIT && arm_arch6 && arm_arch_thumb2")) + (const_string "yes") + (and (eq_attr "arch" "avoid_neon_for_64bits") (match_test "TARGET_NEON") (not (match_test "TARGET_PREFER_NEON_64BITS"))) @@ -6961,8 +6966,8 @@ ;; Pattern to recognize insn generated default case above (define_insn "*movhi_insn_arch4" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") - (match_operand:HI 1 "general_operand" "rI,K,r,mi"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m,r") + (match_operand:HI 1 "general_operand" "rI,K,n,r,mi"))] "TARGET_ARM && arm_arch4 && (register_operand (operands[0], HImode) @@ -6970,16 +6975,19 @@ "@ mov%?\\t%0, %1\\t%@ movhi mvn%?\\t%0, #%B1\\t%@ movhi + movw%?\\t%0, %L1\\t%@ movhi str%(h%)\\t%1, %0\\t%@ movhi ldr%(h%)\\t%0, %1\\t%@ movhi" [(set_attr "predicable" "yes") - (set_attr "pool_range" "*,*,*,256") - (set_attr "neg_pool_range" "*,*,*,244") + (set_attr "pool_range" "*,*,*,*,256") + (set_attr "neg_pool_range" "*,*,*,*,244") + (set_attr "arch" "*,*,v6t2,*,*") (set_attr_alternative "type" [(if_then_else (match_operand 1 "const_int_operand" "") (const_string "mov_imm" ) (const_string "mov_reg")) (const_string "mvn_imm") + (const_string "mov_imm") (const_string "store1") (const_string "load1")])] ) diff --git a/gcc/config/arm/t-aprofile b/gcc/config/arm/t-aprofile index ff9e2e1b3be..86741e6b0ca 100644 --- a/gcc/config/arm/t-aprofile +++ b/gcc/config/arm/t-aprofile @@ -88,6 +88,9 @@ MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a53 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57 MULTILIB_MATCHES += march?armv8-a=mcpu?cortex-a57.cortex-a53 +# Arch Matches +MULTILIB_MATCHES += march?armv8-a=march?armv8-a+crc + # FPU matches MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3 MULTILIB_MATCHES += mfpu?vfpv3-d16=mfpu?vfpv3-fp16 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 668c1d10892..81ee71b9f26 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -5006,6 +5006,10 @@ ix86_in_large_data_p (tree exp) if (TREE_CODE (exp) == FUNCTION_DECL) return false; + /* Automatic variables are never large data. */ + if (TREE_CODE (exp) == VAR_DECL && !is_global_var (exp)) + return false; + if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) { const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); @@ -5036,8 +5040,7 @@ ATTRIBUTE_UNUSED static section * x86_64_elf_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align) { - if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) - && ix86_in_large_data_p (decl)) + if (ix86_in_large_data_p (decl)) { const char *sname = NULL; unsigned int flags = SECTION_WRITE; @@ -5123,8 +5126,7 @@ x86_64_elf_section_type_flags (tree decl, const char *name, int reloc) static void ATTRIBUTE_UNUSED x86_64_elf_unique_section (tree decl, int reloc) { - if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) - && ix86_in_large_data_p (decl)) + if (ix86_in_large_data_p (decl)) { const char *prefix = NULL; /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */ @@ -5193,7 +5195,7 @@ x86_elf_aligned_common (FILE *file, { if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) && size > (unsigned int)ix86_section_threshold) - fputs (".largecomm\t", file); + fputs ("\t.largecomm\t", file); else fputs (COMMON_ASM_OP, file); assemble_name (file, name); @@ -14503,7 +14505,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, if (mode == CCmode) suffix = "b"; else if (mode == CCCmode) - suffix = "c"; + suffix = fp ? "b" : "c"; else gcc_unreachable (); break; @@ -14526,9 +14528,9 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, bool reverse, break; case GEU: if (mode == CCmode) - suffix = fp ? "nb" : "ae"; + suffix = "nb"; else if (mode == CCCmode) - suffix = "nc"; + suffix = fp ? "nb" : "nc"; else gcc_unreachable (); break; @@ -23890,7 +23892,8 @@ decide_alg (HOST_WIDE_INT count, HOST_WIDE_INT expected_size, *noalign = alg_noalign; return alg; } - break; + else if (!any_alg_usable_p) + break; } else if (alg_usable_p (candidate, memset)) { @@ -41076,9 +41079,7 @@ ix86_encode_section_info (tree decl, rtx rtl, int first) { default_encode_section_info (decl, rtl, first); - if (TREE_CODE (decl) == VAR_DECL - && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) - && ix86_in_large_data_p (decl)) + if (ix86_in_large_data_p (decl)) SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR; } diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index a9421ac2e61..f4f966a6c3e 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -123,7 +123,7 @@ ;; type "binary" insns have two input operands (1,2) and one output (0) (define_attr "type" - "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload" + "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,sh_func_adrs,parallel_branch,fpstore_load,store_fpload,trap" (const_string "binary")) (define_attr "pa_combine_type" @@ -166,7 +166,7 @@ ;; For conditional branches. Frame related instructions are not allowed ;; because they confuse the unwind support. (define_attr "in_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch") + (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -175,7 +175,7 @@ ;; Disallow instructions which use the FPU since they will tie up the FPU ;; even if the instruction is nullified. (define_attr "in_nullified_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch") + (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -184,7 +184,7 @@ ;; For calls and millicode calls. Allow unconditional branches in the ;; delay slot. (define_attr "in_call_delay" "false,true" - (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch") + (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,sibcall,dyncall,multi,milli,sh_func_adrs,parallel_branch,trap") (eq_attr "length" "4") (not (match_test "RTX_FRAME_RELATED_P (insn)"))) (const_string "true") @@ -5331,6 +5331,15 @@ [(set_attr "type" "binary,binary") (set_attr "length" "4,4")]) +;; Trap instructions. + +(define_insn "trap" + [(trap_if (const_int 1) (const_int 0))] + "" + "{addit|addi,tc},<> 1,%%r0,%%r0" + [(set_attr "type" "trap") + (set_attr "length" "4")]) + ;; Clobbering a "register_operand" instead of a match_scratch ;; in operand3 of millicode calls avoids spilling %r1 and ;; produces better code. diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h index 129cf6fa162..9ee0ae5eccf 100644 --- a/gcc/config/rs6000/altivec.h +++ b/gcc/config/rs6000/altivec.h @@ -124,6 +124,7 @@ #define vec_vcfux __builtin_vec_vcfux #define vec_cts __builtin_vec_cts #define vec_ctu __builtin_vec_ctu +#define vec_cpsgn __builtin_vec_copysign #define vec_expte __builtin_vec_expte #define vec_floor __builtin_vec_floor #define vec_loge __builtin_vec_loge @@ -214,8 +215,10 @@ #define vec_lvsl __builtin_vec_lvsl #define vec_lvsr __builtin_vec_lvsr #define vec_max __builtin_vec_max +#define vec_mergee __builtin_vec_vmrgew #define vec_mergeh __builtin_vec_mergeh #define vec_mergel __builtin_vec_mergel +#define vec_mergeo __builtin_vec_vmrgow #define vec_min __builtin_vec_min #define vec_mladd __builtin_vec_mladd #define vec_msum __builtin_vec_msum @@ -319,6 +322,8 @@ #define vec_sqrt __builtin_vec_sqrt #define vec_vsx_ld __builtin_vec_vsx_ld #define vec_vsx_st __builtin_vec_vsx_st +#define vec_xl __builtin_vec_vsx_ld +#define vec_xst __builtin_vec_vsx_st /* Note, xxsldi and xxpermdi were added as __builtin_vsx_<xxx> functions instead of __builtin_vec_<xxx> */ @@ -336,6 +341,7 @@ #define vec_vadduqm __builtin_vec_vadduqm #define vec_vbpermq __builtin_vec_vbpermq #define vec_vclz __builtin_vec_vclz +#define vec_cntlz __builtin_vec_vclz #define vec_vclzb __builtin_vec_vclzb #define vec_vclzd __builtin_vec_vclzd #define vec_vclzh __builtin_vec_vclzh diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 97b32cdca3c..9a2f5d764f4 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -67,7 +67,7 @@ UNSPEC_VCTSXS UNSPEC_VLOGEFP UNSPEC_VEXPTEFP - UNSPEC_VLSDOI + UNSPEC_VSLDOI UNSPEC_VUNPACK_HI_SIGN UNSPEC_VUNPACK_LO_SIGN UNSPEC_VUNPACK_HI_SIGN_DIRECT @@ -2079,7 +2079,7 @@ (unspec:VM [(match_operand:VM 1 "register_operand" "v") (match_operand:VM 2 "register_operand" "v") (match_operand:QI 3 "immediate_operand" "i")] - UNSPEC_VLSDOI))] + UNSPEC_VSLDOI))] "TARGET_ALTIVEC" "vsldoi %0,%1,%2,%3" [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/darwin.h b/gcc/config/rs6000/darwin.h index 0329f3f621b..dfd181e43cb 100644 --- a/gcc/config/rs6000/darwin.h +++ b/gcc/config/rs6000/darwin.h @@ -206,7 +206,11 @@ extern int darwin_emit_branch_islands; "vrsave", "vscr", \ "spe_acc", "spefscr", \ "sfp", \ - "tfhar", "tfiar", "texasr" \ + "tfhar", "tfiar", "texasr", \ + "rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7", \ + "rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15", \ + "rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23", \ + "rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31" \ } /* This outputs NAME to FILE. */ diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 220d1e97065..9bb8703949c 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -1258,6 +1258,16 @@ BU_VSX_2 (VEC_MERGEL_V2DF, "mergel_2df", CONST, vsx_mergel_v2df) BU_VSX_2 (VEC_MERGEL_V2DI, "mergel_2di", CONST, vsx_mergel_v2di) BU_VSX_2 (VEC_MERGEH_V2DF, "mergeh_2df", CONST, vsx_mergeh_v2df) BU_VSX_2 (VEC_MERGEH_V2DI, "mergeh_2di", CONST, vsx_mergeh_v2di) +BU_VSX_2 (XXSPLTD_V2DF, "xxspltd_2df", CONST, vsx_xxspltd_v2df) +BU_VSX_2 (XXSPLTD_V2DI, "xxspltd_2di", CONST, vsx_xxspltd_v2di) +BU_VSX_2 (DIV_V2DI, "div_2di", CONST, vsx_div_v2di) +BU_VSX_2 (UDIV_V2DI, "udiv_2di", CONST, vsx_udiv_v2di) +BU_VSX_2 (MUL_V2DI, "mul_2di", CONST, vsx_mul_v2di) + +BU_VSX_2 (XVCVSXDDP_SCALE, "xvcvsxddp_scale", CONST, vsx_xvcvsxddp_scale) +BU_VSX_2 (XVCVUXDDP_SCALE, "xvcvuxddp_scale", CONST, vsx_xvcvuxddp_scale) +BU_VSX_2 (XVCVDPSXDS_SCALE, "xvcvdpsxds_scale", CONST, vsx_xvcvdpsxds_scale) +BU_VSX_2 (XVCVDPUXDS_SCALE, "xvcvdpuxds_scale", CONST, vsx_xvcvdpuxds_scale) /* VSX abs builtin functions. */ BU_VSX_A (XVABSDP, "xvabsdp", CONST, absv2df2) diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c index 5a9da5f042b..3c6e45afb08 100644 --- a/gcc/config/rs6000/rs6000-c.c +++ b/gcc/config/rs6000/rs6000-c.c @@ -601,6 +601,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, + { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, @@ -881,6 +883,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -935,6 +949,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -1122,18 +1148,30 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, + { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, + RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, @@ -1599,6 +1637,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, @@ -1647,6 +1695,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, @@ -1775,6 +1833,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_XVMULDP, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { VSX_BUILTIN_VEC_MUL, VSX_BUILTIN_MUL_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, @@ -1816,6 +1878,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, @@ -1846,6 +1920,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -1949,6 +2035,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, + RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, @@ -2131,6 +2219,14 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, + { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, + RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, @@ -2523,6 +2619,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, + { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, @@ -2782,6 +2890,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, + { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, @@ -2822,6 +2932,12 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, + RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, @@ -3271,6 +3387,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, + { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, + RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, @@ -3325,6 +3443,8 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, + { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, + RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, @@ -3435,6 +3555,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, + { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, + RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, @@ -3893,12 +4025,16 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = { { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, + { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW, + RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index e1355b3a615..aa8e762491c 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -65,6 +65,7 @@ extern void altivec_expand_stvx_be (rtx, rtx, enum machine_mode, unsigned); extern void altivec_expand_stvex_be (rtx, rtx, enum machine_mode, unsigned); extern void rs6000_expand_extract_even (rtx, rtx, rtx); extern void rs6000_expand_interleave (rtx, rtx, rtx, bool); +extern void rs6000_scale_v2df (rtx, rtx, int); extern void build_mask64_2_operands (rtx, rtx *); extern int expand_block_clear (rtx[]); extern int expand_block_move (rtx[]); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4532f6e88b6..15ed0b921f1 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6995,24 +6995,6 @@ rs6000_delegitimize_address (rtx orig_x) if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_TOCREL) { -#ifdef ENABLE_CHECKING - if (REG_P (XVECEXP (y, 0, 1)) - && REGNO (XVECEXP (y, 0, 1)) == TOC_REGISTER) - { - /* All good. */ - } - else if (GET_CODE (XVECEXP (y, 0, 1)) == DEBUG_EXPR) - { - /* Weirdness alert. df_note_compute can replace r2 with a - debug_expr when this unspec is in a debug_insn. - Seen in gcc.dg/pr51957-1.c */ - } - else - { - debug_rtx (orig_x); - abort (); - } -#endif y = XVECEXP (y, 0, 0); #ifdef HAVE_AS_TLS @@ -31276,6 +31258,23 @@ rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp) rs6000_do_expand_vec_perm (target, op0, op1, vmode, nelt, perm); } +/* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */ +void +rs6000_scale_v2df (rtx tgt, rtx src, int scale) +{ + HOST_WIDE_INT hwi_scale (scale); + REAL_VALUE_TYPE r_pow; + rtvec v = rtvec_alloc (2); + rtx elt; + rtx scale_vec = gen_reg_rtx (V2DFmode); + (void)real_powi (&r_pow, DFmode, &dconst2, hwi_scale); + elt = CONST_DOUBLE_FROM_REAL_VALUE (r_pow, DFmode); + RTVEC_ELT (v, 0) = elt; + RTVEC_ELT (v, 1) = elt; + rs6000_expand_vector_init (scale_vec, gen_rtx_PARALLEL (V2DFmode, v)); + emit_insn (gen_mulv2df3 (tgt, src, scale_vec)); +} + /* Return an RTX representing where to find the function value of a function returning MODE. */ static rtx diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a94ec9a7ade..ae7db4012b4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -260,6 +260,14 @@ UNSPEC_VSX_ROUND_IC UNSPEC_VSX_SLDWI UNSPEC_VSX_XXSPLTW + UNSPEC_VSX_XXSPLTD + UNSPEC_VSX_DIVSD + UNSPEC_VSX_DIVUD + UNSPEC_VSX_MULSD + UNSPEC_VSX_XVCVSXDDP + UNSPEC_VSX_XVCVUXDDP + UNSPEC_VSX_XVCVDPSXDS + UNSPEC_VSX_XVCVDPUXDS ]) ;; VSX moves @@ -746,6 +754,34 @@ [(set_attr "type" "<VStype_simple>") (set_attr "fp_type" "<VSfptype_mul>")]) +; Emulate vector with scalar for vec_mul in V2DImode +(define_insn_and_split "vsx_mul_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_MULSD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_muldi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_muldi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdouble")]) + (define_insn "*vsx_div<mode>3" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=<VSr>,?<VSa>") (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" "<VSr>,<VSa>") @@ -755,6 +791,61 @@ [(set_attr "type" "<VStype_div>") (set_attr "fp_type" "<VSfptype_div>")]) +; Emulate vector with scalar for vec_div in V2DImode +(define_insn_and_split "vsx_div_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_DIVSD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_divdi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_divdi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdiv")]) + +(define_insn_and_split "vsx_udiv_v2di" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DI 1 "vsx_register_operand" "wa") + (match_operand:V2DI 2 "vsx_register_operand" "wa")] + UNSPEC_VSX_DIVUD))] + "VECTOR_MEM_VSX_P (V2DImode)" + "#" + "VECTOR_MEM_VSX_P (V2DImode) && !reload_completed && !reload_in_progress" + [(const_int 0)] + " +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op3 = gen_reg_rtx (DImode); + rtx op4 = gen_reg_rtx (DImode); + rtx op5 = gen_reg_rtx (DImode); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (0))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (0))); + emit_insn (gen_udivdi3 (op5, op3, op4)); + emit_insn (gen_vsx_extract_v2di (op3, op1, GEN_INT (1))); + emit_insn (gen_vsx_extract_v2di (op4, op2, GEN_INT (1))); + emit_insn (gen_udivdi3 (op3, op3, op4)); + emit_insn (gen_vsx_concat_v2di (op0, op5, op3)); +}" + [(set_attr "type" "vecdiv")]) + ;; *tdiv* instruction returning the FG flag (define_expand "vsx_tdiv<mode>3_fg" [(set (match_dup 3) @@ -1268,6 +1359,102 @@ "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) +;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long) + +(define_expand "vsx_xvcvsxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvsxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvsxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVSXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvsxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvuxddp_scale" + [(match_operand:V2DF 0 "vsx_register_operand" "") + (match_operand:V2DI 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + int scale = INTVAL(operands[2]); + emit_insn (gen_vsx_xvcvuxddp (op0, op1)); + if (scale != 0) + rs6000_scale_v2df (op0, op0, -scale); + DONE; +}) + +(define_insn "vsx_xvcvuxddp" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVUXDDP))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvuxddp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpsxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpsxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpsxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPSXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpsxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvdpuxds_scale" + [(match_operand:V2DI 0 "vsx_register_operand" "") + (match_operand:V2DF 1 "vsx_register_operand" "") + (match_operand:QI 2 "immediate_operand" "")] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx tmp = gen_reg_rtx (V2DFmode); + int scale = INTVAL(operands[2]); + if (scale != 0) + rs6000_scale_v2df (tmp, op1, scale); + emit_insn (gen_vsx_xvcvdpuxds (op0, tmp)); + DONE; +}) + +(define_insn "vsx_xvcvdpuxds" + [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa") + (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_XVCVDPUXDS))] + "VECTOR_UNIT_VSX_P (V2DFmode)" + "xvcvdpuxds %x0,%x1" + [(set_attr "type" "vecdouble")]) + ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. @@ -1921,6 +2108,22 @@ "xxspltw %x0,%x1,%2" [(set_attr "type" "vecperm")]) +;; V2DF/V2DI splat for use by vec_splat builtin +(define_insn "vsx_xxspltd_<mode>" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wa") + (match_operand:QI 2 "u5bit_cint_operand" "i")] + UNSPEC_VSX_XXSPLTD))] + "VECTOR_MEM_VSX_P (<MODE>mode)" +{ + if ((VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 0) + || (!VECTOR_ELT_ORDER_BIG && INTVAL (operands[2]) == 1)) + return "xxpermdi %x0,%x1,%x1,0"; + else + return "xxpermdi %x0,%x1,%x1,3"; +} + [(set_attr "type" "vecperm")]) + ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_<mode>" [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?<VSa>") diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h index f2b7bd07acf..10123313f99 100644 --- a/gcc/config/rs6000/xcoff.h +++ b/gcc/config/rs6000/xcoff.h @@ -304,14 +304,15 @@ do { fputs (LOCAL_COMMON_ASM_OP, (FILE)); \ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ if ((ALIGN) > 32) \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,%u\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s%u_,%u\n", \ (SIZE), xcoff_bss_section_name, \ + floor_log2 ((ALIGN) / BITS_PER_UNIT), \ floor_log2 ((ALIGN) / BITS_PER_UNIT)); \ else if ((SIZE) > 4) \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,3\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s3_,3\n", \ (SIZE), xcoff_bss_section_name); \ else \ - fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s\n", \ + fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",%s,2\n", \ (SIZE), xcoff_bss_section_name); \ } while (0) #endif diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index 3d4553a6e61..06798181a5b 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -2957,7 +2957,7 @@ enum struct ashl_lshr_sequence { char insn_count; - char amount[6]; + signed char amount[6]; char clobbers_t; }; diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 7978be4e4bf..d957e55400b 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -6331,10 +6331,9 @@ label: }) (define_expand "extendqihi2" - [(set (match_operand:HI 0 "arith_reg_dest" "") - (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "")))] - "" - "") + [(set (match_operand:HI 0 "arith_reg_dest") + (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))] + "TARGET_SH1") (define_insn "*extendqihi2_compact_reg" [(set (match_operand:HI 0 "arith_reg_dest" "=r") diff --git a/gcc/config/sh/sh_optimize_sett_clrt.cc b/gcc/config/sh/sh_optimize_sett_clrt.cc index 313e5b5f4c2..3791cc76c80 100644 --- a/gcc/config/sh/sh_optimize_sett_clrt.cc +++ b/gcc/config/sh/sh_optimize_sett_clrt.cc @@ -111,7 +111,7 @@ private: // Given a start insn and its basic block, recursively determine all // possible ccreg values in all basic block paths that can lead to the // start insn. - void find_last_ccreg_values (rtx start_insn, basic_block bb, + bool find_last_ccreg_values (rtx start_insn, basic_block bb, std::vector<ccreg_value>& values_out, std::vector<basic_block>& prev_visited_bb) const; @@ -226,8 +226,8 @@ sh_optimize_sett_clrt::execute (void) ccreg_values.clear (); visited_bbs.clear (); - find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values, - visited_bbs); + bool ok = find_last_ccreg_values (PREV_INSN (i), bb, ccreg_values, + visited_bbs); log_msg ("number of ccreg values collected: %u\n", (unsigned int)ccreg_values.size ()); @@ -235,7 +235,7 @@ sh_optimize_sett_clrt::execute (void) // If all the collected values are equal and are equal to the // constant value of the setcc insn, the setcc insn can be // removed. - if (all_ccreg_values_equal (ccreg_values) + if (ok && all_ccreg_values_equal (ccreg_values) && rtx_equal_p (ccreg_values.front ().value, setcc_val)) { log_msg ("all values are "); @@ -309,7 +309,7 @@ sh_optimize_sett_clrt gcc_unreachable (); } -void +bool sh_optimize_sett_clrt ::find_last_ccreg_values (rtx start_insn, basic_block bb, std::vector<ccreg_value>& values_out, @@ -348,7 +348,7 @@ sh_optimize_sett_clrt log_msg ("\n"); values_out.push_back (v); - return; + return true; } if (any_condjump_p (i) && onlyjump_p (i) && !prev_visited_bb.empty ()) @@ -372,7 +372,7 @@ sh_optimize_sett_clrt log_msg ("\n"); values_out.push_back (v); - return; + return true; } } @@ -393,10 +393,14 @@ sh_optimize_sett_clrt for (edge_iterator ei = ei_start (bb->preds); !ei_end_p (ei); ei_next (&ei)) { + if (ei_edge (ei)->flags & EDGE_COMPLEX) + log_return (false, "aborting due to complex edge\n"); + basic_block pred_bb = ei_edge (ei)->src; pred_bb_count += 1; - find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out, - prev_visited_bb); + if (!find_last_ccreg_values (BB_END (pred_bb), pred_bb, values_out, + prev_visited_bb)) + return false; } prev_visited_bb.pop_back (); @@ -419,6 +423,8 @@ sh_optimize_sett_clrt values_out.push_back (v); } + + return true; } bool diff --git a/gcc/config/sh/sh_treg_combine.cc b/gcc/config/sh/sh_treg_combine.cc index e7360402251..38e28038d2e 100644 --- a/gcc/config/sh/sh_treg_combine.cc +++ b/gcc/config/sh/sh_treg_combine.cc @@ -78,14 +78,17 @@ Example 1) In [bb 4] elimination of the comparison would require inversion of the branch condition and compensation of other BBs. -Instead an inverting reg-move can be used: +Instead the comparison in [bb 3] can be replaced with the comparison in [bb 5] +by using a reg-reg move. In [bb 4] a logical not is used to compensate the +inverted condition. [bb 3] (set (reg:SI 167) (reg:SI 173)) -> bb 5 [BB 4] -(set (reg:SI 167) (not:SI (reg:SI 177))) +(set (reg:SI 147 t) (eq:SI (reg:SI 177) (const_int 0))) +(set (reg:SI 167) (reg:SI 147 t)) -> bb 5 [bb 5] @@ -214,9 +217,9 @@ In order to handle cases such as above the RTL pass does the following: and replace the comparisons in the BBs with reg-reg copies to get the operands in place (create new pseudo regs). - - If the cstores differ, try to apply the special case - (eq (reg) (const_int 0)) -> inverted = (not (reg)). - for the subordinate cstore types and eliminate the dominating ones. + - If the cstores differ and the comparison is a test against zero, + use reg-reg copies for the dominating cstores and logical not cstores + for the subordinate cstores. - If the comparison types in the BBs are not the same, or the first approach doesn't work out for some reason, try to eliminate the comparison before the @@ -558,7 +561,8 @@ private: bool can_extend_ccreg_usage (const bb_entry& e, const cbranch_trace& trace) const; - // Create an insn rtx that is a negating reg move (not operation). + // Create an insn rtx that performs a logical not (test != 0) on the src_reg + // and stores the result in dst_reg. rtx make_not_reg_insn (rtx dst_reg, rtx src_reg) const; // Create an insn rtx that inverts the ccreg. @@ -892,12 +896,32 @@ sh_treg_combine::can_remove_comparison (const bb_entry& e, rtx sh_treg_combine::make_not_reg_insn (rtx dst_reg, rtx src_reg) const { - // This will to go through expanders and may output multiple insns - // for multi-word regs. + // On SH we can do only SImode and DImode comparisons. + if (! (GET_MODE (src_reg) == SImode || GET_MODE (src_reg) == DImode)) + return NULL; + + // On SH we can store the ccreg into an SImode or DImode reg only. + if (! (GET_MODE (dst_reg) == SImode || GET_MODE (dst_reg) == DImode)) + return NULL; + start_sequence (); - expand_simple_unop (GET_MODE (dst_reg), NOT, src_reg, dst_reg, 0); + + emit_insn (gen_rtx_SET (VOIDmode, m_ccreg, + gen_rtx_fmt_ee (EQ, SImode, src_reg, const0_rtx))); + + if (GET_MODE (dst_reg) == SImode) + emit_move_insn (dst_reg, m_ccreg); + else if (GET_MODE (dst_reg) == DImode) + { + emit_move_insn (gen_lowpart (SImode, dst_reg), m_ccreg); + emit_move_insn (gen_highpart (SImode, dst_reg), const0_rtx); + } + else + gcc_unreachable (); + rtx i = get_insns (); end_sequence (); + return i; } @@ -1080,7 +1104,12 @@ sh_treg_combine::try_combine_comparisons (cbranch_trace& trace, // There is one special case though, where an integer comparison // (eq (reg) (const_int 0)) // can be inverted with a sequence - // (eq (not (reg)) (const_int 0)) + // (set (t) (eq (reg) (const_int 0)) + // (set (reg) (t)) + // (eq (reg) (const_int 0)) + // + // FIXME: On SH2A it might be better to use the nott insn in this case, + // i.e. do the try_eliminate_cstores approach instead. if (inv_cstore_count != 0 && cstore_count != 0) { if (make_not_reg_insn (comp_op0, comp_op0) == NULL_RTX) diff --git a/gcc/config/sparc/leon.md b/gcc/config/sparc/leon.md index 82b6a0d9633..ad22e3b592d 100644 --- a/gcc/config/sparc/leon.md +++ b/gcc/config/sparc/leon.md @@ -29,11 +29,11 @@ ;; Use a double reservation to work around the load pipeline hazard on UT699. (define_insn_reservation "leon3_load" 1 - (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload")) + (and (eq_attr "cpu" "leon3,leon3v7") (eq_attr "type" "load,sload")) "leon_memory*2") (define_insn_reservation "leon_store" 2 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "store")) "leon_memory*2") ;; This describes Gaisler Research's FPU @@ -44,21 +44,21 @@ (define_cpu_unit "grfpu_ds" "grfpu") (define_insn_reservation "leon_fp_alu" 4 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fp,fpcmp,fpmul")) "grfpu_alu, nothing*3") (define_insn_reservation "leon_fp_divs" 16 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivs")) "grfpu_ds*14, nothing*2") (define_insn_reservation "leon_fp_divd" 17 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpdivd")) "grfpu_ds*15, nothing*2") (define_insn_reservation "leon_fp_sqrts" 24 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrts")) "grfpu_ds*22, nothing*2") (define_insn_reservation "leon_fp_sqrtd" 25 - (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd")) + (and (eq_attr "cpu" "leon,leon3,leon3v7") (eq_attr "type" "fpsqrtd")) "grfpu_ds*23, nothing*2") diff --git a/gcc/config/sparc/sparc-opts.h b/gcc/config/sparc/sparc-opts.h index 13b375ae164..26017edc037 100644 --- a/gcc/config/sparc/sparc-opts.h +++ b/gcc/config/sparc/sparc-opts.h @@ -31,6 +31,7 @@ enum processor_type { PROCESSOR_HYPERSPARC, PROCESSOR_LEON, PROCESSOR_LEON3, + PROCESSOR_LEON3V7, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 5b00cca4751..d00c7b6fef5 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1246,6 +1246,7 @@ sparc_option_override (void) { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, { TARGET_CPU_leon, PROCESSOR_LEON }, { TARGET_CPU_leon3, PROCESSOR_LEON3 }, + { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 }, { TARGET_CPU_sparclite, PROCESSOR_F930 }, { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, @@ -1274,6 +1275,7 @@ sparc_option_override (void) { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU }, { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU }, { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU }, + { "leon3v7", MASK_ISA, MASK_LEON3|MASK_FPU }, { "sparclite", MASK_ISA, MASK_SPARCLITE }, /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, @@ -1526,6 +1528,7 @@ sparc_option_override (void) sparc_costs = &leon_costs; break; case PROCESSOR_LEON3: + case PROCESSOR_LEON3V7: sparc_costs = &leon3_costs; break; case PROCESSOR_SPARCLET: @@ -6801,28 +6804,30 @@ function_arg_union_value (int size, enum machine_mode mode, int slotno, } /* Used by function_arg and sparc_function_value_1 to implement the conventions - for passing and returning large (BLKmode) vectors. + for passing and returning BLKmode vectors. Return an expression valid as a return value for the FUNCTION_ARG and TARGET_FUNCTION_VALUE. - SIZE is the size in bytes of the vector (at least 8 bytes). + SIZE is the size in bytes of the vector. REGNO is the FP hard register the vector will be passed in. */ static rtx function_arg_vector_value (int size, int regno) { - int i, nregs = size / 8; - rtx regs; - - regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); + const int nregs = MAX (1, size / 8); + rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); - for (i = 0; i < nregs; i++) - { + if (size < 8) + XVECEXP (regs, 0, 0) + = gen_rtx_EXPR_LIST (VOIDmode, + gen_rtx_REG (SImode, regno), + const0_rtx); + else + for (int i = 0; i < nregs; i++) XVECEXP (regs, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (DImode, regno + 2*i), GEN_INT (i*8)); - } return regs; } @@ -6868,10 +6873,9 @@ sparc_function_arg_1 (cumulative_args_t cum_v, enum machine_mode mode, || (TARGET_ARCH64 && size <= 16)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST + 2*slotno); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno); + + mclass = MODE_FLOAT; } if (TARGET_ARCH32) @@ -7315,10 +7319,9 @@ sparc_function_value_1 (const_tree type, enum machine_mode mode, || (TARGET_ARCH64 && size <= 32)); if (mode == BLKmode) - return function_arg_vector_value (size, - SPARC_FP_ARG_FIRST); - else - mclass = MODE_FLOAT; + return function_arg_vector_value (size, SPARC_FP_ARG_FIRST); + + mclass = MODE_FLOAT; } if (TARGET_ARCH64 && type) diff --git a/gcc/config/sparc/sparc.h b/gcc/config/sparc/sparc.h index dd2b5ad9cf0..79dbba22d09 100644 --- a/gcc/config/sparc/sparc.h +++ b/gcc/config/sparc/sparc.h @@ -137,21 +137,22 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_hypersparc 3 #define TARGET_CPU_leon 4 #define TARGET_CPU_leon3 5 -#define TARGET_CPU_sparclite 6 -#define TARGET_CPU_f930 6 /* alias */ -#define TARGET_CPU_f934 6 /* alias */ -#define TARGET_CPU_sparclite86x 7 -#define TARGET_CPU_sparclet 8 -#define TARGET_CPU_tsc701 8 /* alias */ -#define TARGET_CPU_v9 9 /* generic v9 implementation */ -#define TARGET_CPU_sparcv9 9 /* alias */ -#define TARGET_CPU_sparc64 9 /* alias */ -#define TARGET_CPU_ultrasparc 10 -#define TARGET_CPU_ultrasparc3 11 -#define TARGET_CPU_niagara 12 -#define TARGET_CPU_niagara2 13 -#define TARGET_CPU_niagara3 14 -#define TARGET_CPU_niagara4 15 +#define TARGET_CPU_leon3v7 6 +#define TARGET_CPU_sparclite 7 +#define TARGET_CPU_f930 7 /* alias */ +#define TARGET_CPU_f934 7 /* alias */ +#define TARGET_CPU_sparclite86x 8 +#define TARGET_CPU_sparclet 9 +#define TARGET_CPU_tsc701 9 /* alias */ +#define TARGET_CPU_v9 10 /* generic v9 implementation */ +#define TARGET_CPU_sparcv9 10 /* alias */ +#define TARGET_CPU_sparc64 10 /* alias */ +#define TARGET_CPU_ultrasparc 11 +#define TARGET_CPU_ultrasparc3 12 +#define TARGET_CPU_niagara 13 +#define TARGET_CPU_niagara2 14 +#define TARGET_CPU_niagara3 15 +#define TARGET_CPU_niagara4 16 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ @@ -239,6 +240,11 @@ extern enum cmodel sparc_cmodel; #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG #endif +#if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 +#define CPP_CPU32_DEFAULT_SPEC "-D__leon__" +#define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG +#endif + #endif #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) @@ -285,6 +291,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ +%{mcpu=leon3v7:-D__leon__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ %{mcpu=ultrasparc3:-D__sparc_v9__} \ @@ -334,6 +341,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=hypersparc:-Av8} \ %{mcpu=leon:" AS_LEON_FLAG "} \ %{mcpu=leon3:" AS_LEON_FLAG "} \ +%{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ %{mv8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ @@ -1760,8 +1768,10 @@ extern int sparc_indent_opcode; #ifdef HAVE_AS_LEON #define AS_LEON_FLAG "-Aleon" +#define AS_LEONV7_FLAG "-Aleon" #else #define AS_LEON_FLAG "-Av8" +#define AS_LEONV7_FLAG "-Av7" #endif /* We use gcc _mcount for profiling. */ diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index 76c331597e4..954c297fd98 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -221,6 +221,7 @@ hypersparc, leon, leon3, + leon3v7, sparclite, f930, f934, diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt index 64e40955a53..3cd2b603a8c 100644 --- a/gcc/config/sparc/sparc.opt +++ b/gcc/config/sparc/sparc.opt @@ -153,6 +153,9 @@ EnumValue Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3) EnumValue +Enum(sparc_processor_type) String(leon3v7) Value(PROCESSOR_LEON3V7) + +EnumValue Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE) EnumValue diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems index 86a2302614c..ae7a33ab447 100644 --- a/gcc/config/sparc/t-rtems +++ b/gcc/config/sparc/t-rtems @@ -17,6 +17,15 @@ # <http://www.gnu.org/licenses/>. # -MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3 -MULTILIB_DIRNAMES = soft v8 leon3 +MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3/mcpu=leon3v7 muser-mode +MULTILIB_DIRNAMES = soft v8 leon3 leon3v7 user-mode MULTILIB_MATCHES = msoft-float=mno-fpu + +MULTILIB_EXCEPTIONS = muser-mode +MULTILIB_EXCEPTIONS += mcpu=leon3 +MULTILIB_EXCEPTIONS += mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3 +MULTILIB_EXCEPTIONS += msoft-float/mcpu=leon3v7 +MULTILIB_EXCEPTIONS += msoft-float/muser-mode +MULTILIB_EXCEPTIONS += msoft-float/mcpu=v8/muser-mode +MULTILIB_EXCEPTIONS += mcpu=v8/muser-mode diff --git a/gcc/configure b/gcc/configure index 291e4638843..f48dd189e6a 100755 --- a/gcc/configure +++ b/gcc/configure @@ -27851,7 +27851,47 @@ if test "x${CLOOGLIBS}" != "x" ; then $as_echo "#define HAVE_cloog 1" >>confdefs.h + + # Check whether isl_schedule_constraints_compute_schedule is available; + # it's new in ISL-0.13. + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $ISLINC" + saved_LIBS="$LIBS" + LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS" + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking Checking for isl_schedule_constraints_compute_schedule" >&5 +$as_echo_n "checking Checking for isl_schedule_constraints_compute_schedule... " >&6; } + cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ +#include <isl/schedule.h> +int +main () +{ +isl_schedule_constraints_compute_schedule (NULL); + ; + return 0; +} +_ACEOF +if ac_fn_c_try_link "$LINENO"; then : + ac_has_isl_schedule_constraints_compute_schedule=yes +else + ac_has_isl_schedule_constraints_compute_schedule=no fi +rm -f core conftest.err conftest.$ac_objext \ + conftest$ac_exeext conftest.$ac_ext + { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_has_isl_schedule_constraints_compute_schedule" >&5 +$as_echo "$ac_has_isl_schedule_constraints_compute_schedule" >&6; } + + LIBS="$saved_LIBS" + CFLAGS="$saved_CFLAGS" + + if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then + +$as_echo "#define HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE 1" >>confdefs.h + + fi +fi + # Check for plugin support # Check whether --enable-plugin was given. diff --git a/gcc/configure.ac b/gcc/configure.ac index b9a37992655..e54df10949e 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -5495,8 +5495,31 @@ AC_ARG_VAR(CLOOGLIBS,[How to link CLOOG]) AC_ARG_VAR(CLOOGINC,[How to find CLOOG include files]) if test "x${CLOOGLIBS}" != "x" ; then AC_DEFINE(HAVE_cloog, 1, [Define if cloog is in use.]) + + # Check whether isl_schedule_constraints_compute_schedule is available; + # it's new in ISL-0.13. + saved_CFLAGS="$CFLAGS" + CFLAGS="$CFLAGS $ISLINC" + saved_LIBS="$LIBS" + LIBS="$LIBS $CLOOGLIBS $ISLLIBS $GMPLIBS" + + AC_MSG_CHECKING([Checking for isl_schedule_constraints_compute_schedule]) + AC_TRY_LINK([#include <isl/schedule.h>], + [isl_schedule_constraints_compute_schedule (NULL);], + [ac_has_isl_schedule_constraints_compute_schedule=yes], + [ac_has_isl_schedule_constraints_compute_schedule=no]) + AC_MSG_RESULT($ac_has_isl_schedule_constraints_compute_schedule) + + LIBS="$saved_LIBS" + CFLAGS="$saved_CFLAGS" + + if test x"$ac_has_isl_schedule_constraints_compute_schedule" = x"yes"; then + AC_DEFINE(HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE, 1, + [Define if isl_schedule_constraints_compute_schedule exists.]) + fi fi + # Check for plugin support AC_ARG_ENABLE(plugin, [AS_HELP_STRING([--enable-plugin], [enable plugin support])], diff --git a/gcc/convert.c b/gcc/convert.c index 91c1da265a8..cb57b29e07e 100644 --- a/gcc/convert.c +++ b/gcc/convert.c @@ -97,6 +97,15 @@ convert_to_real (tree type, tree expr) enum built_in_function fcode = builtin_mathfn_code (expr); tree itype = TREE_TYPE (expr); + if (TREE_CODE (expr) == COMPOUND_EXPR) + { + tree t = convert_to_real (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t), + TREE_OPERAND (expr, 0), t); + } + /* Disable until we figure out how to decide whether the functions are present in runtime. */ /* Convert (float)sqrt((double)x) where x is float into sqrtf(x) */ @@ -403,6 +412,15 @@ convert_to_integer (tree type, tree expr) return error_mark_node; } + if (ex_form == COMPOUND_EXPR) + { + tree t = convert_to_integer (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, TREE_TYPE (t), + TREE_OPERAND (expr, 0), t); + } + /* Convert e.g. (long)round(d) -> lround(d). */ /* If we're converting to char, we may encounter differing behavior between converting from double->char vs double->long->char. @@ -891,6 +909,14 @@ convert_to_complex (tree type, tree expr) if (TYPE_MAIN_VARIANT (elt_type) == TYPE_MAIN_VARIANT (subtype)) return expr; + else if (TREE_CODE (expr) == COMPOUND_EXPR) + { + tree t = convert_to_complex (type, TREE_OPERAND (expr, 1)); + if (t == TREE_OPERAND (expr, 1)) + return expr; + return build2_loc (EXPR_LOCATION (expr), COMPOUND_EXPR, + TREE_TYPE (t), TREE_OPERAND (expr, 0), t); + } else if (TREE_CODE (expr) == COMPLEX_EXPR) return fold_build2 (COMPLEX_EXPR, type, convert (subtype, TREE_OPERAND (expr, 0)), diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index d79d629bdf2..2dfc5d379a5 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,14 @@ +2014-11-21 Jason Merrill <jason@redhat.com> + + PR c++/63849 + * mangle.c (decl_mangling_context): Use template_type_parameter_p. + +2014-11-11 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/63265 + * pt.c (tsubst_copy_and_build, case COND_EXPR): Maybe fold to + constant the condition. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/gcc/cp/mangle.c b/gcc/cp/mangle.c index c8f57d3912c..d944d5e0f3a 100644 --- a/gcc/cp/mangle.c +++ b/gcc/cp/mangle.c @@ -763,8 +763,7 @@ decl_mangling_context (tree decl) if (extra) return extra; } - else if (TREE_CODE (decl) == TYPE_DECL - && TREE_CODE (TREE_TYPE (decl)) == TEMPLATE_TYPE_PARM) + else if (template_type_parameter_p (decl)) /* template type parms have no mangling context. */ return NULL_TREE; return CP_DECL_CONTEXT (decl); diff --git a/gcc/cp/pt.c b/gcc/cp/pt.c index 0f989097442..c0b8b9238b5 100644 --- a/gcc/cp/pt.c +++ b/gcc/cp/pt.c @@ -14875,11 +14875,13 @@ tsubst_copy_and_build (tree t, case COND_EXPR: { tree cond = RECUR (TREE_OPERAND (t, 0)); + tree folded_cond = (maybe_constant_value + (fold_non_dependent_expr_sfinae (cond, tf_none))); tree exp1, exp2; - if (TREE_CODE (cond) == INTEGER_CST) + if (TREE_CODE (folded_cond) == INTEGER_CST) { - if (integer_zerop (cond)) + if (integer_zerop (folded_cond)) { ++c_inhibit_evaluation_warnings; exp1 = RECUR (TREE_OPERAND (t, 1)); @@ -14893,6 +14895,7 @@ tsubst_copy_and_build (tree t, exp2 = RECUR (TREE_OPERAND (t, 2)); --c_inhibit_evaluation_warnings; } + cond = folded_cond; } else { diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 10ad6e4faf8..c42add7f16f 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -13233,16 +13233,22 @@ vector bool int vec_cmplt (vector unsigned int, vector unsigned int); vector bool int vec_cmplt (vector signed int, vector signed int); vector bool int vec_cmplt (vector float, vector float); +vector float vec_cpsgn (vector float, vector float); + vector float vec_ctf (vector unsigned int, const int); vector float vec_ctf (vector signed int, const int); +vector double vec_ctf (vector unsigned long, const int); +vector double vec_ctf (vector signed long, const int); vector float vec_vcfsx (vector signed int, const int); vector float vec_vcfux (vector unsigned int, const int); vector signed int vec_cts (vector float, const int); +vector signed long vec_cts (vector double, const int); vector unsigned int vec_ctu (vector float, const int); +vector unsigned long vec_ctu (vector double, const int); void vec_dss (const int); @@ -14078,6 +14084,16 @@ vector float vec_splat (vector float, const int); vector signed int vec_splat (vector signed int, const int); vector unsigned int vec_splat (vector unsigned int, const int); vector bool int vec_splat (vector bool int, const int); +vector signed long vec_splat (vector signed long, const int); +vector unsigned long vec_splat (vector unsigned long, const int); + +vector signed char vec_splats (signed char); +vector unsigned char vec_splats (unsigned char); +vector signed short vec_splats (signed short); +vector unsigned short vec_splats (unsigned short); +vector signed int vec_splats (signed int); +vector unsigned int vec_splats (unsigned int); +vector float vec_splats (float); vector float vec_vspltw (vector float, const int); vector signed int vec_vspltw (vector signed int, const int); @@ -14782,17 +14798,32 @@ vector double vec_add (vector double, vector double); vector double vec_and (vector double, vector double); vector double vec_and (vector double, vector bool long); vector double vec_and (vector bool long, vector double); +vector long vec_and (vector long, vector long); +vector long vec_and (vector long, vector bool long); +vector long vec_and (vector bool long, vector long); +vector unsigned long vec_and (vector unsigned long, vector unsigned long); +vector unsigned long vec_and (vector unsigned long, vector bool long); +vector unsigned long vec_and (vector bool long, vector unsigned long); vector double vec_andc (vector double, vector double); vector double vec_andc (vector double, vector bool long); vector double vec_andc (vector bool long, vector double); +vector long vec_andc (vector long, vector long); +vector long vec_andc (vector long, vector bool long); +vector long vec_andc (vector bool long, vector long); +vector unsigned long vec_andc (vector unsigned long, vector unsigned long); +vector unsigned long vec_andc (vector unsigned long, vector bool long); +vector unsigned long vec_andc (vector bool long, vector unsigned long); vector double vec_ceil (vector double); vector bool long vec_cmpeq (vector double, vector double); vector bool long vec_cmpge (vector double, vector double); vector bool long vec_cmpgt (vector double, vector double); vector bool long vec_cmple (vector double, vector double); vector bool long vec_cmplt (vector double, vector double); +vector double vec_cpsgn (vector double, vector double); vector float vec_div (vector float, vector float); vector double vec_div (vector double, vector double); +vector long vec_div (vector long, vector long); +vector unsigned long vec_div (vector unsigned long, vector unsigned long); vector double vec_floor (vector double); vector double vec_ld (int, const vector double *); vector double vec_ld (int, const double *); @@ -14802,38 +14833,83 @@ vector unsigned char vec_lvsl (int, const volatile double *); vector unsigned char vec_lvsr (int, const volatile double *); vector double vec_madd (vector double, vector double, vector double); vector double vec_max (vector double, vector double); +vector signed long vec_mergeh (vector signed long, vector signed long); +vector signed long vec_mergeh (vector signed long, vector bool long); +vector signed long vec_mergeh (vector bool long, vector signed long); +vector unsigned long vec_mergeh (vector unsigned long, vector unsigned long); +vector unsigned long vec_mergeh (vector unsigned long, vector bool long); +vector unsigned long vec_mergeh (vector bool long, vector unsigned long); +vector signed long vec_mergel (vector signed long, vector signed long); +vector signed long vec_mergel (vector signed long, vector bool long); +vector signed long vec_mergel (vector bool long, vector signed long); +vector unsigned long vec_mergel (vector unsigned long, vector unsigned long); +vector unsigned long vec_mergel (vector unsigned long, vector bool long); +vector unsigned long vec_mergel (vector bool long, vector unsigned long); vector double vec_min (vector double, vector double); vector float vec_msub (vector float, vector float, vector float); vector double vec_msub (vector double, vector double, vector double); vector float vec_mul (vector float, vector float); vector double vec_mul (vector double, vector double); +vector long vec_mul (vector long, vector long); +vector unsigned long vec_mul (vector unsigned long, vector unsigned long); vector float vec_nearbyint (vector float); vector double vec_nearbyint (vector double); vector float vec_nmadd (vector float, vector float, vector float); vector double vec_nmadd (vector double, vector double, vector double); vector double vec_nmsub (vector double, vector double, vector double); vector double vec_nor (vector double, vector double); +vector long vec_nor (vector long, vector long); +vector long vec_nor (vector long, vector bool long); +vector long vec_nor (vector bool long, vector long); +vector unsigned long vec_nor (vector unsigned long, vector unsigned long); +vector unsigned long vec_nor (vector unsigned long, vector bool long); +vector unsigned long vec_nor (vector bool long, vector unsigned long); vector double vec_or (vector double, vector double); vector double vec_or (vector double, vector bool long); vector double vec_or (vector bool long, vector double); -vector double vec_perm (vector double, - vector double, - vector unsigned char); +vector long vec_or (vector long, vector long); +vector long vec_or (vector long, vector bool long); +vector long vec_or (vector bool long, vector long); +vector unsigned long vec_or (vector unsigned long, vector unsigned long); +vector unsigned long vec_or (vector unsigned long, vector bool long); +vector unsigned long vec_or (vector bool long, vector unsigned long); +vector double vec_perm (vector double, vector double, vector unsigned char); +vector long vec_perm (vector long, vector long, vector unsigned char); +vector unsigned long vec_perm (vector unsigned long, vector unsigned long, + vector unsigned char); vector double vec_rint (vector double); vector double vec_recip (vector double, vector double); vector double vec_rsqrt (vector double); vector double vec_rsqrte (vector double); vector double vec_sel (vector double, vector double, vector bool long); vector double vec_sel (vector double, vector double, vector unsigned long); -vector double vec_sub (vector double, vector double); +vector long vec_sel (vector long, vector long, vector long); +vector long vec_sel (vector long, vector long, vector unsigned long); +vector long vec_sel (vector long, vector long, vector bool long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector unsigned long); +vector unsigned long vec_sel (vector unsigned long, vector unsigned long, + vector bool long); +vector double vec_splats (double); +vector signed long vec_splats (signed long); +vector unsigned long vec_splats (unsigned long); vector float vec_sqrt (vector float); vector double vec_sqrt (vector double); void vec_st (vector double, int, vector double *); void vec_st (vector double, int, double *); +vector double vec_sub (vector double, vector double); vector double vec_trunc (vector double); vector double vec_xor (vector double, vector double); vector double vec_xor (vector double, vector bool long); vector double vec_xor (vector bool long, vector double); +vector long vec_xor (vector long, vector long); +vector long vec_xor (vector long, vector bool long); +vector long vec_xor (vector bool long, vector long); +vector unsigned long vec_xor (vector unsigned long, vector unsigned long); +vector unsigned long vec_xor (vector unsigned long, vector bool long); +vector unsigned long vec_xor (vector bool long, vector unsigned long); int vec_all_eq (vector double, vector double); int vec_all_ge (vector double, vector double); int vec_all_gt (vector double, vector double); @@ -14962,17 +15038,30 @@ vector unsigned long long vec_add (vector unsigned long long, vector unsigned long long); int vec_all_eq (vector long long, vector long long); +int vec_all_eq (vector unsigned long long, vector unsigned long long); int vec_all_ge (vector long long, vector long long); +int vec_all_ge (vector unsigned long long, vector unsigned long long); int vec_all_gt (vector long long, vector long long); +int vec_all_gt (vector unsigned long long, vector unsigned long long); int vec_all_le (vector long long, vector long long); +int vec_all_le (vector unsigned long long, vector unsigned long long); int vec_all_lt (vector long long, vector long long); +int vec_all_lt (vector unsigned long long, vector unsigned long long); int vec_all_ne (vector long long, vector long long); +int vec_all_ne (vector unsigned long long, vector unsigned long long); + int vec_any_eq (vector long long, vector long long); +int vec_any_eq (vector unsigned long long, vector unsigned long long); int vec_any_ge (vector long long, vector long long); +int vec_any_ge (vector unsigned long long, vector unsigned long long); int vec_any_gt (vector long long, vector long long); +int vec_any_gt (vector unsigned long long, vector unsigned long long); int vec_any_le (vector long long, vector long long); +int vec_any_le (vector unsigned long long, vector unsigned long long); int vec_any_lt (vector long long, vector long long); +int vec_any_lt (vector unsigned long long, vector unsigned long long); int vec_any_ne (vector long long, vector long long); +int vec_any_ne (vector unsigned long long, vector unsigned long long); vector long long vec_eqv (vector long long, vector long long); vector long long vec_eqv (vector bool long long, vector long long); @@ -15010,6 +15099,14 @@ vector long long vec_max (vector long long, vector long long); vector unsigned long long vec_max (vector unsigned long long, vector unsigned long long); +vector signed int vec_mergee (vector signed int, vector signed int); +vector unsigned int vec_mergee (vector unsigned int, vector unsigned int); +vector bool int vec_mergee (vector bool int, vector bool int); + +vector signed int vec_mergeo (vector signed int, vector signed int); +vector unsigned int vec_mergeo (vector unsigned int, vector unsigned int); +vector bool int vec_mergeo (vector bool int, vector bool int); + vector long long vec_min (vector long long, vector long long); vector unsigned long long vec_min (vector unsigned long long, vector unsigned long long); @@ -15088,6 +15185,8 @@ vector unsigned int vec_packs (vector unsigned long long, vector unsigned long long); vector unsigned int vec_packsu (vector long long, vector long long); +vector unsigned int vec_packsu (vector unsigned long long, + vector unsigned long long); vector long long vec_rl (vector long long, vector unsigned long long); @@ -15129,6 +15228,15 @@ vector unsigned long long vec_vaddudm (vector unsigned long long, vector long long vec_vbpermq (vector signed char, vector signed char); vector long long vec_vbpermq (vector unsigned char, vector unsigned char); +vector long long vec_cntlz (vector long long); +vector unsigned long long vec_cntlz (vector unsigned long long); +vector int vec_cntlz (vector int); +vector unsigned int vec_cntlz (vector int); +vector short vec_cntlz (vector short); +vector unsigned short vec_cntlz (vector unsigned short); +vector signed char vec_cntlz (vector signed char); +vector unsigned char vec_cntlz (vector unsigned char); + vector long long vec_vclz (vector long long); vector unsigned long long vec_vclz (vector unsigned long long); vector int vec_vclz (vector int); diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 0c47349e4b5..871a4175446 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -21134,8 +21134,8 @@ the rules of the ABI@. Set the instruction set, register set, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc}, -@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934}, -@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, +@samp{leon}, @samp{leon3}, @samp{leon3v7}, @samp{sparclite}, @samp{f930}, +@samp{f934}, @samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. @@ -21153,7 +21153,7 @@ implementations. @table @asis @item v7 -cypress +cypress, leon3v7 @item v8 supersparc, hypersparc, leon, leon3 @@ -21218,11 +21218,11 @@ option @option{-mcpu=@var{cpu_type}} does. The same values for @option{-mcpu=@var{cpu_type}} can be used for @option{-mtune=@var{cpu_type}}, but the only useful values are those that select a particular CPU implementation. Those are @samp{cypress}, -@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930}, -@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, -@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and -@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native} -can also be used. +@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, +@samp{leon3v7}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, @samp{tsc701}, +@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, +@samp{niagara3} and @samp{niagara4}. With native Solaris and GNU/Linux +toolchains, @samp{native} can also be used. @item -mv8plus @itemx -mno-v8plus diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 0221870cd97..3ad66463ef8 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -4441,10 +4441,6 @@ to return a nonzero value when it is required, the compiler will run out of spill registers and print a fatal error message. @end deftypefn -@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM -If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately. -@end deftypevr - @node Scalar Return @subsection How Scalar Function Values Are Returned @cindex return values in registers @@ -6047,10 +6043,11 @@ for comparisons whose argument is a @code{plus}: @smallexample #define SELECT_CC_MODE(OP,X,Y) \ - (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ - ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ - : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ - || GET_CODE (X) == NEG) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == LT || OP == LE || OP == GT || OP == GE) \ + ? CCFPEmode : CCFPmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \ ? CC_NOOVmode : CCmode)) @end smallexample @@ -6093,10 +6090,11 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero. You need not define this macro if it would always returns zero or if the floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}. For example, here is the definition used on the SPARC, where floating-point -inequality comparisons are always given @code{CCFPEmode}: +inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}: @smallexample -#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) +#define REVERSIBLE_CC_MODE(MODE) \ + ((MODE) != CCFPEmode && (MODE) != CCFPmode) @end smallexample @end defmac @@ -6106,7 +6104,7 @@ comparison done in CC_MODE @var{mode}. The macro is used only in case @code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case machine has some non-standard way how to reverse certain conditionals. For instance in case all floating point conditions are non-trapping, compiler may -freely convert unordered compares to ordered one. Then definition may look +freely convert unordered compares to ordered ones. Then definition may look like: @smallexample @@ -6144,6 +6142,10 @@ same. If they are, it returns that mode. If they are different, it returns @code{VOIDmode}. @end deftypefn +@deftypevr {Target Hook} {unsigned int} TARGET_FLAGS_REGNUM +If the target has a dedicated flags register, and it needs to use the post-reload comparison elimination pass, then this value should be set appropriately. +@end deftypevr + @node Costs @section Describing Relative Costs of Operations @cindex costs of instructions diff --git a/gcc/doc/tm.texi.in b/gcc/doc/tm.texi.in index 0c7c9aa96c1..0c8335d88d5 100644 --- a/gcc/doc/tm.texi.in +++ b/gcc/doc/tm.texi.in @@ -3714,8 +3714,6 @@ stack. @hook TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P -@hook TARGET_FLAGS_REGNUM - @node Scalar Return @subsection How Scalar Function Values Are Returned @cindex return values in registers @@ -4631,10 +4629,11 @@ for comparisons whose argument is a @code{plus}: @smallexample #define SELECT_CC_MODE(OP,X,Y) \ - (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ - ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \ - : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ - || GET_CODE (X) == NEG) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + ? ((OP == LT || OP == LE || OP == GT || OP == GE) \ + ? CCFPEmode : CCFPmode) \ + : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \ + || GET_CODE (X) == NEG || GET_CODE (x) == ASHIFT) \ ? CC_NOOVmode : CCmode)) @end smallexample @@ -4657,10 +4656,11 @@ then @code{REVERSIBLE_CC_MODE (@var{mode})} must be zero. You need not define this macro if it would always returns zero or if the floating-point format is anything other than @code{IEEE_FLOAT_FORMAT}. For example, here is the definition used on the SPARC, where floating-point -inequality comparisons are always given @code{CCFPEmode}: +inequality comparisons are given either @code{CCFPEmode} or @code{CCFPmode}: @smallexample -#define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode) +#define REVERSIBLE_CC_MODE(MODE) \ + ((MODE) != CCFPEmode && (MODE) != CCFPmode) @end smallexample @end defmac @@ -4670,7 +4670,7 @@ comparison done in CC_MODE @var{mode}. The macro is used only in case @code{REVERSIBLE_CC_MODE (@var{mode})} is nonzero. Define this macro in case machine has some non-standard way how to reverse certain conditionals. For instance in case all floating point conditions are non-trapping, compiler may -freely convert unordered compares to ordered one. Then definition may look +freely convert unordered compares to ordered ones. Then definition may look like: @smallexample @@ -4684,6 +4684,8 @@ like: @hook TARGET_CC_MODES_COMPATIBLE +@hook TARGET_FLAGS_REGNUM + @node Costs @section Describing Relative Costs of Operations @cindex costs of instructions diff --git a/gcc/expmed.c b/gcc/expmed.c index cee002bdcfb..57d476eb12b 100644 --- a/gcc/expmed.c +++ b/gcc/expmed.c @@ -3321,6 +3321,9 @@ expand_widening_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, enum mult_variant variant; struct algorithm algorithm; + if (coeff == 0) + return CONST0_RTX (mode); + /* Special case powers of two. */ if (EXACT_POWER_OF_2_OR_ZERO_P (coeff)) { diff --git a/gcc/expr.c b/gcc/expr.c index bf14114d126..6d68d37e95f 100644 --- a/gcc/expr.c +++ b/gcc/expr.c @@ -7630,11 +7630,13 @@ expand_expr_addr_expr_1 (tree exp, rtx target, enum machine_mode tmode, break; case COMPOUND_LITERAL_EXPR: - /* Allow COMPOUND_LITERAL_EXPR in initializers, if e.g. - rtl_for_decl_init is called on DECL_INITIAL with - COMPOUNT_LITERAL_EXPRs in it, they aren't gimplified. */ - if (modifier == EXPAND_INITIALIZER - && COMPOUND_LITERAL_EXPR_DECL (exp)) + /* Allow COMPOUND_LITERAL_EXPR in initializers or coming from + initializers, if e.g. rtl_for_decl_init is called on DECL_INITIAL + with COMPOUND_LITERAL_EXPRs in it, or ARRAY_REF on a const static + array with address of COMPOUND_LITERAL_EXPR in DECL_INITIAL; + the initializers aren't gimplified. */ + if (COMPOUND_LITERAL_EXPR_DECL (exp) + && TREE_STATIC (COMPOUND_LITERAL_EXPR_DECL (exp))) return expand_expr_addr_expr_1 (COMPOUND_LITERAL_EXPR_DECL (exp), target, tmode, modifier, as); /* FALLTHRU */ diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 802c0214251..58df92d328b 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -9024,7 +9024,8 @@ fold_comparison (location_t loc, enum tree_code code, tree type, /* If the constant operation overflowed this can be simplified as a comparison against INT_MAX/INT_MIN. */ if (TREE_CODE (lhs) == INTEGER_CST - && TREE_OVERFLOW (lhs)) + && TREE_OVERFLOW (lhs) + && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (arg0))) { int const1_sgn = tree_int_cst_sgn (const1); enum tree_code code2 = code; @@ -13295,7 +13296,7 @@ fold_binary_loc (location_t loc, tree itype = TREE_TYPE (arg00); if (TREE_INT_CST_HIGH (arg01) == 0 && TREE_INT_CST_LOW (arg01) - == (unsigned HOST_WIDE_INT) (TYPE_PRECISION (itype) - 1)) + == (unsigned HOST_WIDE_INT) (element_precision (itype) - 1)) { if (TYPE_UNSIGNED (itype)) { diff --git a/gcc/fortran/ChangeLog b/gcc/fortran/ChangeLog index 648621cfb68..573c26167b0 100644 --- a/gcc/fortran/ChangeLog +++ b/gcc/fortran/ChangeLog @@ -1,3 +1,12 @@ +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-24 Jakub Jelinek <jakub@redhat.com> + + PR fortran/63938 + * trans-openmp.c (gfc_trans_omp_atomic): Make sure lhsaddr is + simple enough for goa_lhs_expr_p. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/gcc/fortran/trans-openmp.c b/gcc/fortran/trans-openmp.c index e31ede29bfa..3b0e6e9e977 100644 --- a/gcc/fortran/trans-openmp.c +++ b/gcc/fortran/trans-openmp.c @@ -2683,6 +2683,18 @@ gfc_trans_omp_atomic (gfc_code *code) } lhsaddr = save_expr (lhsaddr); + if (TREE_CODE (lhsaddr) != SAVE_EXPR + && (TREE_CODE (lhsaddr) != ADDR_EXPR + || TREE_CODE (TREE_OPERAND (lhsaddr, 0)) != VAR_DECL)) + { + /* Make sure LHS is simple enough so that goa_lhs_expr_p can recognize + it even after unsharing function body. */ + tree var = create_tmp_var_raw (TREE_TYPE (lhsaddr), NULL); + DECL_CONTEXT (var) = current_function_decl; + lhsaddr = build4 (TARGET_EXPR, TREE_TYPE (lhsaddr), var, lhsaddr, + NULL_TREE, NULL_TREE); + } + rhs = gfc_evaluate_now (rse.expr, &block); if (((atomic_code->ext.omp_atomic & GFC_OMP_ATOMIC_MASK) diff --git a/gcc/graphite-clast-to-gimple.c b/gcc/graphite-clast-to-gimple.c index fc60845d85a..134388c14f9 100644 --- a/gcc/graphite-clast-to-gimple.c +++ b/gcc/graphite-clast-to-gimple.c @@ -30,6 +30,11 @@ along with GCC; see the file COPYING3. If not see #include <isl/aff.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/lp.h> +#include <isl/deprecated/ilp_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-interchange.c b/gcc/graphite-interchange.c index 55e3fab897d..2e625c127ba 100644 --- a/gcc/graphite-interchange.c +++ b/gcc/graphite-interchange.c @@ -31,6 +31,12 @@ along with GCC; see the file COPYING3. If not see #include <isl/ilp.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#include <isl/deprecated/ilp_int.h> +#include <isl/deprecated/constraint_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-optimize-isl.c b/gcc/graphite-optimize-isl.c index 88d6d6cc28f..fc12eebbf10 100644 --- a/gcc/graphite-optimize-isl.c +++ b/gcc/graphite-optimize-isl.c @@ -28,6 +28,10 @@ along with GCC; see the file COPYING3. If not see #include <isl/band.h> #include <isl/aff.h> #include <isl/options.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#endif #endif #include "system.h" @@ -373,7 +377,11 @@ getScheduleForBandList (isl_band_list *BandList) { for (i = ScheduleDimensions - 1 ; i >= 0 ; i--) { +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE + if (isl_band_member_is_coincident (Band, i)) +#else if (isl_band_member_is_zero_distance (Band, i)) +#endif { isl_map *TileMap; isl_union_map *TileUMap; diff --git a/gcc/graphite-poly.c b/gcc/graphite-poly.c index 4ca62f9afbd..fccc2ec6de5 100644 --- a/gcc/graphite-poly.c +++ b/gcc/graphite-poly.c @@ -30,6 +30,10 @@ along with GCC; see the file COPYING3. If not see #include <isl/aff.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/ilp_int.h> +#endif #endif #include "system.h" diff --git a/gcc/graphite-sese-to-poly.c b/gcc/graphite-sese-to-poly.c index 28447e4b6fe..059c10dbb37 100644 --- a/gcc/graphite-sese-to-poly.c +++ b/gcc/graphite-sese-to-poly.c @@ -29,6 +29,11 @@ along with GCC; see the file COPYING3. If not see #include <cloog/cloog.h> #include <cloog/cloog.h> #include <cloog/isl/domain.h> +#ifdef HAVE_ISL_SCHED_CONSTRAINTS_COMPUTE_SCHEDULE +#include <isl/deprecated/int.h> +#include <isl/deprecated/aff_int.h> +#include <isl/deprecated/constraint_int.h> +#endif #endif #include "system.h" diff --git a/gcc/ipa-inline-analysis.c b/gcc/ipa-inline-analysis.c index 8e0f5dd8988..9e71f43e28d 100644 --- a/gcc/ipa-inline-analysis.c +++ b/gcc/ipa-inline-analysis.c @@ -861,9 +861,19 @@ evaluate_conditions_for_known_args (struct cgraph_node *node, } if (c->code == IS_NOT_CONSTANT || c->code == CHANGED) continue; - res = fold_binary_to_constant (c->code, boolean_type_node, val, c->val); - if (res && integer_zerop (res)) - continue; + + if (operand_equal_p (TYPE_SIZE (TREE_TYPE (c->val)), + TYPE_SIZE (TREE_TYPE (val)), 0)) + { + val = fold_unary (VIEW_CONVERT_EXPR, TREE_TYPE (c->val), val); + + res = val + ? fold_binary_to_constant (c->code, boolean_type_node, val, c->val) + : NULL; + + if (res && integer_zerop (res)) + continue; + } clause |= 1 << (i + predicate_first_dynamic_condition); } return clause; diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c index 7d358809965..8f1f5b1ff92 100644 --- a/gcc/ipa-pure-const.c +++ b/gcc/ipa-pure-const.c @@ -1434,7 +1434,7 @@ propagate_nothrow (void) else if (e->can_throw_external && !TREE_NOTHROW (y->decl)) can_throw = true; } - for (ie = node->indirect_calls; ie; ie = ie->next_callee) + for (ie = w->indirect_calls; ie; ie = ie->next_callee) if (ie->can_throw_external) { can_throw = true; diff --git a/gcc/ira.c b/gcc/ira.c index 4d91d2196a6..0c703c514ca 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -5347,7 +5347,18 @@ ira (FILE *f) ira_allocno_iterator ai; FOR_EACH_ALLOCNO (a, ai) - ALLOCNO_REGNO (a) = REGNO (ALLOCNO_EMIT_DATA (a)->reg); + { + int old_regno = ALLOCNO_REGNO (a); + int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); + + ALLOCNO_REGNO (a) = new_regno; + + if (old_regno != new_regno) + setup_reg_classes (new_regno, reg_preferred_class (old_regno), + reg_alternate_class (old_regno), + reg_allocno_class (old_regno)); + } + } else { diff --git a/gcc/omp-low.c b/gcc/omp-low.c index f77df897679..ea45e205bb9 100644 --- a/gcc/omp-low.c +++ b/gcc/omp-low.c @@ -11181,24 +11181,24 @@ simd_clone_adjust_return_type (struct cgraph_node *node) if (orig_rettype == void_type_node) return NULL_TREE; TREE_TYPE (fndecl) = build_distinct_type_copy (TREE_TYPE (fndecl)); - if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (fndecl))) - || POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (fndecl)))) + t = TREE_TYPE (TREE_TYPE (fndecl)); + if (INTEGRAL_TYPE_P (t) || POINTER_TYPE_P (t)) veclen = node->simdclone->vecsize_int; else veclen = node->simdclone->vecsize_float; - veclen /= GET_MODE_BITSIZE (TYPE_MODE (TREE_TYPE (TREE_TYPE (fndecl)))); + veclen /= GET_MODE_BITSIZE (TYPE_MODE (t)); if (veclen > node->simdclone->simdlen) veclen = node->simdclone->simdlen; + if (POINTER_TYPE_P (t)) + t = pointer_sized_int_node; if (veclen == node->simdclone->simdlen) - TREE_TYPE (TREE_TYPE (fndecl)) - = build_vector_type (TREE_TYPE (TREE_TYPE (fndecl)), - node->simdclone->simdlen); + t = build_vector_type (t, node->simdclone->simdlen); else { - t = build_vector_type (TREE_TYPE (TREE_TYPE (fndecl)), veclen); + t = build_vector_type (t, veclen); t = build_array_type_nelts (t, node->simdclone->simdlen / veclen); - TREE_TYPE (TREE_TYPE (fndecl)) = t; } + TREE_TYPE (TREE_TYPE (fndecl)) = t; if (!node->definition) return NULL_TREE; @@ -11287,7 +11287,10 @@ simd_clone_adjust_argument_types (struct cgraph_node *node) if (veclen > node->simdclone->simdlen) veclen = node->simdclone->simdlen; adj.arg_prefix = "simd"; - adj.type = build_vector_type (parm_type, veclen); + if (POINTER_TYPE_P (parm_type)) + adj.type = build_vector_type (pointer_sized_int_node, veclen); + else + adj.type = build_vector_type (parm_type, veclen); node->simdclone->args[i].vector_type = adj.type; for (j = veclen; j < node->simdclone->simdlen; j += veclen) { @@ -11328,7 +11331,10 @@ simd_clone_adjust_argument_types (struct cgraph_node *node) veclen /= GET_MODE_BITSIZE (TYPE_MODE (base_type)); if (veclen > node->simdclone->simdlen) veclen = node->simdclone->simdlen; - adj.type = build_vector_type (base_type, veclen); + if (POINTER_TYPE_P (base_type)) + adj.type = build_vector_type (pointer_sized_int_node, veclen); + else + adj.type = build_vector_type (base_type, veclen); adjustments.safe_push (adj); for (j = veclen; j < node->simdclone->simdlen; j += veclen) diff --git a/gcc/ree.c b/gcc/ree.c index 0d5090bc290..a3bd5610592 100644 --- a/gcc/ree.c +++ b/gcc/ree.c @@ -261,6 +261,50 @@ typedef struct ext_cand static int max_insn_uid; +/* Update or remove REG_EQUAL or REG_EQUIV notes for INSN. */ + +static bool +update_reg_equal_equiv_notes (rtx insn, enum machine_mode new_mode, + enum machine_mode old_mode, enum rtx_code code) +{ + rtx *loc = ®_NOTES (insn); + while (*loc) + { + enum reg_note kind = REG_NOTE_KIND (*loc); + if (kind == REG_EQUAL || kind == REG_EQUIV) + { + rtx orig_src = XEXP (*loc, 0); + /* Update equivalency constants. Recall that RTL constants are + sign-extended. */ + if (GET_CODE (orig_src) == CONST_INT + && HOST_BITS_PER_WIDE_INT >= GET_MODE_BITSIZE (new_mode)) + { + if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND) + /* Nothing needed. */; + else + { + /* Zero-extend the negative constant by masking out the + bits outside the source mode. */ + rtx new_const_int + = gen_int_mode (INTVAL (orig_src) + & GET_MODE_MASK (old_mode), + new_mode); + if (!validate_change (insn, &XEXP (*loc, 0), + new_const_int, true)) + return false; + } + loc = &XEXP (*loc, 1); + } + /* Drop all other notes, they assume a wrong mode. */ + else if (!validate_change (insn, loc, XEXP (*loc, 1), true)) + return false; + } + else + loc = &XEXP (*loc, 1); + } + return true; +} + /* Given a insn (CURR_INSN), an extension candidate for removal (CAND) and a pointer to the SET rtx (ORIG_SET) that needs to be modified, this code modifies the SET rtx to a new SET rtx that extends the @@ -282,6 +326,7 @@ static bool combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) { rtx orig_src = SET_SRC (*orig_set); + enum machine_mode orig_mode = GET_MODE (SET_DEST (*orig_set)); rtx new_set; rtx cand_pat = PATTERN (cand->insn); @@ -318,9 +363,8 @@ combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) { /* Zero-extend the negative constant by masking out the bits outside the source mode. */ - enum machine_mode src_mode = GET_MODE (SET_DEST (*orig_set)); rtx new_const_int - = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (src_mode), + = gen_int_mode (INTVAL (orig_src) & GET_MODE_MASK (orig_mode), GET_MODE (new_reg)); new_set = gen_rtx_SET (VOIDmode, new_reg, new_const_int); } @@ -359,7 +403,9 @@ combine_set_extension (ext_cand *cand, rtx curr_insn, rtx *orig_set) /* This change is a part of a group of changes. Hence, validate_change will not try to commit the change. */ - if (validate_change (curr_insn, orig_set, new_set, true)) + if (validate_change (curr_insn, orig_set, new_set, true) + && update_reg_equal_equiv_notes (curr_insn, cand->mode, orig_mode, + cand->code)) { if (dump_file) { @@ -409,7 +455,9 @@ transform_ifelse (ext_cand *cand, rtx def_insn) ifexpr = gen_rtx_IF_THEN_ELSE (cand->mode, cond, map_srcreg, map_srcreg2); new_set = gen_rtx_SET (VOIDmode, map_dstreg, ifexpr); - if (validate_change (def_insn, &PATTERN (def_insn), new_set, true)) + if (validate_change (def_insn, &PATTERN (def_insn), new_set, true) + && update_reg_equal_equiv_notes (def_insn, cand->mode, GET_MODE (dstreg), + cand->code)) { if (dump_file) { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 56693639b4d..9751d346413 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,197 @@ +2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + Backport from mainline + 2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/builtins-1.c: Add tests for vec_ctf, + vec_cts, and vec_ctu. + * gcc.target/powerpc/builtins-2.c: Likewise. + + Backport from mainline + 2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * gcc.target/powerpc/builtins-1.c: Add tests for vec_xl, vec_xst, + vec_round, vec_splat, vec_div, and vec_mul. + * gcc.target/powerpc/builtins-2.c: New test. + + Backport from mainline + 2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com> + + * testsuite/gcc.target/powerpc/builtins-1.c: New test. + +2014-12-10 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/62021 + * gcc.dg/vect/pr62021.c: New test. + +2014-12-09 Uros Bizjak <ubizjak@gmail.com> + + PR bootstrap/64213 + Revert: + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * g++.dg/pr64037.C: New test. + +2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-12-07 Oleg Endo <olegendo@gcc.gnu.org> + + * gcc.target/h8300/h8300.exp: Fix duplicated text. + * gcc.target/h8300/pragma-isr.c: Likewise. + * gcc.target/h8300/pragma-isr2.c: Likewise. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-12-02 H.J. Lu <hongjiu.lu@intel.com> + + PR target/64108 + * gcc.target/i386/memset-strategy-2.c: New test. + +2014-12-05 H.J. Lu <hongjiu.lu@intel.com> + + Backport from mainline + 2014-11-28 H.J. Lu <hongjiu.lu@intel.com> + + PR rtl-optimization/64037 + * g++.dg/pr64037.C: New test. + +2014-12-04 Jakub Jelinek <jakub@redhat.com> + + PR c++/56493 + * c-c++-common/pr56493.c: New test. + +2014-12-03 Renlin Li <Renlin.Li@arm.com> + + Backported from mainline + 2014-12-03 Renlin Li <Renlin.Li@arm.com> + H.J. Lu <hongjiu.lu@intel.com> + + PR middle-end/63762 + PR target/63661 + * gcc.dg/pr63762.c: New test. + * gcc.target/i386/pr63661.c: New test. + +2014-12-01 Martin Jambor <mjambor@suse.cz> + + PR ipa/63551 + * gcc.dg/ipa/pr63551.c: New test. + * gcc.dg/ipa/pr64041.c: Likewise. + +2014-12-01 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63738 + * gcc.dg/torture/pr63738.c: Fix call to setjmp. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-27 Jakub Jelinek <jakub@redhat.com> + + PR middle-end/64067 + * gcc.c-torture/compile/pr64067.c: New test. + + 2014-11-19 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/63915 + * c-c++-common/gomp/pr60823-4.c: New test. + + PR sanitizer/63913 + * g++.dg/ubsan/pr63913.C: New test. + + 2014-10-31 Jakub Jelinek <jakub@redhat.com> + + PR rtl-optimization/63659 + * gcc.c-torture/execute/pr63659.c: New test. + +2014-11-26 Richard Biener <rguenther@suse.de> + + PR middle-end/63738 + * gcc.dg/torture/pr63738.c: New testcase. + +2014-11-26 Richard Biener <rguenther@suse.de> + + Backport from mainline + 2014-11-26 Richard Biener <rguenther@suse.de> + + PR tree-optimization/62238 + * gcc.dg/torture/pr62238.c: New testcase. + + 2014-11-07 Richard Biener <rguenther@suse.de> + + PR tree-optimization/63605 + * gcc.dg/vect/pr63605.c: New testcase. + + 2014-10-28 Richard Biener <rguenther@suse.de> + + PR middle-end/63665 + * gcc.dg/pr63665.c: New testcase. + +2014-11-24 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/opt45.adb: New test. + +2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-22 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/63783 + PR target/51244 + * gcc.target/sh/torture/pr63783-1.c: New. + * gcc.target/sh/torture/pr63783-2.c: New. + * gcc.target/sh/pr51244-20.c: Adjust. + * gcc.target/sh/pr51244-20-sh2a.c: Adjust. + +2014-11-19 Uros Bizjak <ubizjak@gmail.com> + + PR target/63947 + * gcc.target/i386/pr63947.c: New test. + +2014-11-19 Tom de Vries <tom@codesourcery.com> + + Backport from mainline + PR tree-optimization/62167 + * gcc.dg/pr51879-12.c: Add xfails. + * gcc.dg/pr62167-run.c: New test. + * gcc.dg/pr62167.c: New test. + +2014-11-13 Teresa Johnson <tejohnson@google.com> + + PR tree-optimization/63841 + * g++.dg/tree-ssa/pr63841.C: New test. + +2014-11-12 Jakub Jelinek <jakub@redhat.com> + + PR ipa/63838 + * g++.dg/ipa/pr63838.C: New test. + +2014-11-11 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/63265 + * g++.dg/cpp0x/constexpr-63265.C: New. + +2014-11-09 H.J. Lu <hongjiu.lu@intel.com> + + Backported from mainline + 2014-11-09 H.J. Lu <hongjiu.lu@intel.com> + + PR testsuite/63305 + * gcc.target/i386/avx256-unaligned-load-7.c (avx_test): Fix + buffer overflow. + * gcc.target/i386/avx256-unaligned-store-7.c (avx_test): Likewise. + +2014-11-07 Marek Polacek <polacek@redhat.com> + + * c-c++-common/ubsan/undefined-2.c: New test. + +2014-11-05 Uros Bizjak <ubizjak@gmail.com> + + PR target/63538 + * gcc.target/i386/pr63538.c: New test. + 2014-11-03 Marek Polacek <polacek@redhat.com> PR c/52769 diff --git a/gcc/testsuite/ChangeLog.ibm b/gcc/testsuite/ChangeLog.ibm index 967bce96b3d..ac55e48e3d2 100644 --- a/gcc/testsuite/ChangeLog.ibm +++ b/gcc/testsuite/ChangeLog.ibm @@ -1,3 +1,7 @@ +2014-12-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + Merge up to 218639. + 2014-09-10 Michael Meissner <meissner@linux.vnet.ibm.com> Merge up to 215140. diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner index acf3b57e1d0..614b8976196 100644 --- a/gcc/testsuite/ChangeLog.meissner +++ b/gcc/testsuite/ChangeLog.meissner @@ -1,3 +1,7 @@ +2014-12-11 Michael Meissner <meissner@linux.vnet.ibm.com> + + Merge up to ibm/gcc-4_9-branch, subversion id 218646. + 2014-12-02 Michael Meissner <meissner@linux.vnet.ibm.com> Clone branch from at 8.0 branch, subversion id 218285 (FSF diff --git a/gcc/testsuite/c-c++-common/gomp/pr60823-4.c b/gcc/testsuite/c-c++-common/gomp/pr60823-4.c new file mode 100644 index 00000000000..a9bc0fa2591 --- /dev/null +++ b/gcc/testsuite/c-c++-common/gomp/pr60823-4.c @@ -0,0 +1,7 @@ +/* PR tree-optimization/63915 */ +/* { dg-do run } */ +/* { dg-require-effective-target vect_simd_clones } */ +/* { dg-options "-O2 -fopenmp-simd" } */ +/* { dg-additional-options "-fpic" { target fpic } } */ + +#include "pr60823-2.c" diff --git a/gcc/testsuite/c-c++-common/pr56493.c b/gcc/testsuite/c-c++-common/pr56493.c new file mode 100644 index 00000000000..4181260430f --- /dev/null +++ b/gcc/testsuite/c-c++-common/pr56493.c @@ -0,0 +1,16 @@ +/* PR c++/56493 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-tree-gimple" } */ + +unsigned long long bar (void); +int x; + +void +foo (void) +{ + x += bar (); +} + +/* Verify we narrow the addition from unsigned long long to unsigned int type. */ +/* { dg-final { scan-tree-dump " (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* (\[a-zA-Z._0-9]*) = \\(unsigned int\\) \[^;\n\r]*;.* = \\1 \\+ \\2;" "gimple" { target { ilp32 || lp64 } } } } */ +/* { dg-final { cleanup-tree-dump "gimple" } } */ diff --git a/gcc/testsuite/c-c++-common/ubsan/undefined-2.c b/gcc/testsuite/c-c++-common/ubsan/undefined-2.c new file mode 100644 index 00000000000..fd5b4d3e9e0 --- /dev/null +++ b/gcc/testsuite/c-c++-common/ubsan/undefined-2.c @@ -0,0 +1,26 @@ +/* { dg-do run } */ +/* { dg-options "-fsanitize=undefined" } */ +/* { dg-additional-options "-std=gnu11" { target c } } */ +/* { dg-additional-options "-std=c++11" { target c++ } } */ + +#include <stdio.h> + +volatile int w, z; + +__attribute__ ((noinline, noclone)) int +foo (int x, int y) +{ + z++; + return x << y; +} + +int +main () +{ + fputs ("1st\n", stderr); + w = foo (0, -__INT_MAX__); + return 0; +} + +/* { dg-output "1st(\n|\r\n|\r)" } */ +/* { dg-output "\[^\n\r]*shift exponent -\[^\n\r]* is negative\[^\n\r]*(\n|\r\n|\r)" } */ diff --git a/gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C b/gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C new file mode 100644 index 00000000000..bd20b54f142 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/alias-decl-44.C @@ -0,0 +1,43 @@ +// PR c++/63849 +// { dg-do compile { target c++11 } } + +template <class _T, class...> +using First = _T; // we should not use this + // alias with only + // one pack parameter (?) + +template <template <class...> class _Successor, + int, + class... _Xs> +struct Overlay +{ + using O = _Successor<_Xs...>; +}; + +template <class... _Pack> +struct List +{ + template <int _s> + using O = typename Overlay<List, _s, _Pack...>::O; + + template <template <class...> class _S> + using Pass = _S<_Pack...>; + + template <int _i> + using At = typename O<_i> + ::template Pass<First>; +}; + +template <int _i> +using At = typename List<int, char> +::template At<_i>; + +template <int _i> +void func_crash(At<_i>&) {} + +int main(int argc, char *argv[]) +{ + char ccc; + int iii; + func_crash<0>(iii); +} diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C new file mode 100644 index 00000000000..aa0ce5e7ce2 --- /dev/null +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-63265.C @@ -0,0 +1,19 @@ +// PR c++/63265 +// { dg-do compile { target c++11 } } + +#define LSHIFT (sizeof(unsigned int) * __CHAR_BIT__) + +template <int lshift> +struct SpuriouslyWarns1 { + static constexpr unsigned int v = lshift < LSHIFT ? 1U << lshift : 0; +}; + +static_assert(SpuriouslyWarns1<LSHIFT>::v == 0, "Impossible occurred"); + +template <int lshift> +struct SpuriouslyWarns2 { + static constexpr bool okay = lshift < LSHIFT; + static constexpr unsigned int v = okay ? 1U << lshift : 0; +}; + +static_assert(SpuriouslyWarns2<LSHIFT>::v == 0, "Impossible occurred"); diff --git a/gcc/testsuite/g++.dg/ipa/pr63838.C b/gcc/testsuite/g++.dg/ipa/pr63838.C new file mode 100644 index 00000000000..d6736490080 --- /dev/null +++ b/gcc/testsuite/g++.dg/ipa/pr63838.C @@ -0,0 +1,56 @@ +// PR ipa/63838 +// { dg-do run } +// { dg-options "-O2 -fdump-ipa-pure-const" } +// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void foo" "pure-const" } } +// { dg-final { scan-ipa-dump-not "Function found to be nothrow: void bar" "pure-const" } } +// { dg-final { cleanup-ipa-dump "pure-const" } } + +__attribute__((noinline, noclone)) static void bar (int); +volatile int v; +void (*fn) (); +struct S { S () { v++; } ~S () { v++; } }; + +__attribute__((noinline, noclone)) static void +foo (int x) +{ + v++; + if (x == 5) + bar (x); +} + +__attribute__((noinline, noclone)) static void +bar (int x) +{ + v++; + if (x == 6) + foo (x); + else if (x == 5) + fn (); +} + +__attribute__((noinline, noclone)) int +baz (int x) +{ + S s; + foo (x); +} + +void +throw0 () +{ + throw 0; +} + +int +main () +{ + fn = throw0; + asm volatile ("" : : : "memory"); + try + { + baz (5); + } + catch (int) + { + } +} diff --git a/gcc/testsuite/g++.dg/tree-ssa/pr63841.C b/gcc/testsuite/g++.dg/tree-ssa/pr63841.C new file mode 100644 index 00000000000..2a2c78f9fb2 --- /dev/null +++ b/gcc/testsuite/g++.dg/tree-ssa/pr63841.C @@ -0,0 +1,35 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +#include <string> + +std::string __attribute__ ((noinline)) comp_test_write() { + std::string data; + + for (int i = 0; i < 2; ++i) { + char b = 1 >> (i * 8); + data.append(&b, 1); + } + + return data; +} + +std::string __attribute__ ((noinline)) comp_test_write_good() { + std::string data; + + char b; + for (int i = 0; i < 2; ++i) { + b = 1 >> (i * 8); + data.append(&b, 1); + } + + return data; +} + +int main() { + std::string good = comp_test_write_good(); + std::string bad = comp_test_write(); + + if (good != bad) + __builtin_abort (); +} diff --git a/gcc/testsuite/g++.dg/ubsan/pr63913.C b/gcc/testsuite/g++.dg/ubsan/pr63913.C new file mode 100644 index 00000000000..34dceb4d844 --- /dev/null +++ b/gcc/testsuite/g++.dg/ubsan/pr63913.C @@ -0,0 +1,12 @@ +// PR sanitizer/63913 +// { dg-do compile } +// { dg-options "-fsanitize=bool -fnon-call-exceptions" } + +struct B { B (); ~B (); }; + +double +foo (bool *x) +{ + B b; + return *x; +} diff --git a/gcc/testsuite/gcc.c-torture/compile/pr64067.c b/gcc/testsuite/gcc.c-torture/compile/pr64067.c new file mode 100644 index 00000000000..24ad996efdb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr64067.c @@ -0,0 +1,10 @@ +/* PR middle-end/64067 */ + +struct S { int s; }; +int *const v[1] = { &((struct S) { .s = 42 }).s }; + +int * +foo (void) +{ + return v[0]; +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr63659.c b/gcc/testsuite/gcc.c-torture/execute/pr63659.c new file mode 100644 index 00000000000..780dc8a7e21 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr63659.c @@ -0,0 +1,29 @@ +/* PR rtl-optimization/63659 */ + +int a, b, c, *d = &b, g, h, i; +unsigned char e; +char f; + +int +main () +{ + while (a) + { + for (a = 0; a; a++) + for (; c; c++) + ; + if (i) + break; + } + + char j = c, k = -1, l; + l = g = j >> h; + f = l == 0 ? k : k % l; + e = 0 ? 0 : f; + *d = e; + + if (b != 255) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/ipa/pr63551.c b/gcc/testsuite/gcc.dg/ipa/pr63551.c new file mode 100644 index 00000000000..676c2c2c3d3 --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/pr63551.c @@ -0,0 +1,33 @@ +/* { dg-do run } */ +/* { dg-options "-Os" } */ + +union U +{ + unsigned int f0; + int f1; +}; + +int a, d; + +void +fn1 (union U p) +{ + if (p.f1 <= 0) + if (a) + d = 0; +} + +void +fn2 () +{ + d = 0; + union U b = { 4294967286 }; + fn1 (b); +} + +int +main () +{ + fn2 (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/ipa/pr64041.c b/gcc/testsuite/gcc.dg/ipa/pr64041.c new file mode 100644 index 00000000000..4877b4b68a9 --- /dev/null +++ b/gcc/testsuite/gcc.dg/ipa/pr64041.c @@ -0,0 +1,64 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +int printf (const char *, ...); + +int a, b = 1, d; + +union U1 +{ + unsigned int f0; + int f1; +}; + +union U2 +{ + int f2; + int f3; +} c; + +int +fn1 (int p) +{ + int t = p && a || p && a && p; + return t ? t : a; +} + +unsigned +fn2 (union U1 p1, union U2 p2) +{ + if (p1.f1 <= 0) + { + for (; p2.f2;) + c.f2 = 0; + p2.f2 = fn1 (d); + } + return p2.f3; +} + +int g = 0; + +int +foo () +{ + if (b) + { + union U1 f = { 0xFFFFFFFFU }; + + fn2 (f, c); + } + g = 1; + return 0; +} + + +int +main () +{ + foo (); + + if (g == 0) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr51879-12.c b/gcc/testsuite/gcc.dg/pr51879-12.c index 1b25e296fbf..7490e33f055 100644 --- a/gcc/testsuite/gcc.dg/pr51879-12.c +++ b/gcc/testsuite/gcc.dg/pr51879-12.c @@ -24,6 +24,6 @@ foo (int y) baz (a); } -/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre"} } */ -/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre"} } */ +/* { dg-final { scan-tree-dump-times "bar \\(" 1 "pre" { xfail *-*-* } } } */ +/* { dg-final { scan-tree-dump-times "bar2 \\(" 1 "pre" { xfail *-*-* } } } */ /* { dg-final { cleanup-tree-dump "pre" } } */ diff --git a/gcc/testsuite/gcc.dg/pr62167-run.c b/gcc/testsuite/gcc.dg/pr62167-run.c new file mode 100644 index 00000000000..37214a3ecee --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62167-run.c @@ -0,0 +1,47 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -ftree-tail-merge" } */ + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +int +main () +{ + struct node *p; + + node.next = (void*)0; + + node.prev = (void *)head; + + head->first = &node; + + struct node *n = head->first; + + struct head *h = &heads[k]; + + heads[2].first = n->next; + + if ((void*)n->prev == (void *)h) + p = h->first; + else + /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */ + p = n->prev->next; + + return !(p == (void*)0); +} diff --git a/gcc/testsuite/gcc.dg/pr62167.c b/gcc/testsuite/gcc.dg/pr62167.c new file mode 100644 index 00000000000..f8c31a0792f --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr62167.c @@ -0,0 +1,50 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-tail-merge -fdump-tree-pre" } */ + +struct node +{ + struct node *next; + struct node *prev; +}; + +struct node node; + +struct head +{ + struct node *first; +}; + +struct head heads[5]; + +int k = 2; + +struct head *head = &heads[2]; + +int +main () +{ + struct node *p; + + node.next = (void*)0; + + node.prev = (void *)head; + + head->first = &node; + + struct node *n = head->first; + + struct head *h = &heads[k]; + + heads[2].first = n->next; + + if ((void*)n->prev == (void *)h) + p = h->first; + else + /* Dead tbaa-unsafe load from ((struct node *)&heads[2])->next. */ + p = n->prev->next; + + return !(p == (void*)0); +} + +/* { dg-final { scan-tree-dump-not "Removing basic block" "pre"} } */ +/* { dg-final { cleanup-tree-dump "pre" } } */ diff --git a/gcc/testsuite/gcc.dg/pr63665.c b/gcc/testsuite/gcc.dg/pr63665.c new file mode 100644 index 00000000000..046ecae7c1d --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63665.c @@ -0,0 +1,18 @@ +/* { dg-do run } */ +/* { dg-require-effective-target int32plus } */ +/* { dg-options "-O -fno-tree-ccp -fno-tree-fre -fno-tree-copy-prop -fwrapv" } */ + +static inline int +test5 (int x) +{ + int y = 0x80000000; + return x + y; +} + +int +main () +{ + if (test5 (0x80000000) != 0) + __builtin_abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr63762.c b/gcc/testsuite/gcc.dg/pr63762.c new file mode 100644 index 00000000000..df110676eca --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr63762.c @@ -0,0 +1,77 @@ +/* PR middle-end/63762 */ +/* { dg-do assemble } */ +/* { dg-options "-O2" } */ + +#include <stdlib.h> + +void *astFree (); +void *astMalloc (); +void astNegate (void *); +int astGetNegated (void *); +void astGetRegionBounds (void *, double *, double *); +int astResampleF (void *, ...); + +extern int astOK; + +int +MaskF (int inside, int ndim, const int lbnd[], const int ubnd[], + float in[], float val) +{ + + void *used_region; + float *c, *d, *out, *tmp_out; + double *lbndgd, *ubndgd; + int *lbndg, *ubndg, idim, ipix, nax, nin, nout, npix, npixg, result = 0; + if (!astOK) return result; + lbndg = astMalloc (sizeof (int)*(size_t) ndim); + ubndg = astMalloc (sizeof (int)*(size_t) ndim); + lbndgd = astMalloc (sizeof (double)*(size_t) ndim); + ubndgd = astMalloc (sizeof (double)*(size_t) ndim); + if (astOK) + { + astGetRegionBounds (used_region, lbndgd, ubndgd); + npix = 1; + npixg = 1; + for (idim = 0; idim < ndim; idim++) + { + lbndg[ idim ] = lbnd[ idim ]; + ubndg[ idim ] = ubnd[ idim ]; + npix *= (ubnd[ idim ] - lbnd[ idim ] + 1); + if (npixg >= 0) npixg *= (ubndg[ idim ] - lbndg[ idim ] + 1); + } + if (npixg <= 0 && astOK) + { + if ((inside != 0) == (astGetNegated( used_region ) != 0)) + { + c = in; + for (ipix = 0; ipix < npix; ipix++) *(c++) = val; + result = npix; + } + } + else if (npixg > 0 && astOK) + { + if ((inside != 0) == (astGetNegated (used_region) != 0)) + { + tmp_out = astMalloc (sizeof (float)*(size_t) npix); + if (tmp_out) + { + c = tmp_out; + for (ipix = 0; ipix < npix; ipix++) *(c++) = val; + result = npix - npixg; + } + out = tmp_out; + } + else + { + tmp_out = NULL; + out = in; + } + if (inside) astNegate (used_region); + result += astResampleF (used_region, ndim, lbnd, ubnd, in, NULL, + NULL, NULL, 0, 0.0, 100, val, ndim, + lbnd, ubnd, lbndg, ubndg, out, NULL); + if (inside) astNegate (used_region); + } + } + return result; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr62238.c b/gcc/testsuite/gcc.dg/torture/pr62238.c new file mode 100644 index 00000000000..de8951aae90 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr62238.c @@ -0,0 +1,30 @@ +/* { dg-do run } */ + +int a[4], b, c, d; + +int +fn1 (int p) +{ + for (; d; d++) + { + unsigned int h; + for (h = 0; h < 3; h++) + { + if (a[c+c+h]) + { + if (p) + break; + return 0; + } + b = 0; + } + } + return 0; +} + +int +main () +{ + fn1 (0); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/torture/pr63738.c b/gcc/testsuite/gcc.dg/torture/pr63738.c new file mode 100644 index 00000000000..06ede546192 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr63738.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ + +#include <setjmp.h> + +struct longjmp_buffer { + jmp_buf buf; +}; + +void plouf(); + +extern long interprete() +{ + long * sp; + int i; + long *args; + int n; + + struct longjmp_buffer raise_buf; + setjmp (raise_buf.buf); + + plouf(); + sp -= 4; + for (i = 0; i < n; i++) + args[i] = sp[10-i]; + plouf(); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/vect/pr62021.c b/gcc/testsuite/gcc.dg/vect/pr62021.c new file mode 100644 index 00000000000..e0208e63b36 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr62021.c @@ -0,0 +1,30 @@ +/* { dg-require-effective-target vect_simd_clones } */ +/* { dg-additional-options "-fopenmp-simd" } */ +/* { dg-additional-options "-mavx" { target avx_runtime } } */ + +#pragma omp declare simd linear(y) +__attribute__((noinline)) int * +foo (int *x, int y) +{ + return x + y; +} + +int a[1024]; +int *b[1024] = { &a[0] }; + +int +main () +{ + int i; + for (i = 0; i < 1024; i++) + b[i] = &a[1023 - i]; + #pragma omp simd + for (i = 0; i < 1024; i++) + b[i] = foo (b[i], i); + for (i = 0; i < 1024; i++) + if (b[i] != &a[1023]) + __builtin_abort (); + return 0; +} + +/* { dg-final { cleanup-tree-dump "vect" } } */ diff --git a/gcc/testsuite/gcc.dg/vect/pr63605.c b/gcc/testsuite/gcc.dg/vect/pr63605.c new file mode 100644 index 00000000000..5096c7239d8 --- /dev/null +++ b/gcc/testsuite/gcc.dg/vect/pr63605.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ + +#include "tree-vect.h" + +extern void abort (void); + +int a, b[8] = { 2, 0, 0, 0, 0, 0, 0, 0 }, c[8]; + +int +main () +{ + int d; + check_vect (); + for (; a < 8; a++) + { + d = b[a] >> 1; + c[a] = d != 0; + } + if (c[0] != 1) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/h8300/h8300.exp b/gcc/testsuite/gcc.target/h8300/h8300.exp index 8523a128572..63579f60367 100644 --- a/gcc/testsuite/gcc.target/h8300/h8300.exp +++ b/gcc/testsuite/gcc.target/h8300/h8300.exp @@ -39,44 +39,3 @@ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ # All done. dg-finish -# Copyright (C) 2013-2014 Free Software Foundation, Inc. - -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with GCC; see the file COPYING3. If not see -# <http://www.gnu.org/licenses/>. - -# GCC testsuite that uses the `dg.exp' driver. - -# Exit immediately if this isn't a h8300 target. -if ![istarget h8300*-*-*] then { - return -} - -# Load support procs. -load_lib gcc-dg.exp - -# If a testcase doesn't have special options, use these. -global DEFAULT_CFLAGS -if ![info exists DEFAULT_CFLAGS] then { - set DEFAULT_CFLAGS " -ansi -pedantic-errors" -} - -# Initialize `dg'. -dg-init - -# Main loop. -dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ - "" $DEFAULT_CFLAGS - -# All done. -dg-finish diff --git a/gcc/testsuite/gcc.target/h8300/pragma-isr.c b/gcc/testsuite/gcc.target/h8300/pragma-isr.c index 24fba30d8b7..41bd78ea607 100644 --- a/gcc/testsuite/gcc.target/h8300/pragma-isr.c +++ b/gcc/testsuite/gcc.target/h8300/pragma-isr.c @@ -18,23 +18,3 @@ isr2 (void) { foo (); } -/* Check whether rte is generated for two ISRs. */ -/* { dg-do compile { target h8300-*-* } } */ -/* { dg-options "-O3" } */ -/* { dg-final { scan-assembler-times "rte" 2} } */ - -extern void foo (void); - -#pragma interrupt -void -isr1 (void) -{ - foo (); -} - -#pragma interrupt -void -isr2 (void) -{ - foo (); -} diff --git a/gcc/testsuite/gcc.target/h8300/pragma-isr2.c b/gcc/testsuite/gcc.target/h8300/pragma-isr2.c index 7c242ec3112..3d0a126b908 100644 --- a/gcc/testsuite/gcc.target/h8300/pragma-isr2.c +++ b/gcc/testsuite/gcc.target/h8300/pragma-isr2.c @@ -19,24 +19,3 @@ main (void) { return 0; } -/* Check whether rte is generated only for an ISR. */ -/* { dg-do compile { target h8300-*-* } } */ -/* { dg-options "-O" } */ -/* { dg-final { scan-assembler-times "rte" 1 } } */ - -#pragma interrupt -void -isr (void) -{ -} - -void -delay (int a) -{ -} - -int -main (void) -{ - return 0; -} diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c index ad16a5329bf..d8730dc093d 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-7.c @@ -33,7 +33,7 @@ avx_test (void) cp = mp; dp = lp; - for (i = N; i >= 0; i--) + for (i = N; i > 0; i--) { *cp++ = str; *dp++ = str; @@ -44,13 +44,13 @@ avx_test (void) cp = mp; dp = lp; - for (i = N; i >= 0; i--) + for (i = N; i > 0; i--) { *ap++ = *cp++; *bp++ = *dp++; } - for (i = N; i >= 0; i--) + for (i = N; i > 0; i--) { if (strcmp (*--ap, "STR") != 0) abort (); diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c index 4272dc3cd0d..5ec14947f48 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-7.c @@ -29,13 +29,13 @@ avx_test (void) ap = ep; bp = fp; - for (i = N; i >= 0; i--) + for (i = N; i > 0; i--) { *ap++ = str; *bp++ = str; } - for (i = N; i >= 0; i--) + for (i = N; i > 0; i--) { if (strcmp (*--ap, "STR") != 0) abort (); diff --git a/gcc/testsuite/gcc.target/i386/memset-strategy-2.c b/gcc/testsuite/gcc.target/i386/memset-strategy-2.c new file mode 100644 index 00000000000..aafa54d004f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/memset-strategy-2.c @@ -0,0 +1,10 @@ +/* PR target/64108 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=atom -mmemset-strategy=libcall:-1:align -minline-all-stringops" } */ + +char a[2048]; +void t (void) +{ + __builtin_memset (a, 1, 2048); +} + diff --git a/gcc/testsuite/gcc.target/i386/pr63538.c b/gcc/testsuite/gcc.target/i386/pr63538.c new file mode 100644 index 00000000000..7b979c35d81 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63538.c @@ -0,0 +1,13 @@ +/* PR target/63538 */ +/* { dg-do compile } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcmodel=medium -mlarge-data-threshold=0" } */ + +static char *str = "Hello World"; + +char *foo () +{ + return str; +} + +/* { dg-final { scan-assembler "movabs" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr63661.c b/gcc/testsuite/gcc.target/i386/pr63661.c new file mode 100644 index 00000000000..a5ffd2f4f57 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63661.c @@ -0,0 +1,80 @@ +/* PR target/63661 */ +/* { dg-do run } */ +/* { dg-require-effective-target fpic } */ +/* { dg-options "-mtune=nehalem -fPIC -O2" } */ + +static void __attribute__((noinline,noclone,hot)) +foo (double a, double q, double *ff, double *gx, int e, int ni) +{ + union + { + double n; + unsigned long long o; + } punner; + double d; + + punner.n = q; + __builtin_printf("B: 0x%016llx ---- %g\n", punner.o, q); + + d = q - 5; + if(d < 0) + d = -d; + if (d > 0.1) + __builtin_abort(); +} + +static int __attribute__((noinline,noclone,hot)) +bar (int order, double q, double c[]) +{ + int ni, nn, i, e; + double g2, x2, de, s, ratio, ff; + + nn = 0; + e = order & 1; + s = 0; + ratio = 0; + x2 = 0; + g2 = 0; + + if(q == 0.0) + return 0; + + if (order < 5) + { + ratio = 1.0 / q; + nn = order; + } + + ni = -nn; + + while(1) + { + de = ratio - g2 - x2; + + foo (0, q, &ff, &g2, e, ni); + + if((int)de == 0) + break; + } + + s += 2 * nn * c[nn]; + + for (i = 0; i < 1; i++) + { + c[0] = nn; + for (; i < 10; i++) + c[i] = 0.0; + c[0] /= s; + } + + return 0; +} + +int +main () +{ + double c[1000]; + + bar (1, 5.0, c); + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr63947.c b/gcc/testsuite/gcc.target/i386/pr63947.c new file mode 100644 index 00000000000..3c0a67a73ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr63947.c @@ -0,0 +1,9 @@ +/* PR target/63947 */ +/* { dg-do assemble } */ +/* { dg-options "-Os" } */ +/* { dg-additional-options "-march=i686" { target ia32 } } */ + +long double foo (unsigned a, unsigned b) +{ + return a + b < a; +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c new file mode 100644 index 00000000000..3da714698d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c @@ -0,0 +1,166 @@ +/* { dg-do compile { target { powerpc64le-*-* } } } */ +/* { dg-options "-mcpu=power8 -O0" } */ + +/* Test that a number of newly added builtin overloads are accepted + by the compiler. */ + +#include <altivec.h> + +vector double y = { 2.0, 4.0 }; +vector double z; + +int main () +{ + vector float fa = {1.0, 2.0, 3.0, -4.0}; + vector float fb = {-2.0, -3.0, -4.0, -5.0}; + vector float fc = vec_cpsgn (fa, fb); + + vector long long la = {5L, 14L}; + vector long long lb = {3L, 86L}; + vector long long lc = vec_and (la, lb); + vector bool long long ld = {0, -1}; + vector long long le = vec_and (la, ld); + vector long long lf = vec_and (ld, lb); + + vector unsigned long long ua = {5L, 14L}; + vector unsigned long long ub = {3L, 86L}; + vector unsigned long long uc = vec_and (ua, ub); + vector bool long long ud = {0, -1}; + vector unsigned long long ue = vec_and (ua, ud); + vector unsigned long long uf = vec_and (ud, ub); + + vector long long lg = vec_andc (la, lb); + vector long long lh = vec_andc (la, ld); + vector long long li = vec_andc (ld, lb); + + vector unsigned long long ug = vec_andc (ua, ub); + vector unsigned long long uh = vec_andc (ua, ud); + vector unsigned long long ui = vec_andc (ud, ub); + + vector double da = {1.0, -4.0}; + vector double db = {-2.0, 5.0}; + vector double dc = vec_cpsgn (da, db); + + vector long long lj = vec_mergeh (la, lb); + vector long long lk = vec_mergeh (la, ld); + vector long long ll = vec_mergeh (ld, la); + + vector unsigned long long uj = vec_mergeh (ua, ub); + vector unsigned long long uk = vec_mergeh (ua, ud); + vector unsigned long long ul = vec_mergeh (ud, ua); + + vector long long lm = vec_mergel (la, lb); + vector long long ln = vec_mergel (la, ld); + vector long long lo = vec_mergel (ld, la); + + vector unsigned long long um = vec_mergel (ua, ub); + vector unsigned long long un = vec_mergel (ua, ud); + vector unsigned long long uo = vec_mergel (ud, ua); + + vector long long lp = vec_nor (la, lb); + vector long long lq = vec_nor (la, ld); + vector long long lr = vec_nor (ld, la); + + vector unsigned long long up = vec_nor (ua, ub); + vector unsigned long long uq = vec_nor (ua, ud); + vector unsigned long long ur = vec_nor (ud, ua); + + vector long long ls = vec_or (la, lb); + vector long long lt = vec_or (la, ld); + vector long long lu = vec_or (ld, la); + + vector unsigned long long us = vec_or (ua, ub); + vector unsigned long long ut = vec_or (ua, ud); + vector unsigned long long uu = vec_or (ud, ua); + + vector unsigned char ca = {0,4,8,1,5,9,2,6,10,3,7,11,15,12,14,13}; + vector long long lv = vec_perm (la, lb, ca); + vector unsigned long long uv = vec_perm (ua, ub, ca); + + vector long long lw = vec_sel (la, lb, lc); + vector long long lx = vec_sel (la, lb, uc); + vector long long ly = vec_sel (la, lb, ld); + + vector unsigned long long uw = vec_sel (ua, ub, lc); + vector unsigned long long ux = vec_sel (ua, ub, uc); + vector unsigned long long uy = vec_sel (ua, ub, ld); + + vector long long lz = vec_xor (la, lb); + vector long long l0 = vec_xor (la, ld); + vector long long l1 = vec_xor (ld, la); + + vector unsigned long long uz = vec_xor (ua, ub); + vector unsigned long long u0 = vec_xor (ua, ud); + vector unsigned long long u1 = vec_xor (ud, ua); + + int ia = vec_all_eq (ua, ub); + int ib = vec_all_ge (ua, ub); + int ic = vec_all_gt (ua, ub); + int id = vec_all_le (ua, ub); + int ie = vec_all_lt (ua, ub); + int ig = vec_all_ne (ua, ub); + + int ih = vec_any_eq (ua, ub); + int ii = vec_any_ge (ua, ub); + int ij = vec_any_gt (ua, ub); + int ik = vec_any_le (ua, ub); + int il = vec_any_lt (ua, ub); + int im = vec_any_ne (ua, ub); + + vector int sia = {9, 16, 25, 36}; + vector int sib = {-8, -27, -64, -125}; + vector int sic = vec_mergee (sia, sib); + vector int sid = vec_mergeo (sia, sib); + + vector unsigned int uia = {9, 16, 25, 36}; + vector unsigned int uib = {8, 27, 64, 125}; + vector unsigned int uic = vec_mergee (uia, uib); + vector unsigned int uid = vec_mergeo (uia, uib); + + vector bool int bia = {0, -1, -1, 0}; + vector bool int bib = {-1, -1, 0, -1}; + vector bool int bic = vec_mergee (bia, bib); + vector bool int bid = vec_mergeo (bia, bib); + + vector unsigned int uie = vec_packsu (ua, ub); + + vector long long l2 = vec_cntlz (la); + vector unsigned long long u2 = vec_cntlz (ua); + vector int sie = vec_cntlz (sia); + vector unsigned int uif = vec_cntlz (uia); + vector short ssa = {20, -40, -60, 80, 100, -120, -140, 160}; + vector short ssb = vec_cntlz (ssa); + vector unsigned short usa = {81, 72, 63, 54, 45, 36, 27, 18}; + vector unsigned short usb = vec_cntlz (usa); + vector signed char sca = {-4, 3, -9, 15, -31, 31, 0, 0, + 1, 117, -36, 99, 98, 97, 96, 95}; + vector signed char scb = vec_cntlz (sca); + vector unsigned char cb = vec_cntlz (ca); + + vector double dd = vec_xl (0, &y); + vec_xst (dd, 0, &z); + + vector double de = vec_round (dd); + + vector double df = vec_splat (de, 0); + vector double dg = vec_splat (de, 1); + vector long long l3 = vec_splat (l2, 0); + vector long long l4 = vec_splat (l2, 1); + vector unsigned long long u3 = vec_splat (u2, 0); + vector unsigned long long u4 = vec_splat (u2, 1); + vector bool long long l5 = vec_splat (ld, 0); + vector bool long long l6 = vec_splat (ld, 1); + + vector long long l7 = vec_div (l3, l4); + vector unsigned long long u5 = vec_div (u3, u4); + + vector long long l8 = vec_mul (l3, l4); + vector unsigned long long u6 = vec_mul (u3, u4); + + vector double dh = vec_ctf (la, -2); + vector double di = vec_ctf (ua, 2); + vector long long l9 = vec_cts (dh, -2); + vector unsigned long long u7 = vec_ctu (di, 2); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-2.c b/gcc/testsuite/gcc.target/powerpc/builtins-2.c new file mode 100644 index 00000000000..7f4a3924efd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/builtins-2.c @@ -0,0 +1,47 @@ +/* { dg-do run { target { powerpc64le-*-* } } } */ +/* { dg-options "-mcpu=power8 " } */ + +#include <altivec.h> + +void abort (void); + +int main () +{ + vector long long sa = {27L, -14L}; + vector long long sb = {-9L, -2L}; + + vector unsigned long long ua = {27L, 14L}; + vector unsigned long long ub = {9L, 2L}; + + vector long long sc = vec_div (sa, sb); + vector unsigned long long uc = vec_div (ua, ub); + + if (sc[0] != -3L || sc[1] != 7L || uc[0] != 3L || uc[1] != 7L) + abort (); + + vector long long sd = vec_mul (sa, sb); + vector unsigned long long ud = vec_mul (ua, ub); + + if (sd[0] != -243L || sd[1] != 28L || ud[0] != 243L || ud[1] != 28L) + abort (); + + vector long long se = vec_splat (sa, 0); + vector long long sf = vec_splat (sa, 1); + vector unsigned long long ue = vec_splat (ua, 0); + vector unsigned long long uf = vec_splat (ua, 1); + + if (se[0] != 27L || se[1] != 27L || sf[0] != -14L || sf[1] != -14L + || ue[0] != 27L || ue[1] != 27L || uf[0] != 14L || uf[1] != 14L) + abort (); + + vector double da = vec_ctf (sa, -2); + vector double db = vec_ctf (ua, 2); + vector long long sg = vec_cts (da, -2); + vector unsigned long long ug = vec_ctu (db, 2); + + if (da[0] != 108.0 || da[1] != -56.0 || db[0] != 6.75 || db[1] != 3.5 + || sg[0] != 27L || sg[1] != -14L || ug[0] != 27L || ug[1] != 14L) + abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c b/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c index f2cd2de04f9..3208f932add 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-20-sh2a.c @@ -3,12 +3,12 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ /* { dg-skip-if "" { "sh*-*-*" } { "*" } { "-m2a*" } } */ -/* { dg-final { scan-assembler-times "tst" 5 } } */ -/* { dg-final { scan-assembler-times "movt" 0 } } */ +/* { dg-final { scan-assembler-times "tst" 6 } } */ +/* { dg-final { scan-assembler-times "movt" 1 } } */ /* { dg-final { scan-assembler-times "nott" 1 } } */ /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */ /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */ /* { dg-final { scan-assembler-times "cmp/gt" 3 } } */ -/* { dg-final { scan-assembler-times "not\t" 1 } } */ +/* { dg-final { scan-assembler-not "not\t" } } */ #include "pr51244-20.c" diff --git a/gcc/testsuite/gcc.target/sh/pr51244-20.c b/gcc/testsuite/gcc.target/sh/pr51244-20.c index a9ded463511..aad6a2fd34f 100644 --- a/gcc/testsuite/gcc.target/sh/pr51244-20.c +++ b/gcc/testsuite/gcc.target/sh/pr51244-20.c @@ -1,15 +1,15 @@ /* Check that the SH specific sh_treg_combine RTL optimization pass works as expected. On SH2A the expected insns are slightly different, see - pr51244-21.c. */ + pr51244-20-sh2a.c. */ /* { dg-do compile } */ /* { dg-options "-O2" } */ /* { dg-skip-if "" { "sh*-*-*" } { "-m5*" "-m2a*" } { "" } } */ -/* { dg-final { scan-assembler-times "tst" 6 } } */ -/* { dg-final { scan-assembler-times "movt" 1 } } */ +/* { dg-final { scan-assembler-times "tst" 7 } } */ +/* { dg-final { scan-assembler-times "movt" 2 } } */ /* { dg-final { scan-assembler-times "cmp/eq" 2 } } */ /* { dg-final { scan-assembler-times "cmp/hi" 4 } } */ /* { dg-final { scan-assembler-times "cmp/gt" 2 } } */ -/* { dg-final { scan-assembler-times "not\t" 1 } } */ +/* { dg-final { scan-assembler-not "not\t" } } */ /* non-SH2A: 2x tst, 1x movt, 2x cmp/eq, 1x cmp/hi @@ -81,7 +81,7 @@ get_request_2 (int* q, int rw) } -/* 2x tst, 1x cmp/hi, 1x not */ +/* 3x tst, 1x movt, 1x cmp/hi, 1x not */ static inline int blk_oversized_queue_5 (int* q) { diff --git a/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c b/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c new file mode 100644 index 00000000000..f18beadd9c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/torture/pr63783-1.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include <assert.h> + +int decision_result; +int val; +int truecount = 0; + +static void __attribute__((noinline)) +buggy (int flag) +{ + int condition; + if(flag == 0) + condition = val != 0; + else + condition = !decision_result; + if (condition) + truecount++; +} + +int +main (void) +{ + decision_result = 1; + buggy(1); + assert (truecount == 0); + return 0; +} diff --git a/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c b/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c new file mode 100644 index 00000000000..c0bc9116c23 --- /dev/null +++ b/gcc/testsuite/gcc.target/sh/torture/pr63783-2.c @@ -0,0 +1,29 @@ +/* { dg-do run } */ +/* { dg-additional-options "-std=c99" } */ + +#include <assert.h> + +long long decision_result; +long long val; +int truecount = 0; + +static void __attribute__((noinline)) +buggy (int flag) +{ + int condition; + if(flag == 0) + condition = val != 0; + else + condition = !decision_result; + if (condition) + truecount++; +} + +int +main (void) +{ + decision_result = 1; + buggy(1); + assert (truecount == 0); + return 0; +} diff --git a/gcc/testsuite/gnat.dg/opt45.adb b/gcc/testsuite/gnat.dg/opt45.adb new file mode 100644 index 00000000000..f75e46ed42d --- /dev/null +++ b/gcc/testsuite/gnat.dg/opt45.adb @@ -0,0 +1,38 @@ +-- { dg-do compile }
+-- { dg-options "-O3" }
+
+procedure Opt45 is
+
+ type Index_T is mod 2 ** 32;
+ for Index_T'Size use 32;
+ for Index_T'Alignment use 1;
+
+ type Array_T is array (Index_T range <>) of Natural;
+ type Array_Ptr_T is access all Array_T;
+
+ My_Array_1 : aliased Array_T := (1, 2);
+ My_Array_2 : aliased Array_T := (3, 4);
+
+ Array_Ptr : Array_Ptr_T := null;
+ Index : Index_T := Index_T'First;
+
+ My_Value : Natural := Natural'First;
+
+ procedure Proc (Selection : Positive) is
+ begin
+ if Selection = 1 then
+ Array_Ptr := My_Array_1'Access;
+ Index := My_Array_1'First;
+ else
+ Array_Ptr := My_Array_2'Access;
+ Index := My_Array_2'First;
+ end if;
+
+ if My_Value = Natural'First then
+ My_Value := Array_Ptr.all (Index);
+ end if;
+ end;
+
+begin
+ Proc (2);
+end;
diff --git a/gcc/tree-data-ref.c b/gcc/tree-data-ref.c index a15494a89bf..64ac4e99a61 100644 --- a/gcc/tree-data-ref.c +++ b/gcc/tree-data-ref.c @@ -663,6 +663,9 @@ split_constant_offset_1 (tree type, tree op0, enum tree_code code, tree op1, case SSA_NAME: { + if (SSA_NAME_OCCURS_IN_ABNORMAL_PHI (op0)) + return false; + gimple def_stmt = SSA_NAME_DEF_STMT (op0); enum tree_code subcode; diff --git a/gcc/tree-predcom.c b/gcc/tree-predcom.c index 730bad46aa4..20b0e3b0ab8 100644 --- a/gcc/tree-predcom.c +++ b/gcc/tree-predcom.c @@ -1391,8 +1391,8 @@ ref_at_iteration (data_reference_p dr, int iter, gimple_seq *stmts) off = size_binop (PLUS_EXPR, off, size_binop (MULT_EXPR, DR_STEP (dr), ssize_int (iter))); tree addr = fold_build_pointer_plus (DR_BASE_ADDRESS (dr), off); - addr = force_gimple_operand_1 (addr, stmts, is_gimple_mem_ref_addr, - NULL_TREE); + addr = force_gimple_operand_1 (unshare_expr (addr), stmts, + is_gimple_mem_ref_addr, NULL_TREE); tree alias_ptr = fold_convert (reference_alias_ptr_type (DR_REF (dr)), coff); /* While data-ref analysis punts on bit offsets it still handles bitfield accesses at byte boundaries. Cope with that. Note that diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index b2294290077..70567131d73 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -3178,7 +3178,9 @@ simplify_vce (gimple_stmt_iterator *gsi) && (INTEGRAL_TYPE_P (TREE_TYPE (def_op)) || POINTER_TYPE_P (TREE_TYPE (def_op))) && (TYPE_PRECISION (TREE_TYPE (op)) - == TYPE_PRECISION (TREE_TYPE (def_op)))) + == TYPE_PRECISION (TREE_TYPE (def_op))) + && (TYPE_SIZE (TREE_TYPE (op)) + == TYPE_SIZE (TREE_TYPE (def_op)))) { TREE_OPERAND (gimple_assign_rhs1 (stmt), 0) = def_op; update_stmt (stmt); diff --git a/gcc/tree-ssa-reassoc.c b/gcc/tree-ssa-reassoc.c index b5b1d908707..60b4dae38a7 100644 --- a/gcc/tree-ssa-reassoc.c +++ b/gcc/tree-ssa-reassoc.c @@ -2047,7 +2047,7 @@ range_entry_cmp (const void *a, const void *b) else return -1; } - else if (p->high != NULL_TREE) + else if (q->high != NULL_TREE) return 1; /* If both ranges are the same, sort below by ascending idx. */ } @@ -3692,6 +3692,9 @@ acceptable_pow_call (gimple stmt, tree *base, HOST_WIDE_INT *exponent) switch (DECL_FUNCTION_CODE (fndecl)) { CASE_FLT_FN (BUILT_IN_POW): + if (flag_errno_math) + return false; + *base = gimple_call_arg (stmt, 0); arg1 = gimple_call_arg (stmt, 1); diff --git a/gcc/tree-ssa-strlen.c b/gcc/tree-ssa-strlen.c index f55b7ee6dc8..8d99a31d5df 100644 --- a/gcc/tree-ssa-strlen.c +++ b/gcc/tree-ssa-strlen.c @@ -1856,7 +1856,7 @@ strlen_optimize_stmt (gimple_stmt_iterator *gsi) break; } } - else if (is_gimple_assign (stmt)) + else if (is_gimple_assign (stmt) && !gimple_clobber_p (stmt)) { tree lhs = gimple_assign_lhs (stmt); diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index 1aa96a6be4b..6efe02ed495 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -314,7 +314,8 @@ stmt_local_def (gimple stmt) if (gimple_vdef (stmt) != NULL_TREE || gimple_has_side_effects (stmt) - || gimple_could_trap_p_1 (stmt, false, false)) + || gimple_could_trap_p_1 (stmt, false, false) + || gimple_vuse (stmt) != NULL_TREE) return false; def_p = SINGLE_SSA_DEF_OPERAND (stmt, SSA_OP_DEF); @@ -1164,7 +1165,8 @@ gimple_equal_p (same_succ same_succ, gimple s1, gimple s2) gimple_assign_rhs1 (s2))); else if (TREE_CODE (lhs1) == SSA_NAME && TREE_CODE (lhs2) == SSA_NAME) - return vn_valueize (lhs1) == vn_valueize (lhs2); + return operand_equal_p (gimple_assign_rhs1 (s1), + gimple_assign_rhs1 (s2), 0); return false; case GIMPLE_COND: diff --git a/gcc/tree-vect-loop.c b/gcc/tree-vect-loop.c index 797f24cd162..1fbb7b977e9 100644 --- a/gcc/tree-vect-loop.c +++ b/gcc/tree-vect-loop.c @@ -1647,6 +1647,13 @@ vect_analyze_loop_2 (loop_vec_info loop_vinfo) return false; } + /* Classify all cross-iteration scalar data-flow cycles. + Cross-iteration cycles caused by virtual phis are analyzed separately. */ + + vect_analyze_scalar_cycles (loop_vinfo); + + vect_pattern_recog (loop_vinfo, NULL); + /* Analyze the access patterns of the data-refs in the loop (consecutive, complex, etc.). FORNOW: Only handle consecutive access pattern. */ @@ -1659,13 +1666,6 @@ vect_analyze_loop_2 (loop_vec_info loop_vinfo) return false; } - /* Classify all cross-iteration scalar data-flow cycles. - Cross-iteration cycles caused by virtual phis are analyzed separately. */ - - vect_analyze_scalar_cycles (loop_vinfo); - - vect_pattern_recog (loop_vinfo, NULL); - /* Data-flow analysis to detect stmts that do not need to be vectorized. */ ok = vect_mark_stmts_to_be_vectorized (loop_vinfo); diff --git a/gcc/tree-vect-stmts.c b/gcc/tree-vect-stmts.c index eadfdfa7f15..7c4575d391f 100644 --- a/gcc/tree-vect-stmts.c +++ b/gcc/tree-vect-stmts.c @@ -325,7 +325,8 @@ vect_stmt_relevant_p (gimple stmt, loop_vec_info loop_vinfo, /* changing memory. */ if (gimple_code (stmt) != GIMPLE_PHI) - if (gimple_vdef (stmt)) + if (gimple_vdef (stmt) + && !gimple_clobber_p (stmt)) { if (dump_enabled_p ()) dump_printf_loc (MSG_NOTE, vect_location, @@ -3184,7 +3185,7 @@ vectorizable_simd_clone_call (gimple stmt, gimple_stmt_iterator *gsi, set_vinfo_for_stmt (new_stmt, stmt_info); set_vinfo_for_stmt (stmt, NULL); STMT_VINFO_STMT (stmt_info) = new_stmt; - gsi_replace (gsi, new_stmt, false); + gsi_replace (gsi, new_stmt, true); unlink_stmt_vdef (stmt); return true; diff --git a/gcc/tree.c b/gcc/tree.c index b9f3d60ea09..5ce8e902b33 100644 --- a/gcc/tree.c +++ b/gcc/tree.c @@ -1120,7 +1120,7 @@ int_cst_hash_hash (const void *x) const_tree const t = (const_tree) x; return (TREE_INT_CST_HIGH (t) ^ TREE_INT_CST_LOW (t) - ^ htab_hash_pointer (TREE_TYPE (t))); + ^ TYPE_UID (TREE_TYPE (t))); } /* Return nonzero if the value represented by *X (an INTEGER_CST tree node) diff --git a/gcc/ubsan.c b/gcc/ubsan.c index dc70099cccd..25c2cde6040 100644 --- a/gcc/ubsan.c +++ b/gcc/ubsan.c @@ -47,6 +47,7 @@ along with GCC; see the file COPYING3. If not see #include "asan.h" #include "gimplify-me.h" #include "intl.h" +#include "tree-eh.h" /* Map from a tree to a VAR_DECL tree. */ @@ -807,7 +808,9 @@ instrument_bool_enum_load (gimple_stmt_iterator *gsi) || TREE_CODE (gimple_assign_lhs (stmt)) != SSA_NAME) return; + bool can_throw = stmt_could_throw_p (stmt); location_t loc = gimple_location (stmt); + tree lhs = gimple_assign_lhs (stmt); tree ptype = build_pointer_type (TREE_TYPE (rhs)); tree atype = reference_alias_ptr_type (rhs); gimple g = gimple_build_assign (make_ssa_name (ptype, NULL), @@ -817,9 +820,24 @@ instrument_bool_enum_load (gimple_stmt_iterator *gsi) tree mem = build2 (MEM_REF, utype, gimple_assign_lhs (g), build_int_cst (atype, 0)); tree urhs = make_ssa_name (utype, NULL); - g = gimple_build_assign (urhs, mem); - gimple_set_location (g, loc); - gsi_insert_before (gsi, g, GSI_SAME_STMT); + if (can_throw) + { + gimple_assign_set_lhs (stmt, urhs); + g = gimple_build_assign_with_ops (NOP_EXPR, lhs, urhs, NULL_TREE); + gimple_set_location (g, loc); + edge e = find_fallthru_edge (gimple_bb (stmt)->succs); + gsi_insert_on_edge_immediate (e, g); + gimple_assign_set_rhs_from_tree (gsi, mem); + update_stmt (stmt); + *gsi = gsi_for_stmt (g); + g = stmt; + } + else + { + g = gimple_build_assign (urhs, mem); + gimple_set_location (g, loc); + gsi_insert_before (gsi, g, GSI_SAME_STMT); + } minv = fold_convert (utype, minv); maxv = fold_convert (utype, maxv); if (!integer_zerop (minv)) @@ -841,8 +859,11 @@ instrument_bool_enum_load (gimple_stmt_iterator *gsi) gimple_set_location (g, loc); gsi_insert_after (gsi, g, GSI_NEW_STMT); - gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE); - update_stmt (stmt); + if (!can_throw) + { + gimple_assign_set_rhs_with_ops (&gsi2, NOP_EXPR, urhs, NULL_TREE); + update_stmt (stmt); + } tree data = ubsan_create_data ("__ubsan_invalid_value_data", &loc, NULL, diff --git a/gcc/varasm.c b/gcc/varasm.c index 8e8c5f6634e..5e590f713a0 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -95,11 +95,6 @@ tree last_assemble_variable_decl; bool first_function_block_is_cold; -/* We give all constants their own alias set. Perhaps redundant with - MEM_READONLY_P, but pre-dates it. */ - -static alias_set_type const_alias_set; - /* Whether we saw any functions with no_split_stack. */ static bool saw_no_split_stack; @@ -3250,7 +3245,6 @@ build_constant_desc (tree exp) rtl = gen_const_mem (TYPE_MODE (TREE_TYPE (exp)), symbol); set_mem_attributes (rtl, exp, 1); set_mem_alias_set (rtl, 0); - set_mem_alias_set (rtl, const_alias_set); /* We cannot share RTX'es in pool entries. Mark this piece of RTL as required for unsharing. */ @@ -5957,7 +5951,6 @@ init_varasm_once (void) const_desc_htab = htab_create_ggc (1009, const_desc_hash, const_desc_eq, NULL); - const_alias_set = new_alias_set (); shared_constant_pool = create_constant_pool (); #ifdef TEXT_SECTION_ASM_OP diff --git a/libcpp/ChangeLog b/libcpp/ChangeLog index 05dbcc6bedd..47dc9a962ac 100644 --- a/libcpp/ChangeLog +++ b/libcpp/ChangeLog @@ -1,3 +1,13 @@ +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-25 Jakub Jelinek <jakub@redhat.com> + + PR preprocessor/60436 + * line-map.c (linemap_line_start): If highest is above 0x60000000 + and we are still tracking columns or highest is above 0x70000000, + force add_map. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/libcpp/line-map.c b/libcpp/line-map.c index f9a7658cbdb..78c43933d83 100644 --- a/libcpp/line-map.c +++ b/libcpp/line-map.c @@ -527,10 +527,10 @@ linemap_line_start (struct line_maps *set, linenum_type to_line, && line_delta * ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) > 1000) || (max_column_hint >= (1U << ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map))) || (max_column_hint <= 80 - && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10)) - { - add_map = true; - } + && ORDINARY_MAP_NUMBER_OF_COLUMN_BITS (map) >= 10) + || (highest > 0x60000000 + && (set->max_column_hint || highest > 0x70000000))) + add_map = true; else max_column_hint = set->max_column_hint; if (add_map) @@ -541,7 +541,7 @@ linemap_line_start (struct line_maps *set, linenum_type to_line, /* If the column number is ridiculous or we've allocated a huge number of source_locations, give up on column numbers. */ max_column_hint = 0; - if (highest >0x70000000) + if (highest > 0x70000000) return 0; column_bits = 0; } diff --git a/libcpp/po/ChangeLog b/libcpp/po/ChangeLog index fc2c8612047..db8d3126409 100644 --- a/libcpp/po/ChangeLog +++ b/libcpp/po/ChangeLog @@ -1,3 +1,7 @@ +2014-11-07 Joseph Myers <joseph@codesourcery.com> + + * ja.po: Update. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/libcpp/po/ja.po b/libcpp/po/ja.po index cb2c95e1cc2..2c48c2c774d 100644 --- a/libcpp/po/ja.po +++ b/libcpp/po/ja.po @@ -4,22 +4,21 @@ # Daisuke Yamashita <yamad@mb.infoweb.ne.jp>, 1999-2001 # Masahito Yamaga <yamaga@ipc.chiba-u.ac.jp>, 1999. # IIDA Yosiaki <iida@secom.ne.jp>, 1999. -# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011. # Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>, 2012, 2013 +# Yasuaki Taniguchi <yasuakit@gmail.com>, 2010, 2011, 2014. msgid "" msgstr "" -"Project-Id-Version: cpplib 4.8-b20130224\n" +"Project-Id-Version: cpplib 4.9-b20140202\n" "Report-Msgid-Bugs-To: http://gcc.gnu.org/bugs.html\n" "POT-Creation-Date: 2014-02-02 17:35+0000\n" -"PO-Revision-Date: 2013-03-04 18:01+0900\n" -"Last-Translator: Takeshi Hamasaki <hmatrjp@users.sourceforge.jp>\n" +"PO-Revision-Date: 2014-11-07 08:19+0000\n" +"Last-Translator: Yasuaki Taniguchi <yasuakit@gmail.com>\n" "Language-Team: Japanese <translation-team-ja@lists.sourceforge.net>\n" "Language: ja\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=UTF-8\n" "Content-Transfer-Encoding: 8bit\n" "Plural-Forms: nplurals=1; plural=0;\n" -"X-Generator: Poedit 1.5.4\n" #: charset.c:673 #, c-format @@ -456,10 +455,8 @@ msgid "invalid suffix \"%.*s\" on integer constant" msgstr "整数定数に無効な接尾辞 \"%.*s\" があります" #: expr.c:667 -#, fuzzy -#| msgid "use of C++0x long long integer constant" msgid "use of C++11 long long integer constant" -msgstr "C++0x の long long 整数定数を使用しています" +msgstr "C++11 の long long 整数定数を使用しています" #: expr.c:668 msgid "use of C99 long long integer constant" @@ -470,10 +467,8 @@ msgid "imaginary constants are a GCC extension" msgstr "虚数定数は GCC 拡張です" #: expr.c:690 -#, fuzzy -#| msgid "binary constants are a GCC extension" msgid "binary constants are a C++1y feature or GCC extension" -msgstr "二進定数は GCC 拡張です" +msgstr "二進定数は C++1y の機能または GCC 拡張です" #: expr.c:787 msgid "integer constant is too large for its type" @@ -703,10 +698,8 @@ msgid "raw string delimiter longer than 16 characters" msgstr "生の文字列区切りが 16 文字より大きいです" #: lex.c:1558 -#, fuzzy -#| msgid "invalid character '%c' in raw string delimiter" msgid "invalid new-line in raw string delimiter" -msgstr "生の文字列区切り内に無効な文字 '%c' があります" +msgstr "生の文字列区切り内に無効な改行があります" #: lex.c:1562 #, c-format @@ -718,10 +711,8 @@ msgid "unterminated raw string" msgstr "終端されていない生の文字列です" #: lex.c:1654 lex.c:1783 -#, fuzzy -#| msgid "invalid suffix on literal; C++11 requires a space between literal and identifier" msgid "invalid suffix on literal; C++11 requires a space between literal and string macro" -msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと識別子の間にスペースを入れる必要があります。" +msgstr "リテラルの接尾辞が無効です。C++11 では、リテラルと文字列マクロの間にスペースを入れる必要があります。" #: lex.c:1765 msgid "null character(s) preserved in literal" @@ -762,7 +753,7 @@ msgstr "無効な組み込みマクロ \"%s\" です" #: macro.c:236 macro.c:333 #, c-format msgid "macro \"%s\" might prevent reproducible builds" -msgstr "" +msgstr "マクロ \"%s\" は再生性可能なビルドを阻害するかもしれません" #: macro.c:267 msgid "could not determine file timestamp" diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index df187b199cf..d729ccbc761 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,3 +1,35 @@ +2014-12-09 John David Anglin <danglin@gcc.gnu.org> + + Backport from mainline + 2014-11-24 John David Anglin <danglin@gcc.gnu.org> + + * config/pa/linux-atomic.c (ABORT_INSTRUCTION): Use __builtin_trap() + instead. + + 2014-11-21 Guy Martin <gmsoft@tuxicoman.be> + John David Anglin <danglin@gcc.gnu.org> + + * config/pa/linux-atomic.c (__kernel_cmpxchg2): New. + (FETCH_AND_OP_2): New. Use for subword and double word operations. + (OP_AND_FETCH_2): Likewise. + (COMPARE_AND_SWAP_2): Likewise. + (SYNC_LOCK_TEST_AND_SET_2): Likewise. + (SYNC_LOCK_RELEASE_2): Likewise. + (SUBWORD_SYNC_OP): Remove. + (SUBWORD_VAL_CAS): Likewise. + (SUBWORD_BOOL_CAS): Likewise. + (FETCH_AND_OP_WORD): Update. + Consistently use signed types. + +2014-12-09 Oleg Endo <olegendo@gcc.gnu.org> + + Backport from mainline + 2014-11-30 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/55351 + * config/sh/lib1funcs.S: Check value of __SHMEDIA__ instead of checking + whether it's defined. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/libgcc/config/pa/linux-atomic.c b/libgcc/config/pa/linux-atomic.c index d92d6ef79b3..19e37b6f3c4 100644 --- a/libgcc/config/pa/linux-atomic.c +++ b/libgcc/config/pa/linux-atomic.c @@ -41,11 +41,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see using the kernel helper defined below. There is no support for 64-bit operations yet. */ -/* A privileged instruction to crash a userspace program with SIGILL. */ -#define ABORT_INSTRUCTION asm ("iitlbp %r0,(%sr0, %r0)") - /* Determine kernel LWS function call (0=32-bit, 1=64-bit userspace). */ -#define LWS_CAS (sizeof(unsigned long) == 4 ? 0 : 1) +#define LWS_CAS (sizeof(long) == 4 ? 0 : 1) /* Kernel helper for compare-and-exchange a 32-bit value. */ static inline long @@ -64,7 +61,7 @@ __kernel_cmpxchg (int oldval, int newval, int *mem) : "r1", "r20", "r22", "r23", "r29", "r31", "memory" ); if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0)) - ABORT_INSTRUCTION; + __builtin_trap (); /* If the kernel LWS call succeeded (lws_errno == 0), lws_ret contains the old value from memory. If this value is equal to OLDVAL, the @@ -75,6 +72,30 @@ __kernel_cmpxchg (int oldval, int newval, int *mem) return lws_errno; } +static inline long +__kernel_cmpxchg2 (void * oldval, void * newval, void *mem, int val_size) +{ + register unsigned long lws_mem asm("r26") = (unsigned long) (mem); + register long lws_ret asm("r28"); + register long lws_errno asm("r21"); + register unsigned long lws_old asm("r25") = (unsigned long) oldval; + register unsigned long lws_new asm("r24") = (unsigned long) newval; + register int lws_size asm("r23") = val_size; + asm volatile ( "ble 0xb0(%%sr2, %%r0) \n\t" + "ldi %2, %%r20 \n\t" + : "=r" (lws_ret), "=r" (lws_errno) + : "i" (2), "r" (lws_mem), "r" (lws_old), "r" (lws_new), "r" (lws_size) + : "r1", "r20", "r22", "r29", "r31", "fr4", "memory" + ); + if (__builtin_expect (lws_errno == -EFAULT || lws_errno == -ENOSYS, 0)) + __builtin_trap (); + + /* If the kernel LWS call fails, retrun EBUSY */ + if (!lws_errno && lws_ret) + lws_errno = -EBUSY; + + return lws_errno; +} #define HIDDEN __attribute__ ((visibility ("hidden"))) /* Big endian masks */ @@ -84,6 +105,80 @@ __kernel_cmpxchg (int oldval, int newval, int *mem) #define MASK_1 0xffu #define MASK_2 0xffffu +#define FETCH_AND_OP_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX) \ + TYPE HIDDEN \ + __sync_fetch_and_##OP##_##WIDTH (TYPE *ptr, TYPE val) \ + { \ + TYPE tmp, newval; \ + int failure; \ + \ + do { \ + tmp = *ptr; \ + newval = PFX_OP (tmp INF_OP val); \ + failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX); \ + } while (failure != 0); \ + \ + return tmp; \ + } + +FETCH_AND_OP_2 (add, , +, long long, 8, 3) +FETCH_AND_OP_2 (sub, , -, long long, 8, 3) +FETCH_AND_OP_2 (or, , |, long long, 8, 3) +FETCH_AND_OP_2 (and, , &, long long, 8, 3) +FETCH_AND_OP_2 (xor, , ^, long long, 8, 3) +FETCH_AND_OP_2 (nand, ~, &, long long, 8, 3) + +FETCH_AND_OP_2 (add, , +, short, 2, 1) +FETCH_AND_OP_2 (sub, , -, short, 2, 1) +FETCH_AND_OP_2 (or, , |, short, 2, 1) +FETCH_AND_OP_2 (and, , &, short, 2, 1) +FETCH_AND_OP_2 (xor, , ^, short, 2, 1) +FETCH_AND_OP_2 (nand, ~, &, short, 2, 1) + +FETCH_AND_OP_2 (add, , +, signed char, 1, 0) +FETCH_AND_OP_2 (sub, , -, signed char, 1, 0) +FETCH_AND_OP_2 (or, , |, signed char, 1, 0) +FETCH_AND_OP_2 (and, , &, signed char, 1, 0) +FETCH_AND_OP_2 (xor, , ^, signed char, 1, 0) +FETCH_AND_OP_2 (nand, ~, &, signed char, 1, 0) + +#define OP_AND_FETCH_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX) \ + TYPE HIDDEN \ + __sync_##OP##_and_fetch_##WIDTH (TYPE *ptr, TYPE val) \ + { \ + TYPE tmp, newval; \ + int failure; \ + \ + do { \ + tmp = *ptr; \ + newval = PFX_OP (tmp INF_OP val); \ + failure = __kernel_cmpxchg2 (&tmp, &newval, ptr, INDEX); \ + } while (failure != 0); \ + \ + return PFX_OP (tmp INF_OP val); \ + } + +OP_AND_FETCH_2 (add, , +, long long, 8, 3) +OP_AND_FETCH_2 (sub, , -, long long, 8, 3) +OP_AND_FETCH_2 (or, , |, long long, 8, 3) +OP_AND_FETCH_2 (and, , &, long long, 8, 3) +OP_AND_FETCH_2 (xor, , ^, long long, 8, 3) +OP_AND_FETCH_2 (nand, ~, &, long long, 8, 3) + +OP_AND_FETCH_2 (add, , +, short, 2, 1) +OP_AND_FETCH_2 (sub, , -, short, 2, 1) +OP_AND_FETCH_2 (or, , |, short, 2, 1) +OP_AND_FETCH_2 (and, , &, short, 2, 1) +OP_AND_FETCH_2 (xor, , ^, short, 2, 1) +OP_AND_FETCH_2 (nand, ~, &, short, 2, 1) + +OP_AND_FETCH_2 (add, , +, signed char, 1, 0) +OP_AND_FETCH_2 (sub, , -, signed char, 1, 0) +OP_AND_FETCH_2 (or, , |, signed char, 1, 0) +OP_AND_FETCH_2 (and, , &, signed char, 1, 0) +OP_AND_FETCH_2 (xor, , ^, signed char, 1, 0) +OP_AND_FETCH_2 (nand, ~, &, signed char, 1, 0) + #define FETCH_AND_OP_WORD(OP, PFX_OP, INF_OP) \ int HIDDEN \ __sync_fetch_and_##OP##_4 (int *ptr, int val) \ @@ -105,48 +200,6 @@ FETCH_AND_OP_WORD (and, , &) FETCH_AND_OP_WORD (xor, , ^) FETCH_AND_OP_WORD (nand, ~, &) -#define NAME_oldval(OP, WIDTH) __sync_fetch_and_##OP##_##WIDTH -#define NAME_newval(OP, WIDTH) __sync_##OP##_and_fetch_##WIDTH - -/* Implement both __sync_<op>_and_fetch and __sync_fetch_and_<op> for - subword-sized quantities. */ - -#define SUBWORD_SYNC_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH, RETURN) \ - TYPE HIDDEN \ - NAME##_##RETURN (OP, WIDTH) (TYPE *ptr, TYPE val) \ - { \ - int *wordptr = (int *) ((unsigned long) ptr & ~3); \ - unsigned int mask, shift, oldval, newval; \ - int failure; \ - \ - shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ - mask = MASK_##WIDTH << shift; \ - \ - do { \ - oldval = *wordptr; \ - newval = ((PFX_OP (((oldval & mask) >> shift) \ - INF_OP (unsigned int) val)) << shift) & mask; \ - newval |= oldval & ~mask; \ - failure = __kernel_cmpxchg (oldval, newval, wordptr); \ - } while (failure != 0); \ - \ - return (RETURN & mask) >> shift; \ - } - -SUBWORD_SYNC_OP (add, , +, unsigned short, 2, oldval) -SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, oldval) -SUBWORD_SYNC_OP (or, , |, unsigned short, 2, oldval) -SUBWORD_SYNC_OP (and, , &, unsigned short, 2, oldval) -SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, oldval) -SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, oldval) - -SUBWORD_SYNC_OP (add, , +, unsigned char, 1, oldval) -SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, oldval) -SUBWORD_SYNC_OP (or, , |, unsigned char, 1, oldval) -SUBWORD_SYNC_OP (and, , &, unsigned char, 1, oldval) -SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, oldval) -SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, oldval) - #define OP_AND_FETCH_WORD(OP, PFX_OP, INF_OP) \ int HIDDEN \ __sync_##OP##_and_fetch_4 (int *ptr, int val) \ @@ -168,19 +221,41 @@ OP_AND_FETCH_WORD (and, , &) OP_AND_FETCH_WORD (xor, , ^) OP_AND_FETCH_WORD (nand, ~, &) -SUBWORD_SYNC_OP (add, , +, unsigned short, 2, newval) -SUBWORD_SYNC_OP (sub, , -, unsigned short, 2, newval) -SUBWORD_SYNC_OP (or, , |, unsigned short, 2, newval) -SUBWORD_SYNC_OP (and, , &, unsigned short, 2, newval) -SUBWORD_SYNC_OP (xor, , ^, unsigned short, 2, newval) -SUBWORD_SYNC_OP (nand, ~, &, unsigned short, 2, newval) +typedef unsigned char bool; + +#define COMPARE_AND_SWAP_2(TYPE, WIDTH, INDEX) \ + TYPE HIDDEN \ + __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ + TYPE newval) \ + { \ + TYPE actual_oldval; \ + int fail; \ + \ + while (1) \ + { \ + actual_oldval = *ptr; \ + \ + if (__builtin_expect (oldval != actual_oldval, 0)) \ + return actual_oldval; \ + \ + fail = __kernel_cmpxchg2 (&actual_oldval, &newval, ptr, INDEX); \ + \ + if (__builtin_expect (!fail, 1)) \ + return actual_oldval; \ + } \ + } \ + \ + bool HIDDEN \ + __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ + TYPE newval) \ + { \ + int failure = __kernel_cmpxchg2 (&oldval, &newval, ptr, INDEX); \ + return (failure != 0); \ + } -SUBWORD_SYNC_OP (add, , +, unsigned char, 1, newval) -SUBWORD_SYNC_OP (sub, , -, unsigned char, 1, newval) -SUBWORD_SYNC_OP (or, , |, unsigned char, 1, newval) -SUBWORD_SYNC_OP (and, , &, unsigned char, 1, newval) -SUBWORD_SYNC_OP (xor, , ^, unsigned char, 1, newval) -SUBWORD_SYNC_OP (nand, ~, &, unsigned char, 1, newval) +COMPARE_AND_SWAP_2 (long long, 8, 3) +COMPARE_AND_SWAP_2 (short, 2, 1) +COMPARE_AND_SWAP_2 (char, 1, 0) int HIDDEN __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval) @@ -201,41 +276,6 @@ __sync_val_compare_and_swap_4 (int *ptr, int oldval, int newval) } } -#define SUBWORD_VAL_CAS(TYPE, WIDTH) \ - TYPE HIDDEN \ - __sync_val_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ - TYPE newval) \ - { \ - int *wordptr = (int *)((unsigned long) ptr & ~3), fail; \ - unsigned int mask, shift, actual_oldval, actual_newval; \ - \ - shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ - mask = MASK_##WIDTH << shift; \ - \ - while (1) \ - { \ - actual_oldval = *wordptr; \ - \ - if (__builtin_expect (((actual_oldval & mask) >> shift) \ - != (unsigned int) oldval, 0)) \ - return (actual_oldval & mask) >> shift; \ - \ - actual_newval = (actual_oldval & ~mask) \ - | (((unsigned int) newval << shift) & mask); \ - \ - fail = __kernel_cmpxchg (actual_oldval, actual_newval, \ - wordptr); \ - \ - if (__builtin_expect (!fail, 1)) \ - return (actual_oldval & mask) >> shift; \ - } \ - } - -SUBWORD_VAL_CAS (unsigned short, 2) -SUBWORD_VAL_CAS (unsigned char, 1) - -typedef unsigned char bool; - bool HIDDEN __sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval) { @@ -243,18 +283,24 @@ __sync_bool_compare_and_swap_4 (int *ptr, int oldval, int newval) return (failure == 0); } -#define SUBWORD_BOOL_CAS(TYPE, WIDTH) \ - bool HIDDEN \ - __sync_bool_compare_and_swap_##WIDTH (TYPE *ptr, TYPE oldval, \ - TYPE newval) \ +#define SYNC_LOCK_TEST_AND_SET_2(TYPE, WIDTH, INDEX) \ +TYPE HIDDEN \ + __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \ { \ - TYPE actual_oldval \ - = __sync_val_compare_and_swap_##WIDTH (ptr, oldval, newval); \ - return (oldval == actual_oldval); \ + TYPE oldval; \ + int failure; \ + \ + do { \ + oldval = *ptr; \ + failure = __kernel_cmpxchg2 (&oldval, &val, ptr, INDEX); \ + } while (failure != 0); \ + \ + return oldval; \ } -SUBWORD_BOOL_CAS (unsigned short, 2) -SUBWORD_BOOL_CAS (unsigned char, 1) +SYNC_LOCK_TEST_AND_SET_2 (long long, 8, 3) +SYNC_LOCK_TEST_AND_SET_2 (short, 2, 1) +SYNC_LOCK_TEST_AND_SET_2 (signed char, 1, 0) int HIDDEN __sync_lock_test_and_set_4 (int *ptr, int val) @@ -269,37 +315,29 @@ __sync_lock_test_and_set_4 (int *ptr, int val) return oldval; } -#define SUBWORD_TEST_AND_SET(TYPE, WIDTH) \ - TYPE HIDDEN \ - __sync_lock_test_and_set_##WIDTH (TYPE *ptr, TYPE val) \ - { \ - int failure; \ - unsigned int oldval, newval, shift, mask; \ - int *wordptr = (int *) ((unsigned long) ptr & ~3); \ - \ - shift = (((unsigned long) ptr & 3) << 3) ^ INVERT_MASK_##WIDTH; \ - mask = MASK_##WIDTH << shift; \ - \ - do { \ - oldval = *wordptr; \ - newval = (oldval & ~mask) \ - | (((unsigned int) val << shift) & mask); \ - failure = __kernel_cmpxchg (oldval, newval, wordptr); \ - } while (failure != 0); \ - \ - return (oldval & mask) >> shift; \ +#define SYNC_LOCK_RELEASE_2(TYPE, WIDTH, INDEX) \ + void HIDDEN \ + __sync_lock_release_##WIDTH (TYPE *ptr) \ + { \ + TYPE failure, oldval, zero = 0; \ + \ + do { \ + oldval = *ptr; \ + failure = __kernel_cmpxchg2 (&oldval, &zero, ptr, INDEX); \ + } while (failure != 0); \ } -SUBWORD_TEST_AND_SET (unsigned short, 2) -SUBWORD_TEST_AND_SET (unsigned char, 1) +SYNC_LOCK_RELEASE_2 (long long, 8, 3) +SYNC_LOCK_RELEASE_2 (short, 2, 1) +SYNC_LOCK_RELEASE_2 (signed char, 1, 0) -#define SYNC_LOCK_RELEASE(TYPE, WIDTH) \ - void HIDDEN \ - __sync_lock_release_##WIDTH (TYPE *ptr) \ - { \ - *ptr = 0; \ - } +void HIDDEN +__sync_lock_release_4 (int *ptr) +{ + int failure, oldval; -SYNC_LOCK_RELEASE (int, 4) -SYNC_LOCK_RELEASE (short, 2) -SYNC_LOCK_RELEASE (char, 1) + do { + oldval = *ptr; + failure = __kernel_cmpxchg (oldval, 0, ptr); + } while (failure != 0); +} diff --git a/libgcc/config/sh/lib1funcs.S b/libgcc/config/sh/lib1funcs.S index 3410cf7c163..cfd6dc2a283 100644 --- a/libgcc/config/sh/lib1funcs.S +++ b/libgcc/config/sh/lib1funcs.S @@ -1278,7 +1278,7 @@ GLOBAL(sdivsi3_2): #endif ENDFUNC(GLOBAL(sdivsi3_2)) #endif -#elif defined __SHMEDIA__ +#elif __SHMEDIA__ /* m5compact-nofpu */ // clobbered: r18,r19,r20,r21,r25,tr0,tr1,tr2 .mode SHmedia @@ -1683,7 +1683,7 @@ GLOBAL(udivsi3): add.l r18,r25,r0 blink tr0,r63 #endif -#elif defined (__SHMEDIA__) +#elif __SHMEDIA__ /* m5compact-nofpu - more emphasis on code size than on speed, but don't ignore speed altogether - div1 needs 9 cycles, subc 7 and rotcl 4. So use a short shmedia loop. */ @@ -1707,7 +1707,7 @@ LOCAL(udivsi3_dontsub): bnei r25,-32,tr1 add.l r20,r63,r0 blink tr2,r63 -#else /* ! defined (__SHMEDIA__) */ +#else /* ! __SHMEDIA__ */ LOCAL(div8): div1 r5,r4 LOCAL(div7): @@ -1773,7 +1773,7 @@ LOCAL(large_divisor): #endif /* L_udivsi3 */ #ifdef L_udivdi3 -#ifdef __SHMEDIA__ +#if __SHMEDIA__ .mode SHmedia .section .text..SHmedia32,"ax" .align 2 @@ -1901,7 +1901,7 @@ LOCAL(no_lo_adj): #endif /* L_udivdi3 */ #ifdef L_divdi3 -#ifdef __SHMEDIA__ +#if __SHMEDIA__ .mode SHmedia .section .text..SHmedia32,"ax" .align 2 @@ -1925,7 +1925,7 @@ GLOBAL(divdi3): #endif /* L_divdi3 */ #ifdef L_umoddi3 -#ifdef __SHMEDIA__ +#if __SHMEDIA__ .mode SHmedia .section .text..SHmedia32,"ax" .align 2 @@ -2054,7 +2054,7 @@ LOCAL(no_lo_adj): #endif /* L_umoddi3 */ #ifdef L_moddi3 -#ifdef __SHMEDIA__ +#if __SHMEDIA__ .mode SHmedia .section .text..SHmedia32,"ax" .align 2 @@ -3142,7 +3142,7 @@ GLOBAL(GCC_pop_shmedia_regs_nofpu): #ifdef L_div_table #if __SH5__ -#if defined(__pic__) && defined(__SHMEDIA__) +#if defined(__pic__) && __SHMEDIA__ .global GLOBAL(sdivsi3) FUNC(GLOBAL(sdivsi3)) #if __SH5__ == 32 @@ -3215,7 +3215,7 @@ Defects for bias -330: #else /* ! __pic__ || ! __SHMEDIA__ */ .section .rodata #endif /* __pic__ */ -#if defined(TEXT_DATA_BUG) && defined(__pic__) && defined(__SHMEDIA__) +#if defined(TEXT_DATA_BUG) && defined(__pic__) && __SHMEDIA__ .balign 2 .type Local_div_table,@object .size Local_div_table,128 diff --git a/libgomp/ChangeLog b/libgomp/ChangeLog index 29d929745b9..0c5042774e9 100644 --- a/libgomp/ChangeLog +++ b/libgomp/ChangeLog @@ -1,3 +1,16 @@ +2014-12-03 Uros Bizjak <ubizjak@gmail.com> + + * configure.tgt (x86_64-*-linux*): Tune -m32 multilib to generic. + +2014-11-28 Jakub Jelinek <jakub@redhat.com> + + Backported from mainline + 2014-11-24 Jakub Jelinek <jakub@redhat.com> + + PR fortran/63938 + * libgomp.fortran/pr63938-1.f90: New test. + * libgomp.fortran/pr63938-2.f90: New test. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt index 8b1841792d4..ebd9be97d08 100644 --- a/libgomp/configure.tgt +++ b/libgomp/configure.tgt @@ -82,7 +82,7 @@ if test $enable_linux_futex = yes; then config_path="linux/x86 linux posix" case " ${CC} ${CFLAGS} " in *" -m32 "*) - XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686" + XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic" ;; esac ;; diff --git a/libgomp/testsuite/libgomp.fortran/pr63938-1.f90 b/libgomp/testsuite/libgomp.fortran/pr63938-1.f90 new file mode 100644 index 00000000000..27501b2f8ab --- /dev/null +++ b/libgomp/testsuite/libgomp.fortran/pr63938-1.f90 @@ -0,0 +1,14 @@ +! PR fortran/63938 +! { dg-do run } + +program pr63938_1 + integer :: i, x(1) + x(1) = 0 +!$omp parallel do + do i = 1, 1000 + !$omp atomic + x(1) = x(1) + 1 + end do +!$omp end parallel do + if (x(1) .ne. 1000) call abort +end program pr63938_1 diff --git a/libgomp/testsuite/libgomp.fortran/pr63938-2.f90 b/libgomp/testsuite/libgomp.fortran/pr63938-2.f90 new file mode 100644 index 00000000000..e5f37ba7602 --- /dev/null +++ b/libgomp/testsuite/libgomp.fortran/pr63938-2.f90 @@ -0,0 +1,18 @@ +! PR fortran/63938 +! { dg-do run } + +program pr63938_2 + type t + integer :: x + end type + integer :: i + type(t) :: x + x%x = 0 +!$omp parallel do + do i = 1, 1000 + !$omp atomic + x%x = x%x + 1 + end do +!$omp end parallel do + if (x%x .ne. 1000) call abort +end program pr63938_2 diff --git a/libitm/ChangeLog b/libitm/ChangeLog index 0cac303757b..31f63f2616a 100644 --- a/libitm/ChangeLog +++ b/libitm/ChangeLog @@ -1,3 +1,7 @@ +2014-12-03 Uros Bizjak <ubizjak@gmail.com> + + * configure.tgt (x86_64): Tune -m32 multilib to generic. + 2014-10-30 Release Manager * GCC 4.9.2 released. diff --git a/libitm/configure.tgt b/libitm/configure.tgt index 44c1a144a23..bd95509be37 100644 --- a/libitm/configure.tgt +++ b/libitm/configure.tgt @@ -102,7 +102,7 @@ case "${target_cpu}" in x86_64) case " ${CC} ${CFLAGS} " in *" -m32 "*) - XCFLAGS="${XCFLAGS} -march=i486 -mtune=i686" + XCFLAGS="${XCFLAGS} -march=i486 -mtune=generic" XCFLAGS="${XCFLAGS} -fomit-frame-pointer" ;; esac diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 3eca6af45d2..f054f09722a 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,4 +1,69 @@ -2014-10-30 David Edelsohn +2014-12-09 Jonathan Wakely <jwakely@redhat.com> + + PR libstdc++/64203 + * include/std/shared_mutex: Fix preprocessor conditions. + * testsuite/experimental/feat-cxx14.cc: Check conditions. + +2014-12-06 Jonathan Wakely <jwakely@redhat.com> + + PR libstdc++/63840 + * include/std/functional (function::function(const function&)): Set + _M_manager after operations that might throw. + * include/tr1/functional (function::function(const function&), + function::function(_Functor, _Useless)): Likewise. + * testsuite/20_util/function/63840.cc: New. + * testsuite/tr1/3_function_objects/function/63840.cc: New. + + PR libstdc++/61947 + * include/std/tuple (_Head_base): Use allocator_arg_t parameters to + disambiguate unary constructors. + (_Tuple_impl): Pass allocator_arg_t arguments. + * testsuite/20_util/tuple/61947.cc: New. + * testsuite/20_util/uses_allocator/cons_neg.cc: Adjust dg-error line. + +2014-12-06 Tim Shen <timshen@google.com> + + PR libstdc++/64140 + Backport form mainline + 2014-12-04 Tim Shen <timshen@google.com> + + * include/bits/regex.tcc (regex_iterator<>::operator++): Update + prefix.matched after modifying prefix.first. + * testsuite/28_regex/iterators/regex_iterator/char/64140.cc: New + testcase. + +2014-12-02 Matthias Klose <doko@ubuntu.com> + + PR libstdc++/64103 + Backport from mainline + 2014-11-03 Paolo Carlini <paolo.carlini@oracle.com> + + * include/parallel/algo.h: Do not use default arguments in function + template redeclarations (definitions). + + 2014-11-04 Jonathan Wakely <jwakely@redhat.com> + + * include/parallel/numeric.h: Do not use default arguments in function + template redeclarations (definitions). + +2014-11-28 Tim Shen <timshen@google.com> + + PR libstdc++/63497 + * include/bits/regex_executor.tcc (_Executor::_M_dfs, + _Executor::_M_word_boundary): Avoid dereferecing _M_current at _M_end + or other invalid position. + +2014-11-13 Thomas Preud'homme <thomas.preudhomme@arm.com> + + Backport from mainline + 2014-09-10 Tony Wang <tony.wang@arm.com> + + PR target/56846 + * libsupc++/eh_personality.cc (PERSONALITY_FUNCTION): + Return with CONTINUE_UNWINDING when the state pattern + contains: _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND + +2014-10-30 David Edelsohn <dje.gcc@gmail.com> Backported from mainline. 2014-10-30 David Edelsohn <dje.gcc@gmail.com> diff --git a/libstdc++-v3/include/bits/regex.tcc b/libstdc++-v3/include/bits/regex.tcc index 5fa1f018b3d..364294d4184 100644 --- a/libstdc++-v3/include/bits/regex.tcc +++ b/libstdc++-v3/include/bits/regex.tcc @@ -581,7 +581,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION | regex_constants::match_continuous)) { _GLIBCXX_DEBUG_ASSERT(_M_match[0].matched); - _M_match.at(_M_match.size()).first = __prefix_first; + auto& __prefix = _M_match.at(_M_match.size()); + __prefix.first = __prefix_first; + __prefix.matched = __prefix.first != __prefix.second; _M_match._M_in_iterator = true; _M_match._M_begin = _M_begin; return *this; @@ -594,7 +596,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (regex_search(__start, _M_end, _M_match, *_M_pregex, _M_flags)) { _GLIBCXX_DEBUG_ASSERT(_M_match[0].matched); - _M_match.at(_M_match.size()).first = __prefix_first; + auto& __prefix = _M_match.at(_M_match.size()); + __prefix.first = __prefix_first; + __prefix.matched = __prefix.first != __prefix.second; _M_match._M_in_iterator = true; _M_match._M_begin = _M_begin; } diff --git a/libstdc++-v3/include/bits/regex_executor.tcc b/libstdc++-v3/include/bits/regex_executor.tcc index 052302b91f7..1dc65435f11 100644 --- a/libstdc++-v3/include/bits/regex_executor.tcc +++ b/libstdc++-v3/include/bits/regex_executor.tcc @@ -267,9 +267,11 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION _M_dfs<__match_mode>(__state._M_next); break; case _S_opcode_match: + if (_M_current == _M_end) + break; if (__dfs_mode) { - if (_M_current != _M_end && __state._M_matches(*_M_current)) + if (__state._M_matches(*_M_current)) { ++_M_current; _M_dfs<__match_mode>(__state._M_next); @@ -350,23 +352,24 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION bool _Executor<_BiIter, _Alloc, _TraitsT, __dfs_mode>:: _M_word_boundary(_State<_TraitsT> __state) const { - // By definition. - bool __ans = false; - auto __pre = _M_current; - --__pre; - if (!(_M_at_begin() && _M_at_end())) + bool __left_is_word = false; + if (_M_current != _M_begin + || (_M_flags & regex_constants::match_prev_avail)) { - if (_M_at_begin()) - __ans = _M_is_word(*_M_current) - && !(_M_flags & regex_constants::match_not_bow); - else if (_M_at_end()) - __ans = _M_is_word(*__pre) - && !(_M_flags & regex_constants::match_not_eow); - else - __ans = _M_is_word(*_M_current) - != _M_is_word(*__pre); + auto __prev = _M_current; + if (_M_is_word(*std::prev(__prev))) + __left_is_word = true; } - return __ans; + bool __right_is_word = + _M_current != _M_end && _M_is_word(*_M_current); + + if (__left_is_word == __right_is_word) + return false; + if (__left_is_word && !(_M_flags & regex_constants::match_not_eow)) + return true; + if (__right_is_word && !(_M_flags & regex_constants::match_not_bow)) + return true; + return false; } _GLIBCXX_END_NAMESPACE_VERSION diff --git a/libstdc++-v3/include/parallel/algo.h b/libstdc++-v3/include/parallel/algo.h index 2c1f9eb4c5c..4608487dd6a 100644 --- a/libstdc++-v3/include/parallel/algo.h +++ b/libstdc++-v3/include/parallel/algo.h @@ -81,9 +81,8 @@ namespace __parallel template<typename _RAIter, typename _Function> _Function __for_each_switch(_RAIter __begin, _RAIter __end, - _Function __f, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + _Function __f, random_access_iterator_tag, + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -896,8 +895,7 @@ namespace __parallel typename iterator_traits<_RAIter>::difference_type __count_switch(_RAIter __begin, _RAIter __end, const _Tp& __value, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_unbalanced) + __gnu_parallel::_Parallelism __parallelism_tag) { typedef iterator_traits<_RAIter> _TraitsType; typedef typename _TraitsType::value_type _ValueType; @@ -966,8 +964,7 @@ namespace __parallel typename iterator_traits<_RAIter>::difference_type __count_if_switch(_RAIter __begin, _RAIter __end, _Predicate __pred, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_unbalanced) + __gnu_parallel::_Parallelism __parallelism_tag) { typedef iterator_traits<_RAIter> _TraitsType; typedef typename _TraitsType::value_type _ValueType; @@ -1225,8 +1222,7 @@ namespace __parallel __transform1_switch(_RAIter1 __begin, _RAIter1 __end, _RAIter2 __result, _UnaryOperation __unary_op, random_access_iterator_tag, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -1315,8 +1311,7 @@ namespace __parallel _RAIter3 __result, _BinaryOperation __binary_op, random_access_iterator_tag, random_access_iterator_tag, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( (__end1 - __begin1) >= @@ -1422,8 +1417,7 @@ namespace __parallel __replace_switch(_RAIter __begin, _RAIter __end, const _Tp& __old_value, const _Tp& __new_value, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { // XXX parallel version is where? replace(__begin, __end, __old_value, __new_value, @@ -1478,8 +1472,7 @@ namespace __parallel __replace_if_switch(_RAIter __begin, _RAIter __end, _Predicate __pred, const _Tp& __new_value, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -1544,8 +1537,7 @@ namespace __parallel void __generate_switch(_RAIter __begin, _RAIter __end, _Generator __gen, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -1608,8 +1600,7 @@ namespace __parallel inline _RAIter __generate_n_switch(_RAIter __begin, _Size __n, _Generator __gen, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { // XXX parallel version is where? return generate_n(__begin, __n, __gen, __gnu_parallel::sequential_tag()); @@ -2204,8 +2195,7 @@ namespace __parallel _RAIter __max_element_switch(_RAIter __begin, _RAIter __end, _Compare __comp, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -2296,8 +2286,7 @@ namespace __parallel _RAIter __min_element_switch(_RAIter __begin, _RAIter __end, _Compare __comp, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_balanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) diff --git a/libstdc++-v3/include/parallel/numeric b/libstdc++-v3/include/parallel/numeric index 825463502a6..e89f27efead 100644 --- a/libstdc++-v3/include/parallel/numeric +++ b/libstdc++-v3/include/parallel/numeric @@ -85,8 +85,7 @@ namespace __parallel __accumulate_switch(__RAIter __begin, __RAIter __end, _Tp __init, _BinaryOperation __binary_op, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_unbalanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) @@ -193,8 +192,7 @@ namespace __parallel _BinaryFunction2 __binary_op2, random_access_iterator_tag, random_access_iterator_tag, - __gnu_parallel::_Parallelism __parallelism_tag - = __gnu_parallel::parallel_unbalanced) + __gnu_parallel::_Parallelism __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION((__last1 - __first1) >= __gnu_parallel::_Settings::get(). @@ -419,8 +417,7 @@ namespace __parallel random_access_iterator_tag, random_access_iterator_tag, __gnu_parallel::_Parallelism - __parallelism_tag - = __gnu_parallel::parallel_balanced) + __parallelism_tag) { if (_GLIBCXX_PARALLEL_CONDITION( static_cast<__gnu_parallel::_SequenceIndex>(__end - __begin) diff --git a/libstdc++-v3/include/std/functional b/libstdc++-v3/include/std/functional index 0e80fa37cf4..fac1c6708f1 100644 --- a/libstdc++-v3/include/std/functional +++ b/libstdc++-v3/include/std/functional @@ -2407,9 +2407,9 @@ _GLIBCXX_HAS_NESTED_TYPE(result_type) { if (static_cast<bool>(__x)) { + __x._M_manager(_M_functor, __x._M_functor, __clone_functor); _M_invoker = __x._M_invoker; _M_manager = __x._M_manager; - __x._M_manager(_M_functor, __x._M_functor, __clone_functor); } } diff --git a/libstdc++-v3/include/std/shared_mutex b/libstdc++-v3/include/std/shared_mutex index 6405f1025ec..c193eb2d90e 100644 --- a/libstdc++-v3/include/std/shared_mutex +++ b/libstdc++-v3/include/std/shared_mutex @@ -36,10 +36,8 @@ #else #include <bits/c++config.h> -#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) -# include <mutex> -# include <condition_variable> -#endif +#include <mutex> +#include <condition_variable> #include <bits/functexcept.h> namespace std _GLIBCXX_VISIBILITY(default) @@ -51,7 +49,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION * @{ */ -#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) +#ifdef _GLIBCXX_USE_C99_STDINT_TR1 +#ifdef _GLIBCXX_HAS_GTHREADS #define __cpp_lib_shared_timed_mutex 201402 @@ -254,7 +253,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION } } }; -#endif // _GLIBCXX_HAS_GTHREADS && _GLIBCXX_USE_C99_STDINT_TR1 +#endif // _GLIBCXX_HAS_GTHREADS /// shared_lock template<typename _Mutex> @@ -393,6 +392,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION swap(shared_lock<_Mutex>& __x, shared_lock<_Mutex>& __y) noexcept { __x.swap(__y); } +#endif // _GLIBCXX_USE_C99_STDINT_TR1 + // @} group mutexes _GLIBCXX_END_NAMESPACE_VERSION } // namespace diff --git a/libstdc++-v3/include/std/tuple b/libstdc++-v3/include/std/tuple index 9b9cf6b5457..6e0577ddf94 100644 --- a/libstdc++-v3/include/std/tuple +++ b/libstdc++-v3/include/std/tuple @@ -88,21 +88,22 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION constexpr _Head_base(const _Head& __h) : _Head(__h) { } - template<typename _UHead, typename = typename - enable_if<!is_convertible<_UHead, - __uses_alloc_base>::value>::type> + constexpr _Head_base(const _Head_base&) = default; + constexpr _Head_base(_Head_base&&) = default; + + template<typename _UHead> constexpr _Head_base(_UHead&& __h) : _Head(std::forward<_UHead>(__h)) { } - _Head_base(__uses_alloc0) + _Head_base(allocator_arg_t, __uses_alloc0) : _Head() { } template<typename _Alloc> - _Head_base(__uses_alloc1<_Alloc> __a) + _Head_base(allocator_arg_t, __uses_alloc1<_Alloc> __a) : _Head(allocator_arg, *__a._M_a) { } template<typename _Alloc> - _Head_base(__uses_alloc2<_Alloc> __a) + _Head_base(allocator_arg_t, __uses_alloc2<_Alloc> __a) : _Head(*__a._M_a) { } template<typename _UHead> @@ -133,21 +134,22 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION constexpr _Head_base(const _Head& __h) : _M_head_impl(__h) { } - template<typename _UHead, typename = typename - enable_if<!is_convertible<_UHead, - __uses_alloc_base>::value>::type> + constexpr _Head_base(const _Head_base&) = default; + constexpr _Head_base(_Head_base&&) = default; + + template<typename _UHead> constexpr _Head_base(_UHead&& __h) : _M_head_impl(std::forward<_UHead>(__h)) { } - _Head_base(__uses_alloc0) + _Head_base(allocator_arg_t, __uses_alloc0) : _M_head_impl() { } template<typename _Alloc> - _Head_base(__uses_alloc1<_Alloc> __a) + _Head_base(allocator_arg_t, __uses_alloc1<_Alloc> __a) : _M_head_impl(allocator_arg, *__a._M_a) { } template<typename _Alloc> - _Head_base(__uses_alloc2<_Alloc> __a) + _Head_base(allocator_arg_t, __uses_alloc2<_Alloc> __a) : _M_head_impl(*__a._M_a) { } template<typename _UHead> @@ -285,7 +287,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _Alloc> _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a) : _Inherited(__tag, __a), - _Base(__use_alloc<_Head>(__a)) { } + _Base(__tag, __use_alloc<_Head>(__a)) { } template<typename _Alloc> _Tuple_impl(allocator_arg_t __tag, const _Alloc& __a, diff --git a/libstdc++-v3/include/tr1/functional b/libstdc++-v3/include/tr1/functional index 20785ff043d..58af9102441 100644 --- a/libstdc++-v3/include/tr1/functional +++ b/libstdc++-v3/include/tr1/functional @@ -2112,9 +2112,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { if (static_cast<bool>(__x)) { + __x._M_manager(_M_functor, __x._M_functor, __clone_functor); _M_invoker = __x._M_invoker; _M_manager = __x._M_manager; - __x._M_manager(_M_functor, __x._M_functor, __clone_functor); } } @@ -2130,9 +2130,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION if (_My_handler::_M_not_empty_function(__f)) { + _My_handler::_M_init_functor(_M_functor, __f); _M_invoker = &_My_handler::_M_invoke; _M_manager = &_My_handler::_M_manager; - _My_handler::_M_init_functor(_M_functor, __f); } } diff --git a/libstdc++-v3/libsupc++/eh_personality.cc b/libstdc++-v3/libsupc++/eh_personality.cc index f315a8341b8..cb4467aa032 100644 --- a/libstdc++-v3/libsupc++/eh_personality.cc +++ b/libstdc++-v3/libsupc++/eh_personality.cc @@ -378,6 +378,12 @@ PERSONALITY_FUNCTION (int version, switch (state & _US_ACTION_MASK) { case _US_VIRTUAL_UNWIND_FRAME: + // If the unwind state pattern is + // _US_VIRTUAL_UNWIND_FRAME | _US_FORCE_UNWIND + // then we don't need to search for any handler as it is not a real + // exception. Just unwind the stack. + if (state & _US_FORCE_UNWIND) + CONTINUE_UNWINDING; actions = _UA_SEARCH_PHASE; break; diff --git a/libstdc++-v3/testsuite/20_util/function/63840.cc b/libstdc++-v3/testsuite/20_util/function/63840.cc new file mode 100644 index 00000000000..cf80aa1dc11 --- /dev/null +++ b/libstdc++-v3/testsuite/20_util/function/63840.cc @@ -0,0 +1,55 @@ +// Copyright (C) 2014 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// { dg-options "-std=gnu++11" } + +#include <functional> +#include <stdexcept> +#include <testsuite_hooks.h> + +struct functor +{ + functor() = default; + + functor(const functor&) + { + throw std::runtime_error("test"); + } + + functor(functor&& f) = default; + + void operator()() const { } +}; + + +void +test01() +{ + std::function<void()> f = functor{}; + try { + auto g = f; + } catch (const std::runtime_error& e) { + return; + } + VERIFY(false); +} + +int +main() +{ + test01(); +} diff --git a/libstdc++-v3/testsuite/20_util/tuple/61947.cc b/libstdc++-v3/testsuite/20_util/tuple/61947.cc new file mode 100644 index 00000000000..7e77de657a1 --- /dev/null +++ b/libstdc++-v3/testsuite/20_util/tuple/61947.cc @@ -0,0 +1,29 @@ +// { dg-options "-std=gnu++11" } +// { dg-do compile } + +// Copyright (C) 2014 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +#include <tuple> + +struct ConvertibleToAny { + template <class T> operator T() const { return T(); } +}; + +int main() { + std::tuple<ConvertibleToAny&&> t(ConvertibleToAny{}); +} diff --git a/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc b/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc index 5ce344c377f..898406ffaa9 100644 --- a/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc +++ b/libstdc++-v3/testsuite/20_util/uses_allocator/cons_neg.cc @@ -44,4 +44,4 @@ void test01() tuple<Type> t(allocator_arg, a, 1); } -// { dg-error "no matching function" "" { target *-*-* } 118 } +// { dg-error "no matching function" "" { target *-*-* } 119 } diff --git a/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc b/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc new file mode 100644 index 00000000000..32b7e241cb0 --- /dev/null +++ b/libstdc++-v3/testsuite/28_regex/iterators/regex_iterator/char/64140.cc @@ -0,0 +1,53 @@ +// { dg-options "-std=gnu++11" } + +// +// Copyright (C) 2014 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +// libstdc++/64140 + +#include <regex> +#include <testsuite_hooks.h> + +void +test01() +{ + bool test __attribute__((unused)) = true; + + const std::regex e("z*"); + const std::string s("ab"); + + auto it = std::sregex_iterator(s.begin(), s.end(), e); + auto end = std::sregex_iterator(); + VERIFY(it != end); + VERIFY(!it->prefix().matched); + ++it; + VERIFY(it != end); + VERIFY(it->prefix().matched); + ++it; + VERIFY(it != end); + VERIFY(it->prefix().matched); + ++it; + VERIFY(it == end); +} + +int +main() +{ + test01(); + return 0; +} diff --git a/libstdc++-v3/testsuite/experimental/feat-cxx14.cc b/libstdc++-v3/testsuite/experimental/feat-cxx14.cc index 1c590dd841b..2cc31ca03be 100644 --- a/libstdc++-v3/testsuite/experimental/feat-cxx14.cc +++ b/libstdc++-v3/testsuite/experimental/feat-cxx14.cc @@ -106,10 +106,12 @@ # error "<shared_mutex>" #endif -#ifndef __cpp_lib_shared_timed_mutex -# error "__cpp_lib_shared_timed_mutex" -#elif __cpp_lib_shared_timed_mutex != 201402 -# error "__cpp_lib_shared_timed_mutex != 201402" +#if defined(_GLIBCXX_HAS_GTHREADS) && defined(_GLIBCXX_USE_C99_STDINT_TR1) +# ifndef __cpp_lib_shared_timed_mutex +# error "__cpp_lib_shared_timed_mutex" +# elif __cpp_lib_shared_timed_mutex != 201402 +# error "__cpp_lib_shared_timed_mutex != 201402" +# endif #endif #ifndef __cpp_lib_is_final diff --git a/libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc b/libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc new file mode 100644 index 00000000000..760d490f2b2 --- /dev/null +++ b/libstdc++-v3/testsuite/tr1/3_function_objects/function/63840.cc @@ -0,0 +1,55 @@ +// Copyright (C) 2014 Free Software Foundation, Inc. +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +#include <tr1/functional> +#include <stdexcept> +#include <testsuite_hooks.h> + +struct functor +{ + functor() : copies(0) { } + + functor(const functor& f) + : copies(f.copies + 1) + { + if (copies > 1) + throw std::runtime_error("functor"); + } + + void operator()() const { } + + int copies; +}; + + +void +test01() +{ + std::tr1::function<void()> f = functor(); + try { + std::tr1::function<void()> g = f; + } catch (const std::runtime_error& e) { + return; + } + VERIFY(false); +} + +int +main() +{ + test01(); +} |