seems to be working

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/kelvin-rfc2506@234688 138bc75d-0d04-0410-961f-82ee72b054a4

6 files changed, 75 insertions, 1 deletions

diff --git a/gcc/config/rs6000/altivec.h b/gcc/config/rs6000/altivec.h
index 436e9eae847..c286d02a4a9 100644
--- a/gcc/config/rs6000/altivec.h
+++ b/gcc/config/rs6000/altivec.h
@@ -393,6 +393,12 @@
 #define vec_vctzh __builtin_vec_vctzh
 #define vec_vctzw __builtin_vec_vctzw
 
+/* kelvin not sure how to name these.  I've launched an inquiry to 
+ * Michael Meissner.
+ */
+#define vec_slv __builtin_vec_vslv
+#define vec_srv __builtin_vec_vsrv
+
 /* Non-Vector additions added in ISA 3.0. */
 #define darn __builtin_darn
 #define darn_32 __builtin_darn_32
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 16b7cb82ebe..296c94e10e5 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1,4 +1,4 @@
-;; AltiVec patterns.
+; AltiVec patterns.
 ;; Copyright (C) 2002-2016 Free Software Foundation, Inc.
 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
 
@@ -114,6 +114,8 @@
    UNSPEC_STVLXL
    UNSPEC_STVRX
    UNSPEC_STVRXL
+   UNSPEC_VSLV
+   UNSPEC_VSRV
    UNSPEC_VMULWHUB
    UNSPEC_VMULWLUB
    UNSPEC_VMULWHSB
@@ -1632,6 +1634,30 @@
   "vslo %0,%1,%2"
   [(set_attr "type" "vecperm")])
 
+;;
+;; kelvin wants this pattern to look for unsigned operands
+;;
+(define_insn "vslv"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+		       (match_operand:V16QI 2 "register_operand" "v")]
+         UNSPEC_VSLV))]
+  "TARGET_P9_VECTOR"
+  "vslv %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
+
+;;
+;; kelvin wants this pattern to look for unsigned operands
+;;
+(define_insn "vsrv"
+  [(set (match_operand:V16QI 0 "register_operand" "=v")
+	(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
+		       (match_operand:V16QI 2 "register_operand" "v")]
+         UNSPEC_VSRV))]
+  "TARGET_P9_VECTOR"
+  "vsrv %0,%1,%2"
+  [(set_attr "type" "vecsimple")])
+
 (define_insn "*altivec_vsl<VI_char>"
   [(set (match_operand:VI2 0 "register_operand" "=v")
         (ashift:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index ad03251555c..12ed95e8532 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1773,6 +1773,14 @@ BU_P9V_OVERLOAD_1 (VCTZH,	"vctzh")
 BU_P9V_OVERLOAD_1 (VCTZW,	"vctzw")
 BU_P9V_OVERLOAD_1 (VCTZD,	"vctzd")
 
+/* ISA 3.0 vector overloaded 2-argument functions. */
+BU_P9V_AV_2 (VSLV,		"vslv",			CONST, vslv)
+BU_P9V_AV_2 (VSRV,		"vsrv",			CONST, vsrv)
+
+/* ISA 3.0 vector overloaded 2-argument functions. */
+BU_P9V_OVERLOAD_2 (VSLV,	"vslv")
+BU_P9V_OVERLOAD_2 (VSRV,	"vsrv")
+
 
 /* 1 argument crypto functions.  */
 BU_CRYPTO_1 (VSBOX,		"vsbox",	  CONST, crypto_vsbox)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 76b90f4092d..dc7a87af6a3 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4365,6 +4365,13 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD,
     RS6000_BTI_unsigned_V16QI, 0, 0, 0 },
 
+  { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV,
+    RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
+  { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV,
+    RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+    RS6000_BTI_unsigned_V16QI, 0 },
+
   /* Crypto builtins.  */
   { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI,
     RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 3983c3b8f08..ba7ceb312e2 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -1066,6 +1066,7 @@
   "")
 
 ;; Expanders for arithmetic shift left on each vector element
+;; kelvin says this is where the existing builtin comes, with <mode> = v16qi
 (define_expand "vashl<mode>3"
   [(set (match_operand:VEC_I 0 "vint_operand" "")
 	(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 7e9ad7757d5..68614847fc1 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -13865,6 +13865,10 @@ or @option{-mmodulo}):
 long long __builtin_darn (void);
 long long __builtin_darn_raw (void);
 int __builtin_darn_32 (void);
+__vector unsigned char vec_slv (__vector unsigned char src, 
+__vector unsigned char shift_distance);
+__vector unsigned char vec_srv (__vector unsigned char src, 
+__vector unsigned char shift_distance);
 @end smallexample
 
 The @code{__builtin_darn} and @code{__builtin_darn_raw}
@@ -13875,6 +13879,28 @@ random number.  The @code{__builtin_darn_raw} function provides a
 64-bit raw random number.  The @code{__builtin_darn_32} function
 provides a 32-bit random number.
 
+Tne @code{vec_slv} and @code{vec_srv} functions operate in parallel on
+all of the bytes of their @code{src} and @code{shift_distance}
+arguments in parallel.  The behavior of the @code{vec_slv} is as if
+there existed a temporary array of 17 unsigned characters
+@code{slv_array} within which elements 0 through 15 are the same as
+the entries in the @code{src} array and element 16 equals 0.  The
+result returned from the @code{slv_array} function is a
+@code{__vector} of 16 unsigned characters within which element
+@code{i} is computed using the C expression 
+@code{0xff & (*((unsigned short *)(slv_array + i)) << shift_distance[i])}, 
+with this resulting value coerced to the @code{unsigned char} type.
+The behavior of the @code{vec_srv} is as if
+there existed a temporary array of 17 unsigned characters
+@code{srv_array} within which element 0 equals zero and 
+elements 1 through 16 equal the elements 0 through 15 of 
+the @code{src} array.  The
+result returned from the @code{srv_array} function is a
+@code{__vector} of 16 unsigned characters within which element
+@code{i} is computed using the C expression 
+@code{0xff & (*((unsigned short *)(srv_array + i)) >> shift_distance[i])}, 
+with this resulting value coerced to the @code{unsigned char} type.
+
 The following built-in functions are available for the PowerPC family
 of processors when hardware decimal floating point
 (@option{-mhard-dfp}) is available: