diff options
author | Jakub Jelinek <jakub@redhat.com> | 2016-05-24 19:10:55 +0000 |
---|---|---|
committer | Jakub Jelinek <jakub@redhat.com> | 2016-05-24 19:10:55 +0000 |
commit | 0d21854f75259517f6ba305a7cec2cb251a97841 (patch) | |
tree | cf423fd5ae14a32fe59ef3c9b46aeda324c59f63 | |
parent | c318c67645e542bedbb8790a70166714b285bba0 (diff) |
* config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Limit
first two alternatives to noavx, use *x instead of *v in the second
one, add avx alternative without *.
(sse4_1_<code>v4qiv4si2<mask_name>, sse4_1_<code>v4hiv4si2<mask_name>,
sse4_1_<code>v2qiv2di2<mask_name>, sse4_1_<code>v2hiv2di2<mask_name>,
sse4_1_<code>v2siv2di2<mask_name>): Likewise.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@236659 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/config/i386/sse.md | 54 |
2 files changed, 39 insertions, 24 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 9442109e448..f6bc9451c48 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-05-24 Jakub Jelinek <jakub@redhat.com> + + * config/i386/sse.md (sse4_1_<code>v8qiv8hi2<mask_name>): Limit + first two alternatives to noavx, use *x instead of *v in the second + one, add avx alternative without *. + (sse4_1_<code>v4qiv4si2<mask_name>, sse4_1_<code>v4hiv4si2<mask_name>, + sse4_1_<code>v2qiv2di2<mask_name>, sse4_1_<code>v2hiv2di2<mask_name>, + sse4_1_<code>v2siv2di2<mask_name>): Likewise. + 2016-05-24 Jeff Law <law@redhat.com> * tree-ssa-threadbackwards.c (convert_and_register_jump_thread_path): diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 745b6b665f5..742c83ea13c 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14748,19 +14748,20 @@ (set_attr "mode" "XI")]) (define_insn "sse4_1_<code>v8qiv8hi2<mask_name>" - [(set (match_operand:V8HI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] "TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>" "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>" @@ -14790,17 +14791,18 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_<code>v4qiv4si2<mask_name>" - [(set (match_operand:V4SI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI (vec_select:V4QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_<code>v16hiv16si2<mask_name>" @@ -14825,17 +14827,18 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_<code>v4hiv4si2<mask_name>" - [(set (match_operand:V4SI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_<code>v8qiv8di2<mask_name>" @@ -14868,16 +14871,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_<code>v2qiv2di2<mask_name>" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2QI - (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V16QI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %w1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_<code>v8hiv8di2<mask_name>" @@ -14905,16 +14909,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_<code>v2hiv2di2<mask_name>" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2HI - (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V8HI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %k1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) (define_insn "avx512f_<code>v8siv8di2<mask_name>" @@ -14939,16 +14944,17 @@ (set_attr "mode" "OI")]) (define_insn "sse4_1_<code>v2siv2di2<mask_name>" - [(set (match_operand:V2DI 0 "register_operand" "=Yr,*v") + [(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v") (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "Yrm,*vm") + (match_operand:V4SI 1 "nonimmediate_operand" "Yrm,*xm,vm") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE4_1 && <mask_avx512vl_condition>" "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %q1}" - [(set_attr "type" "ssemov") + [(set_attr "isa" "noavx,noavx,avx") + (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "maybe_vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "TI")]) ;; ptestps/ptestpd are very similar to comiss and ucomiss when |