diff options
| author | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-05-24 11:32:35 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <kyrylo.tkachov@arm.com> | 2016-05-24 11:32:35 +0000 |
| commit | 2595ead46dc97ebb828a29f1e3ec593ef55e8852 (patch) | |
| tree | 24097259ebb3b9054ef44887d4cd02eb030d934c | |
| parent | 425b195d9e9d290944f01f1650a3edc8b3dd71fe (diff) | |
[ARM] PR target/69857 Remove bogus early return false; in gen_operands_ldrd_strd
PR target/69857
* config/arm/arm.c (gen_operands_ldrd_strd): Remove bogus early
return. Reindent transformation comment and mention the ARM state
behavior.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@236635 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 18 |
2 files changed, 17 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4dc6e7de1a5..433493df542 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2016-05-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com> + + PR target/69857 + * config/arm/arm.c (gen_operands_ldrd_strd): Remove bogus early + return. Reindent transformation comment and mention the ARM state + behavior. + 2016-05-24 Kugan Vivekanandarajah <kuganv@linaro.org> PR middle-end/71252 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index af9725b93d4..a4f474baea8 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -15982,14 +15982,17 @@ gen_operands_ldrd_strd (rtx *operands, bool load, /* If the same input register is used in both stores when storing different constants, try to find a free register. For example, the code - mov r0, 0 - str r0, [r2] - mov r0, 1 - str r0, [r2, #4] + mov r0, 0 + str r0, [r2] + mov r0, 1 + str r0, [r2, #4] can be transformed into - mov r1, 0 - strd r1, r0, [r2] - in Thumb mode assuming that r1 is free. */ + mov r1, 0 + mov r0, 1 + strd r1, r0, [r2] + in Thumb mode assuming that r1 is free. + For ARM mode do the same but only if the starting register + can be made to be even. */ if (const_store && REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[4]) != INTVAL (operands[5])) @@ -16008,7 +16011,6 @@ gen_operands_ldrd_strd (rtx *operands, bool load, } else if (TARGET_ARM) { - return false; int regno = REGNO (operands[0]); if (!peep2_reg_dead_p (4, operands[0])) { |