fix semicolons in extend.texiibm/rfc2467.2

git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ibm/rfc2467.2@241038 138bc75d-0d04-0410-961f-82ee72b054a4

11 files changed, 71 insertions, 90 deletions

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 4feebf7eeed..703baebcf7c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -162,7 +162,7 @@
    UNSPECV_DSS
   ])
 
-;; Like VI, but add ISA 2.07 integer vector ops
+;; Like VI, defined in vector.md, but add ISA 2.07 integer vector ops
 (define_mode_iterator VI2 [V4SI V8HI V16QI V2DI])
 ;; Short vec in modes
 (define_mode_iterator VIshort [V8HI V16QI])
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 748e44dabde..d21f27580a7 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2019,8 +2019,8 @@ BU_P9V_OVERLOAD_2 (VEXTURX,	"vexturx")
    so is not mentioned here.  */
 BU_P9V_OVERLOAD_2 (CMPNEZ,	"vcmpnez")
 
-BU_P9V_OVERLOAD_P (VCMPNEZ_P,   "vcmpnez_p")
-BU_P9V_OVERLOAD_P (VCMPNE_P,   "vcmpne_p")
+BU_P9V_OVERLOAD_P (VCMPNEZ_P,	"vcmpnez_p")
+BU_P9V_OVERLOAD_P (VCMPNE_P,	"vcmpne_p")
 
 /* ISA 3.0 Vector scalar overloaded 1 argument functions */
 BU_P9V_OVERLOAD_1 (VCLZLSBB,	"vclzlsbb")
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index be6261bfbe2..de66dadac79 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -4568,10 +4568,10 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI,
-    RS6000_BTI_V4SI }, 
+    RS6000_BTI_V4SI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI,
-    RS6000_BTI_bool_V4SI }, 
+    RS6000_BTI_bool_V4SI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P,
@@ -4581,18 +4581,18 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
-    RS6000_BTI_unsigned_V2DI }, 
+    RS6000_BTI_unsigned_V2DI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
-      RS6000_BTI_bool_V2DI }, 
+      RS6000_BTI_bool_V2DI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
-    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 
+    RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI,
     RS6000_BTI_unsigned_V2DI },
 
   /* The following 2 entries have been deprecated.  */
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI,
-    RS6000_BTI_V2DI }, 
+    RS6000_BTI_V2DI },
   { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P,
     RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI,
     RS6000_BTI_bool_V2DI },
@@ -4674,7 +4674,7 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
     RS6000_BTI_INTSI, RS6000_BTI_UINTSI,
     RS6000_BTI_V4SI, 0 },
   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
-    RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 
+    RS6000_BTI_UINTSI, RS6000_BTI_UINTSI,
     RS6000_BTI_unsigned_V4SI, 0 },
   { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX,
     RS6000_BTI_float, RS6000_BTI_UINTSI,
@@ -5210,7 +5210,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
 
       /* Power9 instructions provide the most efficient implementation of
 	 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode.  */
-      if (!TARGET_P9_VECTOR 
+      if (!TARGET_P9_VECTOR
 	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode)
 	  || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode))
 	{
@@ -5219,13 +5219,13 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
 	    goto bad;
 	  if (TREE_CODE (arg0_type) != VECTOR_TYPE)
 	    goto bad;
-	  
-	  
+
+
 	  switch (TYPE_MODE (TREE_TYPE (arg0_type)))
 	    {
 	      /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb),
 		 vec_cmpeq (va, vb)).  */
-	      /* Note:  vec_nand also works but opt changes vec_nand's 
+	      /* Note:  vec_nand also works but opt changes vec_nand's
 		 to vec_nor's anyway.  */
 	    case QImode:
 	    case HImode:
@@ -5241,7 +5241,7 @@ altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
 		vec_safe_push (params, arg0);
 		vec_safe_push (params, arg1);
 		tree call = altivec_resolve_overloaded_builtin
-		  (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ], 
+		  (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ],
 		   params);
 		/* Use save_expr to ensure that operands used more than once
 		   that may have side effects (like calls) are only evaluated
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f7f483e3250..5ce82b131f1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -13873,7 +13873,7 @@ altivec_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
     op1 = copy_to_mode_reg (mode1, op1);
 
   /* Note that for many of the relevant operations (e.g. cmpne or
-     cmpeq) with float or double operands, it makes most sense for the
+     cmpeq) with float or double operands, it makes more sense for the
      mode of the allocated scratch register to select a vector of
      integer.  But the choice to copy the mode of operand 0 was made
      long ago and there are no plans to change it.  */
@@ -14221,7 +14221,6 @@ altivec_expand_stxvl_builtin (enum insn_code icode, tree exp)
   rtx op0 = expand_normal (arg0);
   rtx op1 = expand_normal (arg1);
   rtx op2 = expand_normal (arg2);
-  /*  machine_mode tmode = insn_data[icode].operand[0].mode; */
   machine_mode mode0 = insn_data[icode].operand[0].mode;
   machine_mode mode1 = insn_data[icode].operand[1].mode;
   machine_mode mode2 = insn_data[icode].operand[2].mode;
@@ -17181,7 +17180,7 @@ altivec_init_builtins (void)
   def_builtin ("__builtin_vec_stvrx",  void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRX);
   def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_VEC_STVRXL);
 
-  def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long, 
+  def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long,
 	       P9V_BUILTIN_STXVL);
 
   /* Add the DST variants.  */
@@ -17792,6 +17791,7 @@ rs6000_common_init_builtins (void)
 
 	      continue;
 	    }
+
 	  type = builtin_function_type (insn_data[icode].operand[0].mode,
 					insn_data[icode].operand[1].mode,
 					insn_data[icode].operand[2].mode,
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index a97435e8437..aff99a91b2d 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -689,11 +689,11 @@
 ;; on Power9.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
-	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand" "")
-			     (match_operand:VI 2 "vlogical_operand" ""))]
+    [(set (reg:CC CR6_REGNO)
+	  (unspec:CC [(ne:CC (match_operand:VI 1 "vlogical_operand")
+			     (match_operand:VI 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
-     (set (match_operand:VI 0 "vlogical_operand" "")
+     (set (match_operand:VI 0 "vlogical_operand")
 	  (ne:VI (match_dup 1)
 		 (match_dup 2)))])]
   "TARGET_P9_VECTOR"
@@ -704,13 +704,13 @@
 ;; functions on Power9.
 (define_expand "vector_nez_<mode>_p"
   [(parallel
-    [(set (reg:CC 74)
+    [(set (reg:CC CR6_REGNO)
 	  (unspec:CC [(unspec:VI
-		       [(match_operand:VI 1 "vlogical_operand" "")
-			(match_operand:VI 2 "vlogical_operand" "")]
+		       [(match_operand:VI 1 "vlogical_operand")
+			(match_operand:VI 2 "vlogical_operand")]
 		       UNSPEC_NEZ_P)]
 	   UNSPEC_PREDICATE))
-     (set (match_operand:VI 0 "vlogical_operand" "")
+     (set (match_operand:VI 0 "vlogical_operand")
 	  (unspec:VI [(match_dup 1)
 		      (match_dup 2)]
 	   UNSPEC_NEZ_P))])]
@@ -728,11 +728,11 @@
 ;; likewise in the test for "any equal".)
 (define_expand "vector_ne_v2di_p"
   [(parallel
-    [(set (reg:CC 74)
-	  (unspec:CC [(ne:CC (match_operand:V4SI 1 "vlogical_operand" "")
-			     (match_operand:V4SI 2 "vlogical_operand" ""))]
+    [(set (reg:CC CR6_REGNO)
+	  (unspec:CC [(ne:CC (match_operand:V4SI 1 "vlogical_operand")
+			     (match_operand:V4SI 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
-     (set (match_operand:V4SI 0 "vlogical_operand" "")
+     (set (match_operand:V4SI 0 "vlogical_operand")
 	  (ne:V4SI (match_dup 1)
 		   (match_dup 2)))])]
   "TARGET_P9_VECTOR"
@@ -740,14 +740,14 @@
 
 ;; This expansion handles the V4SF and V2DF modes in the Power9
 ;; implementation of the vec_all_ne and vec_any_eq built-in
-;; functions. 
+;; functions.
 (define_expand "vector_ne_<mode>_p"
   [(parallel
     [(set (reg:CC 74)
-	  (unspec:CC [(ne:CC (match_operand:VEC_F 1 "vlogical_operand" "")
-			     (match_operand:VEC_F 2 "vlogical_operand" ""))]
+	  (unspec:CC [(ne:CC (match_operand:VEC_F 1 "vlogical_operand")
+			     (match_operand:VEC_F 2 "vlogical_operand"))]
 	   UNSPEC_PREDICATE))
-     (set (match_operand:VEC_F 0 "vlogical_operand" "")
+     (set (match_operand:VEC_F 0 "vlogical_operand")
 	  (ne:VEC_F (match_dup 1)
 		    (match_dup 2)))])]
   "TARGET_P9_VECTOR"
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c2e8b7c9643..1c87135a99e 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -272,7 +272,7 @@
 (define_mode_attr VSX_EXTRACT_WIDTH [(V16QI "b")
 		  		     (V8HI "h")
 				     (V4SI "w")])
-				    
+
 ;; Mode attribute to give the correct predicate for ISA 3.0 vector extract and
 ;; insert to validate the operand number.
 (define_mode_attr VSX_EXTRACT_PREDICATE [(V16QI "const_0_to_15_operand")
@@ -3203,14 +3203,14 @@
   "xvtstdc<VSs> %x0,%x1,%2"
   [(set_attr "type" "vecsimple")])
 
-;; ISA 3.0 String Operations (VSU) Support
+;; ISA 3.0 String Operations Support
 
-;; Compare vectors producing a vector result and a predicate, setting CR6 
+;; Compare vectors producing a vector result and a predicate, setting CR6
 ;; to indicate a combined status.  This pattern matches v16qi, v8hi, and
 ;; v4si modes.  It does not match v2df, v4sf, or v2di modes.  There's no
 ;; need to match the v2di mode because that is expanded into v4si.
 (define_insn "*vsx_ne_<mode>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
 	(unspec:CC
 	 [(ne:CC (match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "v")
 		 (match_operand:VSX_EXTRACT_I 2 "gpc_reg_operand" "v"))]
@@ -3222,10 +3222,10 @@
   "xvcmpne<VSX_EXTRACT_WIDTH>. %0,%1,%2"
   [(set_attr "type" "vecsimple")])
 
-;; Compare vectors producing a vector result and a predicate, setting CR6 
+;; Compare vectors producing a vector result and a predicate, setting CR6
 ;; to indicate a combined status, for v4sf and v2df operands.
 (define_insn "*vsx_ne_<mode>_p"
-  [(set (reg:CC 74)
+  [(set (reg:CC CR6_REGNO)
 	(unspec:CC [(ne:CC
 		     (match_operand:VSX_F 1 "vsx_register_operand" "wa")
 		     (match_operand:VSX_F 2 "vsx_register_operand" "wa"))]
@@ -3270,7 +3270,7 @@
   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
 	(unspec:V16QI
 	 [(match_operand:DI 1 "gpc_reg_operand" "b")
-	  (match_operand:DI 2 "register_operand" "r")]
+	  (match_operand:DI 2 "register_operand" "+r")]
 	 UNSPEC_LXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
   "sldi %2,%2, 56\; lxvl %x0,%1,%2"
@@ -3295,7 +3295,7 @@
   [(set (mem:V16QI (match_operand:DI 1 "gpc_reg_operand" "b"))
 	(unspec:V16QI
 	 [(match_operand:V16QI 0 "vsx_register_operand" "wa")
-	  (match_operand:DI 2 "register_operand" "r")]
+	  (match_operand:DI 2 "register_operand" "+r")]
 	 UNSPEC_STXVL))]
   "TARGET_P9_VECTOR && TARGET_64BIT"
   "sldi %2,%2\;stxvl %x0,%1,%2"
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 1875d84f4d0..7316038d32a 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -15025,29 +15025,29 @@ of processors, starting with ISA 3.0 or later
 separately in order to group the descriptions closer to the function
 prototypes:
 @smallexample
-int vec_all_nez (vector signed char, vector signed char)
-int vec_all_nez (vector unsigned char, vector unsigned char)
-int vec_all_nez (vector signed short, vector signed short)
-int vec_all_nez (vector unsigned short, vector unsigned short)
-int vec_all_nez (vector signed int, vector signed int)
-int vec_all_nez (vector unsigned int, vector unsigned int)
-
-int vec_any_eqz (vector signed char, vector signed char)
-int vec_any_eqz (vector unsigned char, vector unsigned char)
-int vec_any_eqz (vector signed short, vector signed short)
-int vec_any_eqz (vector unsigned short, vector unsigned short)
-int vec_any_eqz (vector signed int, vector signed int)
-int vec_any_eqz (vector unsigned int, vector unsigned int)
-
-vector bool char vec_cmpnez (vector signed char arg1, vector signed char arg2)
-vector bool char vec_cmpnez (vector unsigned char arg1, vector unsigned char arg2)
-vector bool short vec_cmpnez (vector signed short arg1, vector signed short arg2)
-vector bool short vec_cmpnez (vector unsigned short arg1, vector unsigned short arg2)
+int vec_all_nez (vector signed char, vector signed char);
+int vec_all_nez (vector unsigned char, vector unsigned char);
+int vec_all_nez (vector signed short, vector signed short);
+int vec_all_nez (vector unsigned short, vector unsigned short);
+int vec_all_nez (vector signed int, vector signed int);
+int vec_all_nez (vector unsigned int, vector unsigned int);
+
+int vec_any_eqz (vector signed char, vector signed char);
+int vec_any_eqz (vector unsigned char, vector unsigned char);
+int vec_any_eqz (vector signed short, vector signed short);
+int vec_any_eqz (vector unsigned short, vector unsigned short);
+int vec_any_eqz (vector signed int, vector signed int);
+int vec_any_eqz (vector unsigned int, vector unsigned int);
+
+vector bool char vec_cmpnez (vector signed char arg1, vector signed char arg2);
+vector bool char vec_cmpnez (vector unsigned char arg1, vector unsigned char arg2);
+vector bool short vec_cmpnez (vector signed short arg1, vector signed short arg2);
+vector bool short vec_cmpnez (vector unsigned short arg1, vector unsigned short arg2);
 vector bool int vec_cmpnez (vector signed int arg1, vector signed int arg2);
 vector bool int vec_cmpnez (vector unsigned int, vector unsigned int);
 
 signed int vec_cntlz_lsbb (vector signed char);
-signed int vec_cntlz_lsbb (vector unsigned char)
+signed int vec_cntlz_lsbb (vector unsigned char);
 
 signed int vec_cnttz_lsbb (vector signed char);
 signed int vec_cnttz_lsbb (vector unsigned char);
@@ -15070,7 +15070,7 @@ void vec_xst_len (vector unsigned char data, unsigned char *addr, size_t len);
 void vec_xst_len (vector signed int data, signed int *addr, size_t len);
 void vec_xst_len (vector unsigned int data, unsigned int *addr, size_t len);
 void vec_xst_len (vector unsigned __int128 data, unsigned __int128 *addr, size_t len);
-void vec_xst_len (vector signed long long data, signed long long *addr, size_t len)
+void vec_xst_len (vector signed long long data, signed long long *addr, size_t len);
 void vec_xst_len (vector unsigned long long data, unsigned long long *addr, size_t len);
 void vec_xst_len (vector signed short data, signed short *addr, size_t len);
 void vec_xst_len (vector unsigned short data, unsigned short *addr, size_t len);
@@ -15124,7 +15124,7 @@ function loads a variable length vector from memory.  The
 @code{vec_xst_len} function stores a variable length vector to memory.
 With both the @code{vec_xl_len} and @code{vec_xst_len} functions, the
 @code{addr} argument represents the memory address to or from which
-data will be transferred, and the 
+data will be transferred, and the
 @code{len} argument represents the number of bytes to be
 transferred, as computed by the C expression @code{min((len & 0xff), 16)}.
 If this expression's value is not a multiple of the vector element's
@@ -15134,9 +15134,9 @@ big-endian mode, the data transfer moves bytes 0 to @code{len} - 1 of
 the corresponding vector.  In little-endian mode, the data transfer
 moves bytes 16 - @code{len} to 15 of the corresponding vector.  For the
 load function, any bytes of the result vector that are not loaded from
-memory are set to zero.  
+memory are set to zero.
 The value of the @code{addr} argument need not be aligned on a
-multiple of the vector's element size.  
+multiple of the vector's element size.
 
 The @code{vec_xlx} and @code{vec_xrx} functions extract the single
 element selected by the @code{index} argument from the vector
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
index e28cbb3a2c0..58d364131ba 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xl-len-13.c
@@ -14,5 +14,5 @@
 __vector float
 fetch_data (float *address, size_t length)
 {
-  return vec_xl_len (address, length);	/* { dg-error "Builtin function __builtin_vec_lxvl not supported in this configuration" } */
+  return __builtin_vec_lxvl (address, length);	/* { dg-error "Builtin function __builtin_vec_lxvl not supported in this compiler configuration" } */
 }
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c
index 8504d532d49..cc07b3a7f64 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-13.c
@@ -11,9 +11,9 @@
    error should be issued because this built-in function is not
    available on 32-bit configurations. */
 void
-store_data (vector double *datap, souble *address, size_t length)
+store_data (vector double *datap, double *address, size_t length)
 {
   vector double data = *datap;
 
-  vec_xst_len (data, address, length); /* { dg-error "Builtin function __builtin_vec_xst not supported in this configuration" } */
+  __builtin_vec_stxvl (data, address, length); /* { dg-error "Builtin function __builtin_altivec_stxvl requires" } */
 }
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-14.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-14.c
deleted file mode 100644
index d3210072037..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-14.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile { target { powerpc*-*-* } } } */
-/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mcpu=power9" } */
-
-#include <stddef.h>
-#include <altivec.h>
-
-void
-store_data (vector signed __int128 *datap, signed __int128 *address,
-	    size_t length)
-{
-  vector signed __int128 data = *datap;
-
-  vec_xst_len (data, address, length);
-}
-
-/* { dg-final { scan-assembler "sldi" } } */
-/* { dg-final { scan-assembler "stxvl" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c
index 5feb672c26b..d3210072037 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-xst-len-4.c
@@ -8,9 +8,10 @@
 #include <altivec.h>
 
 void
-store_data (vector unsigned int *datap, unsigned int *address, size_t length)
+store_data (vector signed __int128 *datap, signed __int128 *address,
+	    size_t length)
 {
-  vector unsigned int data = *datap;
+  vector signed __int128 data = *datap;
 
   vec_xst_len (data, address, length);
 }