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authorUros Bizjak <ubizjak@gmail.com>2011-11-26 10:55:09 +0000
committerUros Bizjak <ubizjak@gmail.com>2011-11-26 10:55:09 +0000
commit6cdc48c8f4805c01f80a96ad637d0cb2f71a94cd (patch)
tree68e5f5d51955cac4e90eacfe13c5d0b2739a5d48
parent0abb887d7eac4d455aa7ed5d8ebba7bb816aa802 (diff)
* config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@181739 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog4
-rw-r--r--gcc/config/i386/sync.md4
2 files changed, 6 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 289ed643633..bb63950d69d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2011-11-26 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.
+
2011-11-26 Joern Rennecke <joern.rennecke@embecosm.com>
PR middle-end/50074
diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 542d3b87882..5799b0aca50 100644
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -123,7 +123,7 @@
DONE;
})
-;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations,
+;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations,
;; Only beginning at Pentium family processors do we get any guarantee of
;; atomicity in aligned 64-bit quantities. Beginning at P6, we get a
;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
@@ -281,7 +281,7 @@
(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_MOVA))
(clobber (match_operand:DF 2 "register_operand" "=f"))]
"TARGET_80387"
- "fild\t%1\;fistp\t%0"
+ "fild%Z1\t%1\;fistp%Z0\t%0"
[(set_attr "type" "multi")
;; Worst case based on full sib+offset32 addressing modes
(set_attr "length" "14")])