[AArch64, 2/6] Reimplement vector fixed-point intrinsics

	* config/aarch64/aarch64-builtins.def (scvtf): Register vector modes.
	(ucvtf): Likewise.
	(fcvtzs): Likewise.
	(fcvtzu): Likewise.
	* config/aarch64/aarch64-simd.md
	(<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3): New.
	(<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3): Likewise.
	* config/aarch64/arm_neon.h (vcvt_n_f32_s32): Remove inline assembly.
	Use builtin.
	(vcvt_n_f32_u32): Likewise.
	(vcvt_n_s32_f32): Likewise.
	(vcvt_n_u32_f32): Likewise.
	(vcvtq_n_f32_s32): Likewise.
	(vcvtq_n_f32_u32): Likewise.
	(vcvtq_n_f64_s64): Likewise.
	(vcvtq_n_f64_u64): Likewise.
	(vcvtq_n_s32_f32): Likewise.
	(vcvtq_n_s64_f64): Likewise.
	(vcvtq_n_u32_f32): Likewise.
	(vcvtq_n_u64_f64): Likewise.
	* config/aarch64/iterators.md (VDQ_SDI): New mode iterator.
	(VSDQ_SDI): Likewise.
	(fcvt_target): Support V4DI, V4SI and V2SI.
	(FCVT_TARGET): Likewise.



git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@237201 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 163 insertions, 178 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 937e86b3691..9f6f3da351d 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,37 +1,64 @@
 2016-06-08  Jiong Wang  <jiong.wang@arm.com>
 
-        * config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New
-        (TYPES_BINOP_SUS): Likewise.
-        (aarch64_simd_builtin_data): Update include file name.
-        (aarch64_builtins): Likewise.
-        * config/aarch64/aarch64-simd-builtins.def (scvtf): New entries
-        for conversion between scalar float-point and fixed-point.
-        (ucvtf): Likewise.
-        (fcvtzs): Likewise.
-        (fcvtzu): Likewise.
-        * config/aarch64/aarch64.md
-        (<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3: New
-        pattern for conversion between scalar float to fixed-pointer.
-        (<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>: Likewise.
-        (UNSPEC_FCVTZS): New UNSPEC enumeration.
-        (UNSPEC_FCVTZU): Likewise.
-        (UNSPEC_SCVTF): Likewise.
-        (UNSPEC_UCVTF): Likewise.
-        * config/aarch64/arm_neon.h (vcvtd_n_f64_s64): Remove inline assembly.
+	* config/aarch64/aarch64-builtins.def (scvtf): Register vector modes.
+	(ucvtf): Likewise.
+	(fcvtzs): Likewise.
+	(fcvtzu): Likewise.
+	* config/aarch64/aarch64-simd.md
+	(<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3): New.
+	(<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3): Likewise.
+	* config/aarch64/arm_neon.h (vcvt_n_f32_s32): Remove inline assembly.
+	Use builtin.
+	(vcvt_n_f32_u32): Likewise.
+	(vcvt_n_s32_f32): Likewise.
+	(vcvt_n_u32_f32): Likewise.
+	(vcvtq_n_f32_s32): Likewise.
+	(vcvtq_n_f32_u32): Likewise.
+	(vcvtq_n_f64_s64): Likewise.
+	(vcvtq_n_f64_u64): Likewise.
+	(vcvtq_n_s32_f32): Likewise.
+	(vcvtq_n_s64_f64): Likewise.
+	(vcvtq_n_u32_f32): Likewise.
+	(vcvtq_n_u64_f64): Likewise.
+	* config/aarch64/iterators.md (VDQ_SDI): New mode iterator.
+	(VSDQ_SDI): Likewise.
+	(fcvt_target): Support V4DI, V4SI and V2SI.
+	(FCVT_TARGET): Likewise.
+
+2016-06-08  Jiong Wang  <jiong.wang@arm.com>
+
+	* config/aarch64/aarch64-builtins.c (TYPES_BINOP_USS): New
+	(TYPES_BINOP_SUS): Likewise.
+	(aarch64_simd_builtin_data): Update include file name.
+	(aarch64_builtins): Likewise.
+	* config/aarch64/aarch64-simd-builtins.def (scvtf): New entries
+	for conversion between scalar float-point and fixed-point.
+	(ucvtf): Likewise.
+	(fcvtzs): Likewise.
+	(fcvtzu): Likewise.
+	* config/aarch64/aarch64.md
+	(<FCVT_F2FIXED:fcvt_fixed_insn><GPF:mode>3: New
+	pattern for conversion between scalar float to fixed-pointer.
+	(<FCVT_FIXED2F:fcvt_fixed_insn><GPI:mode>: Likewise.
+	(UNSPEC_FCVTZS): New UNSPEC enumeration.
+	(UNSPEC_FCVTZU): Likewise.
+	(UNSPEC_SCVTF): Likewise.
+	(UNSPEC_UCVTF): Likewise.
+	* config/aarch64/arm_neon.h (vcvtd_n_f64_s64): Remove inline assembly.
 	Use builtin.
-        (vcvtd_n_f64_u64): Likewise.
-        (vcvtd_n_s64_f64): Likewise.
-        (vcvtd_n_u64_f64): Likewise.
-        (vcvtd_n_f32_s32): Likewise.
-        (vcvts_n_f32_u32): Likewise.
-        (vcvtd_n_s32_f32): Likewise.
-        (vcvts_n_u32_f32): Likewise.
-        * config/aarch64/iterators.md (fcvt_target): Support integer to float
+	(vcvtd_n_f64_u64): Likewise.
+	(vcvtd_n_s64_f64): Likewise.
+	(vcvtd_n_u64_f64): Likewise.
+	(vcvtd_n_f32_s32): Likewise.
+	(vcvts_n_f32_u32): Likewise.
+	(vcvtd_n_s32_f32): Likewise.
+	(vcvts_n_u32_f32): Likewise.
+	* config/aarch64/iterators.md (fcvt_target): Support integer to float
 	mapping.
-        (FCVT_TARGET): Likewise.
-        (FCVT_FIXED2F): New iterator.
-        (FCVT_F2FIXED): Likewise.
-        (fcvt_fixed_insn): New define_int_attr.
+	(FCVT_TARGET): Likewise.
+	(FCVT_FIXED2F): New iterator.
+	(FCVT_F2FIXED): Likewise.
+	(fcvt_fixed_insn): New define_int_attr.
 
 2016-06-07  Jan Hubicka  <hubicka@ucw.cz>
 
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 0b2f0631c74..a7ea3c4b8ea 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -447,7 +447,7 @@
   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
 
   /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3.  */
-  BUILTIN_GPI (BINOP, scvtf, 3)
-  BUILTIN_GPI (BINOP_SUS, ucvtf, 3)
-  BUILTIN_GPF (BINOP, fcvtzs, 3)
-  BUILTIN_GPF (BINOP_USS, fcvtzu, 3)
+  BUILTIN_VSDQ_SDI (BINOP, scvtf, 3)
+  BUILTIN_VSDQ_SDI (BINOP_SUS, ucvtf, 3)
+  BUILTIN_VALLF (BINOP, fcvtzs, 3)
+  BUILTIN_VALLF (BINOP_USS, fcvtzu, 3)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 6ea35bf487e..d2a6cc27de9 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1778,6 +1778,28 @@
   [(set_attr "type" "neon_fp_cvt_widen_s")]
 )
 
+;; Convert between fixed-point and floating-point (vector modes)
+
+(define_insn "<FCVT_F2FIXED:fcvt_fixed_insn><VDQF:mode>3"
+  [(set (match_operand:<VDQF:FCVT_TARGET> 0 "register_operand" "=w")
+	(unspec:<VDQF:FCVT_TARGET> [(match_operand:VDQF 1 "register_operand" "w")
+				    (match_operand:SI 2 "immediate_operand" "i")]
+	 FCVT_F2FIXED))]
+  "TARGET_SIMD"
+  "<FCVT_F2FIXED:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
+  [(set_attr "type" "neon_fp_to_int_<VDQF:Vetype><q>")]
+)
+
+(define_insn "<FCVT_FIXED2F:fcvt_fixed_insn><VDQ_SDI:mode>3"
+  [(set (match_operand:<VDQ_SDI:FCVT_TARGET> 0 "register_operand" "=w")
+	(unspec:<VDQ_SDI:FCVT_TARGET> [(match_operand:VDQ_SDI 1 "register_operand" "w")
+				       (match_operand:SI 2 "immediate_operand" "i")]
+	 FCVT_FIXED2F))]
+  "TARGET_SIMD"
+  "<FCVT_FIXED2F:fcvt_fixed_insn>\t%<v>0<Vmtype>, %<v>1<Vmtype>, #%2"
+  [(set_attr "type" "neon_int_to_fp_<VDQ_SDI:Vetype><q>")]
+)
+
 ;; ??? Note that the vectorizer usage of the vec_unpacks_[lo/hi] patterns
 ;; is inconsistent with vector ordering elsewhere in the compiler, in that
 ;; the meaning of HI and LO changes depending on the target endianness.
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 8a0fba6513e..04bce9ab80c 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -6025,150 +6025,6 @@ vaddlvq_u32 (uint32x4_t a)
        result;                                                          \
      })
 
-#define vcvt_n_f32_s32(a, b)                                            \
-  __extension__                                                         \
-    ({                                                                  \
-       int32x2_t a_ = (a);                                              \
-       float32x2_t result;                                              \
-       __asm__ ("scvtf %0.2s, %1.2s, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvt_n_f32_u32(a, b)                                            \
-  __extension__                                                         \
-    ({                                                                  \
-       uint32x2_t a_ = (a);                                             \
-       float32x2_t result;                                              \
-       __asm__ ("ucvtf %0.2s, %1.2s, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvt_n_s32_f32(a, b)                                            \
-  __extension__                                                         \
-    ({                                                                  \
-       float32x2_t a_ = (a);                                            \
-       int32x2_t result;                                                \
-       __asm__ ("fcvtzs %0.2s, %1.2s, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvt_n_u32_f32(a, b)                                            \
-  __extension__                                                         \
-    ({                                                                  \
-       float32x2_t a_ = (a);                                            \
-       uint32x2_t result;                                               \
-       __asm__ ("fcvtzu %0.2s, %1.2s, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_f32_s32(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       int32x4_t a_ = (a);                                              \
-       float32x4_t result;                                              \
-       __asm__ ("scvtf %0.4s, %1.4s, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_f32_u32(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       uint32x4_t a_ = (a);                                             \
-       float32x4_t result;                                              \
-       __asm__ ("ucvtf %0.4s, %1.4s, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_f64_s64(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       int64x2_t a_ = (a);                                              \
-       float64x2_t result;                                              \
-       __asm__ ("scvtf %0.2d, %1.2d, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_f64_u64(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       uint64x2_t a_ = (a);                                             \
-       float64x2_t result;                                              \
-       __asm__ ("ucvtf %0.2d, %1.2d, #%2"                               \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_s32_f32(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       float32x4_t a_ = (a);                                            \
-       int32x4_t result;                                                \
-       __asm__ ("fcvtzs %0.4s, %1.4s, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_s64_f64(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       float64x2_t a_ = (a);                                            \
-       int64x2_t result;                                                \
-       __asm__ ("fcvtzs %0.2d, %1.2d, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_u32_f32(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       float32x4_t a_ = (a);                                            \
-       uint32x4_t result;                                               \
-       __asm__ ("fcvtzu %0.4s, %1.4s, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
-#define vcvtq_n_u64_f64(a, b)                                           \
-  __extension__                                                         \
-    ({                                                                  \
-       float64x2_t a_ = (a);                                            \
-       uint64x2_t result;                                               \
-       __asm__ ("fcvtzu %0.2d, %1.2d, #%2"                              \
-                : "=w"(result)                                          \
-                : "w"(a_), "i"(b)                                       \
-                : /* No clobbers */);                                   \
-       result;                                                          \
-     })
-
 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
 vcvtx_f32_f64 (float64x2_t a)
 {
@@ -12760,6 +12616,42 @@ vcvts_n_f32_u32 (uint32_t __a, const int __b)
   return __builtin_aarch64_ucvtfsi_sus (__a, __b);
 }
 
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vcvt_n_f32_s32 (int32x2_t __a, const int __b)
+{
+  return __builtin_aarch64_scvtfv2si (__a, __b);
+}
+
+__extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
+vcvt_n_f32_u32 (uint32x2_t __a, const int __b)
+{
+  return __builtin_aarch64_ucvtfv2si_sus (__a, __b);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvtq_n_f32_s32 (int32x4_t __a, const int __b)
+{
+  return __builtin_aarch64_scvtfv4si (__a, __b);
+}
+
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvtq_n_f32_u32 (uint32x4_t __a, const int __b)
+{
+  return __builtin_aarch64_ucvtfv4si_sus (__a, __b);
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vcvtq_n_f64_s64 (int64x2_t __a, const int __b)
+{
+  return __builtin_aarch64_scvtfv2di (__a, __b);
+}
+
+__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
+vcvtq_n_f64_u64 (uint64x2_t __a, const int __b)
+{
+  return __builtin_aarch64_ucvtfv2di_sus (__a, __b);
+}
+
 /* vcvt (float -> <u>fixed-point).  */
 
 __extension__ static __inline int64_t __attribute__ ((__always_inline__))
@@ -12786,6 +12678,42 @@ vcvts_n_u32_f32 (float32_t __a, const int __b)
   return __builtin_aarch64_fcvtzusf_uss (__a, __b);
 }
 
+__extension__ static __inline int32x2_t __attribute__ ((__always_inline__))
+vcvt_n_s32_f32 (float32x2_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzsv2sf (__a, __b);
+}
+
+__extension__ static __inline uint32x2_t __attribute__ ((__always_inline__))
+vcvt_n_u32_f32 (float32x2_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzuv2sf_uss (__a, __b);
+}
+
+__extension__ static __inline int32x4_t __attribute__ ((__always_inline__))
+vcvtq_n_s32_f32 (float32x4_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzsv4sf (__a, __b);
+}
+
+__extension__ static __inline uint32x4_t __attribute__ ((__always_inline__))
+vcvtq_n_u32_f32 (float32x4_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzuv4sf_uss (__a, __b);
+}
+
+__extension__ static __inline int64x2_t __attribute__ ((__always_inline__))
+vcvtq_n_s64_f64 (float64x2_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzsv2df (__a, __b);
+}
+
+__extension__ static __inline uint64x2_t __attribute__ ((__always_inline__))
+vcvtq_n_u64_f64 (float64x2_t __a, const int __b)
+{
+  return __builtin_aarch64_fcvtzuv2df_uss (__a, __b);
+}
+
 /* vcvt  (<u>int -> float)  */
 
 __extension__ static __inline float64_t __attribute__ ((__always_inline__))
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 2d59bed99b9..e8fbb1281de 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -154,6 +154,12 @@
 ;; Vector modes for S type.
 (define_mode_iterator VDQ_SI [V2SI V4SI])
 
+;; Vector modes for S and D
+(define_mode_iterator VDQ_SDI [V2SI V4SI V2DI])
+
+;; Scalar and Vector modes for S and D
+(define_mode_iterator VSDQ_SDI [V2SI V4SI V2DI SI DI])
+
 ;; Vector modes for Q and H types.
 (define_mode_iterator VDQQH [V8QI V16QI V4HI V8HI])
 
@@ -649,8 +655,10 @@
   [(QI "b") (HI "h") (SI "") (DI "")])
 
 (define_mode_attr fcvt_target [(V2DF "v2di") (V4SF "v4si") (V2SF "v2si")
+			       (V2DI "v2df") (V4SI "v4sf") (V2SI "v2sf")
 			       (SF "si") (DF "di") (SI "sf") (DI "df")])
 (define_mode_attr FCVT_TARGET [(V2DF "V2DI") (V4SF "V4SI") (V2SF "V2SI")
+			       (V2DI "V2DF") (V4SI "V4SF") (V2SI "V2SF")
 			       (SF "SI") (DF "DI") (SI "SF") (DI "DF")])