diff options
| author | Oleg Endo <olegendo@gcc.gnu.org> | 2013-05-06 19:59:26 +0000 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2013-05-06 19:59:26 +0000 |
| commit | eabb1d6f2aa0359c96523ec559e89cb49a2d7924 (patch) | |
| tree | 998d3bf0ad1255806f66ad6e1f4ebb154e130197 | |
| parent | fe1050b4ff801f34ce03d15d4afab49b685a72ad (diff) | |
PR target/52933
* config/sh/sh.md (*cmp_div0s_0, *cmp_div0s_1, *movsicc_div0s): Add
variations of these patterns.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@198646 138bc75d-0d04-0410-961f-82ee72b054a4
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/sh/sh.md | 44 |
2 files changed, 50 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f1c214f3c17..09108c32ab2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2013-05-06 Oleg Endo <olegendo@gcc.gnu.org> + + PR target/52933 + * config/sh/sh.md (*cmp_div0s_0, *cmp_div0s_1, *movsicc_div0s): Add + variations of these patterns. + 2013-05-06 Uros Bizjak <ubizjak@gmail.com> * config/i386/i386.md (isa): Add x64_sse4 member. diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 4adff505c83..71ad1c1a2f6 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -866,6 +866,16 @@ (lshiftrt:SI (xor:SI (match_dup 1) (match_dup 2)) (const_int 31))) (set (match_dup 0) (reg:SI T_REG))]) +(define_insn "*cmp_div0s_0" + [(set (reg:SI T_REG) + (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") + (const_int 31)) + (ge:SI (match_operand:SI 1 "arith_reg_operand") + (const_int 0))))] + "TARGET_SH1" + "div0s %0,%1" + [(set_attr "type" "arith")]) + (define_insn_and_split "*cmp_div0s_1" [(set (match_operand:SI 0 "arith_reg_dest" "") (ge:SI (xor:SI (match_operand:SI 1 "arith_reg_operand" "") @@ -896,6 +906,19 @@ (const_int 0))) (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) +(define_insn_and_split "*cmp_div0s_1" + [(set (reg:SI T_REG) + (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") + (const_int 31)) + (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand") + (const_int 31))))] + "TARGET_SH1" + "#" + "&& can_create_pseudo_p ()" + [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 0) (match_dup 1)) + (const_int 0))) + (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]) + ;; ------------------------------------------------------------------------- ;; SImode compare and branch ;; ------------------------------------------------------------------------- @@ -1069,6 +1092,27 @@ (match_dup 4) (match_dup 3)))]) +(define_insn_and_split "*movsicc_div0s" + [(set (match_operand:SI 0 "arith_reg_dest") + (if_then_else:SI (eq (lshiftrt:SI + (match_operand:SI 1 "arith_reg_operand") + (const_int 31)) + (lshiftrt:SI + (match_operand:SI 2 "arith_reg_operand") + (const_int 31))) + (match_operand:SI 3 "arith_reg_operand") + (match_operand:SI 4 "general_movsrc_operand"))) + (clobber (reg:SI T_REG))] + "TARGET_PRETEND_CMOVE" + "#" + "&& 1" + [(set (reg:SI T_REG) (lt:SI (xor:SI (match_dup 1) (match_dup 2)) + (const_int 0))) + (set (match_dup 0) + (if_then_else (ne (reg:SI T_REG) (const_int 0)) + (match_dup 4) + (match_dup 3)))]) + ;; ------------------------------------------------------------------------- ;; SImode unsigned integer comparisons ;; ------------------------------------------------------------------------- |