aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorVladimir Makarov <vmakarov@redhat.com>2002-10-08 20:40:10 +0000
committerVladimir Makarov <vmakarov@redhat.com>2002-10-08 20:40:10 +0000
commit0d5624a5329811fe9bb2bbe6774224c5d644a41f (patch)
tree44979d07e688b2cfb2b7334756ca53fb1b0fe176
parent925e64262d445b518aa7eb57f9ab78c4a573e121 (diff)
2002-10-08 Vladimir Makarov <vmakarov@redhat.com>
Richard Henderson <rth@redhat.com> * config/ia64/ia64.h (MASK_TUNE_STOP_BITS): Rename it to MASK_EARLY_STOP_BITS. (TARGET_TUNE_STOP_BITS): Rename it to TARGET_EARLY_STOP_BITS. (TARGET_SWITCHES): Rename option `tune-stop-bits' to `early-stop-bits'. * config/ia64/ia64.c (ia64_dfa_new_cycle, final_emit_insn_group_barriers): Use TARGET_EARLY_STOP_BITS instead of TARGET_TUNE_STOP_BITS. * doc/invoke.texi: Rename option `-mtune-stop-bits' to `-mearly-stop-bits'. * config/ia64/ia64.c (automata_option "v"): Comment it. git-svn-id: https://gcc.gnu.org/svn/gcc/branches/itanium-sched-branch@57941 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog18
-rw-r--r--gcc/config/ia64/ia64.c4
-rw-r--r--gcc/config/ia64/ia64.h12
-rw-r--r--gcc/config/ia64/ia64.md5
-rw-r--r--gcc/doc/invoke.texi13
5 files changed, 37 insertions, 15 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c71a131e182..d5cfd72d50a 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,21 @@
+2002-10-08 Vladimir Makarov <vmakarov@redhat.com>
+ Richard Henderson <rth@redhat.com>
+
+ * config/ia64/ia64.h (MASK_TUNE_STOP_BITS): Rename it to
+ MASK_EARLY_STOP_BITS.
+ (TARGET_TUNE_STOP_BITS): Rename it to TARGET_EARLY_STOP_BITS.
+ (TARGET_SWITCHES): Rename option `tune-stop-bits' to
+ `early-stop-bits'.
+
+ * config/ia64/ia64.c (ia64_dfa_new_cycle,
+ final_emit_insn_group_barriers): Use TARGET_EARLY_STOP_BITS
+ instead of TARGET_TUNE_STOP_BITS.
+
+ * doc/invoke.texi: Rename option `-mtune-stop-bits' to
+ `-mearly-stop-bits'.
+
+ * config/ia64/ia64.c (automata_option "v"): Comment it.
+
2002-10-07 Vladimir Makarov <vmakarov@redhat.com>
* config/ia64/ia64.h (MASK_TUNE_STOP_BITS, TARGET_TUNE_STOP_BITS):
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index fc96574ddc1..87d99c8b722 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -5779,7 +5779,7 @@ ia64_dfa_new_cycle (dump, verbose, insn, last_clock, clock, sort_p)
if (last_clock == clock)
{
state_transition (curr_state, dfa_stop_insn);
- if (TARGET_TUNE_STOP_BITS)
+ if (TARGET_EARLY_STOP_BITS)
*sort_p = (last_scheduled_insn == NULL_RTX
|| GET_CODE (last_scheduled_insn) != CALL_INSN);
else
@@ -6667,7 +6667,7 @@ final_emit_insn_group_barriers (dump)
}
else if (need_barrier_p || group_barrier_needed_p (insn))
{
- if (TARGET_TUNE_STOP_BITS)
+ if (TARGET_EARLY_STOP_BITS)
{
rtx last;
diff --git a/gcc/config/ia64/ia64.h b/gcc/config/ia64/ia64.h
index eea5d1b0336..6b9ebe6beeb 100644
--- a/gcc/config/ia64/ia64.h
+++ b/gcc/config/ia64/ia64.h
@@ -91,7 +91,7 @@ extern int target_flags;
#define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */
-#define MASK_TUNE_STOP_BITS 0x00002000 /* tune stop bits for the model. */
+#define MASK_EARLY_STOP_BITS 0x00002000 /* tune stop bits for the model. */
#define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
@@ -128,7 +128,7 @@ extern int ia64_tls_size;
#define TARGET_TLS14 (ia64_tls_size == 14)
#define TARGET_TLS22 (ia64_tls_size == 22)
#define TARGET_TLS64 (ia64_tls_size == 64)
-#define TARGET_TUNE_STOP_BITS (target_flags & MASK_TUNE_STOP_BITS)
+#define TARGET_EARLY_STOP_BITS (target_flags & MASK_EARLY_STOP_BITS)
#define TARGET_HPUX_LD 0
@@ -176,10 +176,10 @@ extern int ia64_tls_size;
N_("Enable Dwarf 2 line debug info via GNU as")}, \
{ "no-dwarf2-asm", -MASK_DWARF2_ASM, \
N_("Disable Dwarf 2 line debug info via GNU as")}, \
- { "tune-stop-bits", MASK_TUNE_STOP_BITS, \
- N_("Enable tuning stop bits for better scheduling")}, \
- { "no-tune-stop-bits", -MASK_TUNE_STOP_BITS, \
- N_("Disable tuning stop bits for better scheduling")}, \
+ { "early-stop-bits", MASK_EARLY_STOP_BITS, \
+ N_("Enable earlier placing stop bits for better scheduling")}, \
+ { "no-early-stop-bits", -MASK_EARLY_STOP_BITS, \
+ N_("Disable earlier placing stop bits")}, \
SUBTARGET_SWITCHES \
{ "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
NULL } \
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index ca7577de295..76c2d8b91c1 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -388,7 +388,10 @@
*/
(automata_option "ndfa")
-(automata_option "v")
+
+;; Uncomment the following line to output automata for debugging.
+;; (automata_option "v")
+
(automata_option "w")
;;============================================================================
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index ec9f5de9fdd..250f1358b20 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -9211,12 +9211,13 @@ useful when compiling kernel code. A register range is specified as
two registers separated by a dash. Multiple register ranges can be
specified separated by a comma.
-@item -mtune-stop-bits
-@itemx -mno-tune-stop-bits
-@opindex mtune-stop-bits
-@opindex mno-tune-stop-bits
-Permit to place stop bits not right before insn requiring it. It might
-improve insn scheduling.
+@item -mearly-stop-bits
+@itemx -mno-early-stop-bits
+@opindex mearly-stop-bits
+@opindex mno-early-stop-bits
+Allow stop bits to be placed earlier than immediately preceding the
+instruction that triggered the stop bit. This can improve instruction
+scheduling, but does not always do so.
@end table
@node D30V Options