2008-05-21 H.J. Lu <hongjiu.lu@intel.com>

	* config/i386/i386.c (ix86_expand_vector_init_one_var): Support
	256bit AVX modes.

	* config/i386/mmx.md (*mov<mode>_internal_rex64_avx): New for
	AVX.
	(*mov<mode>_internal_avx): Likewise.

	* config/i386/sse.md (*vec_concatv2sf_avx): Set prefix to
	orig for MMX instructions.
	(*vec_concatv2di_avx): Likewise.
	(*vec_concatv2si_avx): Likewise.
	(*vec_concatv2di_rex64_avx): Likewise.

2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (ix86_expand_vector_init_general): Remove
	goto for vec_concat and vec_interleave.

2008-05-21  Joey Ye  <joey.ye@intel.com>
	    Xuepeng Guo  <xuepeng.guo@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.md (*movsi_1): Support AVX.
	(*movsf_1): Likewise.
	(*truncdfsf_fast_sse): Likewise.
	(*sse4_1_round<mode>2): Likewise.

	* config/i386/sse.md (*vec_extractv2di_1_rex64_avx): New.
	(*vec_extractv2di_1_avx): Likewise.


git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ix86/avx@135749 138bc75d-0d04-0410-961f-82ee72b054a4

5 files changed, 194 insertions, 43 deletions

diff --git a/gcc/ChangeLog.avx b/gcc/ChangeLog.avx
index 8196be809de..3b1b211fb66 100644
--- a/gcc/ChangeLog.avx
+++ b/gcc/ChangeLog.avx
@@ -1,5 +1,37 @@
 2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
 
+	* config/i386/i386.c (ix86_expand_vector_init_one_var): Support
+	256bit AVX modes.
+
+	* config/i386/mmx.md (*mov<mode>_internal_rex64_avx): New for
+	AVX.
+	(*mov<mode>_internal_avx): Likewise.
+
+	* config/i386/sse.md (*vec_concatv2sf_avx): Set prefix to
+	orig for MMX instructions.
+	(*vec_concatv2di_avx): Likewise.
+	(*vec_concatv2si_avx): Likewise.
+	(*vec_concatv2di_rex64_avx): Likewise.
+
+2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (ix86_expand_vector_init_general): Remove
+	goto for vec_concat and vec_interleave.
+
+2008-05-21  Joey Ye  <joey.ye@intel.com>
+	    Xuepeng Guo  <xuepeng.guo@intel.com>
+	    H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.md (*movsi_1): Support AVX.
+	(*movsf_1): Likewise.
+	(*truncdfsf_fast_sse): Likewise.
+	(*sse4_1_round<mode>2): Likewise.
+
+	* config/i386/sse.md (*vec_extractv2di_1_rex64_avx): New.
+	(*vec_extractv2di_1_avx): Likewise.
+
+2008-05-21  H.J. Lu  <hongjiu.lu@intel.com>
+
 	* config/i386/i386.c (bdesc_args): Updated.
 	(ix86_expand_args_builtin): Likewise.
 	(ix86_expand_vector_set): Don't cast to V4DFmode for 256bit AVX
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index c7b9e35c9a0..918c6fec507 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -25032,6 +25032,12 @@ ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode,
 	 the general case.  */
       return false;
 
+    case V4DFmode:
+    case V4DImode:
+    case V8SFmode:
+    case V8SImode:
+    case V16HImode:
+    case V32QImode:
     case V4SFmode:
     case V4SImode:
     case V8HImode:
@@ -25340,28 +25346,17 @@ ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode,
     case V2SImode:
       if (!mmx_ok && !TARGET_SSE)
 	break;
+      /* FALLTHRU */
 
-      n = 2;
-      goto vec_concat;
-
+    case V8SFmode:
+    case V8SImode:
     case V4DFmode:
     case V4DImode:
     case V4SFmode:
     case V4SImode:
-      n = 4;
-      goto vec_concat;
-
     case V2DFmode:
     case V2DImode:
-      n = 2;
-      goto vec_concat;
-
-    case V8SFmode:
-    case V8SImode:
-      n = 8;
-      goto vec_concat;
-
-vec_concat:
+      n = GET_MODE_NUNITS (mode);
       for (i = 0; i < n; i++)
 	ops[i] = XVECEXP (vals, 0, i);
       ix86_expand_vector_init_concat (mode, target, ops, n);
@@ -25369,15 +25364,14 @@ vec_concat:
 
     case V32QImode:
       half_mode = V16QImode;
-      n = 32;
       goto half;
 
     case V16HImode:
       half_mode = V8HImode;
-      n = 16;
       goto half;
 
 half:
+      n = GET_MODE_NUNITS (mode);
       for (i = 0; i < n; i++)
 	ops[i] = XVECEXP (vals, 0, i);
       op0 = gen_reg_rtx (half_mode);
@@ -25393,18 +25387,13 @@ half:
     case V16QImode:
       if (!TARGET_SSE4_1)
 	break;
-
-      n = 16;
-      goto vec_interleave;
+      /* FALLTHRU */
 
     case V8HImode:
       if (!TARGET_SSE2)
 	break;
 
-      n = 8;
-      goto vec_interleave;
-
-vec_interleave:
+      n = GET_MODE_NUNITS (mode);
       for (i = 0; i < n; i++)
 	ops[i] = XVECEXP (vals, 0, i);
       ix86_expand_vector_init_interleave (mode, target, ops, n >> 1);
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 8d9c3dc3425..121174b599e 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1505,20 +1505,26 @@
     {
     case TYPE_SSELOG1:
       if (get_attr_mode (insn) == MODE_TI)
-        return "pxor\t%0, %0";
-      return "xorps\t%0, %0";
+        return TARGET_AVX ? "vpxor\t%0, %0, %0"
+                          : "pxor\t%0, %0";
+      return TARGET_AVX ? "vxorps\t%0, %0, %0"
+                        : "xorps\t%0, %0";
 
     case TYPE_SSEMOV:
       switch (get_attr_mode (insn))
 	{
 	case MODE_TI:
-	  return "movdqa\t{%1, %0|%0, %1}";
+	  return TARGET_AVX ? "vmovdqa\t{%1, %0|%0, %1}"
+	                    : "movdqa\t{%1, %0|%0, %1}";
 	case MODE_V4SF:
-	  return "movaps\t{%1, %0|%0, %1}";
+	  return TARGET_AVX ? "vmovaps\t{%1, %0|%0, %1}"
+	                    : "movaps\t{%1, %0|%0, %1}";
 	case MODE_SI:
-          return "movd\t{%1, %0|%0, %1}";
+          return TARGET_AVX ? "vmovd\t{%1, %0|%0, %1}"
+                            : "movd\t{%1, %0|%0, %1}";
 	case MODE_SF:
-          return "movss\t{%1, %0|%0, %1}";
+          return TARGET_AVX ? "vmovss\t{%1, %0|%0, %1}"
+                            : "movss\t{%1, %0|%0, %1}";
 	default:
 	  gcc_unreachable ();
 	}
@@ -1552,6 +1558,10 @@
 	      (const_string "lea")
 	   ]
 	   (const_string "imov")))
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
+       (const_string "orig")
+       (const_string "maybe_vex")))
    (set (attr "mode")
      (cond [(eq_attr "alternative" "2,3")
 	      (const_string "DI")
@@ -2715,20 +2725,31 @@
       return "mov{l}\t{%1, %0|%0, %1}";
     case 5:
       if (get_attr_mode (insn) == MODE_TI)
-	return "pxor\t%0, %0";
+	return TARGET_AVX ? "vpxor\t%0, %0, %0" : "pxor\t%0, %0";
       else
-	return "xorps\t%0, %0";
+	return TARGET_AVX ? "xorps\t%0, %0, %0": "xorps\t%0, %0";
     case 6:
       if (get_attr_mode (insn) == MODE_V4SF)
-	return "movaps\t{%1, %0|%0, %1}";
+	return TARGET_AVX ? "vmovaps\t{%1, %0|%0, %1}"
+			  : "movaps\t{%1, %0|%0, %1}";
+      else
+	return TARGET_AVX ? "vmovss\t{%1, %0, %0|%0, %0, %1}"
+			  : "movss\t{%1, %0|%0, %1}";
+    case 7:
+      if (TARGET_AVX)
+	return REG_P (operands[1]) ? "vmovss\t{%1, %0, %0|%0, %0, %1}"
+				   : "vmovss\t{%1, %0|%0, %1}";
       else
 	return "movss\t{%1, %0|%0, %1}";
-    case 7: case 8:
-      return "movss\t{%1, %0|%0, %1}";
+    case 8:
+      return TARGET_AVX ? "vmovss\t{%1, %0|%0, %1}"
+			: "movss\t{%1, %0|%0, %1}";
 
-    case 9: case 10:
-    case 12: case 13: case 14: case 15:
+    case 9: case 10: case 14: case 15:
       return "movd\t{%1, %0|%0, %1}";
+    case 12: case 13:
+      return TARGET_AVX ? "vmovd\t{%1, %0|%0, %1}"
+			: "movd\t{%1, %0|%0, %1}";
 
     case 11:
       return "movq\t{%1, %0|%0, %1}";
@@ -2738,6 +2759,10 @@
     }
 }
   [(set_attr "type" "fmov,fmov,fmov,imov,imov,sselog1,ssemov,ssemov,ssemov,mmxmov,mmxmov,mmxmov,ssemov,ssemov,mmxmov,mmxmov")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "5,6,7,8,12,13")
+       (const_string "maybe_vex")
+       (const_string "orig")))
    (set (attr "mode")
         (cond [(eq_attr "alternative" "3,4,9,10")
 		 (const_string "SI")
@@ -4337,8 +4362,10 @@
         (float_truncate:SF
           (match_operand:DF 1 "nonimmediate_operand" "xm")))]
   "TARGET_SSE2 && TARGET_SSE_MATH"
-  "cvtsd2ss\t{%1, %0|%0, %1}"
+  "* return TARGET_AVX ? \"vcvtsd2ss\t{%1, %0, %0|%0, %0, %1}\"
+                       : \"cvtsd2ss\t{%1, %0|%0, %1}\";"
   [(set_attr "type" "ssecvt")
+   (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "SF")])
 
 (define_insn "*truncdfsf_fast_i387"
@@ -17746,9 +17773,11 @@
 		       (match_operand:SI 2 "const_0_to_15_operand" "n")]
 		      UNSPEC_ROUND))]
   "TARGET_ROUND"
-  "rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
+  "* return TARGET_AVX ? \"vrounds<ssemodefsuffix>\t{%2, %1, %0, %0|%0, %0, %1, %2}\"
+                       : \"rounds<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}\";"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_extra" "1")
+   (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "rintxf2"
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 0a507e07a2f..b77a6fa1656 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -63,6 +63,34 @@
   DONE;
 })
 
+(define_insn "*mov<mode>_internal_rex64_avx"
+  [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
+				"=rm,r,!?y,!?y ,m  ,!y,Y2,x,x ,m,r,x")
+	(match_operand:MMXMODEI8 1 "vector_move_operand"
+				"Cr ,m,C  ,!?ym,!?y,Y2,!y,C,xm,x,x,r"))]
+  "TARGET_64BIT && TARGET_AVX
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+    mov{q}\t{%1, %0|%0, %1}
+    mov{q}\t{%1, %0|%0, %1}
+    pxor\t%0, %0
+    movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
+    vpxor\t%0, %0, %0
+    vmovq\t{%1, %0|%0, %1}
+    vmovq\t{%1, %0|%0, %1}
+    vmovq\t{%1, %0|%0, %1}
+    vmovq\t{%1, %0|%0, %1}"
+  [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
+   (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "7,8,9,10,11")
+       (const_string "vex")
+       (const_string "orig")))
+   (set_attr "mode" "DI")])
+
 (define_insn "*mov<mode>_internal_rex64"
   [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
 				"=rm,r,!?y,!?y ,m  ,!y,Y2,x,x ,m,r,x")
@@ -87,6 +115,32 @@
    (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
    (set_attr "mode" "DI")])
 
+(define_insn "*mov<mode>_internal_avx"
+  [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
+			"=!?y,!?y,m  ,!y ,*Y2,*Y2,*Y2 ,m  ,r  ,m")
+	(match_operand:MMXMODEI8 1 "vector_move_operand"
+			"C   ,!ym,!?y,*Y2,!y ,C  ,*Y2m,*Y2,irm,r"))]
+  "TARGET_AVX
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+    pxor\t%0, %0
+    movq\t{%1, %0|%0, %1}
+    movq\t{%1, %0|%0, %1}
+    movdq2q\t{%1, %0|%0, %1}
+    movq2dq\t{%1, %0|%0, %1}
+    vpxor\t%0, %0, %0
+    vmovq\t{%1, %0|%0, %1}
+    vmovq\t{%1, %0|%0, %1}
+    #
+    #"
+  [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*")
+   (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "5,6,7")
+       (const_string "vex")
+       (const_string "orig")))
+   (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,DI,DI")])
+
 (define_insn "*mov<mode>_internal"
   [(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
 			"=!?y,!?y,m  ,!y ,*Y2,*Y2,*Y2 ,m  ,*x,*x,*x,m ,r  ,m")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index bcf866b38cc..f24d9df9f95 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -3431,7 +3431,10 @@
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
-   (set_attr "prefix" "vex")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "3,4")
+       (const_string "orig")
+       (const_string "vex")))
    (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
 
 ;; Although insertps takes register source, we prefer
@@ -6825,6 +6828,24 @@
   operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
 })
 
+(define_insn "*vec_extractv2di_1_rex64_avx"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
+	(vec_select:DI
+	  (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o,o")
+	  (parallel [(const_int 1)])))]
+  "TARGET_64BIT
+   && TARGET_AVX
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+   vmovhps\t{%1, %0|%0, %1}
+   vpsrldq\t{$8, %1, %0|%0, %1, 8}
+   vmovq\t{%H1, %0|%0, %H1}
+   vmov{q}\t{%H1, %0|%0, %H1}"
+  [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+   (set_attr "memory" "*,none,*,*")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V2SF,TI,TI,DI")])
+
 (define_insn "*vec_extractv2di_1_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
 	(vec_select:DI
@@ -6840,6 +6861,23 @@
    (set_attr "memory" "*,none,*,*")
    (set_attr "mode" "V2SF,TI,TI,DI")])
 
+(define_insn "*vec_extractv2di_1_avx"
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
+	(vec_select:DI
+	  (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
+	  (parallel [(const_int 1)])))]
+  "!TARGET_64BIT
+   && TARGET_AVX
+   && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+  "@
+   vmovhps\t{%1, %0|%0, %1}
+   vpsrldq\t{$8, %1, %0|%0, %1, 8}
+   vmovq\t{%H1, %0|%0, %H1}"
+  [(set_attr "type" "ssemov,sseishft,ssemov")
+   (set_attr "memory" "*,none,*")
+   (set_attr "prefix" "vex")
+   (set_attr "mode" "V2SF,TI,TI")])
+
 (define_insn "*vec_extractv2di_1_sse2"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
 	(vec_select:DI
@@ -6924,7 +6962,10 @@
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
-   (set_attr "prefix" "vex")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "3,4")
+       (const_string "orig")
+       (const_string "vex")))
    (set_attr "mode" "TI,TI,TI,DI,DI")])
 
 (define_insn "*vec_concatv2si_sse4_1"
@@ -7013,7 +7054,10 @@
    vmovhps\t{%2, %1, %0|%0, %1, %2}
    vmovlps\t{%1, %2, %0|%0, %2, %1}"
   [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov")
-   (set_attr "prefix" "vex")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "1")
+       (const_string "orig")
+       (const_string "vex")))
    (set_attr "mode" "TI,TI,TI,V2SF,V2SF")])
 
 (define_insn "vec_concatv2di"
@@ -7047,7 +7091,10 @@
    vmovhps\t{%2, %1, %0|%0, %1, %2}
    vmovlps\t{%1, %2, %0|%0, %2, %1}"
   [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
-   (set_attr "prefix" "vex")
+   (set (attr "prefix")
+     (if_then_else (eq_attr "alternative" "3")
+       (const_string "orig")
+       (const_string "vex")))
    (set_attr "mode" "TI,TI,TI,TI,TI,V2SF,V2SF")])
 
 (define_insn "*vec_concatv2di_rex64_sse4_1"