2008-06-04 H.J. Lu <hongjiu.lu@intel.com>

	* config/i386/i386.c (setup_incoming_varargs_64): Support
	AVX encoding for *sse_prologue_save_insn.

	* config/i386/i386.h (UNITS_PER_SIMD_WORD): Limit AVX to
	128bit.

	* config/i386/i386.md (*sse_prologue_save_insn): Disallow
	REX prefix for AVX.  Set length attribute properly for AVX.


git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ix86/avx@136371 138bc75d-0d04-0410-961f-82ee72b054a4

4 files changed, 40 insertions, 6 deletions

diff --git a/gcc/ChangeLog.avx b/gcc/ChangeLog.avx
index 9f8eeebe148..6eb608d1618 100644
--- a/gcc/ChangeLog.avx
+++ b/gcc/ChangeLog.avx
@@ -1,3 +1,14 @@
+2008-06-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* config/i386/i386.c (setup_incoming_varargs_64): Support
+	AVX encoding for *sse_prologue_save_insn.
+
+	* config/i386/i386.h (UNITS_PER_SIMD_WORD): Limit AVX to
+	128bit.
+
+	* config/i386/i386.md (*sse_prologue_save_insn): Disallow
+	REX prefix for AVX.  Set length attribute properly for AVX.
+
 2008-06-03  H.J. Lu  <hongjiu.lu@intel.com>
 	    Xuepeng Guo  <xuepeng.guo@intel.com>
 	    Joey Ye  <joey.ye@intel.com>
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e22d0955117..5c86e451faf 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -5370,28 +5370,39 @@ setup_incoming_varargs_64 (CUMULATIVE_ARGS *cum)
       label = gen_label_rtx ();
       label_ref = gen_rtx_LABEL_REF (Pmode, label);
 
+      /* FIXME: It doesn't work for 256bit AVX registers.  */
       /* Compute address to jump to :
-         label - 5*eax + nnamed_sse_arguments*5  */
+         label - (4*eax + nnamed_sse_arguments*4) Or
+         label - (5*eax + nnamed_sse_arguments*5) for AVX.  */
       tmp_reg = gen_reg_rtx (Pmode);
       nsse_reg = gen_reg_rtx (Pmode);
       emit_insn (gen_zero_extendqidi2 (nsse_reg, gen_rtx_REG (QImode, AX_REG)));
       emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
 			      gen_rtx_MULT (Pmode, nsse_reg,
 					    GEN_INT (4))));
+
+      /* vmovaps is one byte longer than movaps.  */
+      if (TARGET_AVX)
+	emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
+				gen_rtx_PLUS (Pmode, tmp_reg,
+					      nsse_reg)));
+
       if (cum->sse_regno)
 	emit_move_insn
 	  (nsse_reg,
 	   gen_rtx_CONST (DImode,
 			  gen_rtx_PLUS (DImode,
 					label_ref,
-					GEN_INT (cum->sse_regno * 4))));
+					GEN_INT (cum->sse_regno
+						 * (TARGET_AVX ? 5 : 4)))));
       else
 	emit_move_insn (nsse_reg, label_ref);
       emit_insn (gen_subdi3 (nsse_reg, nsse_reg, tmp_reg));
 
       /* Compute address of memory block we save into.  We always use pointer
 	 pointing 127 bytes after first byte to store - this is needed to keep
-	 instruction size limited by 4 bytes.  */
+	 instruction size limited by 4 bytes (5 bytes for AVX) with one
+	 byte displacement.  */
       tmp_reg = gen_reg_rtx (Pmode);
       emit_insn (gen_rtx_SET (VOIDmode, tmp_reg,
 			      plus_constant (save_area,
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 88dc2477ca8..7e5ec353a19 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1169,9 +1169,13 @@ do {									\
    || (MODE) == V4HImode || (MODE) == V8QImode)
 
 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
-   place emms and femms instructions.  */
+   place emms and femms instructions.
+   FIXME: AVX has 32byte floating point vector operations and 16byte
+   integer vector operations.  But vectorizer doesn't support
+   different sizes for integer and floating point vectors.  We limit
+   vector size to 16byte.  */
 #define UNITS_PER_SIMD_WORD(MODE)					\
-  (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 32 : 16)	\
+  (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16)	\
    	      : (TARGET_SSE ? 16 : UNITS_PER_WORD))
 
 #define VALID_DFP_MODE_P(MODE) \
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 391cd341467..9193d485aa8 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -21165,6 +21165,10 @@
   int i;
   operands[0] = gen_rtx_MEM (Pmode,
 			     gen_rtx_PLUS (Pmode, operands[0], operands[4]));
+  /* VEX instruction with a REX prefix will #UD.  */
+  if (TARGET_AVX && GET_CODE (XEXP (operands[0], 0)) != PLUS)
+    gcc_unreachable ();
+
   output_asm_insn ("jmp\t%A1", operands);
   for (i = X86_64_SSE_REGPARM_MAX - 1; i >= INTVAL (operands[2]); i--)
     {
@@ -21182,7 +21186,11 @@
   [(set_attr "type" "other")
    (set_attr "length_immediate" "0")
    (set_attr "length_address" "0")
-   (set_attr "length" "34")
+   (set (attr "length")
+     (if_then_else
+       (eq (symbol_ref "TARGET_AVX") (const_int 0))
+       (const_string "34")
+       (const_string "42")))
    (set_attr "memory" "store")
    (set_attr "modrm" "0")
    (set_attr "prefix" "maybe_vex")