Add execution tests of ARM REV intrinsics.

	gcc.target/arm/simd/vrev16p8_1.c: New file.
	gcc.target/arm/simd/vrev16qp8_1.c: New file.
	gcc.target/arm/simd/vrev16qs8_1.c: New file.
	gcc.target/arm/simd/vrev16qu8_1.c: New file.
	gcc.target/arm/simd/vrev16s8_1.c: New file.
	gcc.target/arm/simd/vrev16u8_1.c: New file.
	gcc.target/arm/simd/vrev32p16_1.c: New file.
	gcc.target/arm/simd/vrev32p8_1.c: New file.
	gcc.target/arm/simd/vrev32qp16_1.c: New file.
	gcc.target/arm/simd/vrev32qp8_1.c: New file.
	gcc.target/arm/simd/vrev32qs16_1.c: New file.
	gcc.target/arm/simd/vrev32qs8_1.c: New file.
	gcc.target/arm/simd/vrev32qu16_1.c: New file.
	gcc.target/arm/simd/vrev32qu8_1.c: New file.
	gcc.target/arm/simd/vrev32s16_1.c: New file.
	gcc.target/arm/simd/vrev32s8_1.c: New file.
	gcc.target/arm/simd/vrev32u16_1.c: New file.
	gcc.target/arm/simd/vrev32u8_1.c: New file.
	gcc.target/arm/simd/vrev64f32_1.c: New file.
	gcc.target/arm/simd/vrev64p16_1.c: New file.
	gcc.target/arm/simd/vrev64p8_1.c: New file.
	gcc.target/arm/simd/vrev64qf32_1.c: New file.
	gcc.target/arm/simd/vrev64qp16_1.c: New file.
	gcc.target/arm/simd/vrev64qp8_1.c: New file.
	gcc.target/arm/simd/vrev64qs16_1.c: New file.
	gcc.target/arm/simd/vrev64qs32_1.c: New file.
	gcc.target/arm/simd/vrev64qs8_1.c: New file.
	gcc.target/arm/simd/vrev64qu16_1.c: New file.
	gcc.target/arm/simd/vrev64qu32_1.c: New file.
	gcc.target/arm/simd/vrev64qu8_1.c: New file.
	gcc.target/arm/simd/vrev64s16_1.c: New file.
	gcc.target/arm/simd/vrev64s32_1.c: New file.
	gcc.target/arm/simd/vrev64s8_1.c: New file.
	gcc.target/arm/simd/vrev64u16_1.c: New file.
	gcc.target/arm/simd/vrev64u32_1.c: New file.
	gcc.target/arm/simd/vrev64u8_1.c: New file.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@211075 138bc75d-0d04-0410-961f-82ee72b054a4

37 files changed, 471 insertions, 0 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 8bf5b1fed00..1ed6aed7804 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,42 @@
+2014-04-30  Alan Lawrence  <alan.lawrence@arm.com>
+
+	gcc.target/arm/simd/vrev16p8_1.c: New file.
+	gcc.target/arm/simd/vrev16qp8_1.c: New file.
+	gcc.target/arm/simd/vrev16qs8_1.c: New file.
+	gcc.target/arm/simd/vrev16qu8_1.c: New file.
+	gcc.target/arm/simd/vrev16s8_1.c: New file.
+	gcc.target/arm/simd/vrev16u8_1.c: New file.
+	gcc.target/arm/simd/vrev32p16_1.c: New file.
+	gcc.target/arm/simd/vrev32p8_1.c: New file.
+	gcc.target/arm/simd/vrev32qp16_1.c: New file.
+	gcc.target/arm/simd/vrev32qp8_1.c: New file.
+	gcc.target/arm/simd/vrev32qs16_1.c: New file.
+	gcc.target/arm/simd/vrev32qs8_1.c: New file.
+	gcc.target/arm/simd/vrev32qu16_1.c: New file.
+	gcc.target/arm/simd/vrev32qu8_1.c: New file.
+	gcc.target/arm/simd/vrev32s16_1.c: New file.
+	gcc.target/arm/simd/vrev32s8_1.c: New file.
+	gcc.target/arm/simd/vrev32u16_1.c: New file.
+	gcc.target/arm/simd/vrev32u8_1.c: New file.
+	gcc.target/arm/simd/vrev64f32_1.c: New file.
+	gcc.target/arm/simd/vrev64p16_1.c: New file.
+	gcc.target/arm/simd/vrev64p8_1.c: New file.
+	gcc.target/arm/simd/vrev64qf32_1.c: New file.
+	gcc.target/arm/simd/vrev64qp16_1.c: New file.
+	gcc.target/arm/simd/vrev64qp8_1.c: New file.
+	gcc.target/arm/simd/vrev64qs16_1.c: New file.
+	gcc.target/arm/simd/vrev64qs32_1.c: New file.
+	gcc.target/arm/simd/vrev64qs8_1.c: New file.
+	gcc.target/arm/simd/vrev64qu16_1.c: New file.
+	gcc.target/arm/simd/vrev64qu32_1.c: New file.
+	gcc.target/arm/simd/vrev64qu8_1.c: New file.
+	gcc.target/arm/simd/vrev64s16_1.c: New file.
+	gcc.target/arm/simd/vrev64s32_1.c: New file.
+	gcc.target/arm/simd/vrev64s8_1.c: New file.
+	gcc.target/arm/simd/vrev64u16_1.c: New file.
+	gcc.target/arm/simd/vrev64u32_1.c: New file.
+	gcc.target/arm/simd/vrev64u8_1.c: New file.
+
 2014-05-29  Vladimir Makarov  <vmakarov@redhat.com>
 
 	PR rtl-optimization/61325
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
new file mode 100644
index 00000000000..fddb32fbb8b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16p8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
new file mode 100644
index 00000000000..b4634b8dbde
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16q_p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16qp8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
new file mode 100644
index 00000000000..691799b6b94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16q_s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16qs8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
new file mode 100644
index 00000000000..f6ab4ac5cd1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16q_u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16qu8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
new file mode 100644
index 00000000000..0a03721f29c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16s8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
new file mode 100644
index 00000000000..7e5f54808ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev16u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev16u8.x"
+
+/* { dg-final { scan-assembler "vrev16\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
new file mode 100644
index 00000000000..f3643fa96da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32p16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32p16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
new file mode 100644
index 00000000000..d823e59ff1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32p8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
new file mode 100644
index 00000000000..f8ba8a916ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_p16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qp16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
new file mode 100644
index 00000000000..0ddf6081a82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qp8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
new file mode 100644
index 00000000000..30d0314c202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_s16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qs16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
new file mode 100644
index 00000000000..03ddd2be25c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qs8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
new file mode 100644
index 00000000000..71765437b65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_u16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qu16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
new file mode 100644
index 00000000000..403292c7cd8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32q_u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32qu8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
new file mode 100644
index 00000000000..e182ab988ce
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32s16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32s16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
new file mode 100644
index 00000000000..a48c4155176
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32s8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
new file mode 100644
index 00000000000..076f8ab885b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32u16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32u16.x"
+
+/* { dg-final { scan-assembler "vrev32\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
new file mode 100644
index 00000000000..240d4596e8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev32u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev32u8.x"
+
+/* { dg-final { scan-assembler "vrev32\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
new file mode 100644
index 00000000000..f5d3bcae564
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64f32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64f32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
new file mode 100644
index 00000000000..8c685c0f8ca
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64p16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64p16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
new file mode 100644
index 00000000000..67ac1e49117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64p8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
new file mode 100644
index 00000000000..74130b7d821
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_f32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qf32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
new file mode 100644
index 00000000000..71f3b4ba4b7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_p16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qp16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
new file mode 100644
index 00000000000..324a738c660
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_p8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qp8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
new file mode 100644
index 00000000000..9a373ec4100
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_s16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qs16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
new file mode 100644
index 00000000000..0f10c6cb078
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_s32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qs32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
new file mode 100644
index 00000000000..cf380143be6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qs8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
new file mode 100644
index 00000000000..010d6dbb805
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_u16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qu16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
new file mode 100644
index 00000000000..908769cc682
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_u32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qu32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
new file mode 100644
index 00000000000..2fa07d12980
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64q_u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64qu8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[qQ\]\[0-9\]+, \[qQ\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
new file mode 100644
index 00000000000..f14319c3214
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64s16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64s16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
new file mode 100644
index 00000000000..ead57225f3e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64s32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64s32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
new file mode 100644
index 00000000000..29d684dcd1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64s8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64s8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
new file mode 100644
index 00000000000..feddacce2b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64u16' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64u16.x"
+
+/* { dg-final { scan-assembler "vrev64\.16\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
new file mode 100644
index 00000000000..92a81f44041
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64u32' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64u32.x"
+
+/* { dg-final { scan-assembler "vrev64\.32\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
new file mode 100644
index 00000000000..f904af5ca77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
@@ -0,0 +1,12 @@
+/* Test the `vrev64u8' ARM Neon intrinsic.  */
+
+/* { dg-do run } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-options "-save-temps -fno-inline" } */
+/* { dg-add-options arm_neon } */
+
+#include "arm_neon.h"
+#include "../../aarch64/simd/vrev64u8.x"
+
+/* { dg-final { scan-assembler "vrev64\.8\[ \t\]+\[dD\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" } } */
+/* { dg-final { cleanup-saved-temps } } */