diff options
author | Ira Rosen <ira.rosen@linaro.org> | 2011-05-05 07:34:59 +0000 |
---|---|---|
committer | Ira Rosen <ira.rosen@linaro.org> | 2011-05-05 07:34:59 +0000 |
commit | c8e5015900efa346ef2d23978afb0f03bfd8f327 (patch) | |
tree | 9c8bca0f4b3ecfdaee06ccc3f7618cd0f698a5aa | |
parent | ac9036df868c30cf8e0cd79a410f6374d5e0de72 (diff) |
Backport from mainline:
2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org>
Ira Rosen <ira.rosen@linaro.org>
PR target/48252
* config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments
to match neon_vzip/vuzp/vtrn_internal.
* config/arm/neon.md (neon_vtrn<mode>_internal): Make both
outputs explicitly dependent on both inputs.
(neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Likewise.
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch@173417 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r-- | gcc/ChangeLog | 13 | ||||
-rw-r--r-- | gcc/config/arm/arm.c | 2 | ||||
-rw-r--r-- | gcc/config/arm/neon.md | 37 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 9 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/arm/pr48252.c | 31 |
5 files changed, 74 insertions, 18 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 20f684bc4e2..ac97e8278d2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2010-05-05 Ira Rosen <ira.rosen@linaro.org> + + Backport from mainline: + 2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org> + Ira Rosen <ira.rosen@linaro.org> + + PR target/48252 + * config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments + to match neon_vzip/vuzp/vtrn_internal. + * config/arm/neon.md (neon_vtrn<mode>_internal): Make both + outputs explicitly dependent on both inputs. + (neon_vzip<mode>_internal, neon_vuzp<mode>_internal): Likewise. + 2011-05-04 Uros Bizjak <ubizjak@gmail.com> Backport from mainline diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 144cf7913ef..08208b75fc0 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -18237,7 +18237,7 @@ neon_emit_pair_result_insn (enum machine_mode mode, rtx tmp1 = gen_reg_rtx (mode); rtx tmp2 = gen_reg_rtx (mode); - emit_insn (intfn (tmp1, op1, tmp2, op2)); + emit_insn (intfn (tmp1, op1, op2, tmp2)); emit_move_insn (mem, tmp1); mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 8036bc5a9a1..666910e193a 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -3895,13 +3895,14 @@ (define_insn "neon_vtrn<mode>_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] - UNSPEC_VTRN1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VTRN2))] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] + UNSPEC_VTRN1)) + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VTRN2))] "TARGET_NEON" - "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2" + "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) (const_string "neon_bp_simple") @@ -3921,13 +3922,14 @@ (define_insn "neon_vzip<mode>_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] - UNSPEC_VZIP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VZIP2))] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] + UNSPEC_VZIP1)) + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VZIP2))] "TARGET_NEON" - "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2" + "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) (const_string "neon_bp_simple") @@ -3947,13 +3949,14 @@ (define_insn "neon_vuzp<mode>_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] UNSPEC_VUZP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VUZP2))] + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VUZP2))] "TARGET_NEON" - "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2" + "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0)) (const_string "neon_bp_simple") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4a230a26cdc..4776422c43c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,12 @@ +2010-05-05 Ira Rosen <ira.rosen@linaro.org> + + Backport from mainline: + 2011-04-18 Ulrich Weigand <ulrich.weigand@linaro.org> + Ira Rosen <ira.rosen@linaro.org> + + PR target/48252 + * gcc.target/arm/pr48252.c: New test. + 2011-05-04 Uros Bizjak <ubizjak@gmail.com> Backport from mainline diff --git a/gcc/testsuite/gcc.target/arm/pr48252.c b/gcc/testsuite/gcc.target/arm/pr48252.c new file mode 100644 index 00000000000..1a06c71e1be --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr48252.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include <stdlib.h> + +int main(void) +{ + uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1}; + uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2}; + uint8x8x2_t vd1, vd2; + union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4; + int i; + + vd1 = vzip_u8(v1, vdup_n_u8(0)); + vd2 = vzip_u8(v2, vdup_n_u8(0)); + + vst1_u8(d1.buf, vd1.val[0]); + vst1_u8(d2.buf, vd1.val[1]); + vst1_u8(d3.buf, vd2.val[0]); + vst1_u8(d4.buf, vd2.val[1]); + + for (i = 0; i < 8; i++) + if ((i % 2 == 0 && d4.buf[i] != 2) + || (i % 2 == 1 && d4.buf[i] != 0)) + abort (); + + return 0; +} |