diff options
| author | Jakub Jelinek <jakub@redhat.com> | 2012-11-05 13:13:59 +0000 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2012-11-05 13:13:59 +0000 |
| commit | efcdaf2448f702e3077ea7486269c705647ca24c (patch) | |
| tree | 0819b1a6df2acbf18372ed5bbf076b6829c8cfc4 | |
| parent | a356980097cdecf41ca868fb1fbca0f994768ecf (diff) | |
| parent | cc2fba7b31a93d08653a2fd7f135ea13ff690141 (diff) | |
svn merge -r192444:193148 svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-4_7-branch
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/redhat/gcc-4_7-branch@193160 138bc75d-0d04-0410-961f-82ee72b054a4
82 files changed, 1713 insertions, 552 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 97dfaac7f68..487532f809c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,246 @@ +2012-11-03 Peter Bergner <bergner@vnet.ibm.com> + + Backport from mainline + 2012-10-31 Jakub Jelinek <jakub@redhat.com> + + PR tree-optimization/53708 + * tree-vect-data-refs.c (vect_can_force_dr_alignment_p): Preserve + user-supplied alignment when used with an explicit section name. + +2012-11-02 Jeff Law <law@redhat.com> + + PR tree-optimization/54985 + * tree-ssa-threadedge.c (cond_arg_set_in_bb): New function extracted + from thread_across_edge. + (thread_across_edge): Use it in all cases where we might thread + across a back edge. + +2012-10-31 Eric Botcazou <ebotcazou@adacore.com> + + * config/i386/i386.c (ix86_expand_prologue): Emit frame info for the + special register pushes before frame probing and allocation. + +2012-10-31 Ralf Corsépius <ralf.corsepius@rtems.org>, + Joel Sherrill <joel.sherrill@oarcorp.com> + + * config/sparc/t-rtems: New (Custom multilibs). + * config/sparc/t-rtems-64: New (Custom multilibs). + * config.gcc (sparc64-*-rtems*): Add sparc/t-rtems-64. + (sparc-*-rtems*): Add sparc/t-rtems. + +2012-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * cse.c (hash_rtx_cb): Replace RTX_UNCHANGING_P with MEM_READONLY_P in + head comment. + (hash_rtx): Likewise. + +2012-10-29 Terry Guo <terry.guo@arm.com> + + Backport from mainline + 2012-10-11 Terry Guo <terry.guo@arm.com> + + * config/arm/arm.c (arm_arch6m): New variable to denote armv6-m + architecture. + * config/arm/arm.h (TARGET_HAVE_DMB): The armv6-m also has DMB + instruction. + +2012-10-26 Gunther Nikl <gnikl@users.sourceforge.net> + + * common/config/m68k/m68k-common.c (m68k_handle_option): Set + gcc_options fields of opts_set for -m68020-40 and -m68020-60. + +2012-10-26 Ralf Corsépius <ralf.corsepius@rtems.org> + + * config/avr/t-rtems: Revert previous commit. + +2012-10-26 Terry Guo <terry.guo@arm.com> + + Backport from mainline + 2012-10-23 Terry Guo <terry.guo@arm.com> + + PR target/55019 + * config/arm/arm.c (thumb1_expand_prologue): Don't push high regs with + live argument regs. + +2012-10-26 Ralf Corsépius <ralf.corsepius@rtems.org> + + * config/avr/rtems.h (TARGET_OS_CPP_BUILTINS): Remove + __USE_INIT_FINI__. + * config/avr/t-rtems (LIB1ASMFUNCS): Filter out _exit. + +2012-10-25 Ralf Corsépius <ralf.corsepius@rtems.org> + + * config.gcc (microblaze*-*-rtems*): New target. + * config/microblaze/rtems.h: New. + * config/microblaze/t-rtems: New. + +2012-10-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/54902 + * tree-ssa-pre.c (fini_pre): Return TODO. + (execute_pre): Adjust. + * tree-ssa-tailmerge.c (tail_merge_optimize): Delete unreachable + blocks before computing dominators. + +2012-10-24 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2012-10-22 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (memory_address_length): Assert that non-null + base or index RTXes are registers. Do not check for REG RTXes. + Determine addr32 prefix using SImode_address_operand or + from original base and index RTXes. Simplify code. + + 2012-10-21 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386-protos.h (memory_address_length): Add new bool + argument. Update all uses. + * config/i386/i386.c (memory_address_length): If not LEA insn, then + add length of addr32 prefix based on mode of base or index register. + (ix86_attr_length_address_default) <TYPE_LEA>: Do not handle SImode + addresses here. Update call to memory_address_length. + (ix86_print_address_operand): Use SImode_address_operand predicate. + * config/i386/predicates.md (SImode_address_operand): New. + * config/i386/i386.md (lea<mode>): Use SImode_address_operand + to calculate "mode" attribute. Use SImode_address_operand predicate + instead of open-coding accepted RTX codes. + +2012-10-22 Georg-Johann Lay <avr@gjlay.de> + + Backport from 2012-10-22 trunk r192685. + * doc/invoke.texi (AVR Options): Document __AVR_ARCH__. + Note __AVR_<device>__ is not defined for cores. + Don't point to --help=target. + Order --mcu= documentation according to trunk:/gcc/doc/avr-mmcu.texi. + +2012-10-19 Marek Polacek <polacek@redhat.com> + + Backported from mainline + 2012-10-19 Marek Polacek <polacek@redhat.com> + + PR middle-end/54945 + * fold-const.c (fold_sign_changed_comparison): Punt if folding + pointer/non-pointer comparison. + +2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + Backported from mainline + 2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + PR target/54892 + * config/arm/arm.c (arm_expand_compare_and_swap): Use SImode to make + sure the mode is correct when falling through from above cases. + +2012-10-19 Alan Modra <amodra@gmail.com> + + * configure.ac (HAVE_LD_NO_DOT_SYMS): Set if using gold. + (HAVE_LD_LARGE_TOC): Likewise. + * configure: Regenerate. + +2012-10-19 Alan Modra <amodra@gmail.com> + + * config/rs6000/predicates.md (splat_input_operand): Don't call + input_operand for MEMs. Instead check for volatile and call + memory_address_addr_space_p with modified mode. + +2012-10-17 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> + + Backported from mainline + 2012-07-23 Ulrich Weigand <ulrich.weigand@linaro.org> + + * config/arm/arm.c (arm_reorg): Ensure all insns are split. + +2012-10-16 Eric Botcazou <ebotcazou@adacore.com> + + PR rtl-optimization/54870 + * tree.h (TREE_ADDRESSABLE): Document special usage on SSA_NAME. + * cfgexpand.c (update_alias_info_with_stack_vars ): Set it on the + SSA_NAME pointer that points to a partition if there is at least + one variable with it set in the partition. + * dse.c (local_variable_can_escape): New predicate. + (can_escape): Call it. + * gimplify.c (mark_addressable): If this is a partitioned decl, also + mark the SSA_NAME pointer that points to a partition. + +2012-10-16 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2012-08-09 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/53701 + * sel-sched.c (vinsn_vec_has_expr_p): Clarify function comment. + rocess not only expr's vinsns but all old vinsns from expr's + istory of changes. + +2012-10-16 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2012-07-31 Andrey Belevantsev <abel@ispras.ru> + PR target/53975 + + * sel-sched-ir.c (has_dependence_note_reg_use): Clarify comment. + Revert + 2011-08-04 Sergey Grechanik <mouseentity@ispras.ru> + * sel-sched-ir.c (has_dependence_note_reg_use): Call ds_full_merge + only if producer writes to the register given by regno. + +2012-09-15 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2012-10-15 Uros Bizjak <ubizjak@gmail.com> + + * config/i386/sse.md (UNSPEC_MOVU): Remove. + (UNSPEC_LOADU): New. + (UNSPEC_STOREU): Ditto. + (<sse>_movu<ssemodesuffix><avxsizesuffix>): Split to ... + (<sse>_loadu<ssemodesuffix><avxsizesuffix>): ... this and ... + (<sse>_storeu<ssemodesuffix><avxsizesuffix>) ... this. + (<sse2>_movdqu<avxsizesuffix>): Split to ... + (<sse2>_loaddqu<avxsizesuffix>): ... this and ... + (<sse2>_storedqu<avxsizesuffix>): ... this. + (*sse4_2_pcmpestr_unaligned): Update. + (*sse4_2_pcmpistr_unaligned): Ditto. + + * config/i386/i386.c (ix86_avx256_split_vector_move_misalign): Use + gen_avx_load{dqu,ups,upd}256 to load from unaligned memory and + gen_avx_store{dqu,ups,upd}256 to store to unaligned memory. + (ix86_expand_vector_move_misalign): Use gen_sse_loadups or + gen_sse2_load{dqu,upd} to load from unaligned memory and + gen_sse_loadups or gen_sse2_store{dqu,upd}256 to store to + unaligned memory. + (struct builtin_description bdesc_spec) <IX86_BUILTIN_LOADUPS>: + Use CODE_FOR_sse_loadups. + <IX86_BUILTIN_LOADUPD>: Use CODE_FOR_sse2_loadupd. + <IX86_BUILTIN_LOADDQU>: Use CODE_FOR_sse2_loaddqu. + <IX86_BUILTIN_STOREUPS>: Use CODE_FOR_sse_storeups. + <IX86_BUILTIN_STOREUPD>: Use CODE_FOR_sse2_storeupd. + <IX86_BUILTIN_STOREDQU>: Use CODE_FOR_sse2_storedqu. + <IX86_BUILTIN_LOADUPS256>: Use CODE_FOR_avx_loadups256. + <IX86_BUILTIN_LOADUPD256>: Use CODE_FOR_avx_loadupd256. + <IX86_BUILTIN_LOADDQU256>: Use CODE_FOR_avx_loaddqu256. + <IX86_BUILTIN_STOREUPS256>: Use CODE_FOR_avx_storeups256. + <IX86_BUILTIN_STOREUPD256>: Use CODE_FOR_avx_storeupd256. + <IX86_BUILTIN_STOREDQU256>: Use CODE_FOR_avx_storedqu256. + +2012-10-15 Steven Bosscher <steven@gcc.gnu.org> + + Backport from trunk (r190222): + + PR tree-optimization/54146 + * ifcvt.c: Include pointer-set.h. + (cond_move_process_if_block): Change type of then_regs and + else_regs from alloca'd array to pointer_sets. + (check_cond_move_block): Update for this change. + (cond_move_convert_if_block): Likewise. + * Makefile.in: Fix dependencies for ifcvt.o. + +2012-10-15 Richard Guenther <rguenther@suse.de> + + PR tree-optimization/54920 + * tree-ssa-pre.c (create_expression_by_pieces): Properly + allocate temporary storage for all NARY elements. + 2012-10-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config.gcc: Enable zEC12 for with-arch and with-tune @@ -186,7 +429,7 @@ * config.gcc (*-*-openbsd4.[3-9]|*-*-openbsd[5-9]*): Set default_use_cxa_atexit to yes. - + 2012-10-05 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> * config/pa/pa.md: Adjust unamed HImode add insn pattern. @@ -203,7 +446,7 @@ Backported from mainline 2012-10-03 Andrew W. Nosenko <andrew.w.nosenko@gmail.com> - * config/i386/driver-i386.c (host_detect_local_cpu): Fix logic + * config/i386/driver-i386.c (host_detect_local_cpu): Fix logic in SSE and YMM state support check for -march=native. 2012-10-03 Alexandre Oliva <aoliva@redhat.com> @@ -268,8 +511,7 @@ PR target/54703 * simplify-rtx.c (simplify_binary_operation_1): Perform - (x - (x & y)) -> (x & ~y) optimization only for integral - modes. + (x - (x & y)) -> (x & ~y) optimization only for integral modes. 2012-09-24 Eric Botcazou <ebotcazou@adacore.com> @@ -347,12 +589,12 @@ Backport from mainline 2012-09-07 Andi Kleen <ak@linux.intel.com> - * gcc/lto-streamer.h (res_pair): Add. - (lto_file_decl_data): Replace resolutions with respairs. - Add max_index. - * gcc/lto/lto.c (lto_resolution_read): Remove max_index. Add rp. - Initialize respairs. - (lto_file_finalize): Set up resolutions vector lazily from respairs. + * gcc/lto-streamer.h (res_pair): Add. + (lto_file_decl_data): Replace resolutions with respairs. + Add max_index. + * gcc/lto/lto.c (lto_resolution_read): Remove max_index. Add rp. + Initialize respairs. + (lto_file_finalize): Set up resolutions vector lazily from respairs. 2012-09-14 Walter Lee <walt@tilera.com> @@ -418,7 +660,7 @@ 2012-09-12 Christian Bruel <christian.bruel@st.com> - * config/sh/newlib.h (NO_IMPLICIT_EXTERN_C): Define. + * config/sh/newlib.h (NO_IMPLICIT_EXTERN_C): Define. 2012-09-12 Jakub Jelinek <jakub@redhat.com> diff --git a/gcc/DATESTAMP b/gcc/DATESTAMP index bc72ebf083a..0217b4d9ded 100644 --- a/gcc/DATESTAMP +++ b/gcc/DATESTAMP @@ -1 +1 @@ -20121015 +20121105 diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 034f036f20d..0ee23e51337 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -3421,7 +3421,7 @@ regrename.o : regrename.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ ifcvt.o : ifcvt.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(RTL_H) \ $(REGS_H) $(DIAGNOSTIC_CORE_H) $(FLAGS_H) insn-config.h $(FUNCTION_H) $(RECOG_H) \ $(TARGET_H) $(BASIC_BLOCK_H) $(EXPR_H) output.h $(EXCEPT_H) $(TM_P_H) \ - $(OPTABS_H) $(CFGLOOP_H) hard-reg-set.h $(TIMEVAR_H) \ + $(OPTABS_H) $(CFGLOOP_H) hard-reg-set.h pointer-set.h $(TIMEVAR_H) \ $(TREE_PASS_H) $(DF_H) $(DBGCNT_H) params.o : params.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(COMMON_TARGET_H) \ $(PARAMS_H) $(DIAGNOSTIC_CORE_H) diff --git a/gcc/ada/ChangeLog b/gcc/ada/ChangeLog index 4fac921a89e..c8c9b74d4f5 100644 --- a/gcc/ada/ChangeLog +++ b/gcc/ada/ChangeLog @@ -1,3 +1,28 @@ +2012-10-30 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/Make-lang.in: Fix and clean up rules for C files. + +2012-10-22 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Array_Type>: Force + BLKmode on the type if it is passed by reference. + <E_Array_Subtype>: Likewise. + <E_Record_Type>: Guard the call to Is_By_Reference_Type predicate. + <E_Record_Subtype>: Likewise. + + * gcc-interface/Makefile.in: Remove outdated comment and reference to + non-existing file. + +2012-10-22 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/trans.c (Loop_Statement_to_gnu): Use gnat_type_for_size + directly to obtain an unsigned version of the base type. + +2012-10-22 Eric Botcazou <ebotcazou@adacore.com> + + * gcc-interface/decl.c (gnat_to_gnu_entity) <E_Out_Parameter>: Do not + generate the special PARM_DECL for an Out parameter in LTO mode. + 2012-10-02 Eric Botcazou <ebotcazou@adacore.com> * gcc-interfaces/decl.c (elaborate_expression_1): Use the variable for diff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-interface/Make-lang.in index 06a88030bdb..289f0b7f8b9 100644 --- a/gcc/ada/gcc-interface/Make-lang.in +++ b/gcc/ada/gcc-interface/Make-lang.in @@ -1225,33 +1225,20 @@ ada/mdll-fil.o : ada/mdll-fil.adb ada/mdll.ads ada/mdll-fil.ads ada/mdll-utl.o : ada/mdll-utl.adb ada/mdll.ads ada/mdll-utl.ads ada/sdefault.ads ada/types.ads $(CC) -c $(ALL_ADAFLAGS) $(ADA_INCLUDES) $< $(OUTPUT_OPTION) -ada/adadecode.o : ada/adadecode.c $(CONFIG_H) $(SYSTEM_H) ada/adadecode.h -ada/adaint.o : ada/adaint.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h -ada/argv.o : ada/argv.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h -ada/cstreams.o : ada/cstreams.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h -ada/exit.o : ada/exit.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h -ada/final.o : ada/final.c $(CONFIG_H) $(SYSTEM_H) ada/raise.h -ada/link.o : ada/link.c - -ada/targext.o : ada/targext.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) - $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ADA_CFLAGS) \ - $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) - +ada/adadecode.o : ada/adadecode.c $(CONFIG_H) $(SYSTEM_H) ada/adadecode.h ada/adaint.h +ada/adaint.o : ada/adaint.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h version.h +ada/argv.o : ada/argv.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h ada/cio.o : ada/cio.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h - $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ADA_CFLAGS) \ - $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) - +ada/cstreams.o : ada/cstreams.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h +ada/env.o: ada/env.c $(CONFIG_H) $(SYSTEM_H) ada/env.h +ada/exit.o : ada/exit.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h +ada/final.o : ada/final.c ada/init.o : ada/init.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h ada/raise.h - $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ADA_CFLAGS) \ - $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) - -ada/initialize.o : ada/initialize.c - $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ADA_CFLAGS) \ - $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) - +ada/initialize.o : ada/initialize.c $(CONFIG_H) $(SYSTEM_H) ada/raise.h +ada/link.o : ada/link.c auto-host.h ada/raise.o : ada/raise.c $(CONFIG_H) $(SYSTEM_H) ada/adaint.h ada/raise.h - $(COMPILER) -c $(ALL_COMPILERFLAGS) $(ADA_CFLAGS) \ - $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) +ada/seh_init.o: ada/seh_init.c $(CONFIG_H) $(SYSTEM_H) ada/raise.h +ada/targext.o : ada/targext.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) ada/cuintp.o : ada/gcc-interface/cuintp.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \ $(TM_H) $(TREE_H) ada/gcc-interface/ada.h ada/types.h ada/uintp.h \ diff --git a/gcc/ada/gcc-interface/Makefile.in b/gcc/ada/gcc-interface/Makefile.in index a47b8f90a85..0f5854cc142 100644 --- a/gcc/ada/gcc-interface/Makefile.in +++ b/gcc/ada/gcc-interface/Makefile.in @@ -1242,7 +1242,6 @@ ifeq ($(strip $(filter-out %86_64 freebsd%,$(arch) $(osys))),) s-taprop.adb<s-taprop-posix.adb \ s-taspri.ads<s-taspri-posix.ads \ s-tpopsp.adb<s-tpopsp-posix.adb \ - g-trasym.adb<g-trasym-dwarf.adb \ $(ATOMICS_TARGET_PAIRS) \ $(X86_64_TARGET_PAIRS) \ system.ads<system-freebsd-x86_64.ads @@ -2518,8 +2517,6 @@ install-gnatlib: ../stamp-gnatlib-$(RTSDIR) $(RM) ../stamp-gnatlib-$(RTSDIR) touch ../stamp-gnatlib1-$(RTSDIR) -# GNULLI End ############################################################# - ifeq ($(strip $(filter-out alpha64 ia64 dec hp vms% openvms% alphavms%,$(subst -, ,$(host)))),) OSCONS_CPP=../../$(DECC) -E /comment=as_is -DNATIVE \ -DTARGET='""$(target)""' $(fsrcpfx)ada/s-oscons-tmplt.c diff --git a/gcc/ada/gcc-interface/decl.c b/gcc/ada/gcc-interface/decl.c index 72bbd80d97e..97f8d65d2f5 100644 --- a/gcc/ada/gcc-interface/decl.c +++ b/gcc/ada/gcc-interface/decl.c @@ -1508,7 +1508,11 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) the VAR_DECL. Suppress debug info for the latter but make sure it will live on the stack so that it can be accessed from within the debugger through the PARM_DECL. */ - if (kind == E_Out_Parameter && definition && !optimize && debug_info_p) + if (kind == E_Out_Parameter + && definition + && debug_info_p + && !optimize + && !flag_generate_lto) { tree param = create_param_decl (gnu_entity_name, gnu_type, false); gnat_pushdecl (param, gnat_entity); @@ -2251,6 +2255,12 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) TYPE_MULTI_ARRAY_P (tem) = (index > 0); if (array_type_has_nonaliased_component (tem, gnat_entity)) TYPE_NONALIASED_COMPONENT (tem) = 1; + + /* If it is passed by reference, force BLKmode to ensure that + objects of this type will always be put in memory. */ + if (TYPE_MODE (tem) != BLKmode + && Is_By_Reference_Type (gnat_entity)) + SET_TYPE_MODE (tem, BLKmode); } /* If an alignment is specified, use it if valid. But ignore it @@ -2590,6 +2600,11 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) TYPE_MULTI_ARRAY_P (gnu_type) = (index > 0); if (array_type_has_nonaliased_component (gnu_type, gnat_entity)) TYPE_NONALIASED_COMPONENT (gnu_type) = 1; + + /* See the E_Array_Type case for the rationale. */ + if (TYPE_MODE (gnu_type) != BLKmode + && Is_By_Reference_Type (gnat_entity)) + SET_TYPE_MODE (gnu_type, BLKmode); } /* Attach the TYPE_STUB_DECL in case we have a parallel type. */ @@ -3158,7 +3173,8 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) /* If it is passed by reference, force BLKmode to ensure that objects of this type will always be put in memory. */ - if (Is_By_Reference_Type (gnat_entity)) + if (TYPE_MODE (gnu_type) != BLKmode + && Is_By_Reference_Type (gnat_entity)) SET_TYPE_MODE (gnu_type, BLKmode); /* We used to remove the associations of the discriminants and _Parent @@ -3526,12 +3542,12 @@ gnat_to_gnu_entity (Entity_Id gnat_entity, tree gnu_expr, int definition) modify it below. */ gnu_field_list = nreverse (gnu_field_list); finish_record_type (gnu_type, gnu_field_list, 2, false); + compute_record_mode (gnu_type); /* See the E_Record_Type case for the rationale. */ - if (Is_By_Reference_Type (gnat_entity)) + if (TYPE_MODE (gnu_type) != BLKmode + && Is_By_Reference_Type (gnat_entity)) SET_TYPE_MODE (gnu_type, BLKmode); - else - compute_record_mode (gnu_type); TYPE_VOLATILE (gnu_type) = Treat_As_Volatile (gnat_entity); diff --git a/gcc/ada/gcc-interface/trans.c b/gcc/ada/gcc-interface/trans.c index 63363f5ffde..aabe9b6bd02 100644 --- a/gcc/ada/gcc-interface/trans.c +++ b/gcc/ada/gcc-interface/trans.c @@ -2402,7 +2402,8 @@ Loop_Statement_to_gnu (Node_Id gnat_node) { if (TYPE_PRECISION (gnu_base_type) > TYPE_PRECISION (size_type_node)) - gnu_base_type = gnat_unsigned_type (gnu_base_type); + gnu_base_type + = gnat_type_for_size (TYPE_PRECISION (gnu_base_type), 1); else gnu_base_type = size_type_node; diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index bde15f69683..c2385685ead 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -697,6 +697,8 @@ update_alias_info_with_stack_vars (void) (void *)(size_t) uid)) = part; *((tree *) pointer_map_insert (cfun->gimple_df->decls_to_pointers, decl)) = name; + if (TREE_ADDRESSABLE (decl)) + TREE_ADDRESSABLE (name) = 1; } /* Make the SSA name point to all partition members. */ diff --git a/gcc/common/config/m68k/m68k-common.c b/gcc/common/config/m68k/m68k-common.c index 3a81b678a24..55b3e4a59c2 100644 --- a/gcc/common/config/m68k/m68k-common.c +++ b/gcc/common/config/m68k/m68k-common.c @@ -1,6 +1,6 @@ /* Common hooks for Motorola 68000 family. Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 + 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. This file is part of GCC. @@ -33,7 +33,7 @@ along with GCC; see the file COPYING3. If not see static bool m68k_handle_option (struct gcc_options *opts, - struct gcc_options *opts_set ATTRIBUTE_UNUSED, + struct gcc_options *opts_set, const struct cl_decoded_option *decoded, location_t loc) { @@ -45,12 +45,16 @@ m68k_handle_option (struct gcc_options *opts, { case OPT_m68020_40: opts->x_m68k_tune_option = u68020_40; + opts_set->x_m68k_tune_option = (enum uarch_type) 1; opts->x_m68k_cpu_option = m68020; + opts_set->x_m68k_cpu_option = (enum target_device) 1; return true; case OPT_m68020_60: opts->x_m68k_tune_option = u68020_60; + opts_set->x_m68k_tune_option = (enum uarch_type) 1; opts->x_m68k_cpu_option = m68020; + opts_set->x_m68k_cpu_option = (enum target_device) 1; return true; case OPT_mshared_library_id_: diff --git a/gcc/config.gcc b/gcc/config.gcc index f41cb3a57b6..0c728a0bc18 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -1730,6 +1730,14 @@ microblaze*-linux*) c_target_objs="${c_target_objs} microblaze-c.o" cxx_target_objs="${cxx_target_objs} microblaze-c.o" ;; +microblaze*-*-rtems*) + tm_file="${tm_file} dbxelf.h" + tm_file="${tm_file} microblaze/rtems.h rtems.h newlib-stdint.h" + c_target_objs="${c_target_objs} microblaze-c.o" + cxx_target_objs="${cxx_target_objs} microblaze-c.o" + tmake_file="${tmake_file} microblaze/t-microblaze" + tmake_file="${tmake_file} t-rtems microblaze/t-rtems" + ;; microblaze*-*-*) tm_file="${tm_file} dbxelf.h" c_target_objs="${c_target_objs} microblaze-c.o" @@ -2411,7 +2419,7 @@ sparc-*-elf*) ;; sparc-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h sparc/sp-elf.h sparc/rtemself.h rtems.h newlib-stdint.h" - tmake_file="sparc/t-sparc sparc/t-elf t-rtems" + tmake_file="sparc/t-sparc sparc/t-elf sparc/t-rtems t-rtems" ;; sparc-*-linux*) tm_file="${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/tso.h" @@ -2464,7 +2472,7 @@ sparc64-*-elf*) sparc64-*-rtems*) tm_file="${tm_file} dbxelf.h elfos.h newlib-stdint.h sparc/sysv4.h sparc/sp64-elf.h sparc/rtemself.h rtems.h" extra_options="${extra_options}" - tmake_file="${tmake_file} sparc/t-sparc t-rtems" + tmake_file="${tmake_file} sparc/t-sparc sparc/t-rtems-64 t-rtems" ;; sparc64-*-linux*) tm_file="sparc/biarch64.h ${tm_file} dbxelf.h elfos.h sparc/sysv4.h gnu-user.h linux.h glibc-stdint.h sparc/default-64.h sparc/linux64.h sparc/tso.h" diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 35b73c56ad1..66765df3cde 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -745,6 +745,9 @@ int arm_arch6 = 0; /* Nonzero if this chip supports the ARM 6K extensions. */ int arm_arch6k = 0; +/* Nonzero if instructions present in ARMv6-M can be used. */ +int arm_arch6m = 0; + /* Nonzero if this chip supports the ARM 7 extensions. */ int arm_arch7 = 0; @@ -1704,6 +1707,7 @@ arm_option_override (void) arm_arch6 = (insn_flags & FL_ARCH6) != 0; arm_arch6k = (insn_flags & FL_ARCH6K) != 0; arm_arch_notm = (insn_flags & FL_NOTM) != 0; + arm_arch6m = arm_arch6 && !arm_arch_notm; arm_arch7 = (insn_flags & FL_ARCH7) != 0; arm_arch7em = (insn_flags & FL_ARCH7EM) != 0; arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0; @@ -13337,6 +13341,13 @@ arm_reorg (void) if (TARGET_THUMB2) thumb2_reorg (); + /* Ensure all insns that must be split have been split at this point. + Otherwise, the pool placement code below may compute incorrect + insn lengths. Note that when optimizing, all insns have already + been split at this point. */ + if (!optimize) + split_all_insns_noflow (); + minipool_fix_head = minipool_fix_tail = NULL; /* The first insn must always be a note, or the code below won't @@ -22286,12 +22297,18 @@ thumb1_expand_prologue (void) { unsigned pushable_regs; unsigned next_hi_reg; + unsigned arg_regs_num = TARGET_AAPCS_BASED ? crtl->args.info.aapcs_ncrn + : crtl->args.info.nregs; + unsigned arg_regs_mask = (1 << arg_regs_num) - 1; for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) if (live_regs_mask & (1 << next_hi_reg)) break; - pushable_regs = l_mask & 0xff; + /* Here we need to mask out registers used for passing arguments + even if they can be pushed. This is to avoid using them to stash the high + registers. Such kind of stash may clobber the use of arguments. */ + pushable_regs = l_mask & (~arg_regs_mask) & 0xff; if (pushable_regs == 0) pushable_regs = 1 << thumb_find_work_register (live_regs_mask); @@ -24852,8 +24869,8 @@ arm_expand_compare_and_swap (rtx operands[]) case SImode: /* Force the value into a register if needed. We waited until after the zero-extension above to do this properly. */ - if (!arm_add_operand (oldval, mode)) - oldval = force_reg (mode, oldval); + if (!arm_add_operand (oldval, SImode)) + oldval = force_reg (SImode, oldval); break; case DImode: diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 443d2ed168d..a3db5c4d600 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -267,7 +267,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_UNIFIED_ASM TARGET_THUMB2 /* Nonzero if this chip provides the DMB instruction. */ -#define TARGET_HAVE_DMB (arm_arch7) +#define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) /* Nonzero if this chip implements a memory barrier via CP15. */ #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ @@ -383,6 +383,9 @@ extern int arm_arch6; /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ extern int arm_arch6k; +/* Nonzero if instructions present in ARMv6-M can be used. */ +extern int arm_arch6m; + /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ extern int arm_arch7; diff --git a/gcc/config/avr/rtems.h b/gcc/config/avr/rtems.h index efd8afacefa..4a9c1b4d67b 100644 --- a/gcc/config/avr/rtems.h +++ b/gcc/config/avr/rtems.h @@ -23,6 +23,5 @@ along with GCC; see the file COPYING3. If not see #define TARGET_OS_CPP_BUILTINS() \ do { \ builtin_define ("__rtems__"); \ - builtin_define ("__USE_INIT_FINI__"); \ builtin_assert ("system=rtems"); \ } while (0) diff --git a/gcc/config/i386/i386-protos.h b/gcc/config/i386/i386-protos.h index 14bc6729a98..3eb5ef87f73 100644 --- a/gcc/config/i386/i386-protos.h +++ b/gcc/config/i386/i386-protos.h @@ -270,7 +270,7 @@ struct ix86_address }; extern int ix86_decompose_address (rtx, struct ix86_address *); -extern int memory_address_length (rtx addr); +extern int memory_address_length (rtx, bool); extern void x86_output_aligned_bss (FILE *, tree, const char *, unsigned HOST_WIDE_INT, int); extern void x86_elf_aligned_common (FILE *, const char *, diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index d6101dd2900..86e41480b53 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -10365,7 +10365,7 @@ ix86_expand_prologue (void) rtx eax = gen_rtx_REG (Pmode, AX_REG); rtx r10 = NULL; rtx (*adjust_stack_insn)(rtx, rtx, rtx); - + const bool sp_is_cfa_reg = (m->fs.cfa_reg == stack_pointer_rtx); bool eax_live = false; bool r10_live = false; @@ -10374,16 +10374,31 @@ ix86_expand_prologue (void) if (!TARGET_64BIT_MS_ABI) eax_live = ix86_eax_live_at_start_p (); + /* Note that SEH directives need to continue tracking the stack + pointer even after the frame pointer has been set up. */ if (eax_live) { - emit_insn (gen_push (eax)); + insn = emit_insn (gen_push (eax)); allocate -= UNITS_PER_WORD; + if (sp_is_cfa_reg || TARGET_SEH) + { + if (sp_is_cfa_reg) + m->fs.cfa_offset += UNITS_PER_WORD; + RTX_FRAME_RELATED_P (insn) = 1; + } } + if (r10_live) { r10 = gen_rtx_REG (Pmode, R10_REG); - emit_insn (gen_push (r10)); + insn = emit_insn (gen_push (r10)); allocate -= UNITS_PER_WORD; + if (sp_is_cfa_reg || TARGET_SEH) + { + if (sp_is_cfa_reg) + m->fs.cfa_offset += UNITS_PER_WORD; + RTX_FRAME_RELATED_P (insn) = 1; + } } emit_move_insn (eax, GEN_INT (allocate)); @@ -10397,13 +10412,10 @@ ix86_expand_prologue (void) insn = emit_insn (adjust_stack_insn (stack_pointer_rtx, stack_pointer_rtx, eax)); - /* Note that SEH directives need to continue tracking the stack - pointer even after the frame pointer has been set up. */ - if (m->fs.cfa_reg == stack_pointer_rtx || TARGET_SEH) + if (sp_is_cfa_reg || TARGET_SEH) { - if (m->fs.cfa_reg == stack_pointer_rtx) + if (sp_is_cfa_reg) m->fs.cfa_offset += allocate; - RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_FRAME_RELATED_EXPR, gen_rtx_SET (VOIDmode, stack_pointer_rtx, @@ -14672,19 +14684,24 @@ ix86_print_operand_address (FILE *file, rtx addr) else { /* Print SImode register names to force addr32 prefix. */ - if (GET_CODE (addr) == SUBREG) - { - gcc_assert (TARGET_64BIT); - gcc_assert (GET_MODE (addr) == SImode); - gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); - gcc_assert (!code); - code = 'l'; - } - else if (GET_CODE (addr) == ZERO_EXTEND - || GET_CODE (addr) == AND) + if (SImode_address_operand (addr, VOIDmode)) { +#ifdef ENABLE_CHECKING gcc_assert (TARGET_64BIT); - gcc_assert (GET_MODE (addr) == DImode); + switch (GET_CODE (addr)) + { + case SUBREG: + gcc_assert (GET_MODE (addr) == SImode); + gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); + break; + case ZERO_EXTEND: + case AND: + gcc_assert (GET_MODE (addr) == DImode); + break; + default: + gcc_unreachable (); + } +#endif gcc_assert (!code); code = 'l'; } @@ -15752,7 +15769,8 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1) { rtx m; rtx (*extract) (rtx, rtx, rtx); - rtx (*move_unaligned) (rtx, rtx); + rtx (*load_unaligned) (rtx, rtx); + rtx (*store_unaligned) (rtx, rtx); enum machine_mode mode; switch (GET_MODE (op0)) @@ -15761,39 +15779,52 @@ ix86_avx256_split_vector_move_misalign (rtx op0, rtx op1) gcc_unreachable (); case V32QImode: extract = gen_avx_vextractf128v32qi; - move_unaligned = gen_avx_movdqu256; + load_unaligned = gen_avx_loaddqu256; + store_unaligned = gen_avx_storedqu256; mode = V16QImode; break; case V8SFmode: extract = gen_avx_vextractf128v8sf; - move_unaligned = gen_avx_movups256; + load_unaligned = gen_avx_loadups256; + store_unaligned = gen_avx_storeups256; mode = V4SFmode; break; case V4DFmode: extract = gen_avx_vextractf128v4df; - move_unaligned = gen_avx_movupd256; + load_unaligned = gen_avx_loadupd256; + store_unaligned = gen_avx_storeupd256; mode = V2DFmode; break; } - if (MEM_P (op1) && TARGET_AVX256_SPLIT_UNALIGNED_LOAD) + if (MEM_P (op1)) { - rtx r = gen_reg_rtx (mode); - m = adjust_address (op1, mode, 0); - emit_move_insn (r, m); - m = adjust_address (op1, mode, 16); - r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m); - emit_move_insn (op0, r); + if (TARGET_AVX256_SPLIT_UNALIGNED_LOAD) + { + rtx r = gen_reg_rtx (mode); + m = adjust_address (op1, mode, 0); + emit_move_insn (r, m); + m = adjust_address (op1, mode, 16); + r = gen_rtx_VEC_CONCAT (GET_MODE (op0), r, m); + emit_move_insn (op0, r); + } + else + emit_insn (load_unaligned (op0, op1)); } - else if (MEM_P (op0) && TARGET_AVX256_SPLIT_UNALIGNED_STORE) + else if (MEM_P (op0)) { - m = adjust_address (op0, mode, 0); - emit_insn (extract (m, op1, const0_rtx)); - m = adjust_address (op0, mode, 16); - emit_insn (extract (m, op1, const1_rtx)); + if (TARGET_AVX256_SPLIT_UNALIGNED_STORE) + { + m = adjust_address (op0, mode, 0); + emit_insn (extract (m, op1, const0_rtx)); + m = adjust_address (op0, mode, 16); + emit_insn (extract (m, op1, const1_rtx)); + } + else + emit_insn (store_unaligned (op0, op1)); } else - emit_insn (move_unaligned (op0, op1)); + gcc_unreachable (); } /* Implement the movmisalign patterns for SSE. Non-SSE modes go @@ -15852,6 +15883,7 @@ void ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { rtx op0, op1, m; + rtx (*move_unaligned) (rtx, rtx); op0 = operands[0]; op1 = operands[1]; @@ -15868,14 +15900,28 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) /* If we're optimizing for size, movups is the smallest. */ if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) { + if (MEM_P (op1)) + move_unaligned = gen_sse_loadups; + else if (MEM_P (op0)) + move_unaligned = gen_sse_storeups; + else + gcc_unreachable (); + op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (move_unaligned (op0, op1)); return; } + if (MEM_P (op1)) + move_unaligned = gen_sse2_loaddqu; + else if (MEM_P (op0)) + move_unaligned = gen_sse2_storedqu; + else + gcc_unreachable (); + op0 = gen_lowpart (V16QImode, op0); op1 = gen_lowpart (V16QImode, op1); - emit_insn (gen_sse2_movdqu (op0, op1)); + emit_insn (move_unaligned (op0, op1)); break; case 32: op0 = gen_lowpart (V32QImode, op0); @@ -15893,7 +15939,14 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) switch (mode) { case V4SFmode: - emit_insn (gen_sse_movups (op0, op1)); + if (MEM_P (op1)) + move_unaligned = gen_sse_loadups; + else if (MEM_P (op0)) + move_unaligned = gen_sse_storeups; + else + gcc_unreachable (); + + emit_insn (move_unaligned (op0, op1)); break; case V8SFmode: ix86_avx256_split_vector_move_misalign (op0, op1); @@ -15901,12 +15954,26 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) case V2DFmode: if (TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL) { + if (MEM_P (op1)) + move_unaligned = gen_sse_loadups; + else if (MEM_P (op0)) + move_unaligned = gen_sse_storeups; + else + gcc_unreachable (); + op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (move_unaligned (op0, op1)); return; } - emit_insn (gen_sse2_movupd (op0, op1)); + if (MEM_P (op1)) + move_unaligned = gen_sse2_loadupd; + else if (MEM_P (op0)) + move_unaligned = gen_sse2_storeupd; + else + gcc_unreachable (); + + emit_insn (move_unaligned (op0, op1)); break; case V4DFmode: ix86_avx256_split_vector_move_misalign (op0, op1); @@ -15931,7 +15998,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (gen_sse_loadups (op0, op1)); return; } @@ -15942,7 +16009,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V16QImode, op0); op1 = gen_lowpart (V16QImode, op1); - emit_insn (gen_sse2_movdqu (op0, op1)); + emit_insn (gen_sse2_loaddqu (op0, op1)); return; } @@ -15954,7 +16021,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V2DFmode, op0); op1 = gen_lowpart (V2DFmode, op1); - emit_insn (gen_sse2_movupd (op0, op1)); + emit_insn (gen_sse2_loadupd (op0, op1)); return; } @@ -15989,7 +16056,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (gen_sse_loadups (op0, op1)); return; } @@ -16014,7 +16081,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V4SFmode, op0); op1 = gen_lowpart (V4SFmode, op1); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (gen_sse_storeups (op0, op1)); return; } @@ -16025,7 +16092,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V16QImode, op0); op1 = gen_lowpart (V16QImode, op1); - emit_insn (gen_sse2_movdqu (op0, op1)); + emit_insn (gen_sse2_storedqu (op0, op1)); return; } @@ -16035,7 +16102,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { op0 = gen_lowpart (V2DFmode, op0); op1 = gen_lowpart (V2DFmode, op1); - emit_insn (gen_sse2_movupd (op0, op1)); + emit_insn (gen_sse2_storeupd (op0, op1)); } else { @@ -16053,7 +16120,7 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) if (TARGET_SSE_UNALIGNED_STORE_OPTIMAL) { op0 = gen_lowpart (V4SFmode, op0); - emit_insn (gen_sse_movups (op0, op1)); + emit_insn (gen_sse_storeups (op0, op1)); } else { @@ -23352,10 +23419,10 @@ assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n) /* Calculate the length of the memory address in the instruction encoding. Includes addr32 prefix, does not include the one-byte modrm, opcode, - or other prefixes. */ + or other prefixes. We never generate addr32 prefix for LEA insn. */ int -memory_address_length (rtx addr) +memory_address_length (rtx addr, bool lea) { struct ix86_address parts; rtx base, index, disp; @@ -23371,18 +23438,26 @@ memory_address_length (rtx addr) ok = ix86_decompose_address (addr, &parts); gcc_assert (ok); - if (parts.base && GET_CODE (parts.base) == SUBREG) - parts.base = SUBREG_REG (parts.base); - if (parts.index && GET_CODE (parts.index) == SUBREG) - parts.index = SUBREG_REG (parts.index); + len = (parts.seg == SEG_DEFAULT) ? 0 : 1; + + /* If this is not LEA instruction, add the length of addr32 prefix. */ + if (TARGET_64BIT && !lea + && (SImode_address_operand (addr, VOIDmode) + || (parts.base && GET_MODE (parts.base) == SImode) + || (parts.index && GET_MODE (parts.index) == SImode))) + len++; base = parts.base; index = parts.index; disp = parts.disp; - /* Add length of addr32 prefix. */ - len = (GET_CODE (addr) == ZERO_EXTEND - || GET_CODE (addr) == AND); + if (base && GET_CODE (base) == SUBREG) + base = SUBREG_REG (base); + if (index && GET_CODE (index) == SUBREG) + index = SUBREG_REG (index); + + gcc_assert (base == NULL_RTX || REG_P (base)); + gcc_assert (index == NULL_RTX || REG_P (index)); /* Rule of thumb: - esp as the base always wants an index, @@ -23396,14 +23471,13 @@ memory_address_length (rtx addr) /* esp (for its index) and ebp (for its displacement) need the two-byte modrm form. Similarly for r12 and r13 in 64-bit code. */ - if (REG_P (addr) - && (addr == arg_pointer_rtx - || addr == frame_pointer_rtx - || REGNO (addr) == SP_REG - || REGNO (addr) == BP_REG - || REGNO (addr) == R12_REG - || REGNO (addr) == R13_REG)) - len = 1; + if (base == arg_pointer_rtx + || base == frame_pointer_rtx + || REGNO (base) == SP_REG + || REGNO (base) == BP_REG + || REGNO (base) == R12_REG + || REGNO (base) == R13_REG) + len++; } /* Direct Addressing. In 64-bit mode mod 00 r/m 5 @@ -23413,7 +23487,7 @@ memory_address_length (rtx addr) by UNSPEC. */ else if (disp && !base && !index) { - len = 4; + len += 4; if (TARGET_64BIT) { rtx symbol = disp; @@ -23431,43 +23505,30 @@ memory_address_length (rtx addr) || (XINT (symbol, 1) != UNSPEC_GOTPCREL && XINT (symbol, 1) != UNSPEC_PCREL && XINT (symbol, 1) != UNSPEC_GOTNTPOFF))) - len += 1; + len++; } } - else { /* Find the length of the displacement constant. */ if (disp) { if (base && satisfies_constraint_K (disp)) - len = 1; + len += 1; else - len = 4; + len += 4; } /* ebp always wants a displacement. Similarly r13. */ - else if (base && REG_P (base) - && (REGNO (base) == BP_REG || REGNO (base) == R13_REG)) - len = 1; + else if (base && (REGNO (base) == BP_REG || REGNO (base) == R13_REG)) + len++; /* An index requires the two-byte modrm form.... */ if (index /* ...like esp (or r12), which always wants an index. */ || base == arg_pointer_rtx || base == frame_pointer_rtx - || (base && REG_P (base) - && (REGNO (base) == SP_REG || REGNO (base) == R12_REG))) - len += 1; - } - - switch (parts.seg) - { - case SEG_FS: - case SEG_GS: - len += 1; - break; - default: - break; + || (base && (REGNO (base) == SP_REG || REGNO (base) == R12_REG))) + len++; } return len; @@ -23521,7 +23582,8 @@ ix86_attr_length_immediate_default (rtx insn, bool shortform) case MODE_SI: len = 4; break; - /* Immediates for DImode instructions are encoded as 32bit sign extended values. */ + /* Immediates for DImode instructions are encoded + as 32bit sign extended values. */ case MODE_DI: len = 4; break; @@ -23531,6 +23593,7 @@ ix86_attr_length_immediate_default (rtx insn, bool shortform) } return len; } + /* Compute default value for "length_address" attribute. */ int ix86_attr_length_address_default (rtx insn) @@ -23547,15 +23610,8 @@ ix86_attr_length_address_default (rtx insn) gcc_assert (GET_CODE (set) == SET); addr = SET_SRC (set); - if (TARGET_64BIT && get_attr_mode (insn) == MODE_SI) - { - if (GET_CODE (addr) == ZERO_EXTEND) - addr = XEXP (addr, 0); - if (GET_CODE (addr) == SUBREG) - addr = SUBREG_REG (addr); - } - return memory_address_length (addr); + return memory_address_length (addr, true); } extract_insn_cached (insn); @@ -23577,7 +23633,7 @@ ix86_attr_length_address_default (rtx insn) if (*constraints == 'X') continue; } - return memory_address_length (XEXP (recog_data.operand[i], 0)); + return memory_address_length (XEXP (recog_data.operand[i], 0), false); } return 0; } @@ -26058,9 +26114,9 @@ static const struct builtin_description bdesc_special_args[] = { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID }, /* SSE */ - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, + { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF }, - { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT }, + { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT }, { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF }, { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF }, @@ -26074,14 +26130,14 @@ static const struct builtin_description bdesc_special_args[] = /* SSE2 */ { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT }, { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE }, - { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movdqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE }, + { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE }, { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE }, @@ -26106,12 +26162,12 @@ static const struct builtin_description bdesc_special_args[] = { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, - { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movdqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, + { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR }, { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI }, diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 97358dbf9d5..27a831b7f27 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5412,18 +5412,9 @@ { rtx addr = operands[1]; - if (GET_CODE (addr) == SUBREG) + if (SImode_address_operand (addr, VOIDmode)) { gcc_assert (TARGET_64BIT); - gcc_assert (<MODE>mode == SImode); - gcc_assert (GET_MODE (SUBREG_REG (addr)) == DImode); - return "lea{l}\t{%E1, %0|%0, %E1}"; - } - else if (GET_CODE (addr) == ZERO_EXTEND - || GET_CODE (addr) == AND) - { - gcc_assert (TARGET_64BIT); - gcc_assert (<MODE>mode == DImode); return "lea{l}\t{%E1, %k0|%k0, %E1}"; } else @@ -5436,7 +5427,11 @@ DONE; } [(set_attr "type" "lea") - (set_attr "mode" "<MODE>")]) + (set (attr "mode") + (if_then_else + (match_operand 1 "SImode_address_operand") + (const_string "SI") + (const_string "<MODE>")))]) ;; Add instructions @@ -17734,7 +17729,7 @@ [(set_attr "type" "sse") (set_attr "atom_sse_attr" "prefetch") (set (attr "length_address") - (symbol_ref "memory_address_length (operands[0])")) + (symbol_ref "memory_address_length (operands[0], false)")) (set_attr "memory" "none")]) (define_insn "*prefetch_3dnow" @@ -17750,7 +17745,7 @@ } [(set_attr "type" "mmx") (set (attr "length_address") - (symbol_ref "memory_address_length (operands[0])")) + (symbol_ref "memory_address_length (operands[0], false)")) (set_attr "memory" "none")]) (define_expand "stack_protect_set" diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index c78384b300e..9e312915bfc 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -822,6 +822,10 @@ return parts.seg == SEG_DEFAULT; }) +;; Return true for RTX codes that force SImode address. +(define_predicate "SImode_address_operand" + (match_code "subreg,zero_extend,and")) + ;; Return true if op if a valid base register, displacement or ;; sum of base register and displacement for VSIB addressing. (define_predicate "vsib_address_operand" @@ -991,7 +995,7 @@ ;; by the modRM array. (define_predicate "long_memory_operand" (and (match_operand 0 "memory_operand") - (match_test "memory_address_length (op)"))) + (match_test "memory_address_length (op, false)"))) ;; Return true if OP is a comparison operator that can be issued by fcmov. (define_predicate "fcmov_comparison_operator" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1917cb660a5..0621d61d68a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21,7 +21,8 @@ (define_c_enum "unspec" [ ;; SSE UNSPEC_MOVNT - UNSPEC_MOVU + UNSPEC_LOADU + UNSPEC_STOREU ;; SSE3 UNSPEC_LDDQU @@ -580,23 +581,51 @@ DONE; }) -(define_insn "<sse>_movu<ssemodesuffix><avxsizesuffix>" - [(set (match_operand:VF 0 "nonimmediate_operand" "=x,m") +(define_insn "<sse>_loadu<ssemodesuffix><avxsizesuffix>" + [(set (match_operand:VF 0 "register_operand" "=x") (unspec:VF - [(match_operand:VF 1 "nonimmediate_operand" "xm,x")] - UNSPEC_MOVU))] - "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + [(match_operand:VF 1 "memory_operand" "m")] + UNSPEC_LOADU))] + "TARGET_SSE" "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") (set_attr "prefix" "maybe_vex") (set_attr "mode" "<MODE>")]) -(define_insn "<sse2>_movdqu<avxsizesuffix>" - [(set (match_operand:VI1 0 "nonimmediate_operand" "=x,m") - (unspec:VI1 [(match_operand:VI1 1 "nonimmediate_operand" "xm,x")] - UNSPEC_MOVU))] - "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))" +(define_insn "<sse>_storeu<ssemodesuffix><avxsizesuffix>" + [(set (match_operand:VF 0 "memory_operand" "=m") + (unspec:VF + [(match_operand:VF 1 "register_operand" "x")] + UNSPEC_STOREU))] + "TARGET_SSE" + "%vmovu<ssemodesuffix>\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "<MODE>")]) + +(define_insn "<sse2>_loaddqu<avxsizesuffix>" + [(set (match_operand:VI1 0 "register_operand" "=x") + (unspec:VI1 [(match_operand:VI1 1 "memory_operand" "m")] + UNSPEC_LOADU))] + "TARGET_SSE2" + "%vmovdqu\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "movu" "1") + (set (attr "prefix_data16") + (if_then_else + (match_test "TARGET_AVX") + (const_string "*") + (const_string "1"))) + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "<sseinsnmode>")]) + +(define_insn "<sse2>_storedqu<avxsizesuffix>" + [(set (match_operand:VI1 0 "memory_operand" "=m") + (unspec:VI1 [(match_operand:VI1 1 "register_operand" "x")] + UNSPEC_STOREU))] + "TARGET_SSE2" "%vmovdqu\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "movu" "1") diff --git a/gcc/config/microblaze/rtems.h b/gcc/config/microblaze/rtems.h new file mode 100644 index 00000000000..fecf7a295d5 --- /dev/null +++ b/gcc/config/microblaze/rtems.h @@ -0,0 +1,25 @@ +/* Definitions for rtems targeting a microblaze using ELF. + Copyright (C) 2012 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +<http://www.gnu.org/licenses/>. */ + +/* Specify predefined symbols in preprocessor. */ + +#define TARGET_OS_CPP_BUILTINS() do { \ + builtin_define( "__rtems__" ); \ + builtin_assert( "system=rtems" ); \ +} while (0) diff --git a/gcc/config/microblaze/t-rtems b/gcc/config/microblaze/t-rtems new file mode 100644 index 00000000000..d0c38261aaa --- /dev/null +++ b/gcc/config/microblaze/t-rtems @@ -0,0 +1 @@ +# Custom multilibs for RTEMS diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 29dd18d75bd..72377f9dc42 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -891,12 +891,16 @@ { if (MEM_P (op)) { + if (! volatile_ok && MEM_VOLATILE_P (op)) + return 0; if (mode == DFmode) mode = V2DFmode; else if (mode == DImode) mode = V2DImode; else - gcc_unreachable (); + gcc_unreachable (); + return memory_address_addr_space_p (mode, XEXP (op, 0), + MEM_ADDR_SPACE (op)); } return input_operand (op, mode); }) diff --git a/gcc/config/sparc/t-rtems b/gcc/config/sparc/t-rtems new file mode 100644 index 00000000000..4a01e1eaaf3 --- /dev/null +++ b/gcc/config/sparc/t-rtems @@ -0,0 +1,22 @@ +# Copyright (C) 2012 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. +# + +MULTILIB_OPTIONS = msoft-float mcpu=v8 +MULTILIB_DIRNAMES = soft v8 +MULTILIB_MATCHES = msoft-float=mno-fpu diff --git a/gcc/config/sparc/t-rtems-64 b/gcc/config/sparc/t-rtems-64 new file mode 100644 index 00000000000..d6a6e3eea37 --- /dev/null +++ b/gcc/config/sparc/t-rtems-64 @@ -0,0 +1,22 @@ +# Copyright (C) 2012 Free Software Foundation, Inc. +# +# This file is part of GCC. +# +# GCC is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3, or (at your option) +# any later version. +# +# GCC is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# <http://www.gnu.org/licenses/>. +# + +MULTILIB_OPTIONS = msoft-float +MULTILIB_DIRNAMES = soft +MULTILIB_MATCHES = msoft-float=mno-fpu diff --git a/gcc/configure b/gcc/configure index 0dcbd40283f..51aa3e169e3 100755 --- a/gcc/configure +++ b/gcc/configure @@ -26563,7 +26563,9 @@ if test "${gcc_cv_ld_no_dot_syms+set}" = set; then : $as_echo_n "(cached) " >&6 else gcc_cv_ld_no_dot_syms=no - if test $in_tree_ld = yes ; then + if test x"$ld_is_gold" = xyes; then + gcc_cv_ld_no_dot_syms=yes + elif test $in_tree_ld = yes ; then if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 16 -o "$gcc_cv_gld_major_version" -gt 2; then gcc_cv_ld_no_dot_syms=yes fi @@ -26607,7 +26609,9 @@ if test "${gcc_cv_ld_large_toc+set}" = set; then : $as_echo_n "(cached) " >&6 else gcc_cv_ld_large_toc=no - if test $in_tree_ld = yes ; then + if test x"$ld_is_gold" = xyes; then + gcc_cv_ld_large_toc=yes + elif test $in_tree_ld = yes ; then if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then gcc_cv_ld_large_toc=yes fi diff --git a/gcc/configure.ac b/gcc/configure.ac index 1b61b6f13f8..0db75b3decc 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -4467,7 +4467,9 @@ case "$target:$tm_file" in AC_CACHE_CHECK(linker support for omitting dot symbols, gcc_cv_ld_no_dot_syms, [gcc_cv_ld_no_dot_syms=no - if test $in_tree_ld = yes ; then + if test x"$ld_is_gold" = xyes; then + gcc_cv_ld_no_dot_syms=yes + elif test $in_tree_ld = yes ; then if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 16 -o "$gcc_cv_gld_major_version" -gt 2; then gcc_cv_ld_no_dot_syms=yes fi @@ -4504,7 +4506,9 @@ EOF AC_CACHE_CHECK(linker large toc support, gcc_cv_ld_large_toc, [gcc_cv_ld_large_toc=no - if test $in_tree_ld = yes ; then + if test x"$ld_is_gold" = xyes; then + gcc_cv_ld_large_toc=yes + elif test $in_tree_ld = yes ; then if test "$gcc_cv_gld_major_version" -eq 2 -a "$gcc_cv_gld_minor_version" -ge 21 -o "$gcc_cv_gld_major_version" -gt 2; then gcc_cv_ld_large_toc=yes fi diff --git a/gcc/cp/ChangeLog b/gcc/cp/ChangeLog index 6ee47f56fa2..7d6c3f41e83 100644 --- a/gcc/cp/ChangeLog +++ b/gcc/cp/ChangeLog @@ -1,3 +1,9 @@ +2012-10-26 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/54984 + * init.c (build_new): Don't turn a null *init into a pointer to + empty vector orig_init. + 2012-10-08 Jakub Jelinek <jakub@redhat.com> PR c++/54858 diff --git a/gcc/cp/init.c b/gcc/cp/init.c index f0023361e22..6c29c209f02 100644 --- a/gcc/cp/init.c +++ b/gcc/cp/init.c @@ -2896,7 +2896,8 @@ build_new (VEC(tree,gc) **placement, tree type, tree nelts, orig_placement = make_tree_vector_copy (*placement); orig_nelts = nelts; - orig_init = make_tree_vector_copy (*init); + if (*init) + orig_init = make_tree_vector_copy (*init); make_args_non_dependent (*placement); if (nelts) diff --git a/gcc/cse.c b/gcc/cse.c index 6424bb1864f..0904ee688b6 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -2555,7 +2555,7 @@ hash_rtx_cb (const_rtx x, enum machine_mode mode, Store 1 in DO_NOT_RECORD_P if any subexpression is volatile. If HASH_ARG_IN_MEMORY_P is not NULL, store 1 in it if X contains - a MEM rtx which does not have the RTX_UNCHANGING_P bit set. + a MEM rtx which does not have the MEM_READONLY_P flag set. Note that cse_insn knows that the hash code of a MEM expression is just (int) MEM plus the hash code of the address. */ @@ -2571,7 +2571,7 @@ hash_rtx (const_rtx x, enum machine_mode mode, int *do_not_record_p, /* Hash an rtx X for cse via hash_rtx. Stores 1 in do_not_record if any subexpression is volatile. Stores 1 in hash_arg_in_memory if X contains a mem rtx which - does not have the RTX_UNCHANGING_P bit set. */ + does not have the MEM_READONLY_P flag set. */ static inline unsigned canon_hash (rtx x, enum machine_mode mode) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e3dc3d47dbb..dcad28fe8e2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -10956,9 +10956,6 @@ defined. @opindex mmcu Specify Atmel AVR instruction set architectures (ISA) or MCU type. -For a complete list of @var{mcu} values that are supported by @command{avr-gcc}, -see the compiler output when called with the @option{--help=target} -command line option. The default for this option is@tie{}@code{avr2}. GCC supports the following AVR devices and ISAs: @@ -10967,22 +10964,22 @@ GCC supports the following AVR devices and ISAs: @item avr2 ``Classic'' devices with up to 8@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{at90c8534}, @code{at90s2313}, -@code{at90s2323}, @code{at90s2333}, @code{at90s2343}, -@code{at90s4414}, @code{at90s4433}, @code{at90s4434}, -@code{at90s8515}, @code{at90s8535}, @code{attiny22}, @code{attiny26}. +@*@var{mcu}@tie{}= @code{attiny22}, @code{attiny26}, @code{at90c8534}, +@code{at90s2313}, @code{at90s2323}, @code{at90s2333}, +@code{at90s2343}, @code{at90s4414}, @code{at90s4433}, +@code{at90s4434}, @code{at90s8515}, @code{at90s8535}. @item avr25 ``Classic'' devices with up to 8@tie{}KiB of program memory and with the @code{MOVW} instruction. -@*@var{mcu}@tie{}= @code{at86rf401}, @code{ata6289}, @code{attiny13}, -@code{attiny13a}, @code{attiny2313}, @code{attiny2313a}, -@code{attiny24}, @code{attiny24a}, @code{attiny25}, @code{attiny261}, -@code{attiny261a}, @code{attiny4313}, @code{attiny43u}, +@*@var{mcu}@tie{}= @code{ata6289}, @code{attiny13}, @code{attiny13a}, +@code{attiny2313}, @code{attiny2313a}, @code{attiny24}, +@code{attiny24a}, @code{attiny25}, @code{attiny261}, +@code{attiny261a}, @code{attiny43u}, @code{attiny4313}, @code{attiny44}, @code{attiny44a}, @code{attiny45}, @code{attiny461}, @code{attiny461a}, @code{attiny48}, @code{attiny84}, @code{attiny84a}, @code{attiny85}, @code{attiny861}, @code{attiny861a}, @code{attiny87}, -@code{attiny88}. +@code{attiny88}, @code{at86rf401}. @item avr3 ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. @@ -10990,57 +10987,58 @@ the @code{MOVW} instruction. @item avr31 ``Classic'' devices with 128@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{at43usb320}, @code{atmega103}. +@*@var{mcu}@tie{}= @code{atmega103}, @code{at43usb320}. @item avr35 ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory and with the @code{MOVW} instruction. -@*@var{mcu}@tie{}= @code{at90usb162}, @code{at90usb82}, -@code{atmega16u2}, @code{atmega32u2}, @code{atmega8u2}, -@code{attiny167}. +@*@var{mcu}@tie{}= @code{atmega16u2}, @code{atmega32u2}, +@code{atmega8u2}, @code{attiny167}, @code{at90usb162}, +@code{at90usb82}. @item avr4 ``Enhanced'' devices with up to 8@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, -@code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}, @code{atmega48}, -@code{atmega48a}, @code{atmega48p}, @code{atmega8}, @code{atmega8515}, -@code{atmega8535}, @code{atmega88}, @code{atmega88a}, -@code{atmega88p}, @code{atmega88pa}, @code{atmega8hva}. +@*@var{mcu}@tie{}= @code{atmega48}, @code{atmega48a}, +@code{atmega48p}, @code{atmega8}, @code{atmega8hva}, +@code{atmega8515}, @code{atmega8535}, @code{atmega88}, +@code{atmega88a}, @code{atmega88p}, @code{atmega88pa}, +@code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3}, +@code{at90pwm3b}, @code{at90pwm81}. @item avr5 ``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{at90can32}, @code{at90can64}, -@code{at90pwm216}, @code{at90pwm316}, @code{at90scr100}, -@code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{atmega16}, -@code{atmega161}, @code{atmega162}, @code{atmega163}, -@code{atmega164a}, @code{atmega164p}, @code{atmega165}, -@code{atmega165a}, @code{atmega165p}, @code{atmega168}, -@code{atmega168a}, @code{atmega168p}, @code{atmega169}, -@code{atmega169a}, @code{atmega169p}, @code{atmega169pa}, -@code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2}, -@code{atmega16hvb}, @code{atmega16m1}, @code{atmega16u4}, -@code{atmega32}, @code{atmega323}, @code{atmega324a}, -@code{atmega324p}, @code{atmega324pa}, @code{atmega325}, +@*@var{mcu}@tie{}= @code{atmega16}, @code{atmega16a}, +@code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb}, +@code{atmega16m1}, @code{atmega16u4}, @code{atmega161}, +@code{atmega162}, @code{atmega163}, @code{atmega164a}, +@code{atmega164p}, @code{atmega165}, @code{atmega165a}, +@code{atmega165p}, @code{atmega168}, @code{atmega168a}, +@code{atmega168p}, @code{atmega169}, @code{atmega169a}, +@code{atmega169p}, @code{atmega169pa}, @code{atmega32}, +@code{atmega32c1}, @code{atmega32hvb}, @code{atmega32m1}, +@code{atmega32u4}, @code{atmega32u6}, @code{atmega323}, +@code{atmega324a}, @code{atmega324p}, @code{atmega324pa}, +@code{atmega325}, @code{atmega325a}, @code{atmega325p}, @code{atmega3250}, @code{atmega3250a}, @code{atmega3250p}, -@code{atmega325a}, @code{atmega325p}, @code{atmega328}, -@code{atmega328p}, @code{atmega329}, @code{atmega3290}, -@code{atmega3290a}, @code{atmega3290p}, @code{atmega329a}, -@code{atmega329p}, @code{atmega329pa}, @code{atmega32c1}, -@code{atmega32hvb}, @code{atmega32m1}, @code{atmega32u4}, -@code{atmega32u6}, @code{atmega406}, @code{atmega64}, -@code{atmega640}, @code{atmega644}, @code{atmega644a}, -@code{atmega644p}, @code{atmega644pa}, @code{atmega645}, -@code{atmega6450}, @code{atmega6450a}, @code{atmega6450p}, -@code{atmega645a}, @code{atmega645p}, @code{atmega649}, -@code{atmega6490}, @code{atmega649a}, @code{atmega649p}, -@code{atmega64c1}, @code{atmega64hve}, @code{atmega64m1}, +@code{atmega328}, @code{atmega328p}, @code{atmega329}, +@code{atmega329a}, @code{atmega329p}, @code{atmega329pa}, +@code{atmega3290}, @code{atmega3290a}, @code{atmega3290p}, +@code{atmega406}, @code{atmega64}, @code{atmega64c1}, +@code{atmega64hve}, @code{atmega64m1}, @code{atmega640}, +@code{atmega644}, @code{atmega644a}, @code{atmega644p}, +@code{atmega644pa}, @code{atmega645}, @code{atmega645a}, +@code{atmega645p}, @code{atmega6450}, @code{atmega6450a}, +@code{atmega6450p}, @code{atmega649}, @code{atmega649a}, +@code{atmega649p}, @code{atmega6490}, @code{at90can32}, +@code{at90can64}, @code{at90pwm216}, @code{at90pwm316}, +@code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{m3000}. @item avr51 ``Enhanced'' devices with 128@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{at90can128}, @code{at90usb1286}, -@code{at90usb1287}, @code{atmega128}, @code{atmega1280}, -@code{atmega1281}, @code{atmega1284p}, @code{atmega128rfa1}. +@*@var{mcu}@tie{}= @code{atmega128}, @code{atmega128rfa1}, +@code{atmega1280}, @code{atmega1281}, @code{atmega1284p}, +@code{at90can128}, @code{at90usb1286}, @code{at90usb1287}. @item avr6 ``Enhanced'' devices with 3-byte PC, i.e.@: with more than @@ -11078,8 +11076,8 @@ more than 64@tie{}KiB of RAM. @item avr1 This ISA is implemented by the minimal AVR core and supported for assembler only. -@*@var{mcu}@tie{}= @code{at90s1200}, @code{attiny11}, @code{attiny12}, -@code{attiny15}, @code{attiny28}. +@*@var{mcu}@tie{}= @code{attiny11}, @code{attiny12}, @code{attiny15}, +@code{attiny28}, @code{at90s1200}. @end table @@ -11376,6 +11374,23 @@ For even more AVR-specific built-in macros see @table @code +@item __AVR_ARCH__ +Build-in macro that resolves to a decimal number that identifies the +architecture and depends on the @code{-mmcu=@var{mcu}} option. +Possible values are: + +@code{2}, @code{25}, @code{3}, @code{31}, @code{35}, +@code{4}, @code{5}, @code{51}, @code{6}, @code{102}, @code{104}, +@code{105}, @code{106}, @code{107} + +for @var{mcu}=@code{avr2}, @code{avr25}, @code{avr3}, +@code{avr31}, @code{avr35}, @code{avr4}, @code{avr5}, @code{avr51}, +@code{avr6}, @code{avrxmega2}, @code{avrxmega4}, @code{avrxmega5}, +@code{avrxmega6}, @code{avrxmega7}, respectively. +If @var{mcu} specifies a device, this built-in macro is set +accordingly. For example, with @code{-mmcu=atmega8} the macro will be +defined to @code{4}. + @item __AVR_@var{Device}__ Setting @code{-mmcu=@var{device}} defines this built-in macro which reflects the device's name. For example, @code{-mmcu=atmega8} defines the @@ -11388,6 +11403,9 @@ the device name as from the AVR user manual. The difference between @var{Device} in the built-in macro and @var{device} in @code{-mmcu=@var{device}} is that the latter is always lowercase. +If @var{device} is not a device but only a core architecture like +@code{avr51}, this macro will not be defined. + @item __AVR_HAVE_ELPM__ The device has the the @code{ELPM} instruction. diff --git a/gcc/dse.c b/gcc/dse.c index a9fe9249369..7d4dbf45a1a 100644 --- a/gcc/dse.c +++ b/gcc/dse.c @@ -996,7 +996,32 @@ delete_dead_store_insn (insn_info_t insn_info) insn_info->wild_read = false; } -/* Check if EXPR can possibly escape the current function scope. */ +/* Return whether DECL, a local variable, can possibly escape the current + function scope. */ + +static bool +local_variable_can_escape (tree decl) +{ + if (TREE_ADDRESSABLE (decl)) + return true; + + /* If this is a partitioned variable, we need to consider all the variables + in the partition. This is necessary because a store into one of them can + be replaced with a store into another and this may not change the outcome + of the escape analysis. */ + if (cfun->gimple_df->decls_to_pointers != NULL) + { + void *namep + = pointer_map_contains (cfun->gimple_df->decls_to_pointers, decl); + if (namep) + return TREE_ADDRESSABLE (*(tree *)namep); + } + + return false; +} + +/* Return whether EXPR can possibly escape the current function scope. */ + static bool can_escape (tree expr) { @@ -1005,7 +1030,11 @@ can_escape (tree expr) return true; base = get_base_address (expr); if (DECL_P (base) - && !may_be_aliased (base)) + && !may_be_aliased (base) + && !(TREE_CODE (base) == VAR_DECL + && !DECL_EXTERNAL (base) + && !TREE_STATIC (base) + && local_variable_can_escape (base))) return false; return true; } diff --git a/gcc/fold-const.c b/gcc/fold-const.c index 26d43e41e82..3636a2f34ee 100644 --- a/gcc/fold-const.c +++ b/gcc/fold-const.c @@ -6781,12 +6781,14 @@ fold_sign_changed_comparison (location_t loc, enum tree_code code, tree type, && TREE_TYPE (TREE_OPERAND (arg1, 0)) == inner_type)) return NULL_TREE; - if ((TYPE_UNSIGNED (inner_type) != TYPE_UNSIGNED (outer_type) - || POINTER_TYPE_P (inner_type) != POINTER_TYPE_P (outer_type)) + if (TYPE_UNSIGNED (inner_type) != TYPE_UNSIGNED (outer_type) && code != NE_EXPR && code != EQ_EXPR) return NULL_TREE; + if (POINTER_TYPE_P (inner_type) != POINTER_TYPE_P (outer_type)) + return NULL_TREE; + if (TREE_CODE (arg1) == INTEGER_CST) arg1 = force_fit_type_double (inner_type, tree_to_double_int (arg1), 0, TREE_OVERFLOW (arg1)); diff --git a/gcc/gimplify.c b/gcc/gimplify.c index a10d17e10da..2eeca40a851 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -119,6 +119,19 @@ mark_addressable (tree x) && TREE_CODE (x) != RESULT_DECL) return; TREE_ADDRESSABLE (x) = 1; + + /* Also mark the artificial SSA_NAME that points to the partition of X. */ + if (TREE_CODE (x) == VAR_DECL + && !DECL_EXTERNAL (x) + && !TREE_STATIC (x) + && cfun->gimple_df != NULL + && cfun->gimple_df->decls_to_pointers != NULL) + { + void *namep + = pointer_map_contains (cfun->gimple_df->decls_to_pointers, x); + if (namep) + TREE_ADDRESSABLE (*(tree *)namep) = 1; + } } /* Return a hash value for a formal temporary table entry. */ diff --git a/gcc/go/ChangeLog b/gcc/go/ChangeLog index 2165911fa72..d78924ba60c 100644 --- a/gcc/go/ChangeLog +++ b/gcc/go/ChangeLog @@ -1,3 +1,14 @@ +2012-10-30 Ian Lance Taylor <iant@google.com> + + * lang.opt (-fgo-relative-import-path): New option. + * go-lang.c (go_relative_import_path): New static variable. + (go_langhook_init): Pass go_relative_import_path to + go_create_gogo. + (go_langhook_handle_option): Handle -fgo-relative-import-path. + * go-c.h (go_create_gogo): Update declaration. + * gccgo.texi (Invoking gccgo): Document + -fgo-relative-import-path. + 2012-09-20 Ian Lance Taylor <iant@google.com> * Make-lang.in (go/gogo.o): Depend on filenames.h. diff --git a/gcc/go/gccgo.texi b/gcc/go/gccgo.texi index a5e37e76e80..91930c812f6 100644 --- a/gcc/go/gccgo.texi +++ b/gcc/go/gccgo.texi @@ -184,6 +184,12 @@ Using either @option{-fgo-pkgpath} or @option{-fgo-prefix} disables the special treatment of the @code{main} package and permits that package to be imported like any other. +@item -fgo-relative-import-path=@var{dir} +@cindex @option{-fgo-relative-import-path} +A relative import is an import that starts with @file{./} or +@file{../}. If this option is used, @command{gccgo} will use +@var{dir} as a prefix for the relative import when searching for it. + @item -frequire-return-statement @itemx -fno-require-return-statement @cindex @option{-frequire-return-statement} diff --git a/gcc/go/go-c.h b/gcc/go/go-c.h index d46a08796e3..ea59fb6b39a 100644 --- a/gcc/go/go-c.h +++ b/gcc/go/go-c.h @@ -42,7 +42,8 @@ extern int go_enable_optimize (const char*); extern void go_add_search_path (const char*); extern void go_create_gogo (int int_type_size, int pointer_size, - const char* pkgpath, const char *prefix); + const char* pkgpath, const char *prefix, + const char *relative_import_path); extern void go_parse_input_files (const char**, unsigned int, bool only_check_syntax, diff --git a/gcc/go/go-lang.c b/gcc/go/go-lang.c index f02f769252b..61ca1478be6 100644 --- a/gcc/go/go-lang.c +++ b/gcc/go/go-lang.c @@ -85,6 +85,7 @@ struct GTY(()) language_function static const char *go_pkgpath = NULL; static const char *go_prefix = NULL; +static const char *go_relative_import_path = NULL; /* Language hooks. */ @@ -101,7 +102,8 @@ go_langhook_init (void) to, e.g., unsigned_char_type_node) but before calling build_common_builtin_nodes (because it calls, indirectly, go_type_for_size). */ - go_create_gogo (INT_TYPE_SIZE, POINTER_SIZE, go_pkgpath, go_prefix); + go_create_gogo (INT_TYPE_SIZE, POINTER_SIZE, go_pkgpath, go_prefix, + go_relative_import_path); build_common_builtin_nodes (); @@ -240,6 +242,10 @@ go_langhook_handle_option ( go_prefix = arg; break; + case OPT_fgo_relative_import_path_: + go_relative_import_path = arg; + break; + default: /* Just return 1 to indicate that the option is valid. */ break; diff --git a/gcc/go/gofrontend/go.cc b/gcc/go/gofrontend/go.cc index 1f2ce8adcde..11692af8095 100644 --- a/gcc/go/gofrontend/go.cc +++ b/gcc/go/gofrontend/go.cc @@ -21,7 +21,7 @@ static Gogo* gogo; GO_EXTERN_C void go_create_gogo(int int_type_size, int pointer_size, const char *pkgpath, - const char *prefix) + const char *prefix, const char *relative_import_path) { go_assert(::gogo == NULL); Linemap* linemap = go_get_linemap(); @@ -32,6 +32,9 @@ go_create_gogo(int int_type_size, int pointer_size, const char *pkgpath, else if (prefix != NULL) ::gogo->set_prefix(prefix); + if (relative_import_path != NULL) + ::gogo->set_relative_import_path(relative_import_path); + // FIXME: This should be in the gcc dependent code. ::gogo->define_builtin_function_trees(); } diff --git a/gcc/go/gofrontend/gogo.cc b/gcc/go/gofrontend/gogo.cc index fa61808ec3c..c0aa496acc3 100644 --- a/gcc/go/gofrontend/gogo.cc +++ b/gcc/go/gofrontend/gogo.cc @@ -44,6 +44,7 @@ Gogo::Gogo(Backend* backend, Linemap* linemap, int int_type_size, pkgpath_set_(false), pkgpath_from_option_(false), prefix_from_option_(false), + relative_import_path_(), verify_types_(), interface_types_(), specific_type_functions_(), @@ -477,7 +478,8 @@ Gogo::import_package(const std::string& filename, return; } - Import::Stream* stream = Import::open_package(filename, location); + Import::Stream* stream = Import::open_package(filename, location, + this->relative_import_path_); if (stream == NULL) { error_at(location, "import file %qs not found", filename.c_str()); diff --git a/gcc/go/gofrontend/gogo.h b/gcc/go/gofrontend/gogo.h index 36709f5b45b..cc707ad2dde 100644 --- a/gcc/go/gofrontend/gogo.h +++ b/gcc/go/gofrontend/gogo.h @@ -206,6 +206,17 @@ class Gogo pkgpath_from_option() const { return this->pkgpath_from_option_; } + // Return the relative import path as set from the command line. + // Returns an empty string if it was not set. + const std::string& + relative_import_path() const + { return this->relative_import_path_; } + + // Set the relative import path from a command line option. + void + set_relative_import_path(const std::string& s) + {this->relative_import_path_ = s; } + // Return the priority to use for the package we are compiling. // This is two more than the largest priority of any package we // import. @@ -732,6 +743,9 @@ class Gogo bool pkgpath_from_option_; // Whether an explicit prefix was set by -fgo-prefix. bool prefix_from_option_; + // The relative import path, from the -fgo-relative-import-path + // option. + std::string relative_import_path_; // A list of types to verify. std::vector<Type*> verify_types_; // A list of interface types defined while parsing. diff --git a/gcc/go/gofrontend/import.cc b/gcc/go/gofrontend/import.cc index 9febf231897..4913100b5fd 100644 --- a/gcc/go/gofrontend/import.cc +++ b/gcc/go/gofrontend/import.cc @@ -41,6 +41,9 @@ go_add_search_path(const char* path) // When FILENAME is not an absolute path and does not start with ./ or // ../, we use the search path provided by -I and -L options. +// When FILENAME does start with ./ or ../, we use +// RELATIVE_IMPORT_PATH as a prefix. + // When FILENAME does not exist, we try modifying FILENAME to find the // file. We use the first of these which exists: // * We append ".gox". @@ -55,19 +58,35 @@ go_add_search_path(const char* path) // later in the search path. Import::Stream* -Import::open_package(const std::string& filename, Location location) +Import::open_package(const std::string& filename, Location location, + const std::string& relative_import_path) { bool is_local; if (IS_ABSOLUTE_PATH(filename)) is_local = true; - else if (filename[0] == '.' && IS_DIR_SEPARATOR(filename[1])) + else if (filename[0] == '.' + && (filename[1] == '\0' || IS_DIR_SEPARATOR(filename[1]))) is_local = true; else if (filename[0] == '.' && filename[1] == '.' - && IS_DIR_SEPARATOR(filename[2])) + && (filename[2] == '\0' || IS_DIR_SEPARATOR(filename[2]))) is_local = true; else is_local = false; + + std::string fn = filename; + if (is_local && !IS_ABSOLUTE_PATH(filename) && !relative_import_path.empty()) + { + if (fn == ".") + { + // A special case. + fn = relative_import_path; + } + else + fn = relative_import_path + '/' + fn; + is_local = false; + } + if (!is_local) { for (std::vector<std::string>::const_iterator p = search_path.begin(); @@ -77,14 +96,14 @@ Import::open_package(const std::string& filename, Location location) std::string indir = *p; if (!indir.empty() && indir[indir.size() - 1] != '/') indir += '/'; - indir += filename; + indir += fn; Stream* s = Import::try_package_in_directory(indir, location); if (s != NULL) return s; } } - Stream* s = Import::try_package_in_directory(filename, location); + Stream* s = Import::try_package_in_directory(fn, location); if (s != NULL) return s; diff --git a/gcc/go/gofrontend/import.h b/gcc/go/gofrontend/import.h index 67bdcb02d57..c6844cda8a5 100644 --- a/gcc/go/gofrontend/import.h +++ b/gcc/go/gofrontend/import.h @@ -124,8 +124,10 @@ class Import // Find import data. This searches the file system for FILENAME and // returns a pointer to a Stream object to read the data that it // exports. LOCATION is the location of the import statement. + // RELATIVE_IMPORT_PATH is used as a prefix for a relative import. static Stream* - open_package(const std::string& filename, Location location); + open_package(const std::string& filename, Location location, + const std::string& relative_import_path); // Constructor. Import(Stream*, Location); diff --git a/gcc/go/lang.opt b/gcc/go/lang.opt index eb9ed9a63a0..22197a71e3d 100644 --- a/gcc/go/lang.opt +++ b/gcc/go/lang.opt @@ -61,6 +61,10 @@ fgo-prefix= Go Joined RejectNegative -fgo-prefix=<string> Set package-specific prefix for exported Go names +fgo-relative-import-path= +Go Joined RejectNegative +-fgo-relative-import-path=<path> Treat a relative import as relative to path + frequire-return-statement Go Var(go_require_return_statement) Init(1) Warning Functions which return values must end with return statements diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index e4e13abe0aa..49b489e0707 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -44,6 +44,7 @@ #include "tree-pass.h" #include "df.h" #include "vec.h" +#include "pointer-set.h" #include "vecprim.h" #include "dbgcnt.h" @@ -2689,12 +2690,14 @@ noce_process_if_block (struct noce_if_info *if_info) /* Check whether a block is suitable for conditional move conversion. Every insn must be a simple set of a register to a constant or a - register. For each assignment, store the value in the array VALS, - indexed by register number, then store the register number in - REGS. COND is the condition we will test. */ + register. For each assignment, store the value in the pointer map + VALS, keyed indexed by register pointer, then store the register + pointer in REGS. COND is the condition we will test. */ static int -check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, +check_cond_move_block (basic_block bb, + struct pointer_map_t *vals, + VEC (rtx, heap) **regs, rtx cond) { rtx insn; @@ -2708,6 +2711,7 @@ check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, FOR_BB_INSNS (bb, insn) { rtx set, dest, src; + void **slot; if (!NONDEBUG_INSN_P (insn) || JUMP_P (insn)) continue; @@ -2734,14 +2738,14 @@ check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, /* Don't try to handle this if the source register was modified earlier in the block. */ if ((REG_P (src) - && vals[REGNO (src)] != NULL) + && pointer_map_contains (vals, src)) || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src)) - && vals[REGNO (SUBREG_REG (src))] != NULL)) + && pointer_map_contains (vals, SUBREG_REG (src)))) return FALSE; /* Don't try to handle this if the destination register was modified earlier in the block. */ - if (vals[REGNO (dest)] != NULL) + if (pointer_map_contains (vals, dest)) return FALSE; /* Don't try to handle this if the condition uses the @@ -2755,17 +2759,18 @@ check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, && modified_between_p (src, insn, NEXT_INSN (BB_END (bb)))) return FALSE; - vals[REGNO (dest)] = src; + slot = pointer_map_insert (vals, (void *) dest); + *slot = (void *) src; - VEC_safe_push (int, heap, *regs, REGNO (dest)); + VEC_safe_push (rtx, heap, *regs, dest); } return TRUE; } /* Given a basic block BB suitable for conditional move conversion, - a condition COND, and arrays THEN_VALS and ELSE_VALS containing the - register values depending on COND, emit the insns in the block as + a condition COND, and pointer maps THEN_VALS and ELSE_VALS containing + the register values depending on COND, emit the insns in the block as conditional moves. If ELSE_BLOCK is true, THEN_BB was already processed. The caller has started a sequence for the conversion. Return true if successful, false if something goes wrong. */ @@ -2773,7 +2778,8 @@ check_cond_move_block (basic_block bb, rtx *vals, VEC (int, heap) **regs, static bool cond_move_convert_if_block (struct noce_if_info *if_infop, basic_block bb, rtx cond, - rtx *then_vals, rtx *else_vals, + struct pointer_map_t *then_vals, + struct pointer_map_t *else_vals, bool else_block_p) { enum rtx_code code; @@ -2786,7 +2792,7 @@ cond_move_convert_if_block (struct noce_if_info *if_infop, FOR_BB_INSNS (bb, insn) { rtx set, target, dest, t, e; - unsigned int regno; + void **then_slot, **else_slot; /* ??? Maybe emit conditional debug insn? */ if (!NONDEBUG_INSN_P (insn) || JUMP_P (insn)) @@ -2795,10 +2801,11 @@ cond_move_convert_if_block (struct noce_if_info *if_infop, gcc_assert (set && REG_P (SET_DEST (set))); dest = SET_DEST (set); - regno = REGNO (dest); - t = then_vals[regno]; - e = else_vals[regno]; + then_slot = pointer_map_contains (then_vals, dest); + else_slot = pointer_map_contains (else_vals, dest); + t = then_slot ? (rtx) *then_slot : NULL_RTX; + e = else_slot ? (rtx) *else_slot : NULL_RTX; if (else_block_p) { @@ -2842,31 +2849,25 @@ cond_move_process_if_block (struct noce_if_info *if_info) rtx jump = if_info->jump; rtx cond = if_info->cond; rtx seq, loc_insn; - int max_reg, size, c, reg; - rtx *then_vals; - rtx *else_vals; - VEC (int, heap) *then_regs = NULL; - VEC (int, heap) *else_regs = NULL; + rtx reg; + int c; + struct pointer_map_t *then_vals; + struct pointer_map_t *else_vals; + VEC (rtx, heap) *then_regs = NULL; + VEC (rtx, heap) *else_regs = NULL; unsigned int i; + int success_p = FALSE; /* Build a mapping for each block to the value used for each register. */ - max_reg = max_reg_num (); - size = (max_reg + 1) * sizeof (rtx); - then_vals = (rtx *) alloca (size); - else_vals = (rtx *) alloca (size); - memset (then_vals, 0, size); - memset (else_vals, 0, size); + then_vals = pointer_map_create (); + else_vals = pointer_map_create (); /* Make sure the blocks are suitable. */ if (!check_cond_move_block (then_bb, then_vals, &then_regs, cond) || (else_bb && !check_cond_move_block (else_bb, else_vals, &else_regs, cond))) - { - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return FALSE; - } + goto done; /* Make sure the blocks can be used together. If the same register is set in both blocks, and is not set to a constant in both @@ -2875,41 +2876,38 @@ cond_move_process_if_block (struct noce_if_info *if_info) source register does not change after the assignment. Also count the number of registers set in only one of the blocks. */ c = 0; - FOR_EACH_VEC_ELT (int, then_regs, i, reg) + FOR_EACH_VEC_ELT (rtx, then_regs, i, reg) { - if (!then_vals[reg] && !else_vals[reg]) - continue; + void **then_slot = pointer_map_contains (then_vals, reg); + void **else_slot = pointer_map_contains (else_vals, reg); - if (!else_vals[reg]) + gcc_checking_assert (then_slot); + if (!else_slot) ++c; else { - if (!CONSTANT_P (then_vals[reg]) - && !CONSTANT_P (else_vals[reg]) - && !rtx_equal_p (then_vals[reg], else_vals[reg])) - { - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return FALSE; - } + rtx then_val = (rtx) *then_slot; + rtx else_val = (rtx) *else_slot; + if (!CONSTANT_P (then_val) && !CONSTANT_P (else_val) + && !rtx_equal_p (then_val, else_val)) + goto done; } } /* Finish off c for MAX_CONDITIONAL_EXECUTE. */ - FOR_EACH_VEC_ELT (int, else_regs, i, reg) - if (!then_vals[reg]) - ++c; + FOR_EACH_VEC_ELT (rtx, else_regs, i, reg) + { + gcc_checking_assert (pointer_map_contains (else_vals, reg)); + if (!pointer_map_contains (then_vals, reg)) + ++c; + } /* Make sure it is reasonable to convert this block. What matters is the number of assignments currently made in only one of the branches, since if we convert we are going to always execute them. */ if (c > MAX_CONDITIONAL_EXECUTE) - { - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return FALSE; - } + goto done; /* Try to emit the conditional moves. First do the then block, then do anything left in the else blocks. */ @@ -2921,17 +2919,11 @@ cond_move_process_if_block (struct noce_if_info *if_info) then_vals, else_vals, true))) { end_sequence (); - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return FALSE; + goto done; } seq = end_ifcvt_sequence (if_info); if (!seq) - { - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return FALSE; - } + goto done; loc_insn = first_active_insn (then_bb); if (!loc_insn) @@ -2962,9 +2954,14 @@ cond_move_process_if_block (struct noce_if_info *if_info) num_updated_if_blocks++; - VEC_free (int, heap, then_regs); - VEC_free (int, heap, else_regs); - return TRUE; + success_p = TRUE; + +done: + pointer_map_destroy (then_vals); + pointer_map_destroy (else_vals); + VEC_free (rtx, heap, then_regs); + VEC_free (rtx, heap, else_regs); + return success_p; } diff --git a/gcc/sel-sched-ir.c b/gcc/sel-sched-ir.c index e74fee248b5..74089df38d7 100644 --- a/gcc/sel-sched-ir.c +++ b/gcc/sel-sched-ir.c @@ -3224,7 +3224,11 @@ has_dependence_note_reg_use (int regno) if (reg_last->clobbers) *dsp = (*dsp & ~SPECULATIVE) | DEP_ANTI; - /* Handle BE_IN_SPEC. */ + /* Merge BE_IN_SPEC bits into *DSP when the dependency producer + is actually a check insn. We need to do this for any register + read-read dependency with the check unless we track properly + all registers written by BE_IN_SPEC-speculated insns, as + we don't have explicit dependence lists. See PR 53975. */ if (reg_last->uses) { ds_t pro_spec_checked_ds; @@ -3232,9 +3236,7 @@ has_dependence_note_reg_use (int regno) pro_spec_checked_ds = INSN_SPEC_CHECKED_DS (has_dependence_data.pro); pro_spec_checked_ds = ds_get_max_dep_weak (pro_spec_checked_ds); - if (pro_spec_checked_ds != 0 - && bitmap_bit_p (INSN_REG_SETS (has_dependence_data.pro), regno)) - /* Merge BE_IN_SPEC bits into *DSP. */ + if (pro_spec_checked_ds != 0) *dsp = ds_full_merge (*dsp, pro_spec_checked_ds, NULL_RTX, NULL_RTX); } diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c index 2af01aea99e..abbfa84ff3a 100644 --- a/gcc/sel-sched.c +++ b/gcc/sel-sched.c @@ -3567,29 +3567,41 @@ process_use_exprs (av_set_t *av_ptr) return NULL; } -/* Lookup EXPR in VINSN_VEC and return TRUE if found. */ +/* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from + EXPR's history of changes. */ static bool vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr) { - vinsn_t vinsn; + vinsn_t vinsn, expr_vinsn; int n; + unsigned i; - FOR_EACH_VEC_ELT (vinsn_t, vinsn_vec, n, vinsn) - if (VINSN_SEPARABLE_P (vinsn)) - { - if (vinsn_equal_p (vinsn, EXPR_VINSN (expr))) - return true; - } - else - { - /* For non-separable instructions, the blocking insn can have - another pattern due to substitution, and we can't choose - different register as in the above case. Check all registers - being written instead. */ - if (bitmap_intersect_p (VINSN_REG_SETS (vinsn), - VINSN_REG_SETS (EXPR_VINSN (expr)))) - return true; - } + /* Start with checking expr itself and then proceed with all the old forms + of expr taken from its history vector. */ + for (i = 0, expr_vinsn = EXPR_VINSN (expr); + expr_vinsn; + expr_vinsn = (i < VEC_length (expr_history_def, + EXPR_HISTORY_OF_CHANGES (expr)) + ? VEC_index (expr_history_def, + EXPR_HISTORY_OF_CHANGES (expr), + i++)->old_expr_vinsn + : NULL)) + FOR_EACH_VEC_ELT (vinsn_t, vinsn_vec, n, vinsn) + if (VINSN_SEPARABLE_P (vinsn)) + { + if (vinsn_equal_p (vinsn, expr_vinsn)) + return true; + } + else + { + /* For non-separable instructions, the blocking insn can have + another pattern due to substitution, and we can't choose + different register as in the above case. Check all registers + being written instead. */ + if (bitmap_intersect_p (VINSN_REG_SETS (vinsn), + VINSN_REG_SETS (expr_vinsn))) + return true; + } return false; } @@ -5697,8 +5709,8 @@ update_and_record_unavailable_insns (basic_block book_block) || EXPR_TARGET_AVAILABLE (new_expr) != EXPR_TARGET_AVAILABLE (cur_expr)) /* Unfortunately, the below code could be also fired up on - separable insns. - FIXME: add an example of how this could happen. */ + separable insns, e.g. when moving insns through the new + speculation check as in PR 53701. */ vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr); } diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index e2b560ce460..50cb3236af3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,75 @@ +2012-11-02 Jeff Law <law@redhat.com> + + * gcc.c-torture/execute/pr54985.c: New test. + +2012-10-29 Eric Botcazou <ebotcazou@adacore.com> + + PR ada/53517 + * gnat.dg/lto14.adb: Skip on Solaris. + +2012-10-26 Paolo Carlini <paolo.carlini@oracle.com> + + PR c++/54984 + * g++.dg/template/new11.C: New. + +2012-10-26 Terry Guo <terry.guo@arm.com> + + Backport from mainline + 2012-10-23 Terry Guo <terry.guo@arm.com> + + PR target/55019 + * gcc.dg/pr55019.c: New. + +2012-10-25 Richard Biener <rguenther@suse.de> + + PR tree-optimization/54902 + * g++.dg/torture/pr54902.C: New testcase. + +2012-10-22 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/modular4.adb: New test. + * gnat.dg/modular4_pkg.ads: New helper. + +2012-10-21 Eric Botcazou <ebotcazou@adacore.com> + + * gnat.dg/specs/atomic1.ads: XFAIL on MIPS. + * gnat.dg/specs/addr1.ads: Likewise. + +2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + Backport from mainline + 2012-10-19 Zhenqiang Chen <zhenqiang.chen@linaro.org> + + PR target/54892 + * gcc.target/arm/pr54892.c: New. + +2012-10-16 Andrey Belevantsev <abel@ispras.ru> + + Backport from mainline + 2012-08-09 Andrey Belevantsev <abel@ispras.ru> + + PR rtl-optimization/53701 + * gcc.dg/pr53701.c: New test. + +2012-10-15 Uros Bizjak <ubizjak@gmail.com> + + Backport from mainline + 2012-10-15 Uros Bizjak <ubizjak@gmail.com> + + * gcc.target/i386/avx256-unaligned-load-1.c: Update asm scan patterns. + * gcc.target/i386/avx256-unaligned-load-2.c: Ditto. + * gcc.target/i386/avx256-unaligned-load-3.c: Ditto. + * gcc.target/i386/avx256-unaligned-load-4.c: Ditto. + * gcc.target/i386/avx256-unaligned-store-1.c: Ditto. + * gcc.target/i386/avx256-unaligned-store-2.c: Ditto. + * gcc.target/i386/avx256-unaligned-store-3.c: Ditto. + * gcc.target/i386/avx256-unaligned-store-4.c: Ditto. + +2012-10-15 Richard Guenther <rguenther@suse.de> + + PR tree-optimization/54920 + * gcc.dg/torture/pr54920.c: New testcase. + 2012-10-14 Janus Weil <janus@gcc.gnu.org> PR fortran/54784 diff --git a/gcc/testsuite/g++.dg/template/new11.C b/gcc/testsuite/g++.dg/template/new11.C new file mode 100644 index 00000000000..76f6c66997f --- /dev/null +++ b/gcc/testsuite/g++.dg/template/new11.C @@ -0,0 +1,28 @@ +// PR c++/54984 +// { dg-do run } + +int n = 1; + +void* operator new(__SIZE_TYPE__) +{ + n = -1; + return &n; +} + +template <class T> +struct Foo +{ + Foo() + : x(new int) + { + if (*x != -1) + __builtin_abort(); + } + + int* x; +}; + +int main() +{ + Foo<float> foo; +} diff --git a/gcc/testsuite/g++.dg/torture/pr54902.C b/gcc/testsuite/g++.dg/torture/pr54902.C new file mode 100644 index 00000000000..790ffe5fcb5 --- /dev/null +++ b/gcc/testsuite/g++.dg/torture/pr54902.C @@ -0,0 +1,131 @@ +// { dg-do compile } + +namespace std __attribute__ ((__visibility__ ("default"))) { + template<typename _Iterator> struct iterator_traits { + }; + template<typename _Tp> struct iterator_traits<_Tp*> { + typedef _Tp& reference; + }; +} +namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) { + using std::iterator_traits; + template<typename _Iterator, typename _Container> class __normal_iterator { + _Iterator _M_current; + typedef iterator_traits<_Iterator> __traits_type; + public: + typedef typename __traits_type::reference reference; + explicit __normal_iterator(const _Iterator& __i) : _M_current(__i) { + } + reference operator*() const { + return *_M_current; + } + __normal_iterator operator++(int) { + return __normal_iterator(_M_current++); + } + }; + template<typename _Tp> class new_allocator { + public: + typedef _Tp* pointer; + template<typename _Tp1> struct rebind { + typedef new_allocator<_Tp1> other; + }; + }; +} +namespace std __attribute__ ((__visibility__ ("default"))) { + template<typename _Tp> class allocator: public __gnu_cxx::new_allocator<_Tp> { + }; +} +namespace __gnu_cxx __attribute__ ((__visibility__ ("default"))) { + template<typename _Alloc> struct __alloc_traits { + typedef typename _Alloc::pointer pointer; + template<typename _Tp> struct rebind { + typedef typename _Alloc::template rebind<_Tp>::other other; + }; + }; +} +namespace std __attribute__ ((__visibility__ ("default"))) { + template<typename _Tp, typename _Alloc> struct _Vector_base { + typedef typename __gnu_cxx::__alloc_traits<_Alloc>::template rebind<_Tp>::other _Tp_alloc_type; + typedef typename __gnu_cxx::__alloc_traits<_Tp_alloc_type>::pointer pointer; + struct _Vector_impl : public _Tp_alloc_type { + pointer _M_start; + }; + _Vector_impl _M_impl; + }; + template<typename _Tp, typename _Alloc = std::allocator<_Tp> > class vector : protected _Vector_base<_Tp, _Alloc> { + typedef _Vector_base<_Tp, _Alloc> _Base; + public: + typedef typename _Base::pointer pointer; + typedef __gnu_cxx::__normal_iterator<pointer, vector> iterator; + iterator begin() { + return iterator(this->_M_impl._M_start); + } + }; +} +class myServer { + static std::vector<myServer *> server_list; + class Callback; + class myFolder *currentFolder; + static bool eventloop(Callback *); +}; +extern "C" { + typedef unsigned int uint32_t; + typedef uint32_t unicode_char; + extern int strcmp (__const char *__s1, __const char *__s2) throw () __attribute__ ((__pure__)) __attribute__ ((__nonnull__ (1, 2))); +}; +class CursesObj { +}; +class Curses : public CursesObj { +public: + class Key { + public: + unicode_char ukey; + const char *keycode; + Key(unicode_char ch) : ukey(ch), keycode(0) { + } + bool plain() const { + } + bool nokey() const { + } + bool operator==(const Key &k) const { + return strcmp(keycode ? keycode: + "", k.keycode ? k.keycode: + "") == 0 && ukey == k.ukey; + } + }; + static bool processKey(const Key &k); +}; +class CursesContainer : public Curses { +}; +class myFolder { +public: + void checkExpunged(); +}; +class Typeahead { +public: + static Typeahead *typeahead; + bool empty() { + } + Curses::Key pop() { + } +}; +class CursesScreen : public CursesContainer { +public: + Key getKey(); +}; +using namespace std; +extern CursesScreen *cursesScreen; +bool myServer::eventloop(myServer::Callback *callback) { + Curses::Key k1= (callback == __null && !Typeahead::typeahead->empty() ? Typeahead::typeahead->pop() : cursesScreen->getKey()); + if (callback == __null || (k1.plain() && k1.ukey == '\x03')) { + if (!k1.nokey()) { + bool rc=Curses::processKey(k1); + if (rc) { while (k1.plain() && k1 == '\x03' && !Typeahead::typeahead->empty()) Typeahead::typeahead->pop(); } + } + } + vector<myServer *>::iterator b=server_list.begin(); + while (1) { + myServer *p= *b++; + if (p->currentFolder) p->currentFolder->checkExpunged(); + } +} diff --git a/gcc/testsuite/gcc.c-torture/execute/pr54985.c b/gcc/testsuite/gcc.c-torture/execute/pr54985.c new file mode 100644 index 00000000000..678c9f47ae7 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr54985.c @@ -0,0 +1,36 @@ + +typedef struct st { + int a; +} ST; + +int __attribute__((noinline,noclone)) +foo(ST *s, int c) +{ + int first = 1; + int count = c; + ST *item = s; + int a = s->a; + int x; + + while (count--) + { + x = item->a; + if (first) + first = 0; + else if (x >= a) + return 1; + a = x; + item++; + } + return 0; +} + +extern void abort (void); + +int main () +{ + ST _1[2] = {{2}, {1}}; + if (foo(_1, 2) != 0) + abort (); + return 0; +} diff --git a/gcc/testsuite/gcc.dg/pr53701.c b/gcc/testsuite/gcc.dg/pr53701.c new file mode 100644 index 00000000000..2c852238110 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr53701.c @@ -0,0 +1,59 @@ +/* { dg-do compile { target powerpc*-*-* ia64-*-* i?86-*-* x86_64-*-* } } */ +/* { dg-options "-O3 -fselective-scheduling2 -fsel-sched-pipelining" } */ +typedef unsigned short int uint16_t; +typedef unsigned long int uintptr_t; +typedef struct GFX_VTABLE +{ + int color_depth; + unsigned char *line[]; +} +BITMAP; +extern int _drawing_mode; +extern BITMAP *_drawing_pattern; +extern int _drawing_y_anchor; +extern unsigned int _drawing_x_mask; +extern unsigned int _drawing_y_mask; +extern uintptr_t bmp_write_line (BITMAP *, int); + void +_linear_hline15 (BITMAP * dst, int dx1, int dy, int dx2, int color) +{ + int w; + if (_drawing_mode == 0) + { + int x, curw; + unsigned short *sline = + (unsigned short *) (_drawing_pattern-> + line[((dy) - + _drawing_y_anchor) & _drawing_y_mask]); + unsigned short *s; + unsigned short *d = + ((unsigned short *) (bmp_write_line (dst, dy)) + (dx1)); + s = ((unsigned short *) (sline) + (x)); + if (_drawing_mode == 2) + { + } + else if (_drawing_mode == 3) + { + do + { + w -= curw; + do + { + unsigned long c = (*(s)); + if (!((unsigned long) (c) == 0x7C1F)) + { + (*((uint16_t *) ((uintptr_t) (d))) = ((color))); + } + ((s)++); + } + while (--curw > 0); + s = sline; + curw = + (((w) < + ((int) _drawing_x_mask + + 1)) ? (w) : ((int) _drawing_x_mask + 1)); + } + while (curw > 0); + } + } +} diff --git a/gcc/testsuite/gcc.dg/pr55019.c b/gcc/testsuite/gcc.dg/pr55019.c new file mode 100644 index 00000000000..1548fb258c0 --- /dev/null +++ b/gcc/testsuite/gcc.dg/pr55019.c @@ -0,0 +1,41 @@ +/* { dg-do run } */ +/* { dg-options "-O1 -funroll-loops" } */ +/* { dg-add-options ieee } */ + +extern void exit (int); +extern void abort (void); + +void +compare (double a, double b) +{ + do + { + double s1 = __builtin_copysign ((double) 1.0, a); + double s2 = __builtin_copysign ((double) 1.0, b); + + if (s1 != s2) + abort (); + + if ((__builtin_isnan (a) != 0) != (__builtin_isnan (b) != 0)) + abort (); + + if ((a != b) != (__builtin_isnan (a) != 0)) + abort (); + } while (0); +} + +int +main () +{ + double a = 0.0; + double b = 0.0; + _Complex double cr = __builtin_complex (a, b); + static _Complex double cs = __builtin_complex (0.0, 0.0); + + compare (__real__ cr, 0.0); + compare (__imag__ cr, 0.0); + compare (__real__ cs, 0.0); + compare (__imag__ cs, 0.0); + + exit (0); +} diff --git a/gcc/testsuite/gcc.dg/torture/pr54920.c b/gcc/testsuite/gcc.dg/torture/pr54920.c new file mode 100644 index 00000000000..d1622f765a7 --- /dev/null +++ b/gcc/testsuite/gcc.dg/torture/pr54920.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +typedef short __v8hi __attribute__ ((__vector_size__ (16))); +typedef long long __m128i __attribute__ ((__vector_size__ (16))); +int a; +__m128i b; + +void +fn1 () +{ + while (1) + b = (__m128i) (__v8hi) { a, 0, 0, 0, 0, 0 }; +} diff --git a/gcc/testsuite/gcc.target/arm/pr54892.c b/gcc/testsuite/gcc.target/arm/pr54892.c new file mode 100644 index 00000000000..a7fe1bc6676 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr54892.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ + +int set_role(unsigned char role_id, short m_role) +{ + return __sync_bool_compare_and_swap(&m_role, -1, role_id); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c index c2511c643b4..e7eef6d7a90 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-1.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "avx_movups256/1" } } */ -/* { dg-final { scan-assembler "sse_movups/1" } } */ +/* { dg-final { scan-assembler-not "avx_loadups256" } } */ +/* { dg-final { scan-assembler "sse_loadups" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c index 9d7167304e3..3f4fbf76479 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "avx_movdqu256/1" } } */ -/* { dg-final { scan-assembler "sse2_movdqu/1" } } */ +/* { dg-final { scan-assembler-not "avx_loaddqu256" } } */ +/* { dg-final { scan-assembler "sse2_loaddqu" } } */ /* { dg-final { scan-assembler "vinsert.128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c index efb5f573fae..b0e0e79bdd8 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-3.c @@ -14,6 +14,6 @@ avx_test (void) c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "avx_movupd256/1" } } */ -/* { dg-final { scan-assembler "sse2_movupd/1" } } */ +/* { dg-final { scan-assembler-not "avx_loadupd256" } } */ +/* { dg-final { scan-assembler "sse2_loadupd" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c index 7c015a8b90a..b3927be70ab 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-load-4.c @@ -14,6 +14,6 @@ avx_test (void) b[i] = a[i+3] * 2; } -/* { dg-final { scan-assembler "avx_movups256/1" } } */ -/* { dg-final { scan-assembler-not "avx_movups/1" } } */ +/* { dg-final { scan-assembler "avx_loadups256" } } */ +/* { dg-final { scan-assembler-not "sse_loadups" } } */ /* { dg-final { scan-assembler-not "vinsertf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c index 0b5839669a7..1a53ba14a00 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-1.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "avx_movups256/2" } } */ +/* { dg-final { scan-assembler-not "avx_storeups256" } } */ /* { dg-final { scan-assembler "vmovups.*\\*movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c index eac460fef97..e98d1b684de 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-2.c @@ -24,6 +24,6 @@ avx_test (void) } } -/* { dg-final { scan-assembler-not "avx_movdqu256/2" } } */ +/* { dg-final { scan-assembler-not "avx_storedqu256" } } */ /* { dg-final { scan-assembler "vmovdqu.*\\*movv16qi_internal/3" } } */ /* { dg-final { scan-assembler "vextract.128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c index 753625892d7..26c993be7e9 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-3.c @@ -17,6 +17,6 @@ avx_test (void) d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "avx_movupd256/2" } } */ +/* { dg-final { scan-assembler-not "avx_storeupd256" } } */ /* { dg-final { scan-assembler "vmovupd.*\\*movv2df_internal/3" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ diff --git a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c index 39b6f3bef16..6d734faa25e 100644 --- a/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c +++ b/gcc/testsuite/gcc.target/i386/avx256-unaligned-store-4.c @@ -14,7 +14,7 @@ avx_test (void) b[i+3] = a[i] * c[i]; } -/* { dg-final { scan-assembler "avx_movups256/2" } } */ -/* { dg-final { scan-assembler-not "avx_movups/2" } } */ +/* { dg-final { scan-assembler "avx_storeups256" } } */ +/* { dg-final { scan-assembler-not "sse_storeups" } } */ /* { dg-final { scan-assembler-not "\\*avx_movv4sf_internal/3" } } */ /* { dg-final { scan-assembler-not "vextractf128" } } */ diff --git a/gcc/testsuite/gnat.dg/lto14.adb b/gcc/testsuite/gnat.dg/lto14.adb index d81db7af325..22038a6ff93 100644 --- a/gcc/testsuite/gnat.dg/lto14.adb +++ b/gcc/testsuite/gnat.dg/lto14.adb @@ -1,5 +1,6 @@ -- { dg-do link } -- { dg-options "-largs -f -margs -flto" { target lto } } +-- { dg-skip-if "missing linker support" { *-*-solaris2.* } } procedure Lto14 is begin diff --git a/gcc/testsuite/gnat.dg/modular4.adb b/gcc/testsuite/gnat.dg/modular4.adb new file mode 100644 index 00000000000..e8e8f2956e1 --- /dev/null +++ b/gcc/testsuite/gnat.dg/modular4.adb @@ -0,0 +1,11 @@ +-- { dg-do compile } +-- { dg-options "-O" } + +with Modular4_Pkg; use Modular4_Pkg; + +procedure Modular4 is +begin + for I in Zero .. F mod 8 loop + raise Program_Error; + end loop; +end; diff --git a/gcc/testsuite/gnat.dg/modular4_pkg.ads b/gcc/testsuite/gnat.dg/modular4_pkg.ads new file mode 100644 index 00000000000..b38026201ed --- /dev/null +++ b/gcc/testsuite/gnat.dg/modular4_pkg.ads @@ -0,0 +1,9 @@ +package Modular4_Pkg is + + type Word is mod 2**48; + + Zero : constant Word := 0; + + function F return Word; + +end Modular4_Pkg; diff --git a/gcc/testsuite/gnat.dg/specs/addr1.ads b/gcc/testsuite/gnat.dg/specs/addr1.ads index ed048f68ef3..bcb833bec69 100644 --- a/gcc/testsuite/gnat.dg/specs/addr1.ads +++ b/gcc/testsuite/gnat.dg/specs/addr1.ads @@ -18,18 +18,18 @@ package Addr1 is A: Arr (1 .. 4); Obj1: Rec1; - for Obj1'Address use A'Address; -- { dg-bogus "alignment" } + for Obj1'Address use A'Address; -- { dg-bogus "(alignment|erroneous)" } Obj2: Rec2; - for Obj2'Address use A'Address; -- { dg-bogus "alignment" } + for Obj2'Address use A'Address; -- { dg-bogus "(alignment|erroneous)" "" { xfail mips*-*-* } } Obj3: Rec1; - for Obj3'Address use A(1)'Address; -- { dg-bogus "alignment" } + for Obj3'Address use A(1)'Address; -- { dg-bogus "(alignment|erroneous)" } Obj4: Rec1; for Obj4'Address use A(2)'Address; -- { dg-warning "(alignment|erroneous)" } Obj5: Rec1; - for Obj5'Address use A(3)'Address; -- { dg-bogus "alignment" } + for Obj5'Address use A(3)'Address; -- { dg-bogus "(alignment|erroneous)" } end Addr1; diff --git a/gcc/testsuite/gnat.dg/specs/atomic1.ads b/gcc/testsuite/gnat.dg/specs/atomic1.ads index 500cad787f3..02e98b64314 100644 --- a/gcc/testsuite/gnat.dg/specs/atomic1.ads +++ b/gcc/testsuite/gnat.dg/specs/atomic1.ads @@ -6,11 +6,11 @@ package Atomic1 is type UA is access all Arr; U : UA; - pragma Atomic (U); -- { dg-error "atomic access" } + pragma Atomic (U); -- { dg-error "atomic access" "" { xfail mips*-*-* } } type R is record U : UA; - pragma Atomic (U); -- { dg-error "atomic access" } + pragma Atomic (U); -- { dg-error "atomic access" "" { xfail mips*-*-* } } end record; end Atomic1; diff --git a/gcc/tree-ssa-pre.c b/gcc/tree-ssa-pre.c index 9ece2aa3094..2ddd798dc94 100644 --- a/gcc/tree-ssa-pre.c +++ b/gcc/tree-ssa-pre.c @@ -3063,7 +3063,7 @@ create_expression_by_pieces (basic_block block, pre_expr expr, case NARY: { vn_nary_op_t nary = PRE_EXPR_NARY (expr); - tree genop[4]; + tree *genop = XALLOCAVEC (tree, nary->length); unsigned i; for (i = 0; i < nary->length; ++i) { @@ -4820,11 +4820,12 @@ init_pre (bool do_fre) /* Deallocate data structures used by PRE. */ -static void +static unsigned fini_pre (bool do_fre) { bool do_eh_cleanup = !bitmap_empty_p (need_eh_cleanup); bool do_ab_cleanup = !bitmap_empty_p (need_ab_cleanup); + unsigned todo = 0; free (postorder); VEC_free (bitmap_set_t, heap, value_expressions); @@ -4851,10 +4852,12 @@ fini_pre (bool do_fre) BITMAP_FREE (need_ab_cleanup); if (do_eh_cleanup || do_ab_cleanup) - cleanup_tree_cfg (); + todo = TODO_cleanup_cfg; if (!do_fre) loop_optimizer_finalize (); + + return todo; } /* Main entry point to the SSA-PRE pass. DO_FRE is true if the caller @@ -4933,7 +4936,7 @@ execute_pre (bool do_fre) } scev_finalize (); - fini_pre (do_fre); + todo |= fini_pre (do_fre); if (!do_fre) /* TODO: tail_merge_optimize may merge all predecessors of a block, in which diff --git a/gcc/tree-ssa-tail-merge.c b/gcc/tree-ssa-tail-merge.c index 25ec43ebd7d..4be35f69522 100644 --- a/gcc/tree-ssa-tail-merge.c +++ b/gcc/tree-ssa-tail-merge.c @@ -1559,7 +1559,12 @@ tail_merge_optimize (unsigned int todo) timevar_push (TV_TREE_TAIL_MERGE); - calculate_dominance_info (CDI_DOMINATORS); + if (!dom_info_available_p (CDI_DOMINATORS)) + { + /* PRE can leave us with unreachable blocks, remove them now. */ + delete_unreachable_blocks (); + calculate_dominance_info (CDI_DOMINATORS); + } init_worklist (); while (!VEC_empty (same_succ, worklist)) diff --git a/gcc/tree-ssa-threadedge.c b/gcc/tree-ssa-threadedge.c index 707c8df3ec5..a2860f6f978 100644 --- a/gcc/tree-ssa-threadedge.c +++ b/gcc/tree-ssa-threadedge.c @@ -574,6 +574,44 @@ simplify_control_stmt_condition (edge e, return cached_lhs; } +/* Return TRUE if the statement at the end of e->dest depends on + the output of any statement in BB. Otherwise return FALSE. + + This is used when we are threading a backedge and need to ensure + that temporary equivalences from BB do not affect the condition + in e->dest. */ + +static bool +cond_arg_set_in_bb (edge e, basic_block bb) +{ + ssa_op_iter iter; + use_operand_p use_p; + gimple last = last_stmt (e->dest); + + /* E->dest does not have to end with a control transferring + instruction. This can occurr when we try to extend a jump + threading opportunity deeper into the CFG. In that case + it is safe for this check to return false. */ + if (!last) + return false; + + if (gimple_code (last) != GIMPLE_COND + && gimple_code (last) != GIMPLE_GOTO + && gimple_code (last) != GIMPLE_SWITCH) + return false; + + FOR_EACH_SSA_USE_OPERAND (use_p, last, iter, SSA_OP_USE | SSA_OP_VUSE) + { + tree use = USE_FROM_PTR (use_p); + + if (TREE_CODE (use) == SSA_NAME + && gimple_code (SSA_NAME_DEF_STMT (use)) != GIMPLE_PHI + && gimple_bb (SSA_NAME_DEF_STMT (use)) == bb) + return true; + } + return false; +} + /* TAKEN_EDGE represents the an edge taken as a result of jump threading. See if we can thread around TAKEN_EDGE->dest as well. If so, return the edge out of TAKEN_EDGE->dest that we can statically compute will be @@ -707,19 +745,8 @@ thread_across_edge (gimple dummy_cond, safe to thread this edge. */ if (e->flags & EDGE_DFS_BACK) { - ssa_op_iter iter; - use_operand_p use_p; - gimple last = gsi_stmt (gsi_last_bb (e->dest)); - - FOR_EACH_SSA_USE_OPERAND (use_p, last, iter, SSA_OP_USE | SSA_OP_VUSE) - { - tree use = USE_FROM_PTR (use_p); - - if (TREE_CODE (use) == SSA_NAME - && gimple_code (SSA_NAME_DEF_STMT (use)) != GIMPLE_PHI - && gimple_bb (SSA_NAME_DEF_STMT (use)) == e->dest) - goto fail; - } + if (cond_arg_set_in_bb (e, e->dest)) + goto fail; } stmt_count = 0; @@ -760,7 +787,9 @@ thread_across_edge (gimple dummy_cond, address. If DEST is not null, then see if we can thread through it as well, this helps capture secondary effects of threading without having to re-run DOM or VRP. */ - if (dest) + if (dest + && ((e->flags & EDGE_DFS_BACK) == 0 + || ! cond_arg_set_in_bb (taken_edge, e->dest))) { /* We don't want to thread back to a block we have already visited. This may be overly conservative. */ @@ -818,11 +847,16 @@ thread_across_edge (gimple dummy_cond, e3 = taken_edge; do { - e2 = thread_around_empty_block (e3, - dummy_cond, - handle_dominating_asserts, - simplify, - visited); + if ((e->flags & EDGE_DFS_BACK) == 0 + || ! cond_arg_set_in_bb (e3, e->dest)) + e2 = thread_around_empty_block (e3, + dummy_cond, + handle_dominating_asserts, + simplify, + visited); + else + e2 = NULL; + if (e2) { e3 = e2; diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c index 79c0f1dab7b..b08d7bbdcd1 100644 --- a/gcc/tree-vect-data-refs.c +++ b/gcc/tree-vect-data-refs.c @@ -4574,6 +4574,13 @@ vect_can_force_dr_alignment_p (const_tree decl, unsigned int alignment) if (TREE_ASM_WRITTEN (decl)) return false; + /* Do not override explicit alignment set by the user when an explicit + section name is also used. This is a common idiom used by many + software projects. */ + if (DECL_SECTION_NAME (decl) != NULL_TREE + && !DECL_HAS_IMPLICIT_SECTION_NAME_P (decl)) + return false; + if (TREE_STATIC (decl)) return (alignment <= MAX_OFILE_ALIGNMENT); else diff --git a/gcc/tree.h b/gcc/tree.h index d9e826b26dd..77cd5f6cddf 100644 --- a/gcc/tree.h +++ b/gcc/tree.h @@ -490,9 +490,10 @@ struct GTY(()) tree_common { TREE_ADDRESSABLE in VAR_DECL, PARM_DECL, RESULT_DECL, FUNCTION_DECL, LABEL_DECL + SSA_NAME all types CONSTRUCTOR, IDENTIFIER_NODE - STMT_EXPR, it means we want the result of the enclosed expression + STMT_EXPR CALL_EXPR_TAILCALL in CALL_EXPR @@ -1181,15 +1182,18 @@ extern void omp_clause_range_check_failed (const_tree, const char *, int, /* In VAR_DECL, PARM_DECL and RESULT_DECL nodes, nonzero means address of this is needed. So it cannot be in a register. In a FUNCTION_DECL it has no meaning. - In CONSTRUCTOR nodes, it means object constructed must be in memory. In LABEL_DECL nodes, it means a goto for this label has been seen from a place outside all binding contours that restore stack levels. + In an artificial SSA_NAME that points to a stack partition with at least + two variables, it means that at least one variable has TREE_ADDRESSABLE. In ..._TYPE nodes, it means that objects of this type must be fully addressable. This means that pieces of this object cannot go into register parameters, for example. If this a function type, this means that the value must be returned in memory. + In CONSTRUCTOR nodes, it means object constructed must be in memory. In IDENTIFIER_NODEs, this means that some extern decl for this name - had its address taken. That matters for inline functions. */ + had its address taken. That matters for inline functions. + In a STMT_EXPR, it means we want the result of the enclosed expression. */ #define TREE_ADDRESSABLE(NODE) ((NODE)->base.addressable_flag) /* Set on a CALL_EXPR if the call is in a tail position, ie. just before the diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog index a1c870ec924..7a8401dd4ae 100644 --- a/libgcc/ChangeLog +++ b/libgcc/ChangeLog @@ -1,10 +1,35 @@ +2012-11-04 Uros Bizjak <ubizjak@gmail.com> + + PR target/55175 + * config/i386/32/sfp-machine.h: Guard exception handling and + rounding handling code with _SOFT_FLOAT. + * config/i386/64/sfp-machine.h: Ditto. + +2012-10-31 Joel Sherrill <joel.sherrill@oarcorp.com> + + * config.host (m32r-*-rtems*): Include crtinit.o and crtfinit.o + as extra_parts. + +2012-10-25 Ralf Corsépius <ralf.corsepius@rtems.org> + + * config.host (sparc64-*-rtems*): Remove sparc/t-elf. + +2012-10-25 Ralf Corsépius <ralf.corsepius@rtems.org> + + * config.host (sh*-*-rtems*): Add sh*-*-elf*'s extra_parts. + +2012-10-25 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * config.host (powerpc-*-rtems*): Add rs6000/t-savresfgpr to + tmake_file. + 2012-10-06 Mark Kettenis <kettenis@openbsd.org> * config.host (*-*-openbsd*): Add t-eh-dw2-dip to tmake_file. * unwind-dw2-fde-dip.c: Don't include <elf.h> on OpenBSD. (USE_PT_GNU_EH_FRAME): Define for OpenBSD. (ElfW): Likewise. - + 2012-09-20 Release Manager * GCC 4.7.2 released. @@ -12,7 +37,7 @@ 2012-09-05 Georg-Johann Lay <avr@gjlay.de> Backport from 2012-09-05 mainline r190697. - + PR target/54461 * config.host (tmake_file,host=avr-*-*): Add avr/t-avrlibc if configured --with-avrlibc. diff --git a/libgcc/config.host b/libgcc/config.host index 617254e24d2..bbf21a99f15 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -693,6 +693,7 @@ m32r-*-elf*) ;; m32r-*-rtems*) tmake_file="$tmake_file m32r/t-m32r t-fdpbit" + extra_parts="$extra_parts crtinit.o crtfini.o" ;; m32rle-*-elf*) tmake_file=t-fdpbit @@ -891,7 +892,7 @@ powerpc-*-eabi*) extra_parts="$extra_parts crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o" ;; powerpc-*-rtems*) - tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-crtstuff t-crtstuff-pic t-fdpbit" + tmake_file="${tmake_file} rs6000/t-ppccomm rs6000/t-savresfgpr rs6000/t-crtstuff t-crtstuff-pic t-fdpbit" extra_parts="$extra_parts crtbeginS.o crtendS.o crtbeginT.o ecrti.o ecrtn.o ncrti.o ncrtn.o" ;; powerpc-*-linux* | powerpc64-*-linux*) @@ -995,7 +996,10 @@ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \ sh-*-rtems*) tmake_file="$tmake_file sh/t-sh t-crtstuff-pic t-fdpbit" extra_parts="$extra_parts crt1.o crti.o crtn.o crtbeginS.o crtendS.o \ - $sh_ic_extra_parts $sh_opt_extra_parts" + libic_invalidate_array_4-100.a \ + libic_invalidate_array_4-200.a \ + libic_invalidate_array_4a.a \ + libgcc-Os-4-200.a libgcc-4-300.a" ;; sh-wrs-vxworks) tmake_file="$tmake_file sh/t-sh t-crtstuff-pic t-fdpbit" @@ -1054,7 +1058,7 @@ sparc64-*-elf*) extra_parts="$extra_parts crti.o crtn.o crtfastmath.o" ;; sparc64-*-rtems*) - tmake_file="$tmake_file sparc/t-elf t-crtfm" + tmake_file="$tmake_file t-crtfm" extra_parts="$extra_parts crti.o crtn.o crtfastmath.o" ;; sparc-wrs-vxworks) diff --git a/libgcc/config/i386/32/sfp-machine.h b/libgcc/config/i386/32/sfp-machine.h index 1600a7fe2c7..131b2c453f2 100644 --- a/libgcc/config/i386/32/sfp-machine.h +++ b/libgcc/config/i386/32/sfp-machine.h @@ -107,6 +107,7 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); R##_c = FP_CLS_NAN; \ } while (0) +#ifndef _SOFT_FLOAT #define FP_EX_INVALID 0x01 #define FP_EX_DENORM 0x02 #define FP_EX_DIVZERO 0x04 @@ -187,6 +188,7 @@ struct fenv } while (0) #define FP_ROUNDMODE (_fcw & 0xc00) +#endif #define __LITTLE_ENDIAN 1234 #define __BIG_ENDIAN 4321 diff --git a/libgcc/config/i386/64/sfp-machine.h b/libgcc/config/i386/64/sfp-machine.h index 7a2a4beaaaf..f90305a7642 100644 --- a/libgcc/config/i386/64/sfp-machine.h +++ b/libgcc/config/i386/64/sfp-machine.h @@ -49,6 +49,7 @@ typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__))); R##_c = FP_CLS_NAN; \ } while (0) +#ifndef _SOFT_FLOAT #define FP_EX_INVALID 0x01 #define FP_EX_DENORM 0x02 #define FP_EX_DIVZERO 0x04 @@ -133,6 +134,7 @@ struct fenv } while (0) #define FP_ROUNDMODE (_fcw & 0xc00) +#endif #define __LITTLE_ENDIAN 1234 #define __BIG_ENDIAN 4321 diff --git a/libgo/mksysinfo.sh b/libgo/mksysinfo.sh index 315d60cc39d..12e0310bb43 100755 --- a/libgo/mksysinfo.sh +++ b/libgo/mksysinfo.sh @@ -225,6 +225,16 @@ done grep '^const _SIG[^_]' gen-sysinfo.go | \ grep -v '^const _SIGEV_' | \ sed -e 's/^\(const \)_\(SIG[^= ]*\)\(.*\)$/\1\2 = Signal(_\2)/' >> ${OUT} +if ! grep '^const SIGPOLL ' ${OUT} >/dev/null 2>&1; then + if grep '^const SIGIO ' ${OUT} > /dev/null 2>&1; then + echo "const SIGPOLL = SIGIO" >> ${OUT} + fi +fi +if ! grep '^const SIGCLD ' ${OUT} >/dev/null 2>&1; then + if grep '^const SIGCHLD ' ${OUT} >/dev/null 2>&1; then + echo "const SIGCLD = SIGCHLD" >> ${OUT} + fi +fi # The syscall numbers. We force the names to upper case. grep '^const _SYS_' gen-sysinfo.go | \ diff --git a/libstdc++-v3/ChangeLog b/libstdc++-v3/ChangeLog index 71de3de2a88..a752c0eca68 100644 --- a/libstdc++-v3/ChangeLog +++ b/libstdc++-v3/ChangeLog @@ -1,3 +1,23 @@ +2012-11-02 Paolo Carlini <paolo.carlini@oracle.com> + + PR libstdc++/55169 + * include/bits/random.h: Remove all uses of param(). + +2012-11-01 Haakan Younes <hyounes@google.com> + Paolo Carlini <paolo.carlini@oracle.com> + + PR libstdc++/55047 + * include/bits/random.h (exponential_distribution<>::operator): + Fix formula to std::log(result_type(1) - __aurng()). + * include/bits/random.tcc: Likewise, everywhere. + +2012-10-29 Jonathan Wakely <jwakely.gcc@gmail.com> + + PR libstdc++/55123 + * include/bits/shared_ptr_base.h (__shared_count::_S_create_from_up): + Do not instantiate allocator with element_type. + * testsuite/20_util/shared_ptr/cons/55123.cc: New. + 2012-10-10 Andrew MacLeod <amacleod@redhat.com> PR libstdc++/54861 diff --git a/libstdc++-v3/include/bits/random.h b/libstdc++-v3/include/bits/random.h index aa4ce3e8209..1e8caa023b3 100644 --- a/libstdc++-v3/include/bits/random.h +++ b/libstdc++-v3/include/bits/random.h @@ -1,6 +1,6 @@ // random number generation -*- C++ -*- -// Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +// Copyright (C) 2009-2012 Free Software Foundation, Inc. // // This file is part of the GNU ISO C++ Library. This library is free // software; you can redistribute it and/or modify it under the @@ -1719,28 +1719,28 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng, const param_type& __p); + /** + * @brief Return true if two uniform integer distributions have + * the same parameters. + */ + friend bool + operator==(const uniform_int_distribution& __d1, + const uniform_int_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + + private: param_type _M_param; }; /** * @brief Return true if two uniform integer distributions have - * the same parameters. - */ - template<typename _IntType> - inline bool - operator==(const std::uniform_int_distribution<_IntType>& __d1, - const std::uniform_int_distribution<_IntType>& __d2) - { return __d1.param() == __d2.param(); } - - /** - * @brief Return true if two uniform integer distributions have * different parameters. */ template<typename _IntType> @@ -1894,7 +1894,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -1906,22 +1906,21 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION return (__aurng() * (__p.b() - __p.a())) + __p.a(); } + /** + * @brief Return true if two uniform real distributions have + * the same parameters. + */ + friend bool + operator==(const uniform_real_distribution& __d1, + const uniform_real_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** * @brief Return true if two uniform real distributions have - * the same parameters. - */ - template<typename _IntType> - inline bool - operator==(const std::uniform_real_distribution<_IntType>& __d1, - const std::uniform_real_distribution<_IntType>& __d2) - { return __d1.param() == __d2.param(); } - - /** - * @brief Return true if two uniform real distributions have * different parameters. */ template<typename _IntType> @@ -2088,7 +2087,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -2261,7 +2260,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -2277,7 +2276,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const lognormal_distribution& __d1, const lognormal_distribution& __d2) - { return (__d1.param() == __d2.param() + { return (__d1._M_param == __d2._M_param && __d1._M_nd == __d2._M_nd); } /** @@ -2454,7 +2453,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -2469,7 +2468,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const gamma_distribution& __d1, const gamma_distribution& __d2) - { return (__d1.param() == __d2.param() + { return (__d1._M_param == __d2._M_param && __d1._M_nd == __d2._M_nd); } /** @@ -2633,7 +2632,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const chi_squared_distribution& __d1, const chi_squared_distribution& __d2) - { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; } + { return __d1._M_param == __d2._M_param && __d1._M_gd == __d2._M_gd; } /** * @brief Inserts a %chi_squared_distribution random number distribution @@ -2788,29 +2787,28 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng, const param_type& __p); + /** + * @brief Return true if two Cauchy distributions have + * the same parameters. + */ + friend bool + operator==(const cauchy_distribution& __d1, + const cauchy_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** * @brief Return true if two Cauchy distributions have - * the same parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::cauchy_distribution<_RealType>& __d1, - const std::cauchy_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** - * @brief Return true if two Cauchy distributions have * different parameters. */ template<typename _RealType> @@ -2985,7 +2983,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const fisher_f_distribution& __d1, const fisher_f_distribution& __d2) - { return (__d1.param() == __d2.param() + { return (__d1._M_param == __d2._M_param && __d1._M_gd_x == __d2._M_gd_x && __d1._M_gd_y == __d2._M_gd_y); } @@ -3158,7 +3156,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const student_t_distribution& __d1, const student_t_distribution& __d2) - { return (__d1.param() == __d2.param() + { return (__d1._M_param == __d2._M_param && __d1._M_nd == __d2._M_nd && __d1._M_gd == __d2._M_gd); } /** @@ -3318,7 +3316,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -3333,21 +3331,21 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION return false; } + /** + * @brief Return true if two Bernoulli distributions have + * the same parameters. + */ + friend bool + operator==(const bernoulli_distribution& __d1, + const bernoulli_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** * @brief Return true if two Bernoulli distributions have - * the same parameters. - */ - inline bool - operator==(const std::bernoulli_distribution& __d1, - const std::bernoulli_distribution& __d2) - { return __d1.param() == __d2.param(); } - - /** - * @brief Return true if two Bernoulli distributions have * different parameters. */ inline bool @@ -3518,7 +3516,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -3534,9 +3532,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION operator==(const binomial_distribution& __d1, const binomial_distribution& __d2) #ifdef _GLIBCXX_USE_C99_MATH_TR1 - { return __d1.param() == __d2.param() && __d1._M_nd == __d2._M_nd; } + { return __d1._M_param == __d2._M_param && __d1._M_nd == __d2._M_nd; } #else - { return __d1.param() == __d2.param(); } + { return __d1._M_param == __d2._M_param; } #endif /** @@ -3701,29 +3699,28 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng, const param_type& __p); + /** + * @brief Return true if two geometric distributions have + * the same parameters. + */ + friend bool + operator==(const geometric_distribution& __d1, + const geometric_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** * @brief Return true if two geometric distributions have - * the same parameters. - */ - template<typename _IntType> - inline bool - operator==(const std::geometric_distribution<_IntType>& __d1, - const std::geometric_distribution<_IntType>& __d2) - { return __d1.param() == __d2.param(); } - - /** - * @brief Return true if two geometric distributions have * different parameters. */ template<typename _IntType> @@ -3889,7 +3886,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION friend bool operator==(const negative_binomial_distribution& __d1, const negative_binomial_distribution& __d2) - { return __d1.param() == __d2.param() && __d1._M_gd == __d2._M_gd; } + { return __d1._M_param == __d2._M_param && __d1._M_gd == __d2._M_gd; } /** * @brief Inserts a %negative_binomial_distribution random @@ -4057,7 +4054,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -4073,9 +4070,9 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION operator==(const poisson_distribution& __d1, const poisson_distribution& __d2) #ifdef _GLIBCXX_USE_C99_MATH_TR1 - { return __d1.param() == __d2.param() && __d1._M_nd == __d2._M_nd; } + { return __d1._M_param == __d2._M_param && __d1._M_nd == __d2._M_nd; } #else - { return __d1.param() == __d2.param(); } + { return __d1._M_param == __d2._M_param; } #endif /** @@ -4238,7 +4235,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -4247,24 +4244,23 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { __detail::_Adaptor<_UniformRandomNumberGenerator, result_type> __aurng(__urng); - return -std::log(__aurng()) / __p.lambda(); + return -std::log(result_type(1) - __aurng()) / __p.lambda(); } + /** + * @brief Return true if two exponential distributions have the same + * parameters. + */ + friend bool + operator==(const exponential_distribution& __d1, + const exponential_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** - * @brief Return true if two exponential distributions have the same - * parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::exponential_distribution<_RealType>& __d1, - const std::exponential_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two exponential distributions have different * parameters. */ @@ -4418,28 +4414,27 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng, const param_type& __p); + /** + * @brief Return true if two Weibull distributions have the same + * parameters. + */ + friend bool + operator==(const weibull_distribution& __d1, + const weibull_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** - * @brief Return true if two Weibull distributions have the same - * parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::weibull_distribution<_RealType>& __d1, - const std::weibull_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two Weibull distributions have different * parameters. */ @@ -4593,28 +4588,27 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng, const param_type& __p); + /** + * @brief Return true if two extreme value distributions have the same + * parameters. + */ + friend bool + operator==(const extreme_value_distribution& __d1, + const extreme_value_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + private: param_type _M_param; }; /** - * @brief Return true if two extreme value distributions have the same - * parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::extreme_value_distribution<_RealType>& __d1, - const std::extreme_value_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two extreme value distributions have different * parameters. */ @@ -4794,7 +4788,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -4802,6 +4796,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION const param_type& __p); /** + * @brief Return true if two discrete distributions have the same + * parameters. + */ + friend bool + operator==(const discrete_distribution& __d1, + const discrete_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + + /** * @brief Inserts a %discrete_distribution random number distribution * @p __x into the output stream @p __os. * @@ -4837,16 +4840,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION }; /** - * @brief Return true if two discrete distributions have the same - * parameters. - */ - template<typename _IntType> - inline bool - operator==(const std::discrete_distribution<_IntType>& __d1, - const std::discrete_distribution<_IntType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two discrete distributions have different * parameters. */ @@ -5032,7 +5025,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -5040,6 +5033,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION const param_type& __p); /** + * @brief Return true if two piecewise constant distributions have the + * same parameters. + */ + friend bool + operator==(const piecewise_constant_distribution& __d1, + const piecewise_constant_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + + /** * @brief Inserts a %piecewise_constan_distribution random * number distribution @p __x into the output stream @p __os. * @@ -5076,16 +5078,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION }; /** - * @brief Return true if two piecewise constant distributions have the - * same parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::piecewise_constant_distribution<_RealType>& __d1, - const std::piecewise_constant_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two piecewise constant distributions have * different parameters. */ @@ -5274,7 +5266,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION template<typename _UniformRandomNumberGenerator> result_type operator()(_UniformRandomNumberGenerator& __urng) - { return this->operator()(__urng, this->param()); } + { return this->operator()(__urng, _M_param); } template<typename _UniformRandomNumberGenerator> result_type @@ -5282,6 +5274,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION const param_type& __p); /** + * @brief Return true if two piecewise linear distributions have the + * same parameters. + */ + friend bool + operator==(const piecewise_linear_distribution& __d1, + const piecewise_linear_distribution& __d2) + { return __d1._M_param == __d2._M_param; } + + /** * @brief Inserts a %piecewise_linear_distribution random number * distribution @p __x into the output stream @p __os. * @@ -5318,16 +5319,6 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION }; /** - * @brief Return true if two piecewise linear distributions have the - * same parameters. - */ - template<typename _RealType> - inline bool - operator==(const std::piecewise_linear_distribution<_RealType>& __d1, - const std::piecewise_linear_distribution<_RealType>& __d2) - { return __d1.param() == __d2.param(); } - - /** * @brief Return true if two piecewise linear distributions have * different parameters. */ diff --git a/libstdc++-v3/include/bits/random.tcc b/libstdc++-v3/include/bits/random.tcc index 5b90e5a6157..1dfa9fbe443 100644 --- a/libstdc++-v3/include/bits/random.tcc +++ b/libstdc++-v3/include/bits/random.tcc @@ -1,6 +1,6 @@ // random number generation (out of line) -*- C++ -*- -// Copyright (C) 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +// Copyright (C) 2009-2012 Free Software Foundation, Inc. // // This file is part of the GNU ISO C++ Library. This library is free // software; you can redistribute it and/or modify it under the @@ -1053,7 +1053,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION double __cand; do - __cand = std::floor(std::log(__aurng()) / __param._M_log_1_p); + __cand = std::floor(std::log(1.0 - __aurng()) / __param._M_log_1_p); while (__cand >= __thr); return result_type(__cand + __naf); @@ -1258,7 +1258,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION do { const double __u = __c * __aurng(); - const double __e = -std::log(__aurng()); + const double __e = -std::log(1.0 - __aurng()); double __w = 0.0; @@ -1290,7 +1290,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __x = 1; else { - const double __v = -std::log(__aurng()); + const double __v = -std::log(1.0 - __aurng()); const double __y = __param._M_d + __v * __2cx / __param._M_d; __x = std::ceil(__y); @@ -1434,7 +1434,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION do { - const double __e = -std::log(__aurng()); + const double __e = -std::log(1.0 - __aurng()); __sum += __e / (__t - __x); __x += 1; } @@ -1502,7 +1502,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __reject = __y >= __param._M_d1; if (!__reject) { - const double __e = -std::log(__aurng()); + const double __e = -std::log(1.0 - __aurng()); __x = std::floor(__y); __v = -__e - __n * __n / 2 + __param._M_c; } @@ -1514,15 +1514,15 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION __reject = __y >= __param._M_d2; if (!__reject) { - const double __e = -std::log(__aurng()); + const double __e = -std::log(1.0 - __aurng()); __x = std::floor(-__y); __v = -__e - __n * __n / 2; } } else if (__u <= __a123) { - const double __e1 = -std::log(__aurng()); - const double __e2 = -std::log(__aurng()); + const double __e1 = -std::log(1.0 - __aurng()); + const double __e2 = -std::log(1.0 - __aurng()); const double __y = __param._M_d1 + 2 * __s1s * __e1 / __param._M_d1; @@ -1533,8 +1533,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION } else { - const double __e1 = -std::log(__aurng()); - const double __e2 = -std::log(__aurng()); + const double __e1 = -std::log(1.0 - __aurng()); + const double __e2 = -std::log(1.0 - __aurng()); const double __y = __param._M_d2 + 2 * __s2s * __e1 / __param._M_d2; @@ -2136,7 +2136,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { __detail::_Adaptor<_UniformRandomNumberGenerator, result_type> __aurng(__urng); - return __p.b() * std::pow(-std::log(__aurng()), + return __p.b() * std::pow(-std::log(result_type(1) - __aurng()), result_type(1) / __p.a()); } @@ -2194,7 +2194,8 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { __detail::_Adaptor<_UniformRandomNumberGenerator, result_type> __aurng(__urng); - return __p.a() - __p.b() * std::log(-std::log(__aurng())); + return __p.a() - __p.b() * std::log(-std::log(result_type(1) + - __aurng())); } template<typename _RealType, typename _CharT, typename _Traits> diff --git a/libstdc++-v3/include/bits/shared_ptr_base.h b/libstdc++-v3/include/bits/shared_ptr_base.h index 39449f1b4bb..0d60eeffa5b 100644 --- a/libstdc++-v3/include/bits/shared_ptr_base.h +++ b/libstdc++-v3/include/bits/shared_ptr_base.h @@ -621,7 +621,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION _S_create_from_up(std::unique_ptr<_Tp, _Del>&& __r, typename std::enable_if<!std::is_reference<_Del>::value>::type* = 0) { - return new _Sp_counted_deleter<_Tp*, _Del, std::allocator<_Tp>, + return new _Sp_counted_deleter<_Tp*, _Del, std::allocator<void>, _Lp>(__r.get(), __r.get_deleter()); } @@ -632,7 +632,7 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION { typedef typename std::remove_reference<_Del>::type _Del1; typedef std::reference_wrapper<_Del1> _Del2; - return new _Sp_counted_deleter<_Tp*, _Del2, std::allocator<_Tp>, + return new _Sp_counted_deleter<_Tp*, _Del2, std::allocator<void>, _Lp>(__r.get(), std::ref(__r.get_deleter())); } diff --git a/libstdc++-v3/testsuite/20_util/shared_ptr/cons/55123.cc b/libstdc++-v3/testsuite/20_util/shared_ptr/cons/55123.cc new file mode 100644 index 00000000000..35b517e8863 --- /dev/null +++ b/libstdc++-v3/testsuite/20_util/shared_ptr/cons/55123.cc @@ -0,0 +1,30 @@ +// { dg-options "-std=gnu++0x" } +// { dg-do compile } + +// Copyright (C) 2012 Free Software Foundation +// +// This file is part of the GNU ISO C++ Library. This library is free +// software; you can redistribute it and/or modify it under the +// terms of the GNU General Public License as published by the +// Free Software Foundation; either version 3, or (at your option) +// any later version. + +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License along +// with this library; see the file COPYING3. If not see +// <http://www.gnu.org/licenses/>. + +#include <memory> + +// libstdc++/55123 + +#include <memory> + +void f() { + std::unique_ptr<const int> y; + std::shared_ptr<const int> x = std::move(y); +} |