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authorKyrylo Tkachov <kyrylo.tkachov@arm.com>2014-02-25 10:25:26 +0000
committerKyrylo Tkachov <kyrylo.tkachov@arm.com>2014-02-25 10:25:26 +0000
commit04895256044daf6a719d0cb0b631661ebf3b80e2 (patch)
tree94f99557e87bd4a21614d0d367d7d2cb02a5d26b
parente1d5d0949c8c48366855a9f2099c5ccce59c4fe4 (diff)
PR target/55426
* config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit conversions. git-svn-id: https://gcc.gnu.org/svn/gcc/branches/gcc-4_8-branch@208117 138bc75d-0d04-0410-961f-82ee72b054a4
-rw-r--r--gcc/ChangeLog6
-rw-r--r--gcc/config/arm/arm.h14
2 files changed, 15 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4f80188d8c6..188455bdd07 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2014-02-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ PR target/55426
+ * config/arm/arm.h (CANNOT_CHANGE_MODE_CLASS): Allow 128 to 64-bit
+ conversions.
+
2014-02-24 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.c (pa_output_move_double): Don't valididate when
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 05aea3577d7..14340ebad63 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1213,11 +1213,15 @@ enum reg_class
VFPv2.
In big-endian mode, modes greater than word size (i.e. DFmode) are stored in
VFP registers in little-endian order. We can't describe that accurately to
- GCC, so avoid taking subregs of such values. */
-#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
- (TARGET_VFP && TARGET_BIG_END \
- && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
- || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
+ GCC, so avoid taking subregs of such values.
+ The only exception is going from a 128-bit to a 64-bit type. In that case
+ the data layout happens to be consistent for big-endian, so we explicitly allow
+ that case. */
+#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
+ (TARGET_VFP && TARGET_BIG_END \
+ && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \
+ && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \
+ || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \
&& reg_classes_intersect_p (VFP_REGS, (CLASS)))
/* The class value for index registers, and the one for base regs. */