diff options
| author | Andrew Pinski <apinski@cavium.com> | 2017-02-08 02:54:17 +0000 |
|---|---|---|
| committer | Naveen H.S <Naveen.Hurugalawadi@cavium.com> | 2017-02-08 02:54:17 +0000 |
| commit | 1bc11a21dc97e33a9e8c4f4c28d255b5caa03c40 (patch) | |
| tree | e7d29bf8f776ca98aaa1aba4c0e7275969cbad18 /gcc/config/aarch64 | |
| parent | eedc52906f5d3592a9a6844a719be68f16cf04af (diff) | |
2016-02-07 Andrew Pinski <apinski@cavium.com>
gcc
* config/aarch64/aarch64.md (popcount<mode>2): New pattern.
gcc/testsuite
* gcc.target/aarch64/popcount.c : New Testcase.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@245267 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/aarch64')
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 7550c3e7c2b..5adc5edb8dd 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3779,6 +3779,39 @@ } ) +;; Pop count be done via the "CNT" instruction in AdvSIMD. +;; +;; MOV v.1d, x0 +;; CNT v1.8b, v.8b +;; ADDV b2, v1.8b +;; MOV w0, v2.b[0] + +(define_expand "popcount<mode>2" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "register_operand")] + "TARGET_SIMD" +{ + rtx v = gen_reg_rtx (V8QImode); + rtx v1 = gen_reg_rtx (V8QImode); + rtx r = gen_reg_rtx (QImode); + rtx in = operands[1]; + rtx out = operands[0]; + if(<MODE>mode == SImode) + { + rtx tmp; + tmp = gen_reg_rtx (DImode); + /* If we have SImode, zero extend to DImode, pop count does + not change if we have extra zeros. */ + emit_insn (gen_zero_extendsidi2 (tmp, in)); + in = tmp; + } + emit_move_insn (v, gen_lowpart (V8QImode, in)); + emit_insn (gen_popcountv8qi2 (v1, v)); + emit_insn (gen_reduc_plus_scal_v8qi (r, v1)); + emit_insn (gen_zero_extendqi<mode>2 (out, r)); + DONE; +}) + (define_insn "clrsb<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))] |