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authorSofiane Naci <sofiane.naci@arm.com>2012-10-22 12:28:14 +0000
committerSofiane Naci <sofiane.naci@arm.com>2012-10-22 12:28:14 +0000
commit369b71ecad513571a31ed3989a33629404847832 (patch)
tree77fa03ebcefe174abeaef371e7fb332b2d928284 /gcc/config/arm/arm.h
parent2b86be5b85981f0186dc90c8726e5a86abd99b4b (diff)
parentfe41acb87a4145f35518841c7d83cb8f88dc5d9e (diff)
Merge from trunk 192445:192598.ARM/aarch64-branch
git-svn-id: https://gcc.gnu.org/svn/gcc/branches/ARM/aarch64-branch@192688 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/arm/arm.h')
-rw-r--r--gcc/config/arm/arm.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 34d364f00b9..4ac5de70862 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -296,6 +296,9 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
/* FPU supports fused-multiply-add operations. */
#define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4)
+/* FPU supports Crypto extensions. */
+#define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto)
+
/* FPU supports Neon instructions. The setting of this macro gets
revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
and TARGET_HARD_FLOAT to ensure that NEON instructions are
@@ -400,6 +403,7 @@ extern const struct arm_fpu_desc
enum vfp_reg_type regs;
int neon;
int fp16;
+ int crypto;
} *arm_fpu_desc;
/* Which floating point hardware to schedule for. */
@@ -443,7 +447,8 @@ enum base_architecture
BASE_ARCH_7A = 7,
BASE_ARCH_7R = 7,
BASE_ARCH_7M = 7,
- BASE_ARCH_7EM = 7
+ BASE_ARCH_7EM = 7,
+ BASE_ARCH_8A = 8
};
/* The major revision number of the ARM Architecture implemented by the target. */
@@ -482,6 +487,9 @@ extern int arm_arch_notm;
/* Nonzero if instructions present in ARMv7E-M can be used. */
extern int arm_arch7em;
+/* Nonzero if this chip supports the ARM Architecture 8 extensions. */
+extern int arm_arch8;
+
/* Nonzero if this chip can benefit from load scheduling. */
extern int arm_ld_sched;