* i386.md (adddi3, subdi3 splitters): Update for new pattern.

	(addsi3_cc, addqi3_cc, subsi3_cc): Remove
	(addsi3_carry): Canonicalize.
	(addqi_5): Remove '*'.
	(sbb pattern): Canonicalize.

	* i386.md (cmp to inc/add peep2): New.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@36853 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 87 insertions, 45 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index db8be567a43..5096c1dc89d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3738,42 +3738,22 @@
 		 (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
   "reload_completed"
-  [(parallel [(set (reg:CC 17) (plus:CC (match_dup 1) (match_dup 2)))
+  [(parallel [(set (reg:CC 17) (compare:CC (neg:SI (match_dup 2)) (match_dup 1)))
 	      (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
-		   (plus:SI (match_dup 4)
-		   (plus:SI (match_dup 5)
-			    (ltu:SI (reg:CC 17) (const_int 0)))))
+		   (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+				     (match_dup 4))
+			    (match_dup 5)))
 	      (clobber (reg:CC 17))])]
   "split_di (operands+0, 1, operands+0, operands+3);
    split_di (operands+1, 1, operands+1, operands+4);
    split_di (operands+2, 1, operands+2, operands+5);")
 
-(define_insn "*addsi3_cc"
-  [(set (reg:CC 17) (plus:CC (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-		    (match_operand:SI 2 "general_operand" "ri,rm")))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(plus:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, SImode, operands)"
-  "add{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
-(define_insn "addqi3_cc"
-  [(set (reg:CC 17) (plus:CC (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-		    (match_operand:QI 2 "general_operand" "qi,qm")))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=qm,q")
-	(plus:QI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (PLUS, QImode, operands)"
-  "add{b}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "QI")])
-
 (define_insn "*addsi3_carry"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-	    (plus:SI (match_operand:SI 2 "general_operand" "ri,rm")
-	      (ltu:SI (reg:CC 17) (const_int 0)))))
+	  (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+			    (match_operand:SI 1 "nonimmediate_operand" "%0,0"))
+		   (match_operand:SI 2 "general_operand" "ri,rm")))
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (PLUS, SImode, operands)"
   "adc{l}\\t{%2, %0|%0, %2}"
@@ -4587,6 +4567,15 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
+(define_expand "addqi3_cc"
+  [(parallel [
+     (set (reg:CC 17)
+	  (compare:CC (neg:QI (match_operand:QI 2 "general_operand" ""))
+		      (match_operand:QI 1 "nonimmediate_operand" "")))
+     (clobber (match_scratch:QI 0 ""))])]
+  ""
+  "")
+
 (define_insn "*addqi_5"
   [(set (reg 17)
 	(compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
@@ -4734,32 +4723,22 @@
 		  (match_operand:DI 2 "general_operand" "")))
    (clobber (reg:CC 17))]
   "reload_completed"
-  [(parallel [(set (reg:CC 17) (minus:CC (match_dup 1) (match_dup 2)))
+  [(parallel [(set (reg:CC 17) (compare:CC (match_dup 1) (match_dup 2)))
 	      (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))])
    (parallel [(set (match_dup 3)
 		   (minus:SI (match_dup 4)
-			     (plus:SI (match_dup 5)
-			     (ltu:SI (reg:CC 17) (const_int 0)))))
+			     (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+				      (match_dup 5))))
 	      (clobber (reg:CC 17))])]
   "split_di (operands+0, 1, operands+0, operands+3);
    split_di (operands+1, 1, operands+1, operands+4);
    split_di (operands+2, 1, operands+2, operands+5);")
 
-(define_insn "*subsi3_cc"
-  [(set (reg:CC 17) (minus:CC (match_operand:SI 1 "nonimmediate_operand" "0,0")
-			      (match_operand:SI 2 "general_operand" "ri,rm")))
-   (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
-	(minus:SI (match_dup 1) (match_dup 2)))]
-  "ix86_binary_operator_ok (MINUS, SImode, operands)"
-  "sub{l}\\t{%2, %0|%0, %2}"
-  [(set_attr "type" "alu")
-   (set_attr "mode" "SI")])
-
 (define_insn "subsi3_carry"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
 	  (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
-	    (plus:SI (match_operand:SI 2 "general_operand" "ri,rm")
-	      (ltu:SI (reg:CC 17) (const_int 0)))))
+	    (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+	       (match_operand:SI 2 "general_operand" "ri,rm"))))
    (clobber (reg:CC 17))]
   "ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sbb{l}\\t{%2, %0|%0, %2}"
@@ -6163,9 +6142,9 @@
      (set (match_dup 0) (neg:SI (match_dup 2)))])
    (parallel
     [(set (match_dup 1)
-	  (plus:SI (match_dup 3)
-	    (plus:SI (const_int 0)
-	      (ltu:SI (reg:CC 17) (const_int 0)))))
+	  (plus:SI (plus:SI (ltu:SI (reg:CC 17) (const_int 0))
+			    (match_dup 3))
+		   (const_int 0)))
      (clobber (reg:CC 17))])
    (parallel
     [(set (match_dup 1)
@@ -11425,6 +11404,69 @@
 	      (set (reg:SI 7) (plus:SI (reg:SI 7) (const_int 4)))])]
   "")
 
+;; Convert compares with 1 to shorter inc/dec operations when CF is not
+;; required and register dies.
+(define_peephole2
+  [(set (reg 17)
+	(compare (match_operand:SI 0 "register_operand" "")
+		 (match_operand:SI 1 "incdec_operand" "")))]
+  "ix86_match_ccmode (insn, CCGCmode)
+   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+  [(parallel [(set (reg:CCGC 17)
+		   (compare:CCGC (neg:SI (match_dup 1))
+				 (match_dup 0)))
+	      (clobber (match_dup 0))])]
+  "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;")
+
+(define_peephole2
+  [(set (reg 17)
+	(compare (match_operand:HI 0 "register_operand" "")
+		 (match_operand:HI 1 "incdec_operand" "")))]
+  "ix86_match_ccmode (insn, CCGCmode)
+   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+  [(parallel [(set (reg:CCGC 17)
+		   (compare:CCGC (neg:HI (match_dup 1))
+				 (match_dup 0)))
+	      (clobber (match_dup 0))])]
+  "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;")
+
+(define_peephole2
+  [(set (reg 17)
+	(compare (match_operand:QI 0 "register_operand" "")
+		 (match_operand:QI 1 "incdec_operand" "")))]
+  "ix86_match_ccmode (insn, CCGCmode)
+   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+  [(parallel [(set (reg:CCGC 17)
+		   (compare:CCGC (neg:QI (match_dup 1))
+				 (match_dup 0)))
+	      (clobber (match_dup 0))])]
+  "operands[1] = (operands[1] == const1_rtx) ? constm1_rtx : const1_rtx;")
+
+;; Convert compares with 128 to shorter add -128
+(define_peephole2
+  [(set (reg 17)
+	(compare (match_operand:SI 0 "register_operand" "")
+		 (const_int 128)))]
+  "ix86_match_ccmode (insn, CCmode)
+   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+  [(parallel [(set (reg:CC 17)
+		   (compare:CC (neg:SI (const_int -128))
+			       (match_dup 0)))
+	      (clobber (match_dup 0))])]
+  "")
+
+(define_peephole2
+  [(set (reg 17)
+	(compare (match_operand:HI 0 "register_operand" "")
+		 (const_int 128)))]
+  "ix86_match_ccmode (insn, CCmode)
+   && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
+  [(parallel [(set (reg:CC 17)
+		   (compare:CC (neg:HI (const_int -128))
+			       (match_dup 0)))
+	      (clobber (match_dup 0))])]
+  "")
+
 ;; Call-value patterns last so that the wildcard operand does not
 ;; disrupt insn-recog's switch tables.