* i386.md (add?i_3, add?i_5): New.

	(add?i_4): Rename from add?i_3;  Fix compare pattern.
	(sub?i_3, xor?i_3, ior?i_3): New.

	* genrecog.c (write_tree): Output code to clear insn_extract cache.
	* genattrtab.c (write_attr_case): Gen call to extract_insn_cache
	instead of extract_insn and extract_constrain_insn_cache instead of
	extract_insn and constrain_operands.
	* recog.c (extract_insn_cached, extract_constrain_insn_cached):
	New functions.
	(extract_insn): Clear which_alternative.
	(constrain_operands): Set which_alternative to -1 when failed.
	* recog.h (extract_constrain_insn_cached, extract_insn_cached):
	Declare.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@36342 138bc75d-0d04-0410-961f-82ee72b054a4

1 files changed, 272 insertions, 9 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 51386bc0114..6e8022f6f44 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3997,10 +3997,55 @@
    (set_attr "mode" "SI")])
 
 (define_insn "*addsi_3"
+  [(set (reg 17)
+	(compare (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
+		 (match_operand:SI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:SI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
+   /* Current assemblers are broken and do not allow @GOTOFF in
+      ought but a memory context. */
+   && ! pic_symbolic_operand (operands[2], VOIDmode)"
+  "*
+{
+  switch (get_attr_type (insn))
+    {
+    case TYPE_INCDEC:
+      if (! rtx_equal_p (operands[0], operands[1]))
+	abort ();
+      if (operands[2] == const1_rtx)
+        return \"inc{l}\\t%0\";
+      else if (operands[2] == constm1_rtx)
+        return \"dec{l}\\t%0\";
+      else
+	abort();
+
+    default:
+      if (! rtx_equal_p (operands[0], operands[1]))
+	abort ();
+      /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+	 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
+      if (GET_CODE (operands[2]) == CONST_INT
+          && (INTVAL (operands[2]) == 128
+	      || (INTVAL (operands[2]) < 0
+		  && INTVAL (operands[2]) != -128)))
+        {
+          operands[2] = GEN_INT (-INTVAL (operands[2]));
+          return \"sub{l}\\t{%2, %0|%0, %2}\";
+        }
+      return \"add{l}\\t{%2, %0|%0, %2}\";
+    }
+}"
+  [(set (attr "type")
+     (if_then_else (match_operand:SI 2 "incdec_operand" "")
+	(const_string "incdec")
+	(const_string "alu")))
+   (set_attr "mode" "SI")])
+
+(define_insn "*addsi_4"
   [(set (reg:CC 17)
-	(compare:CC (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
-			     (match_operand:SI 2 "general_operand" "rmni,rni"))
-		    (const_int 0)))			
+	(compare:CC (neg:SI (match_operand:SI 2 "general_operand" "rmni,rni"))
+		    (match_operand:SI 1 "nonimmediate_operand" "%0,0")))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, SImode, operands)
@@ -4011,6 +4056,19 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
+(define_insn "*addsi_5"
+  [(set (reg:CC 17)
+	(compare:CC (neg:SI (match_operand:SI 2 "general_operand" "rmni"))
+		    (match_operand:SI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:SI 0 "=r"))]
+  "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
+   /* Current assemblers are broken and do not allow @GOTOFF in
+      ought but a memory context. */
+   && ! pic_symbolic_operand (operands[2], VOIDmode)"
+  "add{l}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_expand "addhi3"
   [(parallel [(set (match_operand:HI 0 "nonimmediate_operand" "")
 		   (plus:HI (match_operand:HI 1 "nonimmediate_operand" "")
@@ -4151,10 +4209,49 @@
    (set_attr "mode" "HI")])
 
 (define_insn "*addhi_3"
+  [(set (reg 17)
+	(compare (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
+		 (match_operand:HI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:HI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "*
+{
+  switch (get_attr_type (insn))
+    {
+    case TYPE_INCDEC:
+      if (operands[2] == const1_rtx)
+	return \"inc{w}\\t%0\";
+      else if (operands[2] == constm1_rtx
+	       || (GET_CODE (operands[2]) == CONST_INT
+		   && INTVAL (operands[2]) == 65535))
+	return \"dec{w}\\t%0\";
+      abort();
+
+    default:
+      /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
+	 Exceptions: -128 encodes smaller than 128, so swap sign and op.  */
+      if (GET_CODE (operands[2]) == CONST_INT
+          && (INTVAL (operands[2]) == 128
+	      || (INTVAL (operands[2]) < 0
+		  && INTVAL (operands[2]) != -128)))
+	{
+	  operands[2] = GEN_INT (-INTVAL (operands[2]));
+	  return \"sub{w}\\t{%2, %0|%0, %2}\";
+	}
+      return \"add{w}\\t{%2, %0|%0, %2}\";
+    }
+}"
+  [(set (attr "type")
+     (if_then_else (match_operand:HI 2 "incdec_operand" "")
+	(const_string "incdec")
+	(const_string "alu")))
+   (set_attr "mode" "HI")])
+
+(define_insn "*addhi_4"
   [(set (reg:CC 17)
-	(compare:CC (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
-			     (match_operand:HI 2 "general_operand" "rmni,rni"))
-		    (const_int 0)))			
+	(compare:CC (neg:HI (match_operand:HI 2 "general_operand" "rmni,rni"))
+		    (match_operand:HI 1 "nonimmediate_operand" "%0,0")))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(plus:HI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, HImode, operands)"
@@ -4162,6 +4259,16 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "HI")])
 
+(define_insn "*addhi_5"
+  [(set (reg:CC 17)
+	(compare:CC (neg:HI (match_operand:HI 2 "general_operand" "rmni"))
+		    (match_operand:HI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:HI 0 "=r"))]
+  "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "add{w}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
+
 (define_expand "addqi3"
   [(parallel [(set (match_operand:QI 0 "nonimmediate_operand" "")
 		   (plus:QI (match_operand:QI 1 "nonimmediate_operand" "")
@@ -4310,10 +4417,46 @@
    (set_attr "mode" "QI")])
 
 (define_insn "*addqi_3"
+  [(set (reg 17)
+	(compare (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
+		 (match_operand:QI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:QI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "*
+{
+  switch (get_attr_type (insn))
+    {
+    case TYPE_INCDEC:
+      if (operands[2] == const1_rtx)
+	return \"inc{b}\\t%0\";
+      else if (operands[2] == constm1_rtx
+	       || (GET_CODE (operands[2]) == CONST_INT
+		   && INTVAL (operands[2]) == 255))
+	return \"dec{b}\\t%0\";
+      abort();
+
+    default:
+      /* Make things pretty and `subb $4,%al' rather than `addb $-4, %al'.  */
+      if (GET_CODE (operands[2]) == CONST_INT
+          && INTVAL (operands[2]) < 0)
+	{
+	  operands[2] = GEN_INT (-INTVAL (operands[2]));
+	  return \"sub{b}\\t{%2, %0|%0, %2}\";
+	}
+      return \"add{b}\\t{%2, %0|%0, %2}\";
+    }
+}"
+  [(set (attr "type")
+     (if_then_else (match_operand:QI 2 "incdec_operand" "")
+	(const_string "incdec")
+	(const_string "alu")))
+   (set_attr "mode" "QI")])
+
+(define_insn "*addqi_4"
   [(set (reg:CC 17)
-	(compare:CC (plus:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0")
-			     (match_operand:QI 2 "general_operand" "qmni,qni"))
-		    (const_int 0)))			
+	(compare:CC (neg:QI (match_operand:QI 2 "general_operand" "qmni,qni"))
+		    (match_operand:QI 1 "nonimmediate_operand" "%0,0")))
    (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm")
 	(plus:QI (match_dup 1) (match_dup 2)))]
   "ix86_binary_operator_ok (PLUS, QImode, operands)"
@@ -4321,6 +4464,16 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
+(define_insn "*addqi_5"
+  [(set (reg:CC 17)
+	(compare:CC (neg:QI (match_operand:QI 2 "general_operand" "qmni"))
+		    (match_operand:QI 1 "nonimmediate_operand" "%0")))
+   (clobber (match_scratch:QI 0 "=r"))]
+  "(GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "add{b}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 
 (define_insn "addqi_ext_1"
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
@@ -4478,6 +4631,18 @@
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
 	(minus:SI (match_dup 1) (match_dup 2)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (MINUS, SImode, operands)"
+  "sub{l}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
+(define_insn "*subsi_3"
+  [(set (reg 17)
+	(compare (match_operand:SI 1 "nonimmediate_operand" "0,0")
+		 (match_operand:SI 2 "general_operand" "ri,rm")))
+   (set (match_operand:SI 0 "nonimmediate_operand" "=rm,r")
+	(minus:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\\t{%2, %0|%0, %2}"
@@ -4510,6 +4675,18 @@
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
 	(minus:HI (match_dup 1) (match_dup 2)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (MINUS, HImode, operands)"
+  "sub{w}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
+
+(define_insn "*subhi_3"
+  [(set (reg 17)
+	(compare (match_operand:HI 1 "nonimmediate_operand" "0,0")
+		 (match_operand:HI 2 "general_operand" "ri,rm")))
+   (set (match_operand:HI 0 "nonimmediate_operand" "=rm,r")
+	(minus:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, HImode, operands)"
   "sub{w}\\t{%2, %0|%0, %2}"
@@ -4542,6 +4719,18 @@
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
 	(minus:HI (match_dup 1) (match_dup 2)))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && ix86_binary_operator_ok (MINUS, QImode, operands)"
+  "sub{b}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
+(define_insn "*subqi_3"
+  [(set (reg 17)
+	(compare (match_operand:QI 1 "nonimmediate_operand" "0,0")
+		 (match_operand:QI 2 "general_operand" "qi,qm")))
+   (set (match_operand:HI 0 "nonimmediate_operand" "=qm,q")
+	(minus:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCmode)
    && ix86_binary_operator_ok (MINUS, QImode, operands)"
   "sub{b}\\t{%2, %0|%0, %2}"
@@ -5491,6 +5680,18 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
+(define_insn "*iorsi_3"
+  [(set (reg 17)
+	(compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+			 (match_operand:SI 2 "general_operand" "rim"))
+		 (const_int 0)))
+   (clobber (match_scratch:SI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "or{l}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_expand "iorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
 	(ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
@@ -5522,6 +5723,18 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "HI")])
 
+(define_insn "*iorhi_3"
+  [(set (reg 17)
+	(compare (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
+			 (match_operand:HI 2 "general_operand" "rim"))
+		 (const_int 0)))
+   (clobber (match_scratch:HI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "or{w}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
+
 (define_expand "iorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 	(ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
@@ -5556,6 +5769,19 @@
   "or{b}\\t{%2, %0|%0, %2}"
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
+
+(define_insn "*iorqi_3"
+  [(set (reg 17)
+	(compare (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+			 (match_operand:QI 2 "general_operand" "qim"))
+		 (const_int 0)))
+   (clobber (match_scratch:QI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "or{b}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 
 ;; Logical XOR instructions
 
@@ -5593,6 +5819,18 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
 
+(define_insn "*xorsi_3"
+  [(set (reg 17)
+	(compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
+			 (match_operand:SI 2 "general_operand" "rim"))
+		 (const_int 0)))
+   (clobber (match_scratch:SI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "xor{l}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "SI")])
+
 (define_expand "xorhi3"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
 	(xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
@@ -5624,6 +5862,18 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "HI")])
 
+(define_insn "*xorhi_3"
+  [(set (reg 17)
+	(compare (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
+			 (match_operand:HI 2 "general_operand" "rim"))
+		 (const_int 0)))
+   (clobber (match_scratch:HI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "xor{w}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "HI")])
+
 (define_expand "xorqi3"
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 	(xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
@@ -5678,6 +5928,19 @@
   [(set_attr "type" "alu")
    (set_attr "mode" "QI")])
 
+(define_insn "*xorqi_cc_2"
+  [(set (reg 17)
+	(compare
+	  (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
+		  (match_operand:QI 2 "general_operand" "qim"))
+	  (const_int 0)))
+   (clobber (match_scratch:QI 0 "=r"))]
+  "ix86_match_ccmode (insn, CCNOmode)
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "xor{b}\\t{%2, %0|%0, %2}"
+  [(set_attr "type" "alu")
+   (set_attr "mode" "QI")])
+
 (define_insn "xorqi_cc_ext_1"
   [(set (reg:CCNO 17)
 	(compare:CCNO