diff options
| author | Ajit Agarwal <ajitkum@xilinx.com> | 2015-05-05 01:07:26 +0000 |
|---|---|---|
| committer | Michael Eager <eager@eagercon.com> | 2015-05-05 01:07:26 +0000 |
| commit | 894c395e74cf3f83d3da39106bdad2a3e30240b5 (patch) | |
| tree | 6316503f963ae5cd05c04b199351daba3723c3cc /gcc/config/microblaze | |
| parent | be10066f790bdac89b33acae72dd53cbf0f0e837 (diff) | |
The changes are made in the patch for optimized usage of fint instruction.
The sequence of fint/cond_branch is replaced with fcmp/cond_branch. The
fint instruction takes 6/7 cycles as compared to fcmp instruction which
takes 1 cycles. The conversion from float to int with fint instruction
is not required and can directly compared with fcmp instruction which
takes 1 cycle as compared to 6/7 cycles with fint instruction.
ChangeLog:
2015-03-04 Ajit Agarwal <ajitkum@xilinx.com>
* config/microblaze/microblaze.md (peephole2): New.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@222790 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/microblaze')
| -rw-r--r-- | gcc/config/microblaze/microblaze.md | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md index 67e509cde1a..ad97ca69fa9 100644 --- a/gcc/config/microblaze/microblaze.md +++ b/gcc/config/microblaze/microblaze.md @@ -663,6 +663,31 @@ (set_attr "mode" "SI") (set_attr "length" "4")]) +(define_peephole2 + [(set (match_operand:SI 0 "register_operand") + (fix:SI (match_operand:SF 1 "register_operand"))) + (set (pc) + (if_then_else (match_operator 2 "ordered_comparison_operator" + [(match_operand:SI 3 "register_operand") + (match_operand:SI 4 "arith_operand")]) + (label_ref (match_operand 5)) + (pc)))] + "TARGET_HARD_FLOAT" + [(set (match_dup 1) (match_dup 3))] + + { + rtx condition; + rtx cmp_op0 = operands[3]; + rtx cmp_op1 = operands[4]; + rtx comp_reg = gen_rtx_REG (SImode, MB_ABI_ASM_TEMP_REGNUM); + + emit_insn (gen_cstoresf4 (comp_reg, operands[2], + gen_rtx_REG (SFmode, REGNO (cmp_op0)), + gen_rtx_REG (SFmode, REGNO (cmp_op1)))); + condition = gen_rtx_NE (SImode, comp_reg, const0_rtx); + emit_jump_insn (gen_condjump (condition, operands[5])); + } +) ;;---------------------------------------------------------------- ;; Negation and one's complement |