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| author | Kito Cheng <kito.cheng@gmail.com> | 2018-04-05 02:51:45 +0000 |
|---|---|---|
| committer | Chung-Ju Wu <jasonwucj@gmail.com> | 2018-04-05 02:51:45 +0000 |
| commit | 22307666bcd3f82234c424ec2ad8bb03326198a8 (patch) | |
| tree | 0bef54daf5c4fb2485e0d330051132490bcbc1a8 /gcc/config/nds32/predicates.md | |
| parent | 012a9e4b80761e1f274c5c31e3c52968da1280f6 (diff) | |
[NDS32] Refine bit-wise operation and shift patterns.
gcc/
* config/nds32/iterators.md (shift_rotate): New code iterator.
(shift): New code attribute.
* config/nds32/nds32-md-auxiliary.c (nds32_expand_constant): New.
* config/nds32/nds32-protos.h (nds32_expand_constant): Declare.
* config/nds32/nds32.c (nds32_print_operand): Deal with more cases.
* config/nds32/nds32.md (addsi3, *add_srli): Refine implementation for
bit-wise operations.
(andsi3, *andsi3): Ditto.
(iorsi3, *iorsi3, *or_slli, *or_srli): Ditto.
(xorsi3, *xorsi3, *xor_slli, *xor_srli): Ditto.
(<shift>si3, *ashlsi3, *ashrsi3, *lshrsi3, *rotrsi3): Ditto.
* config/nds32/predicates.md (nds32_rimm5u_operand, nds32_and_operand,
nds32_ior_operand, nds32_xor_operand): New predicates.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@259117 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/nds32/predicates.md')
| -rw-r--r-- | gcc/config/nds32/predicates.md | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md index 7cf4635e1cf..066ec3471ea 100644 --- a/gcc/config/nds32/predicates.md +++ b/gcc/config/nds32/predicates.md @@ -51,6 +51,10 @@ (and (match_operand 0 "const_int_operand") (match_test "satisfies_constraint_Iu05 (op)"))) +(define_predicate "nds32_rimm5u_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "nds32_imm5u_operand"))) + (define_predicate "nds32_move_operand" (and (match_operand 0 "general_operand") (not (match_code "high,const,symbol_ref,label_ref"))) @@ -65,6 +69,40 @@ return true; }) +(define_predicate "nds32_and_operand" + (match_operand 0 "nds32_reg_constant_operand") +{ + return REG_P (op) + || GET_CODE (op) == SUBREG + || satisfies_constraint_Izeb (op) + || satisfies_constraint_Izeh (op) + || satisfies_constraint_Ixls (op) + || satisfies_constraint_Ix11 (op) + || satisfies_constraint_Ibms (op) + || satisfies_constraint_Ifex (op) + || satisfies_constraint_Iu15 (op) + || satisfies_constraint_Ii15 (op) + || satisfies_constraint_Ic15 (op); +}) + +(define_predicate "nds32_ior_operand" + (match_operand 0 "nds32_reg_constant_operand") +{ + return REG_P (op) + || GET_CODE (op) == SUBREG + || satisfies_constraint_Iu15 (op) + || satisfies_constraint_Ie15 (op); +}) + +(define_predicate "nds32_xor_operand" + (match_operand 0 "nds32_reg_constant_operand") +{ + return REG_P (op) + || GET_CODE (op) == SUBREG + || satisfies_constraint_Iu15 (op) + || satisfies_constraint_It15 (op); +}) + (define_predicate "nds32_general_register_operand" (match_code "reg,subreg") { |