* doc/invoke.texi (NS32K Options): Document -mieee-compare option

        * config/ns32k/ns32k.md (addsi3, *frame_addr, *stack_addr): merge
        into addsi3 using register class "x" and "y".

        * config/ns32k/ns32k.md (*madddf, *maddsf, *msubdf, *msubsf):
        "earlyclobber" constraint modifier for some alternative.

        * config/ns32k/ns32k.md (tstdf, tstsf, cmpdf, cmpsf, blt, ble)
        (*ble, *blt): Flag to indicate bCOND and sCOND should check for
        unordered.
        config/ns32k/ns32k.h (CC_UNORD): define corresponding mask.

        * config/ns32k/ns32k.h (TARGET_IEEE_COMPARE, MASK_IEEE_COMPARE)
        (TARGET_SWITCHES): Add -mieee-compare option.
        (OVERRIDE_OPTIONS): 32332 is a subset of
        32532. Don't use IEEE_COMPARE -funsafe-math-optimizations.
        (TARGET_SWITCHES): Fix description of bitfield option.
        * config/ns32k/netbsd.h (TARGET_DEFAULT): Add
        -mieee-compare option. Remove 32332 flag.


git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@55489 138bc75d-0d04-0410-961f-82ee72b054a4

3 files changed, 87 insertions, 40 deletions

diff --git a/gcc/config/ns32k/netbsd.h b/gcc/config/ns32k/netbsd.h
index 499b615eff6..28bae88cb88 100644
--- a/gcc/config/ns32k/netbsd.h
+++ b/gcc/config/ns32k/netbsd.h
@@ -34,9 +34,10 @@ Boston, MA 02111-1307, USA.  */
    FPU is 32381;
    Use multiply-add instructions */
 
+#undef TARGET_DEFAULT
 #define TARGET_DEFAULT \
-  (MASK_32532|MASK_32332 | MASK_NO_SB | MASK_NO_BITFIELD | \
-   MASK_32081|MASK_32381 | MASK_MULT_ADD)
+  (MASK_32532 | MASK_NO_SB | MASK_NO_BITFIELD | \
+   MASK_32381 | MASK_IEEE_COMPARE | MASK_MULT_ADD)
 
 /* 32-bit alignment for efficiency */
 
diff --git a/gcc/config/ns32k/ns32k.h b/gcc/config/ns32k/ns32k.h
index f75f60d9cd0..21abff08430 100644
--- a/gcc/config/ns32k/ns32k.h
+++ b/gcc/config/ns32k/ns32k.h
@@ -82,6 +82,7 @@ Boston, MA 02111-1307, USA.  */
 
 extern int target_flags;
 
+/* Masks for target_flags */
 #define MASK_32081		1
 #define MASK_RTD		2
 #define MASK_REGPARM		4
@@ -93,6 +94,7 @@ extern int target_flags;
 #define MASK_32381		256
 #define MASK_MULT_ADD		512
 #define MASK_SRC		1024
+#define MASK_IEEE_COMPARE 2048
 
 /* Macros used in the machine description to test the flags.  */
 
@@ -121,17 +123,19 @@ extern int target_flags;
 
 /* Ok to use the static base register (and presume it's 0) */
 #define TARGET_SB    ((target_flags & MASK_NO_SB) == 0)
+
 #define TARGET_HIMEM (target_flags & MASK_HIMEM)
 
 /* Compile using bitfield insns.  */
 #define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0)
 
+#define TARGET_IEEE_FP (target_flags & MASK_IEEE_COMPARE)
+
 /* Macro to define tables used to set the flags.
    This is a list in braces of pairs in braces,
    each pair being { "NAME", VALUE }
    where VALUE is the bits to set or minus the bits to clear.
    An empty string NAME is used to identify the default VALUE.  */
-
 #define TARGET_SWITCHES							\
   { { "32081", MASK_32081, N_("Use hardware fp")},			\
     { "soft-float", -(MASK_32081|MASK_32381),				\
@@ -148,17 +152,21 @@ extern int target_flags;
       N_("Register sb is zero. Use for absolute addressing")},		\
     { "nosb", MASK_NO_SB, N_("Do not use register sb")},		\
     { "bitfield", -MASK_NO_BITFIELD,					\
+      N_("Use bit-field instructions")},				\
+    { "nobitfield", MASK_NO_BITFIELD,					\
       N_("Do not use bit-field instructions")},				\
-    { "nobitfield", MASK_NO_BITFIELD, N_("Use bit-field instructions")},\
     { "himem", MASK_HIMEM, N_("Generate code for high memory")},	\
     { "nohimem", -MASK_HIMEM, N_("Generate code for low memory")},	\
     { "32381", MASK_32381, N_("32381 fpu")},				\
     { "mult-add", MASK_MULT_ADD,					\
       N_("Use multiply-accumulate fp instructions")},			\
     { "nomult-add", -MASK_MULT_ADD,					\
-      N_("Do not use multiply-accumulate fp instructions") }, 		\
+      N_("Do not use multiply-accumulate fp instructions") },		\
     { "src", MASK_SRC, N_("\"Small register classes\" kludge")},	\
     { "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")},	\
+    { "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")},	\
+    { "noieee-compare", -MASK_IEEE_COMPARE,					\
+      N_("Do not use IEEE math for fp comparisons")},			\
     { "", TARGET_DEFAULT, 0}}
 
 /* TARGET_DEFAULT is defined in encore.h, pc532.h, etc.  */
@@ -166,14 +174,18 @@ extern int target_flags;
 /* When we are generating PIC, the sb is used as a pointer
    to the GOT. 32381 is a superset of 32081  */
 
-#define OVERRIDE_OPTIONS				\
-{							\
-  if (flag_pic || TARGET_HIMEM)				\
-    target_flags |= MASK_NO_SB;				\
-  if (TARGET_32381)					\
-    target_flags |= MASK_32081;				\
-  else							\
-    target_flags &= ~MASK_MULT_ADD;			\
+#define OVERRIDE_OPTIONS			\
+{						\
+  if (target_flags & MASK_32532)		\
+    target_flags |= MASK_32332; 		\
+  if (flag_pic || TARGET_HIMEM)			\
+    target_flags |= MASK_NO_SB;			\
+  if (TARGET_32381)				\
+    target_flags |= MASK_32081;			\
+  else						\
+    target_flags &= ~MASK_MULT_ADD;		\
+  if (flag_unsafe_math_optimizations)		\
+     target_flags &= ~MASK_IEEE_COMPARE;		\
 }
 
 /* Zero or more C statements that may conditionally modify two
@@ -1180,6 +1192,10 @@ __transfer_from_trampoline ()		\
    is complemented in the F bit.  */
 #define CC_Z_IN_NOT_F 010000
 
+/* This bit means that the L bit indicates unordered (IEEE) comparison.
+ */
+#define CC_UNORD 020000
+
 /* Store in cc_status the expressions
    that the condition codes will describe
    after execution of an instruction whose pattern is EXP.
diff --git a/gcc/config/ns32k/ns32k.md b/gcc/config/ns32k/ns32k.md
index 44db4807138..ba450012a4a 100644
--- a/gcc/config/ns32k/ns32k.md
+++ b/gcc/config/ns32k/ns32k.md
@@ -94,6 +94,8 @@
   "TARGET_32081"
   "*
 { cc_status.flags |= CC_REVERSED;
+  if (TARGET_IEEE_COMPARE)
+    cc_status.flags |= CC_UNORD;
   operands[1] = CONST0_RTX (DFmode);
   return \"cmpl %1,%0\"; }")
 
@@ -103,6 +105,8 @@
   "TARGET_32081"
   "*
 { cc_status.flags |= CC_REVERSED;
+  if (TARGET_IEEE_COMPARE)
+    cc_status.flags |= CC_UNORD;
   operands[1] = CONST0_RTX (SFmode);
   return \"cmpf %1,%0\"; }")
 
@@ -202,14 +206,22 @@
 	(compare (match_operand:DF 0 "general_operand" "lmF")
 		 (match_operand:DF 1 "general_operand" "lmF")))]
   "TARGET_32081"
-  "cmpl %0,%1")
+  "*
+{
+  if (TARGET_IEEE_COMPARE)
+    cc_status.flags |= CC_UNORD;
+  return \"cmpl %0,%1\";}")
 
 (define_insn "cmpsf"
   [(set (cc0)
 	(compare (match_operand:SF 0 "general_operand" "fmF")
 		 (match_operand:SF 1 "general_operand" "fmF")))]
   "TARGET_32081"
-  "cmpf %0,%1")
+  "*
+{
+  if (TARGET_IEEE_COMPARE)
+    cc_status.flags |= CC_UNORD;
+  return \"cmpf %0,%1\";}")
 
 ;; movdf and movsf copy between general and floating registers using
 ;; the stack. In principle, we could get better code not allowing
@@ -798,7 +810,7 @@
 
 ;; Multiply-add instructions
 (define_insn "*madddf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,&lm")
 	(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
 		          (match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
                  (match_operand:DF 3 "general_operand" "0,lmF,lmF")))]
@@ -809,7 +821,7 @@
    mull %2,%0\;addl %3,%0")
 
 (define_insn "*maddsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,&fm")
 	(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
 		          (match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
                  (match_operand:SF 3 "general_operand" "0,fmF,fmF")))]
@@ -822,7 +834,7 @@
 
 ;; Multiply-sub instructions
 (define_insn "*msubdf"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=&v,&lm")
 	(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
 		          (match_operand:DF 2 "general_operand" "lmF,lmF"))
                  (match_operand:DF 3 "general_operand" "lmF,lmF")))]
@@ -832,7 +844,7 @@
    mull %2,%0\;subl %3,%0")
 
 (define_insn "*msubsf"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=&u,&fm")
 	(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
 		          (match_operand:SF 2 "general_operand" "fmF,fmF"))
                  (match_operand:SF 3 "general_operand" "fmF,fmF")))]
@@ -883,20 +895,6 @@
   return \"adjspd %n0\";
 }")
 
-(define_insn "*frame_addr"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
-	(plus:SI (reg:SI 24)
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
-  "addr %c1(fp),%0")
-
-(define_insn "*stack_addr"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
-	(plus:SI (reg:SI 25)
-		 (match_operand:SI 1 "immediate_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
-  "addr %c1(sp),%0")
-
 (define_insn "adddi3"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
 	(plus:DI (match_operand:DI 1 "general_operand" "%0")
@@ -940,9 +938,9 @@
 
 ;; See Note 1
 (define_insn "addsi3"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm&<")
-	(plus:SI (match_operand:SI 1 "general_operand" "%0,r")
-		 (match_operand:SI 2 "general_operand" "g,i")))]
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,=rm<,=rm<")
+	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,xy")
+		 (match_operand:SI 2 "general_operand" "g,i,i")))]
   ""
   "*
 {
@@ -964,6 +962,14 @@
 	    return \"addr %c2(%1),%0\";
         }
     }
+  else if (which_alternative == 2)
+    {
+      if (GET_CODE (operands[2]) == CONST_INT &&
+          NS32K_DISPLACEMENT_P (INTVAL (operands[2])))
+        return \"addr %c2(%1),%0\";
+      else
+        return \"sprd %1,%0\;addd %2,%0\";
+    }
   else if (GET_CODE (operands[2]) == CONST_INT)
     {
       int i = INTVAL (operands[2]);
@@ -2313,7 +2319,13 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "blt %l0")
+  "*
+{
+    if (cc_prev_status.flags & CC_UNORD)
+      return \"bhi 0f\;blt %l0\;0:\";
+    else
+      return \"blt %l0\";
+}")
 
 (define_insn "bltu"
   [(set (pc)
@@ -2349,7 +2361,13 @@
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))]
   ""
-  "ble %l0")
+  "*
+{
+    if (cc_prev_status.flags & CC_UNORD)
+      return \"bhi 0f\;ble %l0\;0:\";
+    else
+      return \"ble %l0\";
+}")
 
 (define_insn "bleu"
   [(set (pc)
@@ -2399,7 +2417,13 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "ble %l0")
+  "*
+{
+    if (cc_prev_status.flags & CC_UNORD)
+      return \"bhi 0f\;ble %l0\;0:\";
+    else
+      return \"ble %l0\";
+}")
 
 (define_insn "*bleu"
   [(set (pc)
@@ -2435,7 +2459,13 @@
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))]
   ""
-  "blt %l0")
+  "*
+{
+    if (cc_prev_status.flags & CC_UNORD)
+      return \"bhi 0f\;blt %l0\;0:\";
+    else
+      return \"blt %l0\";
+}")
 
 (define_insn "*bltu"
   [(set (pc)