diff options
author | Jeff Law <law@cygnus.com> | 1999-03-17 20:15:18 +0000 |
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committer | Jeff Law <law@cygnus.com> | 1999-03-17 20:15:18 +0000 |
commit | 5dbd11d929a35866ed38c2fa2877fb6e03fd0b3b (patch) | |
tree | 40655e5eb9df4e6d118483da0bcfd28a4f6c24e0 /gcc/config/pa | |
parent | b2688b93e3298170b6a3cc1e3bb53362278d181a (diff) |
* pa.md: Add real PA8000 scheduling information.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@25829 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/pa')
-rw-r--r-- | gcc/config/pa/pa.md | 52 |
1 files changed, 46 insertions, 6 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index e1d0661b657..0edbf3139cd 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -350,15 +350,55 @@ ;; treat it just like the 7100LC pipeline. ;; Similarly for the multi-issue fake units. -;; PA8000 scheduling +;; +;; Scheduling for the PA8000 is somewhat different than scheduling for a +;; traditional architecture. ;; -;; HP recommends against latency scheduling on the PA8000. +;; The PA8000 has a large (56) entry reorder buffer that is split between +;; memory and non-memory operations. ;; -;; For now we do not actually define any scheduling parameters for the PA8000. +;; The PA800 can issue two memory and two non-memory operations per cycle to +;; the function units. Similarly, the PA8000 can retire two memory and two +;; non-memory operations per cycle. ;; -;; -msched=8000 is mostly so that we can retune the code sequences to improve -;; performance on the PA8000 class machines. -;; +;; Given the large reorder buffer, the processor can hide most latencies. +;; According to HP, they've got the best results by scheduling for retirement +;; bandwidth with limited latency scheduling for floating point operations. +;; Latency for integer operations and memory references is ignored. +;; +;; We claim floating point operations have a 2 cycle latency and are +;; fully pipelined, except for div and sqrt which are not pipelined. +;; +;; It is not necessary to define the shifter and integer alu units. +;; +;; These first two define_unit_unit descriptions model retirement from +;; the reorder buffer. +(define_function_unit "pa8000lsu" 2 1 + (and + (eq_attr "type" "load,fpload,store,fpstore") + (eq_attr "cpu" "8000")) 1 1) + +(define_function_unit "pa8000alu" 2 1 + (and + (eq_attr "type" "!load,fpload,store,fpstore") + (eq_attr "cpu" "8000")) 1 1) + +;; Claim floating point ops have a 2 cycle latency, excluding div and +;; sqrt, which are not pipelined and issue to different units. +(define_function_unit "pa8000fmac" 2 0 + (and + (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl") + (eq_attr "cpu" "8000")) 2 1) + +(define_function_unit "pa8000fdiv" 2 1 + (and + (eq_attr "type" "fpdivsgl,fpsqrtsgl") + (eq_attr "cpu" "8000")) 17 17) + +(define_function_unit "pa8000fdiv" 2 1 + (and + (eq_attr "type" "fpdivdbl,fpsqrtdbl") + (eq_attr "cpu" "8000")) 31 31) ;; Compare instructions. |