diff options
| author | Geoffrey Keating <geoffk@apple.com> | 2005-02-03 06:36:02 +0000 |
|---|---|---|
| committer | Geoffrey Keating <geoffk@apple.com> | 2005-02-03 06:36:02 +0000 |
| commit | f8a3916132b8fa0f2a9322912e5cbcf233ef847d (patch) | |
| tree | b9fc41b4284dd1212ec0f59c15bb2c40b47e1e1e /gcc/config/rs6000/altivec.md | |
| parent | bb343f9c7a812d3226f693f7c3d49727b8c07807 (diff) | |
2005-02-02 Geoffrey Keating <geoffk@apple.com>
* config/rs6000/altivec.md (altivec_dst): Make the first operand
a REG, not a MEM.
(altivec_dstt): Likewise.
(altivec_dstst): Likewise.
(altivec_dststt): Likewise.
* config/rs6000/rs6000.c (altivec_expand_dst_builtin): Adjust creation
of first operand.
Index: testsuite/ChangeLog
2005-02-02 Geoffrey Keating <geoffk@apple.com>
* gcc.dg/altivec-19.c: New.
git-svn-id: https://gcc.gnu.org/svn/gcc/trunk@94652 138bc75d-0d04-0410-961f-82ee72b054a4
Diffstat (limited to 'gcc/config/rs6000/altivec.md')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 6084e165b1d..1b3beffadfc 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1542,35 +1542,35 @@ [(set_attr "type" "vecsimple")]) (define_insn "altivec_dst" - [(unspec [(match_operand:V4SI 0 "memory_operand" "Q") + [(unspec [(match_operand 0 "register_operand" "b") (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "i")] 190)] - "TARGET_ALTIVEC" - "dst %P0,%1,%2" + "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" + "dst %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_dstt" - [(unspec [(match_operand:V4SI 0 "memory_operand" "Q") + [(unspec [(match_operand 0 "register_operand" "b") (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "i")] 191)] - "TARGET_ALTIVEC" - "dstt %P0,%1,%2" + "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" + "dstt %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_dstst" - [(unspec [(match_operand:V4SI 0 "memory_operand" "Q") + [(unspec [(match_operand 0 "register_operand" "b") (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "i")] 192)] - "TARGET_ALTIVEC" - "dstst %P0,%1,%2" + "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" + "dstst %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_dststt" - [(unspec [(match_operand:V4SI 0 "memory_operand" "Q") + [(unspec [(match_operand 0 "register_operand" "b") (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "immediate_operand" "i")] 193)] - "TARGET_ALTIVEC" - "dststt %P0,%1,%2" + "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode" + "dststt %0,%1,%2" [(set_attr "type" "vecsimple")]) (define_insn "altivec_lvsl" |